Texas Instruments TMS380C26 User Manual

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

• IEEE 802.5 and IBM Token-Ring Network

Compatible

• IEEE 802.3 and Blue Book Ethernet

Network Compatible

• Pin and Software Compatible With the

TMS380C16

• Configurable Network Type and Speed:

– Selectable by Host Software Control

(Adapter Control Register) – Selectable by Network Front-End – Readable from Host (Adapter Control

• Token-Ring Features

– 16- or 4-Megabit-per-Second Data Rates – Supports up to 18K-Byte Frame Size

(16 Mbps Operation Only) – Supports Universal and Local Network

Addressing – Early Token Release Option (16 Mbps

Operation Only) – Compatible With the TMS38054

• Ethernet Features

– 10-Megabit-per-Second Data Rate – Compatible With Most Ethernet Serial

Network Interface Devices – Full Duplex Ethernet Operation Allows

Network Speed Self-test

• Expandable Local LAN Subsystem Memory

Space up to 2 Megabytes

• Supports Multicast Addressing of Network

Group Addresses Through Hashing

• Glueless Interface to DRAMs

• High-Performance 16-Bit CPU for

Communications Protocol Processing

• Up to 8 Megabyte-per-Second High-Speed

Bus Master DMA Interface

network commprocessor applications diagram

• Low-Cost Host-Slave I/O Interface Option

• Up to 32-Bit Host Address Bus

• Selectable Host System Bus Options

• 80x8x or 68xxx-Type Bus and Memory

Organization – 8- or 16-Bit Data Bus on 80x8x Buses – Optional Parity Checking

• Dual-Port DMA and Direct I/O Transfers to

Host Bus

• Specification for External Adapter-Bus

Devices (SEADs) Supports External Hardware Interface for User-Defined External Logic

• Enhanced Address Copy Option (EACO)

Interface Supports External Address Checking Logic for Bridging or External Custom Applications

• Support for Module High-Impedance

In-Circuit Testing

• Built-in Real-Time Error Detection

• Bring-Up and Self-Test Diagnostics With

Loopback

• Automatic Frame Buffer Management

• Slow-Clock Low-Power Mode

• Single 5-V Supply

• 1-µm CMOS Technology

• 250 mA Typical Latch-Up Immunity at 25°C

• ESD Protection Exceeds 2,000 V

• 132-Pin JEDEC Plastic Quad Flat Package

(PQ Suffix)

• Operating Temperature Range

0°C to 70 °C

Attached

System

Bus

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

LAN Subsystem

Token Ring or

TMS380C26

Memory

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Ethernet Physical

Layer Circuitry

77251–1443

Transmit

To Network

Receive

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

pinout

The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1.

132-PIN QUAD FLAT PACK

(TOP VIEW)

SSL

DDL

CLKDIV

SSC

NSELOUT0

PRTYEN

BTSTRP

SIACK

SRESET

SRS1 SRS0 SRSX

SCS SBRLS SBBSY

S8/SHALT

SRS2/SBERR

DDL

SI/M

SINTR/SIRQ

SHLDA/SBGR

SDDIR

SRAS/SAS

SWR/SLDS

SSI

SXAL SALE

SBCLK

SADL7 SADL6 SADL5 SADL4 SADL3

DD5

DD4

NMI

EXTINT014EXTINT113EXTINT2

EXTINT3

MADL010MADL19MADL28MADL37MADL46MADL55MADL64MADL73MAXPL

16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

515253545556575859696162636465666768697071727374757677787980818283

SS4

MBGR

MBGQ

MAXPH

MADH0

132

131

130

129

MADH1

MADH2

128

127

SS3

MADH3

126

125

DD3

124

MADH4

MADH5

123

122

MADH6

MADH7

121

120

MBEN

MOE

119

118

SS1

117 116

115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 80 89 88 87 86 85 84

SSC

MRAS MW MCAS MAX2 MAX0 MDDIR V

DD2

SYNCIN OSCIN V

SS2

MROMEN MACS MAL MREF MBIAEN V

DDL

MRESET MBCLK2 MBCLK1 OSCOUT RCVR/RXD RCLK/RXC NSETOUT1 PXTALIN/TXC V

SS1

WRAP

/TXEN DRVR DRVR WFLT/COLL

/LPBK

NSRT FRAQ/TXD REDY

/CRS

SS5

SADL2

SADL1

SPL

SADL0

SOWN

SDBEN

SHRQ/SBRQ

SBHE/SRNW

SPH

SRD/SUDS

SRDY/SDTACK

SADH7

SADH6

SSC

DD6

SS6

SADH5

SADH4

SADH3

SADH2

SADH1

SADH0

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

XFAIL

XMATCH

DD1

SSL

Figure 1. TMS380C26 Pinout

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

description

The TMS380C26 is a single-chip network communications processor (commprocessor) that supports token ring, or Ethernet Local Area Networks (LANs). Either token ring at data rates of 16 Mbps or 4 Mbps, or Ethernet at a data rate of 10 Mbps, can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN subsystems which support both token ring and Ethernet networks, by electrically or physically switched network front-end circuits.

The TMS380C26 conforms to IEEE 802.5–1989 standards and has been verified to be completely IBM



Token-Ring compatible. By integrating the essential control building blocks needed on a LAN subsystem card into one device, the TMS380C26 can ensure that this IBM compatability is maintained in silicon.

The TMS380C26 conforms to ISO/IEC 8802–3 (ANSI/IEEE Std 802.3) CSMA/CD standards, and the Ethernet ”Blue Book” standard.

The high degree of integration of the TMS380C26 makes it a virtual LAN subsystem on a single chip. Protocol handling, host system interfacing, memory interfacing, and communications processing are all provided through the TMS380C26. T o complete LAN subsystem design, only the network interface hardware, local memory , and minimal additional components such as PALs and crystal oscillators need to be added.

The TMS380C26 provides a 32-bit system memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TMS380C26 supports direct I/O and a low-cost 8-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally , selectable 80x8x or 68xxx-type host system bus and memory organization add to design flexibility .

The TMS380C26 supports addressing for up to two Megabytes of local memory. This expanded memory capacity can improve LAN subsystem performance by minimizing the frequency of host LAN subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host.

The proprietary CPU used in the TMS380C26 allows protocol software to be downloaded into RAM or stored in ROM in the local memory space. By moving protocols (such as LLC) to the LAN subsystem, overall system performance is increased. This is accomplished due to the the offloading of processing from the host system to the TMS380C26, which may also reduce LAN subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance will be possible.

In addition, the TMS380C26 includes hardware counters that provide realtime error detection and automatic frame buffer management. These counters control system bus retries, burst size, and track host and LAN subsystem buffer status. Previously , these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN subsystem performance is improved.

The TMS380C26 implements a TI-patented Enhanced Address Copy Option (EACO) interface. This interface supports external address checking devices, such as the TMS380SRA Source Routing Accelerator. The TMS380C26 has a 128-word external I/O space in its memory map to support external address-checker devices and other hardware extensions to the TMS380 architecture. Hardware designed in conformance with TI’s Specification for External Adapter-bus Devices (SEADs) can map registers into this external I/O space and post interrupts to the TMS380C26.

The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF) as shown in Figure 2.

The TMS380C26 is available in a 132-pin JEDEC plastic quad flat pack and is rated from 0°C to 70°C.

IBM is a registered trademark of International Business Machines Corporation.

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

block diagram and signal descriptions

TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical layer circuitry. As a rule of thumb in the pin nomenclature and descriptions that follow, pin names starting with the letter S attach to the host system bus and pin names starting with the letter M attach to the local memory bus. Active-low signals have names with overbars, e.g., SCS

SADH0

SADH7

SADL0

SADL7

SPH

SPL

SBRLS

SINTR/SIRQ

SDDIR

SDBEN

SALE

SXAL SOWN SIACK

SBCLK

/SUDS

SRD

SWR/SLDS

SRDY/SDTACK

SHLDA/SBGR

SBHE/SRNW

SRS2/SBERR

SHRQ/SBRQ

SI/M

SRAS/SAS

S8/SHALT

SRESET

SRS0

SRS1

SCS

SRSX

SBBSY

BTSTRP

PRTYEN

NSELOUT0 NSELOUT1

System

Interface

(SIF)

• DIO Control

• Bus Control

• DMA Control

Communications

Processor

Memory

Interface

(MIF)

• DRAM Refresh

• Local Bus

Arbitrator

• Local Bus

Control

• Local Parity Check/

Generator

Clock

Generator

(CG)

Adapter Support

Function

(ASF)

• Interrupts

• Test Function

MADH0

MADH7 MADL0

MADL7 MRAS

MCAS MAXPH MAXPL MW MOE MDDIR MAL MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF

OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV

NMI EXTINT0

EXTINT

TEST0

TEST5

XMATCH XFAIL

RCLK/RXC

/CRS

REDY

WFLT

/COLL

RCVR/RXD

PXTALIN/TXC

Protocol Handler (PH):

for Token Ring and

Ethernet Interface

FRAQ/TXD

/LPBK

NSRT WRAP

/TXEN DRVR DRVR

Figure 2. TMS380C26 COMMprocessor Block Diagram

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Terminal Functions

PIN NAME NO. I/O DESCRIPTION

Bootstrap. The value on this pin is loaded into the BOOT bit of the SIFACL register at reset (i.e., when the SRESET This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters

BTSTRP 23 IN

CLKDIV 19 IN

EXTINT0 EXTINT1 EXTINT2 EXTINT3

MACS 104 IN Reserved. Must be tied low (see Note 2). MADH0

MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7

MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7

MAL 103 OUT

14 13 12 11

129 128 127 126 123 122 121 120

9 8 7 6 5 4 3

IN Reserved; must be pulled high (see Note 4).

I/O

are RAM then the TMS380C26 is denied access to the local memory bus until the CPHALT bit in the SIFACL register is cleared.

H = Chapters 0 and 31 of local memory are RAM-based (see Note 1). L = Chapters 0 and 31 of local memory are ROM-based.

Clock Divider Select. This pin must be pulled high

H = Indicates 64-MHz OSCIN (see Note 3). L = Reserved.

Local memory Address, Data and Status Bus – high byte. For the first quarter of the local memory cycle these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0 and the least significant bit is MADH7.

Signal AX4,A0–A6 Status D0–D7 D0–D7 Local Memory Address, Data and Status Bus – low byte. For the first quarter of the local memory

cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4 and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant bit is MADL0 and the least significant bit is MADL7.

Signal A7–A14 AX4,A0–A6 D8–D15 D8–D15 Memory Address Latch. This is a strobe signal for sampling the address at the start of the memory

cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH, MAX2, MAXPL, MADH0-MADH7, and MADL0-MADL7. Three 8-bit transparent latches can therefore be used to retain a 20-bit static address throughout the cycle.

pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value.

Memory Cycle

2Q 3Q 4Q

Memory Cycle

2Q 3Q 4Q

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Rising edge = No signal latching. Falling edge = Allows the above address signals to be latched.

Local Memory Extended Address Bit. This signal drives AX0 at ROW address time and it drives A12 at COL address and DAT A time for all cycles. This signal can be latched by MRAS

MAX0 111 OUT

MAX2 112 OUT

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

2. Pin should be connected to ground.

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

4. Each pin must be individually tied to VCC with a 1.0-kΩ pullup resistor.

interfacing to a BIA ROM.

Signal AX0 A12 A12 A12

Local Memory Extended Address Bit. This signal drives AX2 at ROW address time, which can be latched by MRAS interfacing to a BIA ROM.

Signal AX2 A14 A14 A14

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, and A14 at COL address, and DATA time for all cycles. Driving A14 eases

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Memory Cycle 2Q 3Q 4Q

. Driving A12 eases

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Local Memory Extended Address and Parity High Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX1); for the second quarter of a memory cycle this signal carries the extended address bit (AX0); and for the last half of the memory cyle this signal carries the

MAXPH 130 I/O

MAXPL 2 I/O

MBCLK1 MBCLK2

MBEN 119 OUT

MBGR 132 OUT Reserved. Must be left unconnected.

MBIAEN 101 OUT

MBRQ 131 IN Reserved. Must be pulled high (see Note 4).

97 98

OUT

parity bit for the high data byte.

Signal AX1 AX0 Parity Parity

Local Memory Extended Address and Parity Low Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX3), for the second quarter of a memory cycle this signal carries extended address bit (AX2); and for the last half of the memory cycle this signal carries the parity bit for the low data byte.

Signal AX3 AX2 Parity Parity Local Bus Clock1 and local Bus Clock 2. These signals are referenced for all local bus transfers.

MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate at 8 MHz for a 64-MHz OSCIN and 6 MHz for a 48-MHz OSCIN, which is twice the memory cycle rate. The MBCLK signals are always a divide-by-8 of the OSCIN frequency.

Buffer Enable. This signal enables the bidirectional buf fer outputs on the MADH, MAXPH, MAXPL, and MADL buses during the data phase. This signal is used in conjunction with MDDIR which selects the buffer output direction.

H = Buffer output disabled. L = Buffer output enabled.

Burned-In Address Enable. This is an output signal used to provide an output enable for the ROM containing the adapter’s Burned-In Address (BIA).

H = This signal is driven high for any WRITE accesses to the addresses between >00.0000 and

>00.000F, or any accesses (Read/Write) to any other address.

L = This signal is driven low for any READ from addresses between >00.0000 and >00.000F .

Column Address Strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle following the row address portion of the cycle. This signal is driven low every memory cycle while the column address is valid on MADL0-MADL7, MAXPH, and MAXPL, except when one of the following conditions occurs:

Memory Cycle

2Q 3Q 4Q

Memory Cycle

2Q 3Q 4Q

1) When the address accessed is in the BIA ROM (>00.0000 – >00.000F).

MCAS 113 OUT

MDDIR 110 OUT

NOTE 4: Each pin must be individually tied to VCC with a 1.0-kΩ pullup resistor.

2) When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in the SIFACL register is zero and an access is made between >00.0010 – >00.FFFF) or >1F.0000 – >1F.FFFF).

3) When the cycle is a refresh cycle, in which case MCAS MRAS

(for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CASbefore-RAS cycle.

Data Direction. This signal is used as a direction control for bidirectional bus drivers. The signal becomes valid before MBEN

H = TMS380C26 memory bus write. L = TMS380C26 memory bus read.

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refresh, it may be necessary to disable MCAS with MREF during the refresh

active.

77251–1443

is driven at the start of the cycle before

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Memory Output Enable. This signal is used to enable the outputs of the DRAM memory during a read cycle. This signal is high for EPROM or BIA ROM read cycles.

MOE 118 OUT

MRAS 115 OUT

MREF 102 OUT

MRESET 99 OUT

MROMEN 105 OUT

H = Disable DRAM outputs. L = Enable DRAM outputs.

Row Address Strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. This signal is driven low every memory cycle while the row address is valid on MADL0-MADL7, MAXPH, and MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh address is valid on MADL0-MADL7.

DRAM Refresh Cycle in Progress. This signal is used to indicate that a DRAM refresh cycle is occurring. It is also used for disabling MCAS

H = DRAM refresh cycle in process. L = Not a DRAM refresh cycle.

Memory Bus Reset. This is a reset signal generated when either the ARESET bit in the SIFACL register is set or the SRESET logic.

H = External logic not reset. L = External logic reset.

ROM Enable. During the first 5/16 of the memory cycle, this signal is used to provide a chip select for ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not RAM). It can be latched by MA >1F .0000 – >1F .FFFF when the Boot bit in the SIFACL register is zero. It stays high for writes to these addresses, accesses of other addresses, or accesses of any address when the BOOT bit is one. During the final three quarters of the memory cycle, it outputs the A13 address signal for interfacing to a BIA ROM. This means MBIAEN for the BIA ROM.

pin is asserted. This signal is used for resetting external local bus glue

L. It goes low for any read from addresses >00.0010 – >00.FFFF or

to all DRAMs that do not use a CAS before-RAS refresh.

, MAX0, ROMEN, and MAX2 together form a glueless interface

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

H = ROM disabled. L = ROM enabled.

Local Memory Write. This signal is used to specify a write cycle on the local memory bus. The data on the MADH0-MADH7 and MADL0-MADL7 buses is valid while MW

MW 114 OUT

NMI 15 IN Non-Maskable Interrupt Request. This pin must be left unconnected. OSCIN 107 IN

OSCOUT 96 OUT

NOTE 5: Pin has an expanded input voltage specification.

the falling edge MW

H = Not a local memory write cycle. L = Local memory write cycle.

External Oscillator Input. This line provides the clock frequency to the TMS380C26 for a 4-MHz internal bus. OSCIN should be 64 a MHz signal (see Note 5).

Oscillator Output. With OSCIN at 64 MHz and CLKDIV pulled high, this pin provides an 8 MHz output which can be used by TMS3054 for 4 Mbps operation without the need for an additional crystal.

CLKDIV OSCOUT

L Reserved (Reserved) H OSCIN/8 (if OSCIN = 64 MHz, then OSCOUT = 8 MHz).

, while SRAMs latch data on the rising edge of MW.

is low. DRAMs latch data on

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Parity Enable. The value on this pin is loaded into the PEN bit of the SIFACL register at reset (i.e., when the SRESET

PRTYEN 22 IN

NSELOUT0 NSELOUT1

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

21 93

OUT OUT

value. This bit enables parity checking for the local memory.

H = Local memory data bus checked for parity (see Note 1). L = Local memory data bus

Network Selection Outputs. These output signals are controlled by the host through the corresponding bits of the SIFACTL register. The value of these bits/signals can only be changed while the TMS380C26 is reset.

pin is asserted or the ARESET bit in the SIFACL register is set) to form a default

NOT

checked for parity.

NSELOUT0 NSELOUT1 Description

L L Reserved

L H 16 Mbps token ring H L Ethernet (802.3/Blue Book) H H 4 Mbps token ring

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NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7

SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7

SALE 43 OUT

SBBSY 31 IN

SBCLK 44 IN

SBHE/SRNW 57 I/O

SBRLS

SCS 29 IN

SDBEN 58 OUT

†

Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

73 72 71 70 69 68 64 63

54 53 52 49 48 47 46 45

30 IN

I/O

System Address/Data Bus—high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADH0, and the least significant bit is SADH7.

Address Multiplexing†: Bits 31 – 24 and bits 15 – 8. Data Multiplexing†: Bits 15 – 8.

System Address/Data Bus—low byte (see Note 1). These lines make up the least significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0, and the least significant bit is SADL7.

Address Multiplexing†: Bits 23 – 16 and bits 7 – 0. Data Multiplexing†: Bits 7 – 0.

System Address Latch Enable. This is the enable pulse used to externally latch the 16 LSBs of the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched address.

System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has one of (2) two values (see Note 1):

H = Not busy. The TMS380C26 may become Bus Master if the grant condition is met. L = Busy. The TMS380C26 cannot become Bus Master.

System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for all DMA transfers.

System Byte High Enable. This pin is a three-state output that is driven during DMA and an input at all other times.

H = System Byte High not enabled (see Note 1). L = System Byte High enabled.

System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is signal is internally synchronized to SBCLK.

H = The TMS380C26 can hold onto the system bus (see Note 1). L = The TMS380C26 should release the system bus upon completion of current DMA cycle. If the

DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.

System Chip Select. Activates the system interface of the TMS380C26 for a DIO read or write.

H = Not selected (see Note 1). L = Selected.

System Data Bus Enable. This output signals to the external data buffers to begin driving data. This output is activated during both DIO and DMA.

H = Keep external data buffers in high-impedance state. L = Cause external data buffers to begin driving data.

NOT

TMS380C26

perfoming DMA. This

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

System Data Direction. This output provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the

SDDIR 38 OUT

SHLDA/SBGR 37 IN

SHRQ/SBRQ 56 OUT

SIACK 24 IN

TMS380C26). When the system interface is high by default.

DATA

SDDIR

System Hold Acknowledge. This pin indicates that the system DMA hold request has been acknowledged. It is internally synchronized to SBCLK (see Note 1). H = Hold request acknowledged. L = Hold request not acknowledged.

System Hold Request. This pin is used to request control of the system bus in preparation for a DMA transfer. This pin is internally synchronized to SBCLK.

H = System bus requested. L = System bus not requested.

System Interrupt Acknowledge. This signal is from the host processor to acknowledge the interrupt request from the TMS380C26.

H = System interrupt not acknowledged (see Note 1). L = System interrupt acknowledged: the TMS380C26 places its interrupt vector onto the system

bus.

System Intel/Motorola Mode Select. The value on this pin specifies the system interface mode.

DIRECTION DIO DMA

H output read write

L input write read

NOT

involved in a DIO or DMA operation, then SDDIR is

SI/M 35 IN

SINTR/SIRQ 36 OUT

SOWN 59 OUT

SPH 62 I/O

SPL 55 I/O

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

H = Intel-compatible interface mode selected. Intel interface can be 8-bit or 16-bit mode

(see S8/SHALT

L = Motorola-compatible interface mode selected. System Interrupt Request. TMS380C26 activates this output to signal an interrupt request to the host

processor.

H = Interrupt request by TMS380C26. L = No interrupt request.

System Bus Owned. This signal indicates to external devices that TMS380C26 has control of the system bus. This signal drives the enable signal of the bus transceiver chips, which drive the address and bus control signals.

H = TMS380C26 does not have control of the system bus. L = TMS380C26 has control of the system bus.

System Parity High. The optional odd-parity bit for each address or data byte transmitted over SADH0-SADH7 (see Note 1).

System Parity Low. The optional odd-parity bit for each address or data byte transmitted over SADL0-SADL7 (see Note 1).

pin description and Note 1.)

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Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

System Memory Address Strobe (see Note 3). This pin used to latch the SCS, SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied to the SALE output of the System Bus. The latching capability can be defeated since the internal latch for these inputs remains transparent as long as SRAS remains high. This permits SRAS to be pulled high and the signals at the SCS

SRAS/SAS 39 I/O

SRSX – SRS2, and SBHE During DMA this pin remains an input.

to be applied independently of the SALE strobe from the system bus.

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High = transparent mode Low = Holds latched values of SCS Falling edge = latches SCS, SRSX – SRS2, and SBHE

System Read Strobe (see Note 3). Active-low strobe indicating that a read cycle is performed on the system bus. This pin is an input during DIO and an output during DMA.

SRD/SUDS 61 I/O

SRDY/SDTACK 60 I/O

SRESET 25 IN

SRSX SRS0 SRS1 SRS2/SBERR

SWR/SLDS 40 I/O

SXAL 42 OUT

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

28 27 26 33

H = Read cyle is not occurring. L = If DMA: host provides data to system bus.

If DIO: SIF provides data to system bus.

System Bus Ready (see Note 3).The purpose of this signal is to indicate to the bus master that a data transfer is complete. This signal is asynchonous, but during DMA and pseudo-DMA cycles it is internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26 is selected for DIO, and an input otherwise.

H = System bus NOT ready. L = Data transfer is complete; system bus is ready.

System Reset. This input signal is activated to place the TMS380C26 into a known initial state. Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the reset state. DMA bus width selection is latched on the rising edge of SRESET

H = No system reset. L = System reset. Rising edge = Latch bus width for DMA operation.

System Register Select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS2 (see Note 1).

MSb

Registered selected = SRSX SRS0 SRS1 SRS2/SBERR System Write Strobe (see Note 3). This pin serves as an active-low write strobe. This pin is an input

during DIO and an output during DMA.

H = Write cycle is not occurring. L = If DMA: data to be drivien from SIF to host bus.

If DIO: on the rising edge, the data is latched and written to the selected register.

System Extended Address Latch. This output provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry-out of the lower 16 bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.

, SRSX–SRS2, and SBHE

LSb

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Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

SYNCIN 108 IN Reserved. This signal must be left unconnected (see Note 1).

System 8/16-bit bus select. This pin selects the bus width used for communications through the system interface. On the rising edge of SRESET

S8/SHALT 32 IN

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

otherwise the value on this pin dynamically selects the DIO bus width.

H = Selects 8-bit mode (see Note 1). L = Selects 16-bit mode.

, the TMS380C26 latches the DMA bus width;

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System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7

SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7

SALE 43 OUT

SBBSY 31 IN

SBCLK 44 IN

SBHE/SRNW 57 I/O

SBRLS

SCS 29 IN

SDBEN 58 OUT

†

Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

73 72 71 70 69 68 64 63

54 53 52 49 48 47 46 45

30 IN

I/O

Address Multiplexing†: Bits 31 – 24 and bits 15 – 8. Data Multiplexing†: Bits 15 – 8.

Address Multiplexing†: Bits 23 – 16 and bits 7 – 0. Data Multiplexing†: Bits 7 – 0.

System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has one of (2) two values (see Note 1):

H = Not busy. The TMS380C26 may become Bus Master if the grant condition is met. L = Busy. The TMS380C26 cannot become Bus Master.

System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for all DMA transfers.

System Read Not Write. This pin serves as a control signal to indicate a read or write cycle.

H = Read Cycle (see Note 1). L = Write Cycle

H = The TMS380C26 can hold onto the system bus (see Note 1). L = The TMS380C26 should release the system bus upon completion of current DMA cycle. If the

DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.

System Chip Select. Activates the system interface of TMS380C26 for a DIO read or write.

H = Not selected (see Note 1). L = Selected.

System Data Bus Enable. This output signals to the external data buffers to begin driving data. This output is activated during both DIO and DMA.

H = Keep external data buffers in high-impedance state. L = Cause external data buffers to begin driving data.

=L)

NOT

perfoming DMA. This

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Terminal Functions (continued)

System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

SDDIR 38 OUT

SHLDA/SBGR 37 IN

SHRQ/SBRQ 56 OUT

SIACK 24 IN

SI/M 35 IN

SINTR/SIRQ 36 OUT

SOWN 59 OUT

SPH 62 I/O

SPL 55 I/O

SRAS/SAS 39 I/O

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

SDDIR is high by default.

SDDIR

H output read write

L input write read

System Bus Grant. This pin serves as an active-low bus grant, as defined in the standard 68000 interface, and is internally synchronized to SBCLK (see Note 1).

H = System bus not granted, L = System bus granted.

System Bus Request. This pin is used to request control of the system bus in preparation for a DMA transfer. This pin is internally synchronized to SBCLK.

H = System bus not requested. L = System bus requested.

System Interrupt Acknowledge. This signal is from the host processor to acknowledge the interrupt request from the TMS380C26.

H = System interrupt not acknowledged (see Note 1). L = System interrupt acknowledged: the TMS380C26 places its interrupt vector onto the system

bus.

System Intel/Motorola Mode Select. The value on this pin specifies the system interface mode.

H = Intel-compatible interface mode selected. L = Motorola-compatible interface mode selected. Motorola interface mode is always 16 bits.

System Interrupt Request. TMS380C26 activates this output to signal an interrupt request to the host processor.

H = No interrupt request. L = Interrupt request by TMS380C26.

H = TMS380C26 does not have control of the system bus. L = TMS380C26 has control of the system bus.

System Parity High. The optional odd-parity bit for each address or data byte transmitted over SADH0-SADH7 (see Note 1).

System Parity Low. The optional odd-parity bit for each address or data byte transmitted over SADL0-SADL7 (see Note 1).

Sytem Memory Address Strobe (see Note 3). This pin is an active-low address strobe that is an input during DIO (although ignored as an address strobe) and an output during DMA.

H = Address not valid L = Address is valid and a transfer operation is in progress.

DATA

DIRECTION DIO DMA

=L)

NOT

involved in a DIO or DMA operation, then

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System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

Upper Data Strobe (see Note 3). This pin serves as the active-low upper data strobe. This pin is an input during DIO and an output during DMA.

SRD/SUDS 61 I/O

SRDY/SDTACK 60 I/O

SRESET 25 IN

SRSX SRS0 SRS1

SRS2/SBERR 33 IN

SWR/SLDS 40 I/O

SXAL 42 OUT

SYNCIN 108 IN Reserved. This signal must be left unconnected (see Note 1).

S8/SHALT 32 IN

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

28 27 26

H = Not valid data on SADH0-SADH7 lines. L = Valid data on SADH0-SADH7 lines.

System Data Transfer Acknowledge (see Note 3). The purpopse of this signal is to indicate to the bus master that a data transfer is complete. This signal is internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26 is selected for DIO, and an input otherwise.

H = System bus NOT ready. L = Data transfer is complete; system bus is ready.

System Reset. This input is activated to place the adapter into a known initial state. Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the reset state.

H = No system reset. L = System reset.

System Register Select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS1 (see Note 1).

Register Selected = SRSX SRS0 SRS1 Bus Error. Corresponds to the bus error signal of the 68000 microprocessor. It is internally

synchronized to SBCLK. This input is driven low during a DMA cycle to indicate to the TMS380C26 that the cycle must be terminated. See Section 3.4.5.3 of the

Ring User’s Guide

Lower Data Strobe (see Note 3). This pin is an input during DIO and an output during DMA. This pin serves as the active-low lower data strobe.

H = Not valid data on SADL0-SADL7 lines. L = Valid data on SADL0-SADL7 lines.

System Extended Address Latch. This output provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry-out of the lower 16-bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.

System Halt/Bus Error Retry. If this signal is asserted along with bus errror (SBERR), the adapter will retry the last DMA cycle. This is the re-run operation as defined in the 68000 specification. The BERETRY counter is not decremented by SBERR the

TMS380 Second-Generation T oken Ring User’s Guide

MSb

(SPWU005) for more information (see Note 1).

=L)

LSb

TMS380 Second-Generation Token

when SHALT is asserted. See Section 3.4.5.3 of

(SPWU005) for more information.

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Terminal Functions (continued)

Network Media Interface – Token-Ring Mode (TEST1 = H, TEST2 = H)

PIN NAME NO. I/O DESCRIPTION

DRVR DRVR

FRAQ/TXD 85 OUT

NSRT/LPBK 86 OUT

PXTALIN/TXC 92 IN

RCLK/RXC 94 IN

RCVR/RXD 95 IN

REDY/CRS 84 IN

WFLT/COLL 87 IN

WRAP/TXEN 90 OUT

89 88

OUT

Differential Driver Data Output. These pins are the differential outputs that send the TMS380C16 transmit data to the TMS38054 for driving onto the ring transmit signal pair.

Frequency Acquisition Control. This TTL output determines the use of frequency or phase acquisition mode in the TMS38054.

H = Wide range. Frequency centering to PXTALIN by TMS38054. L = Narrow range. Phase-lock onto the incoming data (RCVINA and RCVINB) by the

TMS38054.

Insert Control Signal to the TMS38054. This TTL output signal enables the phantom driver outputs (PHOUTA and PHOUTB) of the TMS38054, through the watchdog timer, for insertion onto the Token-Ring.

Static High = Inactive, phantom current removed (due to watchdog timer) Static Low = Inactive, phantom current removed (due to watchdog timer) NSRT

Low and Pulsed High = Active, current output on PHOUTA and PHOUTB

Ring Interface Clock Frequency Control (see Note 5). At 16-Mbps ring speed, this input must be supplied a 32-MHz signal. At 4-Mbps ring speed, the input signal must be 8-MHz and may be the output from the OSCOUT pin.

Ring Interface Recovered Clock (see Note 5). This input signal is the clock recovered by the TMS38054 from the Token-Ring received data.

For 16-Mbps operation it is a 32-MHz clock. For 4-Mbps operation it is an 8-MHz clock.

Ring Interface Received Data (see Note 5). This input signal contains the data received by the TMS38054 from the token ring.

Ring Interface Ready. This input pin provides an indication of the presence of received data, as monitored by the TMS38054 energy detect capacitor.

H = Not ready. Ignore received data. L = Ready. Received data.

Wire Fault Detect. This signal is an input to the TMS380C16 driven by the TMS38054. It indicates a current imbalance of the TMS38054 PHOUTA and PHOUTB pins.

H = No wire fault detected. L = Wire fault detected.

Internal Wrap Select. This signal is an output from the TMS380C16 to the ring interface to activate an internal attenuated feedback path from the transmitted data (DRVR) to receive data (RCVR) signals for bring-up diagnostic testing. When active, the TMS38054 also cuts off the current drive to the transmission pair.

H = Normal ring operation. L = Transmit data drives receive data (loopback).

NOTE 5: Pin has an expanded input voltage specification.

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Terminal Functions (continued)

Network Media Interface – Ethernet Mode (TEST1 = L, TEST2 = H)

PIN NAME NO. I/O DESCRIPTION

DRVR DRVR

FRAQ/TXD 85 OUT

NSRT/LPBK 86 OUT

PXTALIN/TXC 92 IN

RCLK/RXC 94 IN

RCVR/RXD 95 IN

REDY/CRS 84 IN

WFLT/COLL 87 IN

89 88

OUT

These pins have no Ethernet function. In Ethernet Mode these pins are placed in their token ring reset state of DRVR = High, DRVR

Ethernet Transmit Data. This output signal provides the Ethernet physical layer circuitry with bit-rate from the TMS380C26. Data on this pin is output synchronously to the transmit clock TXC normally connected to the TXD pin of an Ethernet Serial Network Interface (SNI) chip.

Loopback. This enables loopback of Ethernet transmit data through the Ethernet (SNI) device to recieve data.

H = Wrap through the front end device L = Normal operation

Ethernet Transmit Clock. A 10 MHz clock input used to synchronize transmit data from the TMS380C26 to the Ethernet physical layer circuitry . This is a continuously running clock. It is normally connected to the TXC output pin of an Ethernet SNI chip (see Note 5).

Ethernet Receive Clock. A 10 MHz clock input used to synchronize received data from the Ethernet physical layer circuitry to the TMS380C26. This clock must be present whenever the CRS signal is active (although it can be held low for a maximum of 16 clock cycles after the rising edge of CRS). When the CRS signal is inactive it is permissable to hold this clock in a low phase. It is normally connected to the RXC output pin of an Ethernet Serial Network Interface (SNI) chip. The TMS380C26 requires this pin to be maintained in the low state when CRS

Ethernet Received Data. This input signal provides the TMS380C26 with bit rate network data from the Ethernet front end device. Data on this pin must be synchronous with the receive clock RXC. It is normally connected to the RXD pin of an Ethernet SNI chip (see Note 5).

Ethernet Carrier Sense. This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has network data present on the RXD pin. This signal is asserted high when the first bit of the frame is received and is deasserted after the last bit of the frame is received.

H = Receiving data. L = No data on network.

Ethernet Collision Detect. This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has detected a network collision. This signal must be present for at least two TXC clock cycles to ensure it is accepted by the TMS380C26. It is normally connected to the COLL pin of an Ethernet SNI chip. This signal can also be an indication of the SQE test signal.

= Low.

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. It is

is not asserted (see Note 5).

H = COLL detected by the SNI device. L = Normal operation.

Ethernet Transmit Enable. This output signal indicates to the Ethernet physical layer circuitry that bit-rate data is present on the TXD pin. This signal is output synchronously to the transmit clock TXC

WRAP/TXEN 90 OUT

NOTE 5: Pin has an expanded input voltage specification.

It is normally connected to the TXE pin of an Ethernet SNI chip.

H = Data line currently contains data to be transmitted. L = No valid data on TXEN.

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Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Network Select inputs. These pins are used to select the network speed and type to be used by the TMS380C26. These inputs should only be changed during adapter reset.

TEST 0 TEST 1 TEST 2

TEST3 TEST4 TEST5

XFAIL 80 IN

XMATCH 81 IN

79 78 77

76 75 74

IN IN IN

TEST0

Test Pin Inputs. These pins should be left unconnected (see Note 1). Module-in-Place test mode is achieved by tying TEST 3 and TEST 4 pins to ground. In this mode, all TMS380C26 output pins are high impedance. Internal pullups on all TMS380C26 inputs will be disabled (except TEST3-TEST5 pins).

External Fail-to-Match signal. An enhanced address copy option (EACO) device uses this signal to indicate to the TMS380C26 that it should not copy the frame nor set the ARI/FCI in bits in a token ring frame due to an external address match.The ARI/FCI bits in a token ring frame may be set due to an internal address matched frame. If an enhanced address copy option (EACO) device is NOT used, then this pin must be left unconnected. This pin is ignored when CAF mode is enabled. See table given below in XMATCH pin description (see Note 1).

H = No address match by external address checker. L = External address checker armed state.

External Match signal. An enhanced address copy option (EACO) device uses this signal to indicate to the TMS380C26 to copy the frame and set the ARI/FCI bits in a token ring frame. If an enhanced address copy option (EACO) device is NOT used, then this pin must be left unconnected. This pin is ignored when CAF mode is enabled (see Note 1).

H = Address match recognized by external address checker. L = External address checker armed state.

TEST1 TEST2 Description

L L H Reserved

L H H 16 Mbps token ring H L H Ethernet (802.3/Blue Book) H H H 4 Mbps token ring

X X 0 Reserved

XMATCH

XFAIL Function

0 0 Armed (Processing frame data). 0 1 Do NOT externally match the frame. (XFAIL takes precedence) 1 0 COPY the frame. 1 1 Do NOT externally match the frame. (XFAIL takes precedence)

HI-Z HI-Z Reset state (adapter not initialized).

DDL

DD1

DD2

DD3

DD4

DD5

DD6

SSC

SSI

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

100

82 109 124

116

117

Positive supply voltage for digital logic. All VDD pins must be attached to the common system power supply plane.

Positive supply voltage for output buffers. All VDD pins must be attached to the common system power supply plane.

Ground reference for output buffers (clean ground). All VSS pins must be attached to the common system ground plane.

Ground reference for input buffers. All VSS pins must be attached to the common system ground plane.

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Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

V V

V V V V V

SSL SS1

SS2 SS3 SS4 SS5 SS6

91 106 125

1 51 67

IN Ground reference for digital logic. All VSS pins must be attached to the common system ground plane.

IN Ground connections for output buffers. All VSS pins must be attached to system ground plane.

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architecture

communications processor (CP)

The Communications Processor (CP) performs the control and monitoring of the other functional blocks in the TMS380C26. The control and monitoring protocols are specified by the software (downloaded or ROM-based)

local memory . Available protocols include:

• Media Access Control (MAC) software,

• Logical Link Control (LLC) software, (token ring version only), and

• Copy All Frames (CAF) software.

The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for pipelining of instructions. These features enhance the TMS380C26’s maximum performance capability to about 4 million instructions per second (MIPS), with an average of about 2.5 MIPS.

system interface (SIF)

The System Interface (SIF) performs the interfacing of the LAN subsystem to the host system. This interface may require additional logic depending on the application. The system interface can transfer information/data using any of these three methods:

• Direct Memory Access (DMA),

• Direct Input/Output (DIO), or

• Pseudo-Direct Memory Access (PDMA).

DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory . DIO’s main uses are for loading the software to local memory and for initializing the TMS380C26. DIO also allows command/status interrupts to occur to and from the TMS380C26.

The system interface can be hardware selected for either of two modes by use of the SI/M selected determines the memory organizations and control signals used. These modes are:

pin. The mode

• The Intel 80x8x families: 8-, 16-, and 32-bit bus members

• The Motorola 68000 microprocessor family: 16- and 32-bit bus members

The system interface supports host system memory addressing up to 32 bits (32-bit reach into the host system memory). This allows greater flexibility in using/accessing host system memory.

System designers are allowed to customize the system interface to their particular bus by:

• Programmable burst transfers or cycle-steal DMA operations

• Optional parity protection

These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.

The system interface hardware also includes features to enhance the integrity of the TMS380C26 and the data. These features do the following:

• Always internally maintain odd byte parity regardless if parity is disabled,

• Monitor for the presence of a clock failure.

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On every cycle the system interface compares all the system clocks to a reference clock. If any of the clocks become invalid, the TMS380C26 enters the slow clock mode, which prevents latchup of the TMS380C26. If the SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and then the TMS380C26 is placed in slow clock mode.

When the TMS380C26 enters the slow clock mode, the clock that failed is replaced by a slow free-running clock and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the TMS380C26 must be re-initialized.

Using DMA, a continuous transfer rate of 64 Mbits per second (Mbps), which is 8 MBytes per second (MBps), can be obtained. For pseudo-DMA a continuous transfer rate of 48 Mbps (6 MBps) can be obtained when using a 16-MHz clock. The DIO transfer rate is not a significant issue, since the main purpose of DIO is for downloading and initialization. For comparison, the ISA bus continuous DMA transfer is rated for approximately 23 Mbps.

memory interface (MIF)

The Memory Interface (MIF) performs the memory management to allow the TMS380C26 to address 2 MBytes in local memory. Hardware in the MIF allows the TMS380C26 to be directly connected to DRAMs without additional circuitry. This glueless DRAM connection includes the DRAM refresh controller.

The MIF also handles all internal bus arbitration between these blocks. When required, the MIF then arbitrates for the external bus.

The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs, Burned-in Addresses (BIA), and External Devices are appropriately addressed when required by the System Interface (SIF), Protocol Handler (PH), or for a DMA transfer.

The memory interface is capable of a 64 Mbps continuous transfer rate when using a 4-MHz local bus (64-MHz device crystal).

protocol handler (PH)

The Protocol Handler (PH) performs the hardware-based realtime protocol functions for a token ring or Ethernet Local Area Network (LAN). Network type is determined by the test pins TEST0–2. Token ring network is determined by software and can be either 16-Mbps or 4-Mbps. These speeds are not fixed by the hardware, but by the software.

The (PH) converts the parallel transmit data to serial network data of the appropriate coding, and converts the received serial data to parallel data. The PH data management state machines direct the transmission/reception of data to/from local memory through the MIF. The PH’s buffer management state machines automatically oversee this process, directly sending/receiving linked-lists of frames without CPU intervention.

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The Protocol Handler contains many state machines which provide the following features:

• Transmit and receive frames

• Capture tokens (token ring)

• Provide token-priority controls (token ring)

• Automatic retry of frame transmissions after collisions (Ethernet)

• Implement the Random Exponential Backoff algorithm (Ethernet)

• Manage the TMS380C26 buffer memory

• Provide frame address recognition (group, specific, functional, and multicast)

• Provide internal parity protection

• Control and verify the physical layer circuitry interface signals

Integrity of the transmitted and received data is assured by cyclic redundancy checks (CRC), detection of network data violations, and parity on internal data paths. All data paths and registers are optionally parity-protected to assure functional integrity.

adapter support function (ASF)

The Adapter Support Function (ASF) performs support functions not contained in the other blocks. The features are:

• The TMS380C26 base timer,

• Identification, management, and service of internal and external interrupts,

• Test pin mode control, including the unit-in-place mode for board testing,

• Checks for illegal states, such as illegal opcodes and parity.

clock generator (CG)

The Clock Generator (CG) performs the generation of all the clocks required by the other functional blocks and the local memory bus clocks. This block also generates the reference clock to be sampled by the SIF to determine if the TMS380C26 needs to be placed into slow clock mode. This reference clock is free floating in the range of 10 – 100 kHz.

user-accessible hardware registers and TMS380C26-internal pointers

The following tables show how to access internal data via pointers and how to address the registers in the host interface. The SIFACL register, which directly controls device operation, is described in detail.

NOTE:

The Adapter-Internal Pointers Table is defined only after TMS380C26 initialization and until the OPEN command is issued.

These pointers are defined by the TMS380C26 software (microcode), and this table describes the release

1.00 and 2.x software.

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Adapter-Internal Pointers for Token-Ring

ADDRESS DESCRIPTION

>00.FFF8 >00.FFFA

>01.0A00 Pointer to burned-in address in chapter 1. >01.0A02 Pointer to software level in chapter 1. >01.0A04 Pointer to TMS380C26 addresses in chapter 1:

>01.0A06 Pointer to TMS380C26 parameters in chapter 1:

>01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1. >01.0A0A Pointer to LLC counters in chapter 1:

>01.0A0C Pointer to 4-/16-Mbps word flag. If zero, then 4 Mbps. If nonzero, then the adapter is set to run at 16-Mbps data rate. >01.0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1.

†

This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.

‡

This address valid only for microcode release 2.x.

‡

Pointer to software raw microcode level in chapter 0.

‡

Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0.

Pointer + 0 node address. Pointer + 6 group address. Pointer + 10 functional address.

Pointer + 0 physical drop number. Pointer + 4 upstream neighbor address. Pointer + 10 upstream physical drop number. Pointer + 14 last ring poll address. Pointer + 20 reserved. Pointer + 22 transmit access priority. Pointer + 24 source class authorization. Pointer + 26 last attention code. Pointer + 28 source address of the last received frame. Pointer + 34 last beacon type. Pointer + 36 last major vector. Pointer + 38 ring status. Pointer + 40 soft error timer value. Pointer + 42 ring interface error counter. Pointer + 44 local ring number. Pointer + 46 monitor error code. Pointer + 48 last beacon transmit type. Pointer + 50 last beacon receive type. Pointer + 52 last MAC frame correlator. Pointer + 54 last beaconing station UNA. Pointer + 60 reserved. Pointer + 64 last beaconing station physical drop number.

Pointer + 0 MAX_SAPs. Pointer + 1 open SAPs. Pointer + 2 MAX_STATIONs. Pointer + 3 open stations. Pointer + 4 available stations. Pointer + 5 reserved.

†

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Adapter-Internal Pointers for Ethernet

ADDRESS DESCRIPTION

>00.FFF8 >00.FFFA

>01.0A00 Pointer to burned-in address in chapter 1. >01.0A02 Pointer to software level in chapter 1. >01.0A04 Pointer to TMS380C26 addresses in chapter 1:

>01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1. >01.0A0A Pointer to LLC counters in chapter 1:

†

This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.

‡

This address valid only for microcode release 2.x.

‡

Software raw microcode level in chapter 0.

‡

Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0.

Pointer + 0 node address. Pointer + 6 group address. Pointer + 10 functional address.

Pointer + 0 MAX_SAPs. Pointer + 1 open SAPs. Pointer + 2 MAX_STATIONs. Pointer + 3 open stations. Pointer + 4 available stations. Pointer + 5 reserved.

†

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User-Access Hardware Registers

808x 16-Bit Mode: (SI/M = 1, S8/SHALT = 0)

Word Transfers

Byte Transfers

SRSX SRS0 SRS1

000 001 010 011 100 101 110 111

†

(SBHE = 1 and SRS2 = 1 is not defined)

808x 8-Bit Mode: (SI/M = 1, S8/SHALT = 1)

SRSX SRS0 SRS1 SRS2

00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1

SBHE = 0 SBHE = 1 SRS2 = 1 SRS2 = 0

SIFDAT MSB SIFDAT LSB SIFDAT/INC MSB SIFDAT/INC LSB SIFADR MSB SIFADR LSB SIFCMD SIFSTS SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

†

Normal Mode

SBHE = 0 SRS2 = 0

Normal

SBHE = X

SIFDAT LSB SIFDAT MSB SIFDAT/INC LSB SIFDAT/INC MSB SIFADR LSB SIFADR MSB SIFSTS SIFCMD SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Pseudo-DMA Mode Active

SBHE = 0

SRS2 = 0

SBHE = 0 SBHE = 1 SRS2 = 1 SRS2 = 0

— SDMADAT DMALEN MSB DMALEN LSB SDMAADR MSB SDMAADR LSB SDMAADX MSB SDMAADX LSB SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

Pseudo-DMA

SBHE = X

SDMADAT — DMALEN LSB DMALEN MSB SDMAADR LSB SDMAADR MSB SDMAADX LSB SDMAADX MSB SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB

68xxx Mode: (SI/M = 0)

‡

Word Transfers

Byte Transfers

SRSX SRS0 SRS1

000 001 010 011 100 101 110 111

‡

68xxx Mode is always 16-bit.

Normal Mode

SUDS = 0

= 0

SLDS

SUDS = 0 SUDS = 1 SLDS = 1 SLDS = 0

SIFDAT MSB SIFDAT LSB SIFDAT/INC MSB SIFDAT/INC LSB SIFADR MSB SIFADR LSB SIFCMD SIFSTS SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

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Pseudo-DMA Mode Active

SUDS = 0

= 0

SLDS

SUDS = 0 SUDS = 1 SLDS = 1 SLDS = 0

— SDMADAT DMALEN MSB DMALEN LSB SDMAADR MSB SDMAADR LSB SDMAADX MSB SDMAADX LSB SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

SIF Adapter Control Register (SIFACL)

The SIFACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control.

SIFACL Register

Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

S T 0

R R R RP – 0 R –u R – 0 RS –0 RW – 0 RP –b RP –b R RW –1 RP –p RP-0 RP–1

— SWHLDA SWDDIR SWHRQ PSDMAEN ARESET CPHALT BOOT RES0 SINTEN PEN

R = Read, W = Write, P = Write during ARESET = 1 only, S = Set Only, –n = Value after reset (b = V alue on BTSTRP pin, p = Value on PRTYEN pin, u = Indeterminate)

Bits 0-2: TEST (0–2). Value on TEST (0–2) pins.

These bits are read only and always reflect the value on the corresponding device pins. This allows the host S/W to determine the network type and speed configuration. If the network speed and type are software configurable, these bits can be used to determine which configurations are supported by the network hardware.

NSEL OUT0

NSEL OUT1

TEST0 TEST1 TEST2 Description

L L H Reserved

L H H 16 Mbps token ring H L H Ethernet (802.3/Blue Book) H H H 4 Mbps token ring

X X 0 Reserved

Bit 3: Reserved. Read data is indeterminate.

Bit 4: SWHLDA — Software Hold Acknowledge

This bit allows the SHLDA/SBGR pin’s function to be emulated from software control for pseudo-DMA.

PSDMAEN SWHLDA SWHRQ RESULT

†

The value on the SHLDA/SBGR pin is ignored.

X X SWHLDA value in the SIFACL register cannot be set to a one. 0 0 No pseudo-DMA request pending. 0 1 Indicates a pseudo-DMA request interrupt. 1 X Pseudo-DMA process in progress.

Bit 5: SWDDIR — Current SDDIR Signal Value

This bit contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software.

0 = Pseudo-DMA from host system to TMS380C26. 1 = Pseudo-DMA from TMS380C26 to host system.

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Bit 6: SWHRQ — Current SHRQ Signal Value

This bit contains the current value on the SHRQ/SBRQ pin when in Intel mode, and the inverse of the SHRQ/SBRQ pin when in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is requested.

INTEL MODE (SI/M pin = H) MOTOROLA MODE (SI/M pin = L) 0 = System bus not requested System bus not requested 1 = System bus requested System bus requested

Bit 7: PSDMAEN — Pseudo-System-DMA Enable

This bit enables pseudo-DMA operation 0 = Normal bus master DMA operation possible.

1 = Pseudo-DMA operation selected. Operation dependent on the values of the SWHLDA

and SWHRQ bits in the SIFACL register.

Bit 8: ARESET — Adapter Reset

This bit is a hardware reset of the TMS380C26. This bit has the same effect as the SRESET pin, except that the DIO interface to the SIFACL register is maintained. This bit will be set to one if a clock failure is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).

0 = The TMS380C26 operates normally. 1 = The TMS380C26 is held in the reset condition.

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Bit 9: CPHALT — Communications Processor Halt

This bit prevents the TMS380C26’s processor from accessing the internal TMS380C26 buses. This prevents the TMS380C26 from executing instructions before the microcode has been downloaded.

0 = The TMS380C26’s processor can access the internal TMS380C26 buses. 1 = The TMS380C26’s processor is prevented from accessing the internal adapter buses.

Bit 10: BOOT — Bootstrap CP Code

This bit indicates whether the memory in chapters 0 and 31 of the local memory space is RAM or ROM/PROM/EPROM. This bit then controls the operation of the MCAS

0 = ROM/PROM/EPROM memory in chapters 0 and 31. 1 = RAM memory in chapters 0 and 31.

Bit 11: RES0 — Reserved. This bit must be set to zero

and MROMEN pins.

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Bit 12: SINTEN — System-Interrupt Enable

This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26. The system interrupt request from the TMS380C26 is on the SINTR/SIRQ pin. The following equation shows how the SINTR/SIRQ pin is driven. The table also explains the results of the states.

SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT)

PSDMAEN SWHRQ SWHLDA SINTEN

†

X X X 1 1

0 X X 1 0

0 X X 0 X

†

The value on the SHLDA/SBGR pin is ignored.

1 1 X X Pseudo-DMA is active. 1 0 X X 0 0 X X Not a pseudo-DMA interrupt.

SYSTEM

INTERRUPT

(SIFSTS Reg.)

RESULT

The TMS380C26 generated a system interrupt for a pseudo-DMA.

The TMS380C26 will generate a system interrupt.

The TMS380C26 will not generate a system interrupt.

The TMS380C26 can not generate a system interrupt.

Bit 13: PEN — Adapter Parity Enable

This bit determines whether data transfers within the TMS380C26 are checked for parity. 0 = Data transfers are not checked for parity

1 = Data transfers are checked for correct odd parity.

Bit 14 — 15: NSELOUT (0–1) — Network selection outputs.

The values in these bits control the output pins NSELOUT0 and NSELOUT1. These bits can only be modified while the ARESET bit is set.

These bits can be used to software configure a multi-protocol TMS380C26, as follows: The NSELOUT0 and NSELOUT1 pins should be connected to TEST0 and TEST1 pins

respectively (TEST2 should be left unconnected or tied high). NSELOUT0 should be used to select network speed and NSELOUT1 network type, as shown in the table below:

NSELOUT0 NSELOUT1

0 0 Reserved 0 1 16 Mbps token ring 1 0 Ethernet (802.3/Blue Book)

1 1 4 Mbps token ring

At power-up these bits are set NSELOUT1 = 1, NSELOUT0 = 0 corresponding to 16 Mbps token ring.

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+ 64 hidden pages

Texas Instruments TMS380C26 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual