Texas Instruments TMS380C26 User Manual

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

• IEEE 802.5 and IBM Token-Ring Network

Compatible

• IEEE 802.3 and Blue Book Ethernet

Network Compatible

• Pin and Software Compatible With the

TMS380C16

• Configurable Network Type and Speed:

– Selectable by Host Software Control

(Adapter Control Register) – Selectable by Network Front-End – Readable from Host (Adapter Control

• Token-Ring Features

– 16- or 4-Megabit-per-Second Data Rates – Supports up to 18K-Byte Frame Size

(16 Mbps Operation Only) – Supports Universal and Local Network

Addressing – Early Token Release Option (16 Mbps

Operation Only) – Compatible With the TMS38054

• Ethernet Features

– 10-Megabit-per-Second Data Rate – Compatible With Most Ethernet Serial

Network Interface Devices – Full Duplex Ethernet Operation Allows

Network Speed Self-test

• Expandable Local LAN Subsystem Memory

Space up to 2 Megabytes

• Supports Multicast Addressing of Network

Group Addresses Through Hashing

• Glueless Interface to DRAMs

• High-Performance 16-Bit CPU for

Communications Protocol Processing

• Up to 8 Megabyte-per-Second High-Speed

Bus Master DMA Interface

network commprocessor applications diagram

• Low-Cost Host-Slave I/O Interface Option

• Up to 32-Bit Host Address Bus

• Selectable Host System Bus Options

• 80x8x or 68xxx-Type Bus and Memory

Organization – 8- or 16-Bit Data Bus on 80x8x Buses – Optional Parity Checking

• Dual-Port DMA and Direct I/O Transfers to

Host Bus

• Specification for External Adapter-Bus

Devices (SEADs) Supports External Hardware Interface for User-Defined External Logic

• Enhanced Address Copy Option (EACO)

Interface Supports External Address Checking Logic for Bridging or External Custom Applications

• Support for Module High-Impedance

In-Circuit Testing

• Built-in Real-Time Error Detection

• Bring-Up and Self-Test Diagnostics With

Loopback

• Automatic Frame Buffer Management

• Slow-Clock Low-Power Mode

• Single 5-V Supply

• 1-µm CMOS Technology

• 250 mA Typical Latch-Up Immunity at 25°C

• ESD Protection Exceeds 2,000 V

• 132-Pin JEDEC Plastic Quad Flat Package

(PQ Suffix)

• Operating Temperature Range

0°C to 70 °C

Attached

System

Bus

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

LAN Subsystem

Token Ring or

TMS380C26

Memory

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Ethernet Physical

Layer Circuitry

77251–1443

Transmit

To Network

Receive

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

pinout

The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1.

132-PIN QUAD FLAT PACK

(TOP VIEW)

SSL

DDL

CLKDIV

SSC

NSELOUT0

PRTYEN

BTSTRP

SIACK

SRESET

SRS1 SRS0 SRSX

SCS SBRLS SBBSY

S8/SHALT

SRS2/SBERR

DDL

SI/M

SINTR/SIRQ

SHLDA/SBGR

SDDIR

SRAS/SAS

SWR/SLDS

SSI

SXAL SALE

SBCLK

SADL7 SADL6 SADL5 SADL4 SADL3

DD5

DD4

NMI

EXTINT014EXTINT113EXTINT2

EXTINT3

MADL010MADL19MADL28MADL37MADL46MADL55MADL64MADL73MAXPL

16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

515253545556575859696162636465666768697071727374757677787980818283

SS4

MBGR

MBGQ

MAXPH

MADH0

132

131

130

129

MADH1

MADH2

128

127

SS3

MADH3

126

125

DD3

124

MADH4

MADH5

123

122

MADH6

MADH7

121

120

MBEN

MOE

119

118

SS1

117 116

115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 80 89 88 87 86 85 84

SSC

MRAS MW MCAS MAX2 MAX0 MDDIR V

DD2

SYNCIN OSCIN V

SS2

MROMEN MACS MAL MREF MBIAEN V

DDL

MRESET MBCLK2 MBCLK1 OSCOUT RCVR/RXD RCLK/RXC NSETOUT1 PXTALIN/TXC V

SS1

WRAP

/TXEN DRVR DRVR WFLT/COLL

/LPBK

NSRT FRAQ/TXD REDY

/CRS

SS5

SADL2

SADL1

SPL

SADL0

SOWN

SDBEN

SHRQ/SBRQ

SBHE/SRNW

SPH

SRD/SUDS

SRDY/SDTACK

SADH7

SADH6

SSC

DD6

SS6

SADH5

SADH4

SADH3

SADH2

SADH1

SADH0

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

XFAIL

XMATCH

DD1

SSL

Figure 1. TMS380C26 Pinout

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

description

The TMS380C26 is a single-chip network communications processor (commprocessor) that supports token ring, or Ethernet Local Area Networks (LANs). Either token ring at data rates of 16 Mbps or 4 Mbps, or Ethernet at a data rate of 10 Mbps, can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN subsystems which support both token ring and Ethernet networks, by electrically or physically switched network front-end circuits.

The TMS380C26 conforms to IEEE 802.5–1989 standards and has been verified to be completely IBM



Token-Ring compatible. By integrating the essential control building blocks needed on a LAN subsystem card into one device, the TMS380C26 can ensure that this IBM compatability is maintained in silicon.

The TMS380C26 conforms to ISO/IEC 8802–3 (ANSI/IEEE Std 802.3) CSMA/CD standards, and the Ethernet ”Blue Book” standard.

The high degree of integration of the TMS380C26 makes it a virtual LAN subsystem on a single chip. Protocol handling, host system interfacing, memory interfacing, and communications processing are all provided through the TMS380C26. T o complete LAN subsystem design, only the network interface hardware, local memory , and minimal additional components such as PALs and crystal oscillators need to be added.

The TMS380C26 provides a 32-bit system memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TMS380C26 supports direct I/O and a low-cost 8-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally , selectable 80x8x or 68xxx-type host system bus and memory organization add to design flexibility .

The TMS380C26 supports addressing for up to two Megabytes of local memory. This expanded memory capacity can improve LAN subsystem performance by minimizing the frequency of host LAN subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host.

The proprietary CPU used in the TMS380C26 allows protocol software to be downloaded into RAM or stored in ROM in the local memory space. By moving protocols (such as LLC) to the LAN subsystem, overall system performance is increased. This is accomplished due to the the offloading of processing from the host system to the TMS380C26, which may also reduce LAN subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance will be possible.

In addition, the TMS380C26 includes hardware counters that provide realtime error detection and automatic frame buffer management. These counters control system bus retries, burst size, and track host and LAN subsystem buffer status. Previously , these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN subsystem performance is improved.

The TMS380C26 implements a TI-patented Enhanced Address Copy Option (EACO) interface. This interface supports external address checking devices, such as the TMS380SRA Source Routing Accelerator. The TMS380C26 has a 128-word external I/O space in its memory map to support external address-checker devices and other hardware extensions to the TMS380 architecture. Hardware designed in conformance with TI’s Specification for External Adapter-bus Devices (SEADs) can map registers into this external I/O space and post interrupts to the TMS380C26.

The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF) as shown in Figure 2.

The TMS380C26 is available in a 132-pin JEDEC plastic quad flat pack and is rated from 0°C to 70°C.

IBM is a registered trademark of International Business Machines Corporation.

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

block diagram and signal descriptions

TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical layer circuitry. As a rule of thumb in the pin nomenclature and descriptions that follow, pin names starting with the letter S attach to the host system bus and pin names starting with the letter M attach to the local memory bus. Active-low signals have names with overbars, e.g., SCS

SADH0

SADH7

SADL0

SADL7

SPH

SPL

SBRLS

SINTR/SIRQ

SDDIR

SDBEN

SALE

SXAL SOWN SIACK

SBCLK

/SUDS

SRD

SWR/SLDS

SRDY/SDTACK

SHLDA/SBGR

SBHE/SRNW

SRS2/SBERR

SHRQ/SBRQ

SI/M

SRAS/SAS

S8/SHALT

SRESET

SRS0

SRS1

SCS

SRSX

SBBSY

BTSTRP

PRTYEN

NSELOUT0 NSELOUT1

System

Interface

(SIF)

• DIO Control

• Bus Control

• DMA Control

Communications

Processor

Memory

Interface

(MIF)

• DRAM Refresh

• Local Bus

Arbitrator

• Local Bus

Control

• Local Parity Check/

Generator

Clock

Generator

(CG)

Adapter Support

Function

(ASF)

• Interrupts

• Test Function

MADH0

MADH7 MADL0

MADL7 MRAS

MCAS MAXPH MAXPL MW MOE MDDIR MAL MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF

OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV

NMI EXTINT0

EXTINT

TEST0

TEST5

XMATCH XFAIL

RCLK/RXC

/CRS

REDY

WFLT

/COLL

RCVR/RXD

PXTALIN/TXC

Protocol Handler (PH):

for Token Ring and

Ethernet Interface

FRAQ/TXD

/LPBK

NSRT WRAP

/TXEN DRVR DRVR

Figure 2. TMS380C26 COMMprocessor Block Diagram

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Terminal Functions

PIN NAME NO. I/O DESCRIPTION

Bootstrap. The value on this pin is loaded into the BOOT bit of the SIFACL register at reset (i.e., when the SRESET This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters

BTSTRP 23 IN

CLKDIV 19 IN

EXTINT0 EXTINT1 EXTINT2 EXTINT3

MACS 104 IN Reserved. Must be tied low (see Note 2). MADH0

MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7

MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7

MAL 103 OUT

14 13 12 11

129 128 127 126 123 122 121 120

9 8 7 6 5 4 3

IN Reserved; must be pulled high (see Note 4).

I/O

are RAM then the TMS380C26 is denied access to the local memory bus until the CPHALT bit in the SIFACL register is cleared.

H = Chapters 0 and 31 of local memory are RAM-based (see Note 1). L = Chapters 0 and 31 of local memory are ROM-based.

Clock Divider Select. This pin must be pulled high

H = Indicates 64-MHz OSCIN (see Note 3). L = Reserved.

Local memory Address, Data and Status Bus – high byte. For the first quarter of the local memory cycle these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0 and the least significant bit is MADH7.

Signal AX4,A0–A6 Status D0–D7 D0–D7 Local Memory Address, Data and Status Bus – low byte. For the first quarter of the local memory

cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4 and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant bit is MADL0 and the least significant bit is MADL7.

Signal A7–A14 AX4,A0–A6 D8–D15 D8–D15 Memory Address Latch. This is a strobe signal for sampling the address at the start of the memory

cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH, MAX2, MAXPL, MADH0-MADH7, and MADL0-MADL7. Three 8-bit transparent latches can therefore be used to retain a 20-bit static address throughout the cycle.

pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value.

Memory Cycle

2Q 3Q 4Q

Memory Cycle

2Q 3Q 4Q

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Rising edge = No signal latching. Falling edge = Allows the above address signals to be latched.

Local Memory Extended Address Bit. This signal drives AX0 at ROW address time and it drives A12 at COL address and DAT A time for all cycles. This signal can be latched by MRAS

MAX0 111 OUT

MAX2 112 OUT

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

2. Pin should be connected to ground.

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

4. Each pin must be individually tied to VCC with a 1.0-kΩ pullup resistor.

interfacing to a BIA ROM.

Signal AX0 A12 A12 A12

Local Memory Extended Address Bit. This signal drives AX2 at ROW address time, which can be latched by MRAS interfacing to a BIA ROM.

Signal AX2 A14 A14 A14

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, and A14 at COL address, and DATA time for all cycles. Driving A14 eases

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Memory Cycle 2Q 3Q 4Q

. Driving A12 eases

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Local Memory Extended Address and Parity High Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX1); for the second quarter of a memory cycle this signal carries the extended address bit (AX0); and for the last half of the memory cyle this signal carries the

MAXPH 130 I/O

MAXPL 2 I/O

MBCLK1 MBCLK2

MBEN 119 OUT

MBGR 132 OUT Reserved. Must be left unconnected.

MBIAEN 101 OUT

MBRQ 131 IN Reserved. Must be pulled high (see Note 4).

97 98

OUT

parity bit for the high data byte.

Signal AX1 AX0 Parity Parity

Local Memory Extended Address and Parity Low Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX3), for the second quarter of a memory cycle this signal carries extended address bit (AX2); and for the last half of the memory cycle this signal carries the parity bit for the low data byte.

Signal AX3 AX2 Parity Parity Local Bus Clock1 and local Bus Clock 2. These signals are referenced for all local bus transfers.

MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate at 8 MHz for a 64-MHz OSCIN and 6 MHz for a 48-MHz OSCIN, which is twice the memory cycle rate. The MBCLK signals are always a divide-by-8 of the OSCIN frequency.

Buffer Enable. This signal enables the bidirectional buf fer outputs on the MADH, MAXPH, MAXPL, and MADL buses during the data phase. This signal is used in conjunction with MDDIR which selects the buffer output direction.

H = Buffer output disabled. L = Buffer output enabled.

Burned-In Address Enable. This is an output signal used to provide an output enable for the ROM containing the adapter’s Burned-In Address (BIA).

H = This signal is driven high for any WRITE accesses to the addresses between >00.0000 and

>00.000F, or any accesses (Read/Write) to any other address.

L = This signal is driven low for any READ from addresses between >00.0000 and >00.000F .

Column Address Strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle following the row address portion of the cycle. This signal is driven low every memory cycle while the column address is valid on MADL0-MADL7, MAXPH, and MAXPL, except when one of the following conditions occurs:

Memory Cycle

2Q 3Q 4Q

Memory Cycle

2Q 3Q 4Q

1) When the address accessed is in the BIA ROM (>00.0000 – >00.000F).

MCAS 113 OUT

MDDIR 110 OUT

NOTE 4: Each pin must be individually tied to VCC with a 1.0-kΩ pullup resistor.

2) When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in the SIFACL register is zero and an access is made between >00.0010 – >00.FFFF) or >1F.0000 – >1F.FFFF).

3) When the cycle is a refresh cycle, in which case MCAS MRAS

(for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CASbefore-RAS cycle.

Data Direction. This signal is used as a direction control for bidirectional bus drivers. The signal becomes valid before MBEN

H = TMS380C26 memory bus write. L = TMS380C26 memory bus read.

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refresh, it may be necessary to disable MCAS with MREF during the refresh

active.

77251–1443

is driven at the start of the cycle before

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Memory Output Enable. This signal is used to enable the outputs of the DRAM memory during a read cycle. This signal is high for EPROM or BIA ROM read cycles.

MOE 118 OUT

MRAS 115 OUT

MREF 102 OUT

MRESET 99 OUT

MROMEN 105 OUT

H = Disable DRAM outputs. L = Enable DRAM outputs.

Row Address Strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. This signal is driven low every memory cycle while the row address is valid on MADL0-MADL7, MAXPH, and MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh address is valid on MADL0-MADL7.

DRAM Refresh Cycle in Progress. This signal is used to indicate that a DRAM refresh cycle is occurring. It is also used for disabling MCAS

H = DRAM refresh cycle in process. L = Not a DRAM refresh cycle.

Memory Bus Reset. This is a reset signal generated when either the ARESET bit in the SIFACL register is set or the SRESET logic.

H = External logic not reset. L = External logic reset.

ROM Enable. During the first 5/16 of the memory cycle, this signal is used to provide a chip select for ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not RAM). It can be latched by MA >1F .0000 – >1F .FFFF when the Boot bit in the SIFACL register is zero. It stays high for writes to these addresses, accesses of other addresses, or accesses of any address when the BOOT bit is one. During the final three quarters of the memory cycle, it outputs the A13 address signal for interfacing to a BIA ROM. This means MBIAEN for the BIA ROM.

pin is asserted. This signal is used for resetting external local bus glue

L. It goes low for any read from addresses >00.0010 – >00.FFFF or

to all DRAMs that do not use a CAS before-RAS refresh.

, MAX0, ROMEN, and MAX2 together form a glueless interface

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

H = ROM disabled. L = ROM enabled.

Local Memory Write. This signal is used to specify a write cycle on the local memory bus. The data on the MADH0-MADH7 and MADL0-MADL7 buses is valid while MW

MW 114 OUT

NMI 15 IN Non-Maskable Interrupt Request. This pin must be left unconnected. OSCIN 107 IN

OSCOUT 96 OUT

NOTE 5: Pin has an expanded input voltage specification.

the falling edge MW

H = Not a local memory write cycle. L = Local memory write cycle.

External Oscillator Input. This line provides the clock frequency to the TMS380C26 for a 4-MHz internal bus. OSCIN should be 64 a MHz signal (see Note 5).

Oscillator Output. With OSCIN at 64 MHz and CLKDIV pulled high, this pin provides an 8 MHz output which can be used by TMS3054 for 4 Mbps operation without the need for an additional crystal.

CLKDIV OSCOUT

L Reserved (Reserved) H OSCIN/8 (if OSCIN = 64 MHz, then OSCOUT = 8 MHz).

, while SRAMs latch data on the rising edge of MW.

is low. DRAMs latch data on

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Parity Enable. The value on this pin is loaded into the PEN bit of the SIFACL register at reset (i.e., when the SRESET

PRTYEN 22 IN

NSELOUT0 NSELOUT1

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

21 93

OUT OUT

value. This bit enables parity checking for the local memory.

H = Local memory data bus checked for parity (see Note 1). L = Local memory data bus

Network Selection Outputs. These output signals are controlled by the host through the corresponding bits of the SIFACTL register. The value of these bits/signals can only be changed while the TMS380C26 is reset.

pin is asserted or the ARESET bit in the SIFACL register is set) to form a default

NOT

checked for parity.

NSELOUT0 NSELOUT1 Description

L L Reserved

L H 16 Mbps token ring H L Ethernet (802.3/Blue Book) H H 4 Mbps token ring

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NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7

SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7

SALE 43 OUT

SBBSY 31 IN

SBCLK 44 IN

SBHE/SRNW 57 I/O

SBRLS

SCS 29 IN

SDBEN 58 OUT

†

Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

73 72 71 70 69 68 64 63

54 53 52 49 48 47 46 45

30 IN

I/O

System Address/Data Bus—high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADH0, and the least significant bit is SADH7.

Address Multiplexing†: Bits 31 – 24 and bits 15 – 8. Data Multiplexing†: Bits 15 – 8.

System Address/Data Bus—low byte (see Note 1). These lines make up the least significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0, and the least significant bit is SADL7.

Address Multiplexing†: Bits 23 – 16 and bits 7 – 0. Data Multiplexing†: Bits 7 – 0.

System Address Latch Enable. This is the enable pulse used to externally latch the 16 LSBs of the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched address.

System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has one of (2) two values (see Note 1):

H = Not busy. The TMS380C26 may become Bus Master if the grant condition is met. L = Busy. The TMS380C26 cannot become Bus Master.

System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for all DMA transfers.

System Byte High Enable. This pin is a three-state output that is driven during DMA and an input at all other times.

H = System Byte High not enabled (see Note 1). L = System Byte High enabled.

System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is signal is internally synchronized to SBCLK.

H = The TMS380C26 can hold onto the system bus (see Note 1). L = The TMS380C26 should release the system bus upon completion of current DMA cycle. If the

DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.

System Chip Select. Activates the system interface of the TMS380C26 for a DIO read or write.

H = Not selected (see Note 1). L = Selected.

System Data Bus Enable. This output signals to the external data buffers to begin driving data. This output is activated during both DIO and DMA.

H = Keep external data buffers in high-impedance state. L = Cause external data buffers to begin driving data.

NOT

TMS380C26

perfoming DMA. This

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TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

System Data Direction. This output provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the

SDDIR 38 OUT

SHLDA/SBGR 37 IN

SHRQ/SBRQ 56 OUT

SIACK 24 IN

TMS380C26). When the system interface is high by default.

DATA

SDDIR

System Hold Acknowledge. This pin indicates that the system DMA hold request has been acknowledged. It is internally synchronized to SBCLK (see Note 1). H = Hold request acknowledged. L = Hold request not acknowledged.

System Hold Request. This pin is used to request control of the system bus in preparation for a DMA transfer. This pin is internally synchronized to SBCLK.

H = System bus requested. L = System bus not requested.

System Interrupt Acknowledge. This signal is from the host processor to acknowledge the interrupt request from the TMS380C26.

H = System interrupt not acknowledged (see Note 1). L = System interrupt acknowledged: the TMS380C26 places its interrupt vector onto the system

bus.

System Intel/Motorola Mode Select. The value on this pin specifies the system interface mode.

DIRECTION DIO DMA

H output read write

L input write read

NOT

involved in a DIO or DMA operation, then SDDIR is

SI/M 35 IN

SINTR/SIRQ 36 OUT

SOWN 59 OUT

SPH 62 I/O

SPL 55 I/O

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

H = Intel-compatible interface mode selected. Intel interface can be 8-bit or 16-bit mode

(see S8/SHALT

L = Motorola-compatible interface mode selected. System Interrupt Request. TMS380C26 activates this output to signal an interrupt request to the host

processor.

H = Interrupt request by TMS380C26. L = No interrupt request.

System Bus Owned. This signal indicates to external devices that TMS380C26 has control of the system bus. This signal drives the enable signal of the bus transceiver chips, which drive the address and bus control signals.

H = TMS380C26 does not have control of the system bus. L = TMS380C26 has control of the system bus.

System Parity High. The optional odd-parity bit for each address or data byte transmitted over SADH0-SADH7 (see Note 1).

System Parity Low. The optional odd-parity bit for each address or data byte transmitted over SADL0-SADL7 (see Note 1).

pin description and Note 1.)

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Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

System Memory Address Strobe (see Note 3). This pin used to latch the SCS, SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied to the SALE output of the System Bus. The latching capability can be defeated since the internal latch for these inputs remains transparent as long as SRAS remains high. This permits SRAS to be pulled high and the signals at the SCS

SRAS/SAS 39 I/O

SRSX – SRS2, and SBHE During DMA this pin remains an input.

to be applied independently of the SALE strobe from the system bus.

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High = transparent mode Low = Holds latched values of SCS Falling edge = latches SCS, SRSX – SRS2, and SBHE

System Read Strobe (see Note 3). Active-low strobe indicating that a read cycle is performed on the system bus. This pin is an input during DIO and an output during DMA.

SRD/SUDS 61 I/O

SRDY/SDTACK 60 I/O

SRESET 25 IN

SRSX SRS0 SRS1 SRS2/SBERR

SWR/SLDS 40 I/O

SXAL 42 OUT

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

28 27 26 33

H = Read cyle is not occurring. L = If DMA: host provides data to system bus.

If DIO: SIF provides data to system bus.

System Bus Ready (see Note 3).The purpose of this signal is to indicate to the bus master that a data transfer is complete. This signal is asynchonous, but during DMA and pseudo-DMA cycles it is internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26 is selected for DIO, and an input otherwise.

H = System bus NOT ready. L = Data transfer is complete; system bus is ready.

System Reset. This input signal is activated to place the TMS380C26 into a known initial state. Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the reset state. DMA bus width selection is latched on the rising edge of SRESET

H = No system reset. L = System reset. Rising edge = Latch bus width for DMA operation.

System Register Select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS2 (see Note 1).

MSb

Registered selected = SRSX SRS0 SRS1 SRS2/SBERR System Write Strobe (see Note 3). This pin serves as an active-low write strobe. This pin is an input

during DIO and an output during DMA.

H = Write cycle is not occurring. L = If DMA: data to be drivien from SIF to host bus.

If DIO: on the rising edge, the data is latched and written to the selected register.

System Extended Address Latch. This output provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry-out of the lower 16 bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.

, SRSX–SRS2, and SBHE

LSb

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Terminal Functions (continued)

System Interface – Intel Mode (SI/M =H)

PIN NAME NO. I/O DESCRIPTION

SYNCIN 108 IN Reserved. This signal must be left unconnected (see Note 1).

System 8/16-bit bus select. This pin selects the bus width used for communications through the system interface. On the rising edge of SRESET

S8/SHALT 32 IN

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

otherwise the value on this pin dynamically selects the DIO bus width.

H = Selects 8-bit mode (see Note 1). L = Selects 16-bit mode.

, the TMS380C26 latches the DMA bus width;

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System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7

SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7

SALE 43 OUT

SBBSY 31 IN

SBCLK 44 IN

SBHE/SRNW 57 I/O

SBRLS

SCS 29 IN

SDBEN 58 OUT

†

Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

73 72 71 70 69 68 64 63

54 53 52 49 48 47 46 45

30 IN

I/O

Address Multiplexing†: Bits 31 – 24 and bits 15 – 8. Data Multiplexing†: Bits 15 – 8.

Address Multiplexing†: Bits 23 – 16 and bits 7 – 0. Data Multiplexing†: Bits 7 – 0.

System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has one of (2) two values (see Note 1):

H = Not busy. The TMS380C26 may become Bus Master if the grant condition is met. L = Busy. The TMS380C26 cannot become Bus Master.

System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for all DMA transfers.

System Read Not Write. This pin serves as a control signal to indicate a read or write cycle.

H = Read Cycle (see Note 1). L = Write Cycle

H = The TMS380C26 can hold onto the system bus (see Note 1). L = The TMS380C26 should release the system bus upon completion of current DMA cycle. If the

DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.

System Chip Select. Activates the system interface of TMS380C26 for a DIO read or write.

H = Not selected (see Note 1). L = Selected.

System Data Bus Enable. This output signals to the external data buffers to begin driving data. This output is activated during both DIO and DMA.

H = Keep external data buffers in high-impedance state. L = Cause external data buffers to begin driving data.

=L)

NOT

perfoming DMA. This

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Terminal Functions (continued)

System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

SDDIR 38 OUT

SHLDA/SBGR 37 IN

SHRQ/SBRQ 56 OUT

SIACK 24 IN

SI/M 35 IN

SINTR/SIRQ 36 OUT

SOWN 59 OUT

SPH 62 I/O

SPL 55 I/O

SRAS/SAS 39 I/O

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

SDDIR is high by default.

SDDIR

H output read write

L input write read

System Bus Grant. This pin serves as an active-low bus grant, as defined in the standard 68000 interface, and is internally synchronized to SBCLK (see Note 1).

H = System bus not granted, L = System bus granted.

System Bus Request. This pin is used to request control of the system bus in preparation for a DMA transfer. This pin is internally synchronized to SBCLK.

H = System bus not requested. L = System bus requested.

System Interrupt Acknowledge. This signal is from the host processor to acknowledge the interrupt request from the TMS380C26.

H = System interrupt not acknowledged (see Note 1). L = System interrupt acknowledged: the TMS380C26 places its interrupt vector onto the system

bus.

System Intel/Motorola Mode Select. The value on this pin specifies the system interface mode.

H = Intel-compatible interface mode selected. L = Motorola-compatible interface mode selected. Motorola interface mode is always 16 bits.

System Interrupt Request. TMS380C26 activates this output to signal an interrupt request to the host processor.

H = No interrupt request. L = Interrupt request by TMS380C26.

H = TMS380C26 does not have control of the system bus. L = TMS380C26 has control of the system bus.

System Parity High. The optional odd-parity bit for each address or data byte transmitted over SADH0-SADH7 (see Note 1).

System Parity Low. The optional odd-parity bit for each address or data byte transmitted over SADL0-SADL7 (see Note 1).

Sytem Memory Address Strobe (see Note 3). This pin is an active-low address strobe that is an input during DIO (although ignored as an address strobe) and an output during DMA.

H = Address not valid L = Address is valid and a transfer operation is in progress.

DATA

DIRECTION DIO DMA

=L)

NOT

involved in a DIO or DMA operation, then

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System Interface – Motorola Mode (SI/M

PIN NAME NO. I/O DESCRIPTION

Upper Data Strobe (see Note 3). This pin serves as the active-low upper data strobe. This pin is an input during DIO and an output during DMA.

SRD/SUDS 61 I/O

SRDY/SDTACK 60 I/O

SRESET 25 IN

SRSX SRS0 SRS1

SRS2/SBERR 33 IN

SWR/SLDS 40 I/O

SXAL 42 OUT

SYNCIN 108 IN Reserved. This signal must be left unconnected (see Note 1).

S8/SHALT 32 IN

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

3. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.

28 27 26

H = Not valid data on SADH0-SADH7 lines. L = Valid data on SADH0-SADH7 lines.

System Data Transfer Acknowledge (see Note 3). The purpopse of this signal is to indicate to the bus master that a data transfer is complete. This signal is internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26 is selected for DIO, and an input otherwise.

H = System bus NOT ready. L = Data transfer is complete; system bus is ready.

System Reset. This input is activated to place the adapter into a known initial state. Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the reset state.

H = No system reset. L = System reset.

System Register Select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS1 (see Note 1).

Register Selected = SRSX SRS0 SRS1 Bus Error. Corresponds to the bus error signal of the 68000 microprocessor. It is internally

synchronized to SBCLK. This input is driven low during a DMA cycle to indicate to the TMS380C26 that the cycle must be terminated. See Section 3.4.5.3 of the

Ring User’s Guide

Lower Data Strobe (see Note 3). This pin is an input during DIO and an output during DMA. This pin serves as the active-low lower data strobe.

H = Not valid data on SADL0-SADL7 lines. L = Valid data on SADL0-SADL7 lines.

System Extended Address Latch. This output provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry-out of the lower 16-bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.

System Halt/Bus Error Retry. If this signal is asserted along with bus errror (SBERR), the adapter will retry the last DMA cycle. This is the re-run operation as defined in the 68000 specification. The BERETRY counter is not decremented by SBERR the

TMS380 Second-Generation T oken Ring User’s Guide

MSb

(SPWU005) for more information (see Note 1).

=L)

LSb

TMS380 Second-Generation Token

when SHALT is asserted. See Section 3.4.5.3 of

(SPWU005) for more information.

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Terminal Functions (continued)

Network Media Interface – Token-Ring Mode (TEST1 = H, TEST2 = H)

PIN NAME NO. I/O DESCRIPTION

DRVR DRVR

FRAQ/TXD 85 OUT

NSRT/LPBK 86 OUT

PXTALIN/TXC 92 IN

RCLK/RXC 94 IN

RCVR/RXD 95 IN

REDY/CRS 84 IN

WFLT/COLL 87 IN

WRAP/TXEN 90 OUT

89 88

OUT

Differential Driver Data Output. These pins are the differential outputs that send the TMS380C16 transmit data to the TMS38054 for driving onto the ring transmit signal pair.

Frequency Acquisition Control. This TTL output determines the use of frequency or phase acquisition mode in the TMS38054.

H = Wide range. Frequency centering to PXTALIN by TMS38054. L = Narrow range. Phase-lock onto the incoming data (RCVINA and RCVINB) by the

TMS38054.

Insert Control Signal to the TMS38054. This TTL output signal enables the phantom driver outputs (PHOUTA and PHOUTB) of the TMS38054, through the watchdog timer, for insertion onto the Token-Ring.

Static High = Inactive, phantom current removed (due to watchdog timer) Static Low = Inactive, phantom current removed (due to watchdog timer) NSRT

Low and Pulsed High = Active, current output on PHOUTA and PHOUTB

Ring Interface Clock Frequency Control (see Note 5). At 16-Mbps ring speed, this input must be supplied a 32-MHz signal. At 4-Mbps ring speed, the input signal must be 8-MHz and may be the output from the OSCOUT pin.

Ring Interface Recovered Clock (see Note 5). This input signal is the clock recovered by the TMS38054 from the Token-Ring received data.

For 16-Mbps operation it is a 32-MHz clock. For 4-Mbps operation it is an 8-MHz clock.

Ring Interface Received Data (see Note 5). This input signal contains the data received by the TMS38054 from the token ring.

Ring Interface Ready. This input pin provides an indication of the presence of received data, as monitored by the TMS38054 energy detect capacitor.

H = Not ready. Ignore received data. L = Ready. Received data.

Wire Fault Detect. This signal is an input to the TMS380C16 driven by the TMS38054. It indicates a current imbalance of the TMS38054 PHOUTA and PHOUTB pins.

H = No wire fault detected. L = Wire fault detected.

Internal Wrap Select. This signal is an output from the TMS380C16 to the ring interface to activate an internal attenuated feedback path from the transmitted data (DRVR) to receive data (RCVR) signals for bring-up diagnostic testing. When active, the TMS38054 also cuts off the current drive to the transmission pair.

H = Normal ring operation. L = Transmit data drives receive data (loopback).

NOTE 5: Pin has an expanded input voltage specification.

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Terminal Functions (continued)

Network Media Interface – Ethernet Mode (TEST1 = L, TEST2 = H)

PIN NAME NO. I/O DESCRIPTION

DRVR DRVR

FRAQ/TXD 85 OUT

NSRT/LPBK 86 OUT

PXTALIN/TXC 92 IN

RCLK/RXC 94 IN

RCVR/RXD 95 IN

REDY/CRS 84 IN

WFLT/COLL 87 IN

89 88

OUT

These pins have no Ethernet function. In Ethernet Mode these pins are placed in their token ring reset state of DRVR = High, DRVR

Ethernet Transmit Data. This output signal provides the Ethernet physical layer circuitry with bit-rate from the TMS380C26. Data on this pin is output synchronously to the transmit clock TXC normally connected to the TXD pin of an Ethernet Serial Network Interface (SNI) chip.

Loopback. This enables loopback of Ethernet transmit data through the Ethernet (SNI) device to recieve data.

H = Wrap through the front end device L = Normal operation

Ethernet Transmit Clock. A 10 MHz clock input used to synchronize transmit data from the TMS380C26 to the Ethernet physical layer circuitry . This is a continuously running clock. It is normally connected to the TXC output pin of an Ethernet SNI chip (see Note 5).

Ethernet Receive Clock. A 10 MHz clock input used to synchronize received data from the Ethernet physical layer circuitry to the TMS380C26. This clock must be present whenever the CRS signal is active (although it can be held low for a maximum of 16 clock cycles after the rising edge of CRS). When the CRS signal is inactive it is permissable to hold this clock in a low phase. It is normally connected to the RXC output pin of an Ethernet Serial Network Interface (SNI) chip. The TMS380C26 requires this pin to be maintained in the low state when CRS

Ethernet Received Data. This input signal provides the TMS380C26 with bit rate network data from the Ethernet front end device. Data on this pin must be synchronous with the receive clock RXC. It is normally connected to the RXD pin of an Ethernet SNI chip (see Note 5).

Ethernet Carrier Sense. This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has network data present on the RXD pin. This signal is asserted high when the first bit of the frame is received and is deasserted after the last bit of the frame is received.

H = Receiving data. L = No data on network.

Ethernet Collision Detect. This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has detected a network collision. This signal must be present for at least two TXC clock cycles to ensure it is accepted by the TMS380C26. It is normally connected to the COLL pin of an Ethernet SNI chip. This signal can also be an indication of the SQE test signal.

= Low.

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. It is

is not asserted (see Note 5).

H = COLL detected by the SNI device. L = Normal operation.

Ethernet Transmit Enable. This output signal indicates to the Ethernet physical layer circuitry that bit-rate data is present on the TXD pin. This signal is output synchronously to the transmit clock TXC

WRAP/TXEN 90 OUT

NOTE 5: Pin has an expanded input voltage specification.

It is normally connected to the TXE pin of an Ethernet SNI chip.

H = Data line currently contains data to be transmitted. L = No valid data on TXEN.

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Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

Network Select inputs. These pins are used to select the network speed and type to be used by the TMS380C26. These inputs should only be changed during adapter reset.

TEST 0 TEST 1 TEST 2

TEST3 TEST4 TEST5

XFAIL 80 IN

XMATCH 81 IN

79 78 77

76 75 74

IN IN IN

TEST0

Test Pin Inputs. These pins should be left unconnected (see Note 1). Module-in-Place test mode is achieved by tying TEST 3 and TEST 4 pins to ground. In this mode, all TMS380C26 output pins are high impedance. Internal pullups on all TMS380C26 inputs will be disabled (except TEST3-TEST5 pins).

External Fail-to-Match signal. An enhanced address copy option (EACO) device uses this signal to indicate to the TMS380C26 that it should not copy the frame nor set the ARI/FCI in bits in a token ring frame due to an external address match.The ARI/FCI bits in a token ring frame may be set due to an internal address matched frame. If an enhanced address copy option (EACO) device is NOT used, then this pin must be left unconnected. This pin is ignored when CAF mode is enabled. See table given below in XMATCH pin description (see Note 1).

H = No address match by external address checker. L = External address checker armed state.

External Match signal. An enhanced address copy option (EACO) device uses this signal to indicate to the TMS380C26 to copy the frame and set the ARI/FCI bits in a token ring frame. If an enhanced address copy option (EACO) device is NOT used, then this pin must be left unconnected. This pin is ignored when CAF mode is enabled (see Note 1).

H = Address match recognized by external address checker. L = External address checker armed state.

TEST1 TEST2 Description

L L H Reserved

L H H 16 Mbps token ring H L H Ethernet (802.3/Blue Book) H H H 4 Mbps token ring

X X 0 Reserved

XMATCH

XFAIL Function

0 0 Armed (Processing frame data). 0 1 Do NOT externally match the frame. (XFAIL takes precedence) 1 0 COPY the frame. 1 1 Do NOT externally match the frame. (XFAIL takes precedence)

HI-Z HI-Z Reset state (adapter not initialized).

DDL

DD1

DD2

DD3

DD4

DD5

DD6

SSC

SSI

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

100

82 109 124

116

117

Positive supply voltage for digital logic. All VDD pins must be attached to the common system power supply plane.

Positive supply voltage for output buffers. All VDD pins must be attached to the common system power supply plane.

Ground reference for output buffers (clean ground). All VSS pins must be attached to the common system ground plane.

Ground reference for input buffers. All VSS pins must be attached to the common system ground plane.

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Terminal Functions (continued)

PIN NAME NO. I/O DESCRIPTION

V V

V V V V V

SSL SS1

SS2 SS3 SS4 SS5 SS6

91 106 125

1 51 67

IN Ground reference for digital logic. All VSS pins must be attached to the common system ground plane.

IN Ground connections for output buffers. All VSS pins must be attached to system ground plane.

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architecture

communications processor (CP)

The Communications Processor (CP) performs the control and monitoring of the other functional blocks in the TMS380C26. The control and monitoring protocols are specified by the software (downloaded or ROM-based)

local memory . Available protocols include:

• Media Access Control (MAC) software,

• Logical Link Control (LLC) software, (token ring version only), and

• Copy All Frames (CAF) software.

The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for pipelining of instructions. These features enhance the TMS380C26’s maximum performance capability to about 4 million instructions per second (MIPS), with an average of about 2.5 MIPS.

system interface (SIF)

The System Interface (SIF) performs the interfacing of the LAN subsystem to the host system. This interface may require additional logic depending on the application. The system interface can transfer information/data using any of these three methods:

• Direct Memory Access (DMA),

• Direct Input/Output (DIO), or

• Pseudo-Direct Memory Access (PDMA).

DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory . DIO’s main uses are for loading the software to local memory and for initializing the TMS380C26. DIO also allows command/status interrupts to occur to and from the TMS380C26.

The system interface can be hardware selected for either of two modes by use of the SI/M selected determines the memory organizations and control signals used. These modes are:

pin. The mode

• The Intel 80x8x families: 8-, 16-, and 32-bit bus members

• The Motorola 68000 microprocessor family: 16- and 32-bit bus members

The system interface supports host system memory addressing up to 32 bits (32-bit reach into the host system memory). This allows greater flexibility in using/accessing host system memory.

System designers are allowed to customize the system interface to their particular bus by:

• Programmable burst transfers or cycle-steal DMA operations

• Optional parity protection

These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.

The system interface hardware also includes features to enhance the integrity of the TMS380C26 and the data. These features do the following:

• Always internally maintain odd byte parity regardless if parity is disabled,

• Monitor for the presence of a clock failure.

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On every cycle the system interface compares all the system clocks to a reference clock. If any of the clocks become invalid, the TMS380C26 enters the slow clock mode, which prevents latchup of the TMS380C26. If the SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and then the TMS380C26 is placed in slow clock mode.

When the TMS380C26 enters the slow clock mode, the clock that failed is replaced by a slow free-running clock and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the TMS380C26 must be re-initialized.

Using DMA, a continuous transfer rate of 64 Mbits per second (Mbps), which is 8 MBytes per second (MBps), can be obtained. For pseudo-DMA a continuous transfer rate of 48 Mbps (6 MBps) can be obtained when using a 16-MHz clock. The DIO transfer rate is not a significant issue, since the main purpose of DIO is for downloading and initialization. For comparison, the ISA bus continuous DMA transfer is rated for approximately 23 Mbps.

memory interface (MIF)

The Memory Interface (MIF) performs the memory management to allow the TMS380C26 to address 2 MBytes in local memory. Hardware in the MIF allows the TMS380C26 to be directly connected to DRAMs without additional circuitry. This glueless DRAM connection includes the DRAM refresh controller.

The MIF also handles all internal bus arbitration between these blocks. When required, the MIF then arbitrates for the external bus.

The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs, Burned-in Addresses (BIA), and External Devices are appropriately addressed when required by the System Interface (SIF), Protocol Handler (PH), or for a DMA transfer.

The memory interface is capable of a 64 Mbps continuous transfer rate when using a 4-MHz local bus (64-MHz device crystal).

protocol handler (PH)

The Protocol Handler (PH) performs the hardware-based realtime protocol functions for a token ring or Ethernet Local Area Network (LAN). Network type is determined by the test pins TEST0–2. Token ring network is determined by software and can be either 16-Mbps or 4-Mbps. These speeds are not fixed by the hardware, but by the software.

The (PH) converts the parallel transmit data to serial network data of the appropriate coding, and converts the received serial data to parallel data. The PH data management state machines direct the transmission/reception of data to/from local memory through the MIF. The PH’s buffer management state machines automatically oversee this process, directly sending/receiving linked-lists of frames without CPU intervention.

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The Protocol Handler contains many state machines which provide the following features:

• Transmit and receive frames

• Capture tokens (token ring)

• Provide token-priority controls (token ring)

• Automatic retry of frame transmissions after collisions (Ethernet)

• Implement the Random Exponential Backoff algorithm (Ethernet)

• Manage the TMS380C26 buffer memory

• Provide frame address recognition (group, specific, functional, and multicast)

• Provide internal parity protection

• Control and verify the physical layer circuitry interface signals

Integrity of the transmitted and received data is assured by cyclic redundancy checks (CRC), detection of network data violations, and parity on internal data paths. All data paths and registers are optionally parity-protected to assure functional integrity.

adapter support function (ASF)

The Adapter Support Function (ASF) performs support functions not contained in the other blocks. The features are:

• The TMS380C26 base timer,

• Identification, management, and service of internal and external interrupts,

• Test pin mode control, including the unit-in-place mode for board testing,

• Checks for illegal states, such as illegal opcodes and parity.

clock generator (CG)

The Clock Generator (CG) performs the generation of all the clocks required by the other functional blocks and the local memory bus clocks. This block also generates the reference clock to be sampled by the SIF to determine if the TMS380C26 needs to be placed into slow clock mode. This reference clock is free floating in the range of 10 – 100 kHz.

user-accessible hardware registers and TMS380C26-internal pointers

The following tables show how to access internal data via pointers and how to address the registers in the host interface. The SIFACL register, which directly controls device operation, is described in detail.

NOTE:

The Adapter-Internal Pointers Table is defined only after TMS380C26 initialization and until the OPEN command is issued.

These pointers are defined by the TMS380C26 software (microcode), and this table describes the release

1.00 and 2.x software.

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Adapter-Internal Pointers for Token-Ring

ADDRESS DESCRIPTION

>00.FFF8 >00.FFFA

>01.0A00 Pointer to burned-in address in chapter 1. >01.0A02 Pointer to software level in chapter 1. >01.0A04 Pointer to TMS380C26 addresses in chapter 1:

>01.0A06 Pointer to TMS380C26 parameters in chapter 1:

>01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1. >01.0A0A Pointer to LLC counters in chapter 1:

>01.0A0C Pointer to 4-/16-Mbps word flag. If zero, then 4 Mbps. If nonzero, then the adapter is set to run at 16-Mbps data rate. >01.0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1.

†

This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.

‡

This address valid only for microcode release 2.x.

‡

Pointer to software raw microcode level in chapter 0.

‡

Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0.

Pointer + 0 node address. Pointer + 6 group address. Pointer + 10 functional address.

Pointer + 0 physical drop number. Pointer + 4 upstream neighbor address. Pointer + 10 upstream physical drop number. Pointer + 14 last ring poll address. Pointer + 20 reserved. Pointer + 22 transmit access priority. Pointer + 24 source class authorization. Pointer + 26 last attention code. Pointer + 28 source address of the last received frame. Pointer + 34 last beacon type. Pointer + 36 last major vector. Pointer + 38 ring status. Pointer + 40 soft error timer value. Pointer + 42 ring interface error counter. Pointer + 44 local ring number. Pointer + 46 monitor error code. Pointer + 48 last beacon transmit type. Pointer + 50 last beacon receive type. Pointer + 52 last MAC frame correlator. Pointer + 54 last beaconing station UNA. Pointer + 60 reserved. Pointer + 64 last beaconing station physical drop number.

Pointer + 0 MAX_SAPs. Pointer + 1 open SAPs. Pointer + 2 MAX_STATIONs. Pointer + 3 open stations. Pointer + 4 available stations. Pointer + 5 reserved.

†

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Adapter-Internal Pointers for Ethernet

ADDRESS DESCRIPTION

>00.FFF8 >00.FFFA

>01.0A00 Pointer to burned-in address in chapter 1. >01.0A02 Pointer to software level in chapter 1. >01.0A04 Pointer to TMS380C26 addresses in chapter 1:

>01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1. >01.0A0A Pointer to LLC counters in chapter 1:

†

This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.

‡

This address valid only for microcode release 2.x.

‡

Software raw microcode level in chapter 0.

‡

Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0.

Pointer + 0 node address. Pointer + 6 group address. Pointer + 10 functional address.

Pointer + 0 MAX_SAPs. Pointer + 1 open SAPs. Pointer + 2 MAX_STATIONs. Pointer + 3 open stations. Pointer + 4 available stations. Pointer + 5 reserved.

†

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User-Access Hardware Registers

808x 16-Bit Mode: (SI/M = 1, S8/SHALT = 0)

Word Transfers

Byte Transfers

SRSX SRS0 SRS1

000 001 010 011 100 101 110 111

†

(SBHE = 1 and SRS2 = 1 is not defined)

808x 8-Bit Mode: (SI/M = 1, S8/SHALT = 1)

SRSX SRS0 SRS1 SRS2

00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1

SBHE = 0 SBHE = 1 SRS2 = 1 SRS2 = 0

SIFDAT MSB SIFDAT LSB SIFDAT/INC MSB SIFDAT/INC LSB SIFADR MSB SIFADR LSB SIFCMD SIFSTS SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

†

Normal Mode

SBHE = 0 SRS2 = 0

Normal

SBHE = X

SIFDAT LSB SIFDAT MSB SIFDAT/INC LSB SIFDAT/INC MSB SIFADR LSB SIFADR MSB SIFSTS SIFCMD SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Pseudo-DMA Mode Active

SBHE = 0

SRS2 = 0

SBHE = 0 SBHE = 1 SRS2 = 1 SRS2 = 0

— SDMADAT DMALEN MSB DMALEN LSB SDMAADR MSB SDMAADR LSB SDMAADX MSB SDMAADX LSB SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

Pseudo-DMA

SBHE = X

SDMADAT — DMALEN LSB DMALEN MSB SDMAADR LSB SDMAADR MSB SDMAADX LSB SDMAADX MSB SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB

68xxx Mode: (SI/M = 0)

‡

Word Transfers

Byte Transfers

SRSX SRS0 SRS1

000 001 010 011 100 101 110 111

‡

68xxx Mode is always 16-bit.

Normal Mode

SUDS = 0

= 0

SLDS

SUDS = 0 SUDS = 1 SLDS = 1 SLDS = 0

SIFDAT MSB SIFDAT LSB SIFDAT/INC MSB SIFDAT/INC LSB SIFADR MSB SIFADR LSB SIFCMD SIFSTS SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

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Pseudo-DMA Mode Active

SUDS = 0

= 0

SLDS

SUDS = 0 SUDS = 1 SLDS = 1 SLDS = 0

— SDMADAT DMALEN MSB DMALEN LSB SDMAADR MSB SDMAADR LSB SDMAADX MSB SDMAADX LSB SIFACL MSB SIFACL LSB SIFADR MSB SIFADR LSB SIFADX MSB SIFADX LSB DMALEN MSB DMALEN LSB

TMS380C26 NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

SIF Adapter Control Register (SIFACL)

The SIFACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control.

SIFACL Register

Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

S T 0

R R R RP – 0 R –u R – 0 RS –0 RW – 0 RP –b RP –b R RW –1 RP –p RP-0 RP–1

— SWHLDA SWDDIR SWHRQ PSDMAEN ARESET CPHALT BOOT RES0 SINTEN PEN

R = Read, W = Write, P = Write during ARESET = 1 only, S = Set Only, –n = Value after reset (b = V alue on BTSTRP pin, p = Value on PRTYEN pin, u = Indeterminate)

Bits 0-2: TEST (0–2). Value on TEST (0–2) pins.

These bits are read only and always reflect the value on the corresponding device pins. This allows the host S/W to determine the network type and speed configuration. If the network speed and type are software configurable, these bits can be used to determine which configurations are supported by the network hardware.

NSEL OUT0

NSEL OUT1

TEST0 TEST1 TEST2 Description

L L H Reserved

L H H 16 Mbps token ring H L H Ethernet (802.3/Blue Book) H H H 4 Mbps token ring

X X 0 Reserved

Bit 3: Reserved. Read data is indeterminate.

Bit 4: SWHLDA — Software Hold Acknowledge

This bit allows the SHLDA/SBGR pin’s function to be emulated from software control for pseudo-DMA.

PSDMAEN SWHLDA SWHRQ RESULT

†

The value on the SHLDA/SBGR pin is ignored.

X X SWHLDA value in the SIFACL register cannot be set to a one. 0 0 No pseudo-DMA request pending. 0 1 Indicates a pseudo-DMA request interrupt. 1 X Pseudo-DMA process in progress.

Bit 5: SWDDIR — Current SDDIR Signal Value

This bit contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software.

0 = Pseudo-DMA from host system to TMS380C26. 1 = Pseudo-DMA from TMS380C26 to host system.

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Bit 6: SWHRQ — Current SHRQ Signal Value

This bit contains the current value on the SHRQ/SBRQ pin when in Intel mode, and the inverse of the SHRQ/SBRQ pin when in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is requested.

INTEL MODE (SI/M pin = H) MOTOROLA MODE (SI/M pin = L) 0 = System bus not requested System bus not requested 1 = System bus requested System bus requested

Bit 7: PSDMAEN — Pseudo-System-DMA Enable

This bit enables pseudo-DMA operation 0 = Normal bus master DMA operation possible.

1 = Pseudo-DMA operation selected. Operation dependent on the values of the SWHLDA

and SWHRQ bits in the SIFACL register.

Bit 8: ARESET — Adapter Reset

This bit is a hardware reset of the TMS380C26. This bit has the same effect as the SRESET pin, except that the DIO interface to the SIFACL register is maintained. This bit will be set to one if a clock failure is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).

0 = The TMS380C26 operates normally. 1 = The TMS380C26 is held in the reset condition.

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

Bit 9: CPHALT — Communications Processor Halt

This bit prevents the TMS380C26’s processor from accessing the internal TMS380C26 buses. This prevents the TMS380C26 from executing instructions before the microcode has been downloaded.

0 = The TMS380C26’s processor can access the internal TMS380C26 buses. 1 = The TMS380C26’s processor is prevented from accessing the internal adapter buses.

Bit 10: BOOT — Bootstrap CP Code

This bit indicates whether the memory in chapters 0 and 31 of the local memory space is RAM or ROM/PROM/EPROM. This bit then controls the operation of the MCAS

0 = ROM/PROM/EPROM memory in chapters 0 and 31. 1 = RAM memory in chapters 0 and 31.

Bit 11: RES0 — Reserved. This bit must be set to zero

and MROMEN pins.

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Bit 12: SINTEN — System-Interrupt Enable

This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26. The system interrupt request from the TMS380C26 is on the SINTR/SIRQ pin. The following equation shows how the SINTR/SIRQ pin is driven. The table also explains the results of the states.

SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT)

PSDMAEN SWHRQ SWHLDA SINTEN

†

X X X 1 1

0 X X 1 0

0 X X 0 X

†

The value on the SHLDA/SBGR pin is ignored.

1 1 X X Pseudo-DMA is active. 1 0 X X 0 0 X X Not a pseudo-DMA interrupt.

SYSTEM

INTERRUPT

(SIFSTS Reg.)

RESULT

The TMS380C26 generated a system interrupt for a pseudo-DMA.

The TMS380C26 will generate a system interrupt.

The TMS380C26 will not generate a system interrupt.

The TMS380C26 can not generate a system interrupt.

Bit 13: PEN — Adapter Parity Enable

This bit determines whether data transfers within the TMS380C26 are checked for parity. 0 = Data transfers are not checked for parity

1 = Data transfers are checked for correct odd parity.

Bit 14 — 15: NSELOUT (0–1) — Network selection outputs.

The values in these bits control the output pins NSELOUT0 and NSELOUT1. These bits can only be modified while the ARESET bit is set.

These bits can be used to software configure a multi-protocol TMS380C26, as follows: The NSELOUT0 and NSELOUT1 pins should be connected to TEST0 and TEST1 pins

respectively (TEST2 should be left unconnected or tied high). NSELOUT0 should be used to select network speed and NSELOUT1 network type, as shown in the table below:

NSELOUT0 NSELOUT1

0 0 Reserved 0 1 16 Mbps token ring 1 0 Ethernet (802.3/Blue Book)

1 1 4 Mbps token ring

At power-up these bits are set NSELOUT1 = 1, NSELOUT0 = 0 corresponding to 16 Mbps token ring.

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NETWORK COMMPROCESSOR

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SIFACL Control for Pseudo-DMA Operation

Pseudo-DMA is software controlled by the use of five bits in the SIFACL register . The logic model for the SIF ACL register control of pseudo-DMA operation is shown in Figure 3.

Internal

Signals

SYSTEM_INTERRUPT

(SIFSTS Register)

DMA

Request

DMA

Grant

DMADIR

Motorola Mode

U X

SWHLDA

SWDDIR SWHRQ PSDMAEN SINTEN

SIFACL Register

Figure 3. Pseudo-DMA Logic Related to SIFACL Bits

Host Interface

SINTR/SIRQ

SHRQ/SBRQ

SHLDA/SBGR

SDDIR

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TMS380C26

VILLow-level input voltage, TTL-level signal (see Note 8)

IOHigh-impedance output current

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range (see Note 6) – 0.3 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range – 2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1.0 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: Voltage values are with respect to VSS.

(see Note 6) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.75 5 5.25 V

Supply voltage (see Note 7) 0 0 0 V

TTL-level signal 2.0 VDD+0.3

High-level input voltage

High level output current –400 µA

Low level output current (see Note 9) 2 mA

Operating free-air temperature 0 70 °C

†

The minimum level specified is a result of the manufacturing test environment. This signal has been characterized to a minimum level of

2.4 V over the full temperature range.

‡

The maximum level specified is a result of the manufacturing test environment. This signal has been characterized to a maximum level of

0.8 V over the full temperature range.

NOTES: 7. All VSS pins should be routed to minimize inductance to system ground.

8. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used in this data sheet for logic voltage levels only.

9. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst case).

†

OSCIN RCLK, PXTALIN, RCVR 2.6 VDD+0.3

‡

OSCIN All other –0.3 0.8

2.6 VDD+0.3

–0.3 0.6

†

electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)

PARAMETER

High-level output voltage, TTL-level signal (see Note 11) VDD = min, IOH = max 2.4 V

Low-level output voltage, TTL-level signal VDD = min, IOL = max 0.6 V

Input current, any input or input/output pin VI = VSS to V

Supply current VDD = max 220 mA

Input capacitance, any input f = 1 MHz, other pins at 0 V 15 pF

Output capacitance, any output or input/output f = 1 MHz, other pins at 0 V 15 pF

NOTES: 10. For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions.

11. The following signals require an external pullup resistor: SRAS/SAS EXTINT0

–EXTINT3, and MBRQ.

TEST CONDITIONS

(see Note 10)

VDD = max, VO = 2.4 V 20 VDD = max, VO = 0.4 V – 20

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MIN TYP MAX UNIT

, SRDY/SDTACK, SRD/SUDS, SWR/SLDS,

± 20 µA

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. These levels are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 volts, and the level at which the signal is said to be low is 0.8 volts. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 volts, and the level at which the signal is said to be high is 2 volts, as shown below.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

2 V (High)

0.8 V (Low)

test measurement

The test load circuit shown in Figure 4 represents the programmable load of the tester pin electronics which are used to verify timing parameters of TMS380C26 output signals.

Tester Pin

Electronics

LOAD

Output

Under

Test

Where: IOL = 2.0 mA DC level verification (all outputs)

IOH = 400 µA (all outputs) V

= 1.5 V typical DC level verification

LOAD

0.7 V typical timing verification

CT = 65 pF typical load circuit capacitance

Figure 4. Test Load Circuit

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PARAMETER MEASUREMENT INFORMATION

Reference

OSCIN

When CLKDIV = 1

OSCOUT

MBCLK1

MBCLK2

†

The MBCLK1 and MBCLK2 signals have no timing relationship to the OSCOUT signal. The MBCLK1 and MBCLK2 signals can start on any OSCIN rising edge, depending on when the memory cycle starts execution.

†

4 Periods 8 Periods 12 Periods 16 Periods 20 Periods

Figure 5. Clock Waveforms After Clock Stabilization

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TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

timing parameters

The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among the various signals. The parameters are numbered for convenience.

static signals

The following table lists signals that are not allowed to change dynamically and therefore have no timing associated with them. They should be strapped high or low as required.

SIGNAL FUNCTION

SI/M Host processor select. (Intel/Motorola) CLKDIV Reserved BTSTRP Default bootstrap mode. (RAM/ROM) PRTYEN Default parity select. (enabled/disabled) TEST0 Test pin, indicates network type TEST1 Test pin, indicates network type TEST2 Test pin, indicates network type TEST3 Test pin for TI manufacturing test. TEST4 Test pin for TI manufacturing test. TEST5 Test pin for TI manufacturing test.

†

For unit-in-place test.

† † †

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as shown below:

DR DRVR RS SRESET DRN DRVR VDD V OSC OSCIN SCK SBCLK

Lower case subscripts are defined as follows:

c cycle time r rise time d delay time sk skew h hold time su setup time

w pulse duration (width) t transition time

The following additional letters and phrases are defined as follows:

H High Z High impedance

L Low Falling edge No longer high

V Valid Rising edge No longer low

DDL

, V

DDB

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PARAMETER MEASUREMENT INFORMATION

power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN

NO. PARAMETER MIN MAX UNIT 100†t 101†‡t 102†‡t 103 t 104 t 105 t 106†t 107 t 108 t 109 t

†

110

†

111

†

117

†

118

†

119 288†t 289†t

†

This specification is provided as an aid to board design.

‡

If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger dif ference: real value of parameter 101 or 102 minus the max value listed.

NOTE 12: If OSCIN is used to generate PXTALIN, the specification for the tolerance of OSCIN is equal to ± 0.01%.

) Rise time from 1.2 V to VDD minimum high level 1 ms

r(VDD d(VDDH-SCKV) d(VDDH-OSCV) c(SCK) w(SCKH) w(SCKL) t(SCK) c(OSC) w(OSCH) w(OSCL)

t(OSC)

d(OSCV-CKV)

h(VDDH-RSL)

w(RSH)

w(RSL) su(RST) h(RST)

Delay time from minimum VDD high level to first valid SBCLK no longer high 1 ms Delay time from minimum VDD high level to first valid OSCIN high 1 ms Cycle time of SBCLK 62.5 ns Pulse duration of SBCLK high 26 ns Pulse duration of SBCLK low 26 ns Transition time of SBCLK 5 ns Cycle time of OSCIN (see Note 12) 15.6 500 ns Pulse duration of OSCIN high 5.5 ns Pulse duration of OSCIN low 5.5 ns Transition time of OSCIN 3 ns Delay time from OSCIN valid to MBCLK1 and MBCLK2 valid 1 ms Hold time of SRESET low after VDD reaches minimum high level 5 ms Pulse duration of SRESET high 14 µs Pulse duration of SRESET low 14 µs Setup time of DMA size to SRESET high (Intel mode only) 15 ns Hold time of DMA size from SRESET high (Intel mode only) 15 ns One-eighth of an local memory cycle 2t

, and SRESET timing

c(OSC)

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SBCLK

OSCIN

MBCLK1

MBCLK2

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

100

Minimun VDD High Level

103

111

106

104

108

105

110

109

102

101

107

TMS380C26

106

110

117

SRESET

288

S8/SHALT

NOTE A: In order to represent the information on one figure, non-actual phase and timebase characteristics are shown. Please refer to specified

parameters for precise information.

118

119

289

Figure 6. Power Up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET Timing

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: clocks, MAL

, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

1 Period of MBCLK1 and MBCLK2 4t 2 Pulse duration of clock high 2tM–9 ns 3 Pulse duration of clock low 2tM–9 ns 4 Hold time of MBCLK2 low after MBCLK1 high tM–9 ns 5 Hold time of MBCLK1 high after MBCLK2 high tM–9 ns 6 Hold time of MBCLK2 high after MBCLK1 low tM–9 ns 7 Hold time of MBCLK1 low after MBCLK2 low tM–9 ns 8 Setup time of address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high tM–9 ns

9 Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no longer high tM–14 ns 10 Setup time of address on MADH0–MADH7 before MBCLK1 no longer high tM–14 ns 11 Setup time of MAL high before MBCLK1 no longer high tM–13 ns 12 Setup time of address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low 0.5tM–9 ns

Setup time of column address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no

longer low

14 Setup time of status on MADH0–MADH7 before MBCLK1 no longer low 0.5tM–9 ns

120 Setup time of NMI valid before MBCLK1 low 30 ns 121 Hold time of NMI valid after MBCLK1 low 0 ns 126 Delay time from MBCLK1 no longer low to MRESET valid 0 20 ns 129 Hold time of column address/status after MBCLK1 no longer low. tM–7 ns

0.5tM–9 ns

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PARAMETER MEASUREMENT INFORMATION

TMS380C26

MBCLK1

MBCLK2

MAX0, MAX2,

MROMEN

MAXPH,

MAXPL,

MADL0–MADL7

MADH0–MADH7

MAL

M1 M2 M3M8

Address

129

M4 M5 M6 M7 M8 M1

AddressADD/EN

ColRow

Status

120

121

NMI

MRESET

Valid

126

Valid

Figure 7. Memory Bus Timing: Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: clocks, MRAS

, MCAS, and MAL to ADDRESS

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

15 16 Hold time of row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high tM–6.5 ns

17 Delay time from MRAS no longer high to MRAS no longer high in the next memory cycle 8t 18 Pulse duration of MRAS low 4.5tM–9 ns 19 Pulse duration of MRAS high 3.5tM–9 ns

22 23 Pulse duration of MCAS low 3tM–9 ns

24 Pulse duration of MCAS high, refresh cycle follows read or write cycle 2tM–9 ns 25 Hold time of row address on MAXL0–MAXL7, MAXPH, and MAXPL after MAL low 1.5tM–9 ns 26 Setup time of row address on MAXL0–MAXL7, MAXPH, and MAXPL before MAL no longer high tM–9 ns 27 Pulse duration of MAL high tM–9 ns 28 Setup time of address/enable on MAX0, MAX2, and MROMEN before MAL no longer high tM–9 ns 29 Hold time of address/enable of MAX0, MAX2, and MROMEN after MAL low 1.5tM–9 ns 30 Setup time of address on MADH0–MADH7 before MAL no longer high tM–9 ns 31 Hold time of address on MADH0–MADH7 after MAL low 1.5tM–9 ns

Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high

Setup time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) before MCAS

Hold time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) after MCAS

Hold time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) after MRAS

no longer high

low

no longer high

1.5tM – 11.5 ns

0.5tM–9 ns

tM–9 ns

2.5tM–6.5 ns

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PARAMETER MEASUREMENT INFORMATION

TMS380C26

MAXPH,

MAXPL,

MADL0–MADL7

MRAS

MCAS

MAL

MAX0, MAX2,

MROMEN

MADH0–MADH7

Row ColumnColumnRow

AddressADD/EN

Address StatusStatusAddress

Figure 8. Memory Bus Timing: Clocks, MRAS, MCAS, and MAL to ADDRESS

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: read cycle

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

32 Access time from address/enable valid on MAX0, MAX2, and MROMEN to valid data/parity

33 35 Access time from MRAS low to valid data/parity 4.5tM–21.5 ns

36 Hold time of valid data/parity after MRAS no longer low 0 ns

37 38 Access time from MCAS low to valid data/parity 3tM–23 ns

39 Hold time of valid data/parity after MCAS no longer low 0 ns

40 41 Delay time from MCAS no longer high to MOE low tM+13 ns

42 43 Access time from MOE low to valid data/parity 2tM–25 ns

44 Pulse duration MOE low 2tM–9 ns 45 Delay time from MCAS low to MOE no longer low 3tM–9 ns 46 Hold time of valid data/parity in after MOE no longer low 0 ns

48a 49 Access time from MBEN low to valid data/parity 2tM–25 ns

49a Access time from MBIAEN low to valid data/parity 2tM–25 ns 50 Pulse duration MBEN low 2tM–9 ns 50a Pulse duration MBIAEN low 2tM–9 ns 51 Hold time of valid data/parity after MBEN no longer low 0 ns 51a Hold time of valid data/parity after MBIAEN no longer low 0 ns

52a 53 Hold time of MDDIR high after MBEN high, read follows write cycle 1.5tM–12 ns

54 Setup time of MDDIR low before MBEN no longer high 3tM–9 ns 55 Hold time of MDDIR low after MBEN high, write follows read cycle 3tM–12 ns

†

This specification has been characterized to meet stated value.

NOTE 13: The data/parity that exists on the address lines will most likely achieve a high-impedance condition sometime later than the rising edge,

Access time from address valid on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 to valid data/parity

Hold time of address high impedance on MAXPH, MAXPL, MADH0–MADH7 and

†

MADL0–MADL7 after MRAS

Hold time of address high impedance on MAXPH, MAXPL, MADH0–MADH7, and

†

MADL0–MADL7 after MCAS

Setup time of address/status high impedance on MAXPH, MAXPL, MADL0–MADL7, and

†

MADH0–MADH7 before MOE

Hold time of address high impedance on MAXPH, MAXPL, MADH0–MADH7, and

†

MADL0–MADL7 after MOE Setup time of address/status high impedance on MAXPH, MAXPL, MADL0–MADL7, and

†

MADH0–MADH7, before MBEN Setup time of address/status high impedance on MAXPH, MAXPL, MADL0–MADL7, and

†

MADH0–MADH7 and before MBIAEN

Hold time of address high impedance on MAXPH, MAXPL, MADH0–MADH7, and

†

MADL0–MADL7 after MBEN Hold time of address high impedance on MAXPH, MAXPL, MADH0–MADH7, and

†

MADL0–MADL7 after MBIAEN

of MRAS Hence, the MIN time given represents the time from the rising edge of MRAS address, and does not represent the actual high-impedance period on the address bus.

, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read.

high (see Note 13)

no longer high

high (see Note 13)

no longer high

high (see Note 13)

high

2tM–10.5

2tM–13

2tM–15

, MCAS, MOE, or MBEN to the beginning of the next

6tM – 23

6tM–23

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PARAMETER MEASUREMENT INFORMATION

TMS380C26

MAX0, MAX2,

MROMEN

MAXPH, MAXPL, MADH0–MADH7,

MADL0–MADL7

MRAS

MCAS

MOE

Address/

Enable

Address

Address/

Status

Address

Data/Parity

Address

MBIAEN

MBEN

MDDIR

48a

50a

Figure 9. Memory Bus Timing: Read Cycle

49a

51a

52a

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: write cycle

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

58 Setup time of MW low before MRAS no longer low 1.5tM – 9 ns 60 Setup time of MW low before MCAS no longer low 1.5tM–6.5 ns 63 Setup time of valid data/parity before MW no longer high 0.5tM–11.5 ns 64 Pulse duration of MW low 2.5tM–9 ns 65 Hold time of data/parity out valid after MW high 0.5tM–10.5 ns 66 Setup time of address valid on MAX0, MAX2, and MROMEN before MW no longer low 7tM–11.5 ns 67 Hold time from MRAS low to MW no longer low 5.5tM–9 ns 69 Hold time from MCAS low to MW no longer low 4tM–11.5 ns 70 Setup time of MBEN low before MW no longer high 1.5tM–13.5 ns 71 Hold time of MBEN low after MW high 0.5tM–6.5 ns 72 Setup time of MDDIR high before MBEN no longer high 2tM–9 ns 73 Hold time of MDDIR high after MBEN high 1.5tM–12 ns

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PARAMETER MEASUREMENT INFORMATION

TMS380C26

MAX0, MAX2,

MROMEN

MAXPH, MAXPL, MADH0–MADH7,

MADL0–MADL7

MRAS

MCAS

MBEN

Address/

Enable

Address

Data/Parity OutADD/STSAddress

MDDIR

72 73

Figure 10. Memory Bus Timing: Write Cycle

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: TMS380C26 releases control of bus

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

74 Hold time of MIF output after MBCLK1 rising edge, bus release 0.5tM – 13 ns 74a Hold time of MBEN valid after MBCLK1 rising edge, bus release tM – 13 ns 75 Delay time from MBCLK1 high to MIF output high impedance, bus release 0.5t 75a Delay time from MBCLK1 high to MBEN output high impedance, bus release t 76 Setup time of MBRQ low before MBCLK1 falling edge, bus release 24 ns 77 Hold time of MBRQ low after MBCLK1 low, bus release 0 ns 78 Setup time of MBGR low before MBCLK1 rising edge, bus release 29 ns

MBCLK1

MAX0, MAX2,

MROMEN

MAXPH,

MAXPL,

MADH0–MADH7,

MADL0–MADL7

75 74

M M

ns ns

MRAS

MCAS

MOE

Figure 11. Memory Bus Timing: TMS380C26 Releases Control of Bus

75 74

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MBCLK1

MBCLK2

MBEN

MDDIR

MAL

TMS380C26

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PARAMETER MEASUREMENT INFORMATION

75a 74a

75 74

MBIAEN

MBRQ

MBGR

75 74

Figure 12. Memory Bus Timing: TMS380C26 Releases Control of Bus (continued)

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: TMS380C26 resumes control of bus

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

79 Hold time of MIF output high impedance after MBCKL1 rising edge, bus resume tM – 13 ns 80 Delay time from MBCLK1 high to MIF output vallid, bus resume tM + 9 ns 91 Setup time of MBRQ valid before MBCLK1 falling edge, bus resume 24 ns 82 Hold time of MBRQ valid after MBCLK1 low, bus resume 0 ns 83 Setup time of MBGR high before MBCLK1 rising edge, bus resume 29 ns

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MBCLK1

MAX0, MAX2,

MOROMEN

MAXPH,

MAXPL,

MADH0–MADH7,

MADL0–MADL7

MRAS

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

80 79

MCAS

MOE

Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of Bus

80 79

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PARAMETER MEASUREMENT INFORMATION

MBCLK1

MBCLK2

MBEN

MDDIR

MAL

MBIAEN

MBRQ

MBGR

80 79

Figure 14. Memory Bus Timing: TMS380C26 Resumes Control of Bus (continued)

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: external bus master read from TMS380C26

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

84 Setup time of address on MAX0 and MAX2 before MBCLK1 falling edge, external bus master access 21 ns 85 Hold time of address on MAX0 and MAX2 after MBCLK1 low, external bus master access 0 ns 86 Setup time of valid address before MBCLK1 falling edge, external bus master access 21 ns 87 Hold time of valid address after MBCLK1 low, external bus master access 0 ns 88 Setup time of address high impedance before MBCLK1 falling edge, external bus master read 0 ns 89 Setup time of data/parity valid before MBCLK2 falling edge, external bus master read 1.5tM – 17 90 Hold time of valid data/parity after MBCLK2 low, external bus master read tM – 13 ns 91 Setup time of data/parity high impedance before MBCLK2 rising edge, external bus master read tM – 9 ns 92 Setup time of MDDIR low before MBCLK2 falling edge, external bus master read 21 ns 93 Hold time of MDDIR low after MBCLK2 low, external bus master read 0 ns 94 Setup time of MACS low before MBCLK2 falling edge, external bus master read 21 ns 95 Hold time of MACS low after MBCLK2 low, external bus master read 0 ns

†

This specification has been characterized to meet stated value.

†

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PARAMETER MEASUREMENT INFORMATION

MBCLK1

MBCLK2

84 85

MAX0,

MAX2

86 87

MAXPH,

MAXPL,

MADH0–MADH7,

MADL0–MADL7

Address In

Data/Parity

Address In

MDDIR

MACS

Figure 15. Memory Bus Timing: External Bus Master Read From TMS380C26

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: external bus master write to TMS380C26

NO. PARAMETER MIN MAX UNIT

96 Setup time of valid data/parity before MBCLK2 falling edge, external bus master write 21 ns 97 Hold time of valid data/parity after MBCLK2 low, external bus master write 0 ns 98 Setup time of MDDIR high before MBCLK2 falling edge, external bus master write 21 ns 99 Hold time of MDDIR high after MBCLK2 low, external bus master write 0 ns

MBCLK1

Address In

MAX0, MAX2

MAXPH,

MAXPL,

MADH0–MADH7,

MADL0–MADL7

MDDIR

MACS

Address In

Data/Pty

Address In

Figure 16. Memory Bus Timing: External Bus Master Write To TMS380C26

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PARAMETER MEASUREMENT INFORMATION

memory bus timing: DRAM refresh timing

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer

high 16 Hold time of row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high tM–6.5 ns 18 Pulse duration of MRAS low 4.5tM–9 ns 19 Pulse duration of MRAS high 3.5tM–9 ns 73a Setup time of MCAS low before MRAS no longer high 1.5tM–11.5 ns 73b Hold time of MCAS low after MRAS low 4.5tM– 6.5 ns 73c Setup time of MREF high before MCAS no longer high tM–14 ns 73d Hold time of MREF high after MCAS high tM–9 ns

1.5tM–11.5 ns

MADL0–MADL7

MRAS

MCAS

MREF

Refresh Address

73a

73c

73b

Figure 17. Memory Bus Timing: DRAM Refresh Cycle

Address

73d

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PARAMETER MEASUREMENT INFORMATION

XMATCH and XFAIL timing

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO. PARAMETER MIN MAX UNIT

127 Delay from status bit 7 high to XMATCH and XFAIL recognized 7t 128 Pulse duration of XMATCH or XFAIL high 50 ns

MADH7

XMATCH,

XFAIL

Status

Bit 7

127

Figure 18. XMATCH and XFAIL Timing

128

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153

Period of RCLK (see Note 14)

154L

Pulse duration of RCLK lo

154H

Pulse duration of RCLK high

158L

Pulse duration of ring baud clock lo

158H

Pulse duration of ring baud clock high

165

Period of OSCOUT and PXTALIN (see Note 14)

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

token ring — ring interface timing

No. PARAMETER MIN TYP MAX UNIT

4Mbps 125 ns 16 Mbps 31.25 ns

155 Setup of RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbps 10 ns 156 Hold of RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbps 4 ns

166 Tolerance of PXTALIN input frequency (see Note 14) ± 0.01 %

NOTE 14: This parameter is not tested but is required by the IEEE 802.5 specification.

4 Mbps nominal: 62.5 ns 46 ns 16 Mbps nominal: 15.625 ns 15 ns 4 Mbps nominal: 62.5 ns 35 ns 16 Mbps nominal: 15.625 ns 8 ns

4 Mbps 40 ns 16 Mbps 15 ns 4 Mbps 40 ns 16 Mbps 8 ns 4 Mbps 125 ns 16 Mbps (for PXTALIN only) 31.25 ns

RCLK

RCVR

OSCOUT,

PXTALIN

153

154H

154L

155

Valid

158H

156

158L

165

Figure 19. Token Ring — Ring Interface Timing

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PARAMETER MEASUREMENT INFORMATION

token ring — transmitter timing (see Figure 20)

NO. PARAMETER MIN TYP MAX UNIT

Delay from DRVR rising edge (1.8 V) to DRVR falling edge (1.0 V) or DRVR falling edge (1.0 V) to

159

DRVR

rising edge (1.8 V) 160†Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DRVR rising edge (1.8 V) (see Note 15) 161†Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DR VR falling edge (1.0 V) (see Note 15) 162†Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DRVR falling edge (1.0 V) (see Note 15) 163†Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DRVR rising edge (1.8 V) (see Note 15)

)

DRVR/DRVR Asymmetry

164

†

When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock-source is either RCLK or PXTALIN.

NOTE 15: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164.

RCLK or PXTALIN

d(DR)L

d(CRN)H

–

d(DR)H

)

d(DRN)L

2.60

1.50

0.60

±2 ns

±1.5 ns

DRVR

162

160

159

161

159

163

2.40

1.50

0.60

2.40

1.50

0.60

Figure 20. Skew and Asymmetry from RCLK or PXTALIN to DRVR and DRVR

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PARAMETER MEASUREMENT INFORMATION

ethernet timing of clock signals

NO. PARAMETER MIN TYP MAX UNIT

300 CLKPHS Pulse duration of TXC 45 ns 301 CLKPER Cycle time of TXC 95 1000 ns

300

TXC

300

301

2.4 V

0.45 V

Figure 21. Ethernet Timing Of Clock Signals

ethernet timing of XMIT signals

NO. PARAMETER MIN TYP MAX UNIT

305 t 306 t

XDHLD XDVLD

TXC

TXD

TXEN

Hold time of TXD after TXC high 5 ns Delay time from TXC high to TXD valid and

Delay time from TXC high to TXEN high

305

306

40 ns

2.4 V

0.45 V

2.4 V

0.45 V

Figure 22. Ethernet Timing of XMIT Signals

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PARAMETER MEASUREMENT INFORMATION

ethernet timing of RCV signals — start of frame

NO. PARAMETER MIN TYP MAX UNIT

310 RXDSET Setup of RXD before RXC no longer low 20 ns 311 RXDHLD Hold of RXD after RXC high 5 ns 312 CRSSET Setup of CRS high before RXC no longer low for first valid data sample 20 ns 313 SAMDLY Delay of CRS internally recognized to first valid data sample (see Notes 16 and 17) nominal 3 clk cycles 314 RXCHI Pulse duration of RXC high 36 ns 315 RXCL0 Pulse duration of RXC low 36 ns

NOTES: 16. For valid frame synchronization one of the following data sequences must be received. Any other pattern will delay frame

synchronization until after the next CRS rising edge. a) 0n(10) 11 where n is an integer and n is greater than or equal to 3 b) 10n(10) 11

17. If a previous frame or frame fragment completed without extra RXC clock cycles (XTRCVC = 0), then SAMDLY = 2 clock cycles.

312

CRS

RXC

RXD

313

310

314

315

311

Figure 23. Ethernet Timing of RCV Signals — Start Of Frame

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PARAMETER MEASUREMENT INFORMATION

ethernet timing of RCV signals — end of frame

NO. PARAMETER MIN TYP MAX UNIT

320 CRSSET

321 CRSHLD 322 XTRCYC Number of extra RXC clock cycles after last data bit (CRS pin is low) (see Note 18) 0 5 cycle

NOTE 18: TMS380C26 will operate correctly even with no extra RXC clock cycles, providing that CRS does not remain asserted longer than

2 µs (see timing spec, NDRXC). Providing no extra clocks affect receive startup timing, see timing spec, SAMDLY.

Setup time of CRS low before RXC no longer low to determine if last data bit ”seen” on previous RXC no longer low (see Note 18)

Hold time of CRS low after RXC no longer low, to determine if last data bit ”seen” on previous RXC no longer low

RXC

20 ns

0 ns

CRS

RXD

320

321

322

Last

Data Bit

Figure 24. Ethernet Timing of RCV Signals — End Of Frame

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PARAMETER MEASUREMENT INFORMATION

ethernet timing of RCV signals — no RXC

NO. PARAMETER MIN TYP MAX UNIT

330 NORXC Time with no clock pulse on RXC, when CRS is high (see Note 19) 2 µs

NOTE 19: If NORXC is exceeded local clock failure circuitry may become activated, resetting the device.

CRS ”1”

330

RXC

Figure 25. Ethernet Timing of RCV Signals — No RXC

ethernet timing of XMIT signals

NO. PARAMETER MIN TYP MAX UNIT

340 HBWIN 341 COLPUL Minimum pulse duration of COLL high for guaranteed sample 20 ns + 1 cycle ns

342 COLSET Setup of COLL high to TXC high 20 ns

Delay time from TXC high of the last transmitted data bit (TXEN is high) to COLL sampled high, so not to generate a ”heart-beat” error

47 cycles

TXC

COLL

TXD

TXEN

340

341

342

Figure 26. Ethernet Timing of XMIT Signals

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PARAMETER MEASUREMENT INFORMATION

ethernet timing of XMIT signals

NO. PARAMETER MIN TYP MAX UNIT

350 JAMTIM 351 COLSET Setup of COLL high before TXC high 20 ns

352 COLPUL Minimum pulse duration of COLL high for guaranteed sample 20 ns + 1 cycle ns

NOTE 20: The JAM pattern is delayed until after the completion of the preamble pattern. The TMS380C26 transmits a JAM pattern of all ”1”s.

TXC

Time from COLL sampled high (TXC high) to first transmitted ”JAM” bit on TXD (see Note 20)

350

4 cycles

TXD

COLL

Data Data Data JAM JAM JAM

351

352

Figure 27. Ethernet Timing of XMIT Signals

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PARAMETER MEASUREMENT INFORMATION

80x8x DIO read timing

NO. PARAMETER MIN MAX UNIT

255 Delay from SRDY low to either SCS or SRD high 15 ns 256 Pulse duration, SRAS high 30 ns 259†Hold of SAD high-impedance after SRD low (see Note 21) 0 ns 260 Setup of SADH0–SADH7, SADL0–SADL7, SPH and SPL valid before SRDY low 0 ns 261†Delay from SRD or SCS high to SAD high-impedance (see Note 21) 35 ns 261a Hold of output data valid after SRD or SCS high (see Note 21) 0 ns 264 Setup of SRSX, SRS0–SRS2, SCS, and SBHE valid to SRAS no longer high (see Note 22) 30 ns 265 Hold of SRSX, SRS0–SRS2, SCS, and SBHE valid after SRAS low 15 ns 266a Setup of SRAS high to SRD no longer high (see Note 22) 25 ns 267‡Setup of SRSX, SRS0–SRS2 valid before SRD no longer high (see Note 21) 15 ns 268 Hold of SRSX, SRS0–SRS2 valid after SRD no longer low (see Note 22) 0 ns 272a Setup time of SRD, SWR, and SIACK high from previous cycle to SRD no longer high 55 ns 273a Hold time of SRD, SWR, and SIACK high after SRD high 55 ns 275 Delay from SRD and SWR, or SCS high to SRDY high (see Note 21) 35 ns 279†Delay from SRD and SWR, high to SRDY high impedance 65 ns 282a Delay from SDBEN low to SRDY low in a read cycle 35 ns

282R 283R Delay from SRD high to SDBEN high (see Note 21) 35 ns

286 Pulse duration, SRD high between DIO accesses (see Note 21) 55 ns

†

This specification is provided as an aid to board design.

‡

It is the later of SRD

NOTES: 21. The “inactive” chip select is SIACK

Delay from SRD low to SDBEN low (see

SPWU005,

cycles.

22. In 80x8x mode, SRAS may be used to strobe the values of SBHE must meet parameter 266a, and SBHE parameters 266a and 264 are irrelevant, and parameter 268 must be met.

subsection 3.4.1.1.1), provided previous cycle completed.

and SWR or SCS low that indicates the start of the cycle.

TMS380 Second Generation Token-Ring User’s Guide,

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS

, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then

55 ns

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PARAMETER MEASUREMENT INFORMATION

, SRSX,

SCS

SRS0–SRS2,

SBHE

SRAS

256

264

Valid (see Note A)Valid

268265

266a

267

SIACK

SWR

SRD

(High)

SDDIR

SDBEN

†

SRDY

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

(see Note B)

†

When the TMS380C26 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers.

NOTES: A. In 80x8x mode, SRAS may be used to strobe the values of SBHE

meet parameter 266a, and SBHE 266a and 264 are irrelevant, and parameter 268 must be met.

B. In 8-bit 80x8x mode DIO reads, the SADH0–SADH7 contain don’t care data.

HI-Z

272a

282R

282a

260

259

Output Data Valid

, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters

283R

275

255

, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must

279

273a

286

HI-Z

261

261a

HI-ZHI-Z

Figure 28. 80x8x DIO Read Timing

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282b

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

80x8x DIO write timing

NO. PARAMETER MIN MAX UNIT

255 Delay from SRDY low to either SCS or SWR high 15 ns 256 Pulse duration, SRAS high 30 ns 262 Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SCS or SWR no longer low 25 ns 263 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SCS or SWR high 25 ns 264 Setup of SRSX, SRS0–SRS2, SCS, and SBHE to SRAS no longer high (see Note 21) 30 ns

265 Hold of SRSX, SRS0–SRS2, SCS, and SBHE after SRAS low 15 ns 266a Setup of SRAS high to SWR no longer high (see Note 22) 25 ns 267†Setup of SRSX, SRS0–SRS2 before SWR no longer high (see Note 21) 15 ns

268 Hold of SRSX, SRS0–SRS2 valid after SWR no longer low (see Note 22) 0 ns 272a Setup time of SRD, SWR, and SIACK high from previous cycle to SWR no longer high 55 ns 273a Hold time of SRD, SWR, and SIACK high after SWR high 55 ns

Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following

‡

276

279§Delay from SWR high to SRDY high impedance 65 ns

281a Hold of SDDIR low after SWR no longer active (see Note 21) 0 ns

282W Delay from SDDIR low to SDBEN low 25 ns 283W Delay from SCS or SWR high to SDBEN no longer low 25 ns

†

It is the later of SRD and SWR or SCS low that indicates the start of the cycle.

‡

This specification has been characterized to meet stated value.

This specification is provided as an aid to board design.

NOTES: 21. The “inactive” chip select is SIACK

access to the SIF (see

3.4.1.1.1)

275 Delay from SWR or SCS high to SRDY high (see Note 21) 35 ns

280 Delay from SWR low to SDDIR low (see Note 21) 25 ns

281 Delay from SWR high to SDDIR high (see note 21) 55 ns

Delay from SDBEN low to SRDY low (see

User’s Guide,

286 Pulse duration SWR high between DIO accesses (see Note 21) 55 ns

cycles.

22. In 80x8x mode, SRAS may be used to strobe the values of SBHE meet parameter 266a, and SBHE 266a and 264 are irrelevant, and parameter 268 must be met.

SPWU005, subsection 3.4.1.1.1)

TMS380 Second-Generation Token Ring User’s Guide

TMS380 Second Generation T oken-Ring

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must

, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters

, SPWU005, subsection

If SIF register is ready (no waiting required)

If SIF register is not ready (waiting required)

0 35

0 4000

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PARAMETER MEASUREMENT INFORMATION

, SRSX,

SCS

SRS0–SRS2,

SBHE

SRAS

Valid

264

256

265

268

SIACK

SWR

SRD

SDDIR

SDBEN

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

(see Note A)

†

When the TMS380C26 begins to drive SDBEN of the data buffers.

NOTE A: In 8-bit 80x8x mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.

†

SRDY

(High)

266a

267

272a

280

281a

282W

276

282b

HI-Z HI-Z

HI-Z

inactive, it has already latched the write data internally. Parameter 263 must be met to the input

262

283W

255

275

Data

273a

286

273a

281

279

263

HI-Z

Figure 29. 80x8x DIO Write Timing

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PARAMETER MEASUREMENT INFORMATION

TMS380C26

80x8x interrupt acknowledge timing – first SIACK

NO. PARAMETER MIN MAX UNIT

286 Pulse duration, SIACK high between DIO accesses (see Note 21) 55 ns 287 Pulse duration, SIACK low on first pulse of two pulses 62.5 ns

NOTE 21: The “inactive” chip select is SIACK in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

cycles.

SRD, SWR,

SCS

SIACK

287

First

pulse

286

Second

Figure 30. 80x8x Interrupt Acknowledge Timing – First SIACK Pulse

80x8x interrupt acknowledge timing – second SIACK pulse

NO. PARAMETER MIN MAX UNIT

255 Delay from SRDY low to SCS high 15 ns 259†Hold of SAD high-impedance after SIACK low (see Note 21) 0 ns 260 Setup of output data valid before SRDY low 0 ns 261†Delay from SIACK high to SAD high-impedance (see Note 21) 35 ns 261a Hold of output data valid after SIACK high (see Note 21) 0 ns 272a Setup of inactive data strobe high to SIACK no longer high 55 ns 273a Hold of inactive data strobe high after SIACK high 55 ns 275 Delay from SIACK high to SRDY high (see Note 21) 35 ns

Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately

‡

276 279†Delay from SIACK high to SRDY high impedance 65 ns

282a Delay from SDBEN low to SRDY low in a read cycle 35 ns 282R 283R Delay from SIACK high to SDBEN high (see Note 21) 35 ns

†

This specification is provided as an aid to board design.

‡

This specification has been characterized to meet stated value.

NOTE 21: The “inactive” chip select is SIACK

following access to the SIF

Delay from SIACK low to SDBEN low (see

User’s Guide,

cycles.

SPWU005, subsection 3.4.1.1.1), provided previous cycle completed

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

TMS380 Second Generation Token-Ring

4000 ns

55 ns

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PARAMETER MEASUREMENT INFORMATION

SCS, SRSX,

SRS0–SRS2,

SBHE

SIACK

SWR

SRD

SDDIR

SDBEN

SRDY

Only SCS needs to be inactive.

All others are Don’t Care.

272a

(High)

282R

276

†

HI-Z

282a

283R

275

255

279

273a

HI-Z

259

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

(see Note A)

†

SRDY is an active-low bus ready signal. It must be asserted before data output.

NOTE A: In 8-bit 80x8x mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.

HI-Z HI-Z

260

Output Data Valid

Figure 31. 80x8x Interrupt Acknowledge Timing – Second SIACK Pulse

261 261a

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NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

80x8x mode bus arbitration timing, SIF takes control

NO. PARAMETER MIN MAX UNIT

208a

208b 212 Delay from SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid 25 ns

224a Delay from SBCLK low in cycle I2 to SOWN low 25 ns 224c Delay from SBCLK low in cycle I2 to SDDIR low in DMA read 30 ns 230 Delay from SBCLK high to SHRQ high 25 ns 241 Delay from SBCLK high in TX cycle to SRD and SWR high, bus acquisition 25 ns 241a†Hold of SRD and SWR high-impedance after SOWN low, bus acquisition t

†

This specification has been characterized to meet stated value.

Setup of asynchronous signal SBBSY and SHLDA before SBCLK no longer high to guarantee recognition on that cycle

Hold of asynchronous signal SBBSY and SHLDA after SBCLK low to guarantee recognition on that cycle

15 ns

c(SCK)–15

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SIF Inputs:

SBCLK

SBBSY

SHLDA

SIF Outputs:

SHRQ

SRD, SWR

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NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

SIF MasterBus ExchangeUser Master

T1TXI2I1(T4)

208a

230

208b

241

•

SBHE

SADH0–SADH7, SADL0–SADL7,

SPH, SPL

SDDIR

SOWN

(see Note A)

NOTE A: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.

224c

224a

241a

212

Address Valid

Write

Read

212

Figure 32. 80x8x Mode Bus Arbitration Timing, SIF Takes Control

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x mode DMA read timing

NO. PARAMETER MIN MAX UNIT

205

206 207a Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SRD high 0 ns

207b Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SDBEN no longer low 0 ns 208a 208b Hold of asynchronous signal SRDY after SBCLK low to guarantee recognition on this cycle 15 ns

212 Delay from SBCLK low to address valid 25 ns 214 215 Pulse duration, SALE and SXAL high t

216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SRD high t 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns 218 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SALE or SXAL low t 223R Delay from SBCLK low in T4 cycle to SRD high (see Note 23) 25 ns 225R Delay from SBCLK low in T4 cycle to SDBEN high 25 ns 226†Delay from SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-impedance to SRD low 0 ns 227R Delay from SBCLK low in T2 cycle to SRD low 25 ns

229 231 Pulse duration, SRD low 2t 233 237R Delay from SBCLK high in the T2 cyle to SDBEN low 25 ns

247 Setup of data valid before SRDY low if parameter 208a not met 0 ns

†

This specification has been characterized to meet stated value.

NOTE 23: While the system interface DMA controls are active (i.e., SOWN

Setup of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid before SBCLK in T3 cycle no longer high

Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if parameters 207a and 207b not met

Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition on this cycle

Delay from SBCLK low in T1 cycle to SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-im-

†

pedance

Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL high-impedance after SBCLK low in

†

T1 cycle

Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL no longer high

is asserted), the SCS input is disabled.

c(SCK)

w(SCKL)

w(SCKH)

c(SCK)

w(SCKL)

15 ns

25 ns

–25 ns

–15 ns

0 ns –30 ns –15 ns

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SBCLK

PARAMETER MEASUREMENT INFORMATION

TWAIT

TMS380C26

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SPWS010A–APRIL 1992–REVISED MARCH 1993

T1T4T3T1TXT4

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•

SRAS

SBHE

(see Note B)

SWR

SRD

(see Note A)

SXAL

SALE

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

(see Note C)

SRDY

216

212

Extended Address

217

216

233

215

218

217

215

HI-Z

212

Valid

227R 223R

218

212

233

218

(High)

214

226

231

208a

247

205

†

207a

206

207b

216a

229

AddressDataAddress

SDBEN

(see Note A)

SDDIR

†

If parameter 208A is not met then valid data must be present before SRDY goes low.

NOTES: A. Motorola-style bus slaves hold SDTACK

B. In 8-bit 80x8x mode, SBHE C. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held

after T4 high.

/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.

active until the bus master deasserts SAS.

Figure 33. 80x8x Mode DMA Read Timing

237R

Low

208b

225R

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x mode DMA write timing

NO. PARAMETER MIN MAX UNIT

208a 208b Hold of asynchronous signal SRDY after SBCLK low to guarantee recognition on that cycle 15 ns

212 Delay from SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid 25 ns 215 Pulse duration, SALE and SXAL high t 216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SWR high t 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns 218 Hold of address valid after SALE, SXAL low t 219 Delay from SBCLK low in T2 cycle to output data and parity valid 39 ns 221 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SWR high t 223W Delay from SBCLK low to SWR high 25 ns 225W Delay from SBCLK high in T4 cycle to SDBEN high 25 ns 225WH Hold of SDBEN low after SWR, SUDS, and SLDS high t 227W Delay from SBCLK low in T2 cycle to SWR low 31 ns 232 Pulse duration, SWR low 2t

233 237W Delay from SBCLK high in T1 cycle to SDBEN low 25 ns

Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition on that cycle

Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL no longer high

c(SCK)

w(SCKL)

w(SCKH)

c(SCK)

w(SCKL)

c(SCK)

w(SCKL)

15 ns

–25 ns

–15 ns

–25 ns

–30 ns –15 ns

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SBCLK

SBHE

(see Note A)

PARAMETER MEASUREMENT INFORMATION

TWAIT

212

Valid

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NETWORK COMMPROCESSOR

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T1T4T3T2T1TXT4

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•

SRD

SWR

SXAL

SALE

SADL0–SADH7, SADH0–SADL7,

SPH, SPL

(see Note B)

SRDY

SDBEN

216

212

217

215

216

233

218

Extended Address

215

233

237W

217

212

227W

(HIGH)

218

219

208b

223W

232

216a

221

Output DataAddress

208a

225W

225WH

SDDIR

NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.

B. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held

after T4 high.

(HIGH)

Figure 34. 80x8x Mode DMA Write Timing

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

80x8x mode bus arbitration timing, SIF returns control

NO. PARAMETER MIN MAX UNIT

Delay from SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH, SRD, and SWR

†

220 223b†Delay from SBCLK low in I1 cycle to SBHE high-impedance 45 ns

224b Delay from SBCLK low in cycle I2 to SOWN high 25 ns 224d Delay from SBCLK low in cycle I2 to SDDIR high 30 ns 230 Delay from SBCLK high in cycle I1 to SHRQ low 25 ns 240†Setup of SRD, SWR, and SBHE high-impedance before SOWN no longer low 0 ns

†

This specification has been characterized to meet stated value.

high-impedance

User MasterBus ExchangeSIF Master

SBCLK

35 ns

(T2)(T1)I2I1T4T3

SHLDA

SIF Outputs:

SHRQ

(see Note A)

SRD, SWR

SBHE

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

SDDIR

SOWN

(see Note B)

NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus

transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.

B. While the system interface DMA controls are active (i.e., SOWN

SIF

220

SIF

WRITE

READ

230

220

HI-Z

240

223b

HI-Z

240

HI-Z

224d

224b

is asserted), the SCS input is disabled.

Figure 35. 80x8x Mode Bus Arbitration Timing, SIF Returns Control

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PARAMETER MEASUREMENT INFORMATION

80x8x mode bus release timing

NO. PARAMETER MIN MAX UNIT

208a Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee recognition 15 ns 208b Hold of asynchronous input SBRLS low after SBCLK low to guarantee recognition 15 ns 208c Hold of SBRLS low after SOWN high 0 ns

T(W or 2) T3 T4 T1 T2

SBCLK

208a

SBRLS

(see Note A)

SOWN

208b

208c

NOTES: A. The System Interface ignores the assertion of SBRLS

the assertion of SBRLS internally started, then the System Interface will release the bus before starting another.

B. If SBERR

of the value of SRDY Interface will then release control of the system bus. The System Interface ignores the assertion of SBERR a DMA bus cycle on the system bus. When SBERR releases the bus upon completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the System Interface are not defined after a system bus error.

C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer

and whenever the increment of the DMA Address Register carries beyond the least significant 16 bits. D. SDTACK E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,

the signal is also specified to hold its previous value (including high-impedance) until the start of that SBCLK transition.

is asserted when the System Interface controls the system bus, then the current bus transfer is completed, regardless

is not sampled to verify that it is deasserted.

, it will complete any internally started DMA cycle and relinquish control of the bus. If no DMA transfer has

. If the BERETRY register is non-zero, the cycle will be retried. If the BERETRY register is zero, the System

Figure 36. 80x8x Mode Bus Release Timing

if it does not own the system bus. If it does own the bus, then when it detects

if it is not performing

is properly asserted and BERETRY is zero, however, the System Interface

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PARAMETER MEASUREMENT INFORMATION

68xxx DIO read timing

NO. PARAMETER MIN MAX UNIT

255 Delay from SDTACK low to either SCS, SUDS, or SLDS high 15 ns 259†Hold of SAD high-impedance after SUDS or SLDS low (see Note 21) 0 ns 260 Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SDTACK low 0 ns

Delay from SCS, SUDS, or SLDS high to SADH0–SADH7, SADL0–SADL7, SPH, and SPL

†

261 261a Hold of output data valid after SUDS or SLDS no longer low (see Note 21) 0 ns

267 Setup of register address before SUDS or SLDS no longer high (see Note 21) 15 ns 268 Hold of register address valid after SUDS or SLDS no longer low (see Note 22) 0 ns 272 Setup of SRNW before SUDS or SLDS no longer high (see Note 21) 15 ns 273 Hold of SRNW after SUDS or SLDS high 0 ns 273a Hold of SIACK high after SUDS or SLDS high 55 ns 275 Delay from SCS, SUDS, or SLDS high to SDTACK high (see Note 21) 35 ns

276 279†Delay from SUDS or SLDS high to SDTACK high impedance 65 ns

282a Delay from SDBEN low to SDTACK low 35 ns 282R 283R Delay from SUDS or SLDS high to SDBEN high (see Note 21) 35 ns

286 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 21) 55 ns

†

This specification is provided as an aid to board design.

‡

This specification has been characterized to meet stated value.

NOTES: 21. The “inactive” chip select is SIACK

high-impedance (see Note 21)

Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately fol-

‡

lowing access to the SIF

Delay from SUDS or SLDS low to SDBEN low (see

Guide,

SPWU005, subsection 3.4.1.1.1) provided the previous cycle completed

cycles.

22. In 80x8x mode, SRAS may be used to strobe the values of SBHE meet parameter 266a, and SBHE 266a and 264 are irrelevant, and parameter 268 must be met.

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters

TMS380 Second Generation Token-Ring User’s

, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must

35 ns

4000 ns

55 ns

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PARAMETER MEASUREMENT INFORMATION

SCS, SRSX,

SRS0, SRS1

SIACK

SRNW

SUDS,

SLDS

SDDIR

SDBEN

SDTACK

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

Valid

267

272

(High)

282R

276

†

HI-Z

HI-Z HI-Z

282a

259

Output Data Valid

273

283R

275

255

260

268

273a

286

279

HI-Z

261

261a

†

SDTACK

is an active-low bus ready signal. It must be asserted before data output.

Figure 37. 68xxx DIO Read Timing

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282b

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx DIO write timing

NO. PARAMETER MIN MAX UNIT

255 Delay from SDTACK low to either SCS, SUDS or SLDS high 15 ns 262 Setup of write data valid before SUDS or SLDS no longer low 25 ns 263 Hold of write data valid after SUDS or SLDS high 25 ns 267§Setup of register address before SUDS or SLDS no longer high (see Note 21) 15 ns 268 Hold of register address valid after SUDS or SLDS no longer low (see Note 22) 0 ns 272 Setup of SRNW before SUDS or SLDS no longer high (see Note 21) 15 ns 272a Setup of inactive SUDS or SLDS high to active data strobe no longer high 55 ns 273 Hold of SRNW after SUDS or SLDS high 0 ns 273a Hold of inactive SUDS or SLDS high after active data strobe high 55 ns 275 Delay from SCS, SUDS or SLDS high to SDTACK high (see Note 21) 35 ns

Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the

‡

276 279†Delay from SUDS or SLDS high to SDTACK high impedance 65 ns

280 Delay from SUDS or SLDS low to SDDIR low (see Note 21) 25 ns 281 Delay from SUDS or SLDS high to SDDIR high (see Note 21) 55 ns 281a Hold of SDDIR low after SUDS or SLDS no longer active (see Note 21) 0 ns

282W Delay from SDDIR low to SDBEN low 25 ns 283W Delay from SUDS or SLDS high to SDBEN no longer low 25 ns 286 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 21) 55 ns

†

This specification is provided as an aid to board design.

‡

This specification has been characterized to meet stated value.

It is the later of SRD

NOTES: 21. The “inactive” chip select is SIACK

immediately following access to the SIF

Delay from SDBEN low to SDTACK low (see

Ring User’s Guide,

and SWR or SCS low that indicates the start of the cycle.

cycles.

22. In 80x8x mode, SRAS may be used to strobe the values of SBHE meet parameter 266a, and SBHE 266a and 264 are irrelevant, and parameter 268 must be met.

SPWU005, subsection 3.4.1.1.1)

, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters

TMS380 Second Generation T oken-

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

If SIF register is ready (no waiting required)

If SIF register is not ready (waiting required)

, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must

4000 ns

0 35

0 4000

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SPWS010A–APRIL 1992–REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

SCS SRSX,

SRS0, SRS1

SIACK

SRNW

SUDS

SLDS

(see Note A)

SDDIR

SDBEN

SDTACK

Valid

267

272

(High)

‡

†

HI-Z

272a

280

282W

276

273

283W

275

255

268

273a

286

273a

281

281a

279

HI-Z

282b

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

†

SDTACK is an active-low bus ready signal. It must be asserted before data output.

‡

When the TMS380C16 begins to drive SDBEN of the data buffers.

NOTE A: For 68xxx mode, skew between SLDS

to a data strobe edge use the later occurring edge. Events defined by two data strobes edges, such as parameter 286, are measured between latest and earlier edges.

inactive, it has already latched the write date internally. Parameter 263 must be met to the input

and SUDS must not exceed 10 ns. Provided this limitation is observed, all events referenced

262

Figure 38. 68xxx DIO Write Timing

Data

263

(see Note 36)

HI-ZHI-Z

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NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx interrupt acknowledge cycle timing

NO. PARAMETER MIN MAX UNIT

255 Delay from SDTACK low to either SCS or SUDS, or SIACK high 15 ns 259†Hold of SAD high-impedance after SIACK no longer high (see Note 21) 0 ns 260 Setup of output data valid before SDTACK no longer high 0 ns 261†Delay from SIACK high to SAD high-impedance (see Note 21) 35 ns 261a Hold of output data valid after SCS or SIACK no longer low (see Note 21) 0 ns 267§Setup of register address before SIACK no longer high (see Note 21) 15 ns 272a Setup of inactive high SIACK to active data strobe no longer high 55 ns 273a Hold of inactive SRNW high after active data strobe high 55 ns 275 Delay from SCS or SRNW high to SDTACK high (see Note 21) 35 ns

Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately

‡

276 279†Delay from SIACK high to SDTACK high impedance 65 ns

282a Delay from SDBEN low to SDTACK low in a read cycle 35 ns 282R 283R Delay from SIACK high to SDBEN high (see Note 21) 35 ns

286 Pulse duration, SIACK high between DIO accesses (see Note 21) 55 ns

†

This specification is provided as an aid to board design.

‡

This specification has been characterized to meet stated value.

It is the later of SRD

NOTE 21: The “inactive” chip select is SIACK

following access to the SIF

Delay from SIACK low to SDBEN low (see SPWU005, subsection 3.4.1.1.1) provided the previous cycle completed

and SRD or SCS low that indicates the start of the cycle.

in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge

cycles.

TMS380 Second Generation Token-Ring User’s Guide,

4000 ns

55 ns

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PARAMETER MEASUREMENT INFORMATION

SCS, SRSX,

SRS0, SRS1,

SBHE

SIACK

Only SCS needs to be Inactive.

All Others are Don’t Care.

267

SRNW

SLDS

SDDIR

SDBEN

SDTACK

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

(see Note A)

†

SDTACK

NOTE A: Internal logic will drive SDTACK

is an active-low bus ready signal. It must be asserted before data output.

(High)

†

HI-Z

259

272a

282R

283R

276

282a

260

Output Data Valid

high and verify that it has reached a valid high level before three-stating the signal.

275

255

279

286

273a

286

261

261a

HI-Z

HI-ZHI-Z

Figure 39. 68xxx Interrupt Acknowledge Cycle Timing

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NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx mode bus arbitration timing, SIF takes control

NO. PARAMETER MIN MAX UNIT

208a 208b Hold of asynchronous input SBGR after SBCLK low to guarantee recognition on this cycle 15 ns

212 Delay from SBCLK low to address valid 25 ns 224a Delay from SBCLK low in cycle I2 to SOWN low (see Note 24) 25 ns 224c Delay from SBCLK low in cycle I2 to SDDIR low in DMA read 30 ns 230 Delay from SBCLK high to either SHRQ low or SBRQ high 25 ns 241 Delay from SBCLK high in TX cycle to SUDS and SLDS high 25 ns 241a†Hold of SUDS, SLDS, SRNW, and SAS high-impedance after SOWN low, bus acquisition t

†

This specification has been characterized to meet stated value.

NOTE 24: Motorola-style bus slaves hold SDTACK

Setup of asynchronous input SBGR before SBCLK no longer high to guarantee recognition on this cycle

active until the bus master deasserts SAS.

15 ns

c(SCK)–15

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SIF Inputs:

SBCLK

SBGR

SBERR,

SDTACK,

SBBSY

SIF Outputs:

SBRQ

(see Note A)

PARAMETER MEASUREMENT INFORMATION

208b

208a

230

TMS380C26

NETWORK COMMPROCESSOR

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SIF MasterBus ExchangeUser Master

T2T1TXI2I1(T4)

230

208a

SAS

, SLDS,

•

SADH0–SADH7,

SADL0–SADL7,

NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the

SUDS

SRNW

SPH, SPL

SDDIR

SOWN

(see Note B)

system interface deasserts SBRQ

B. While the system interface DMA controls are active (i.e., SOWN

on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.

(Input)

HI-Z

is asserted), the SCS input is disabled.

208b 241

Output

241

READ

WRITE

212

SIF

224c

WRITE

READ

224a

241a

Figure 40. 68xxx Mode Bus Arbitration Timing, SIF Takes Control

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

68xxx mode DMA read timing

NO. PARAMETER MIN MAX UNIT

205 Setup of input data valid before SBCLK in T3 cycle no longer high 15 ns 206 Hold of input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 15 ns 207a Hold of input data valid after data strobe no longer low 0 ns 207b Hold of input data valid after SDBEN no longer low 0 ns

208a 208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle 15 ns 209 Pulse duration, SAS, SUDS, and SLDS high 210 Delay from SBCLK high in T2 cycle to SUDS and SLDS active 25 ns

212 Delay from SBCLK low to address valid 25 ns 214†Delay from SBCLK low in T2 cycle to SAD high-impedance 25 ns 215 Pulse duration, SALE and SXAL high t 216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SUDS and SAS high t 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns 218 Hold of address valid after SALE, SXAL low t 222 Delay from SBCLK high to SAS low 25 ns 223R Delay from SBCLK low in T4 cycle to SUDS, SLDS, and SAS high (see Note 25) 25 ns 225R Delay from SBCLK low in T4 cycle to SDBEN high 25 ns 229†Hold of SAD high-impedance after SBCLK low in T4 cycle 0 ns 233 Setup of address valid before SALE or SXAL no longer high t 233a Setup of address valid before SAS no longer high t 237R Delay from SBCLK high in the T2 cycle to SDBEN low 25 ns

239 Pulse duration, SAS, SUDS, and SLDS 247 Setup of data valid before SDTACK low if parameter 208a not met 0 ns

†

This specification has been characterized to meet stated value.

NOTE 25: While the system interface DMA controls are active (i.e., SOWN

Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition on this cycle

is asserted), the SCS input is disabled.

c(SCK)

w(SCKL)

c(SCK)

w(SCKL)

w(SCKH)

w(SCKL) w(SCKL)

c(SCK)

w(SCKH)

15 ns

–25

–25 ns

–15 ns

–15 ns –15 ns

–30

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SBCLK

SAS

(see Note A)

SUDS,

SLDS

SRNW

SXAL

216

PARAMETER MEASUREMENT INFORMATION

TWAIT

222

210

218

(High)

217

215

217

239

223R

TMS380C26

NETWORK COMMPROCESSOR

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T1T4T3T2T1TXT4

S7S6S5S4S3S2S1

209

216

•

SADL0–SADH7, SADH0–SADL7,

(see Notes B and C)

†

If parameter 208a is not met, then valid data must be present before SDTACK

NOTES: A. Motorola-style bus slaves hold SDTACK

B. All VSS pins should be routed to minimize inductance to system ground. C. On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN

becomes no longer active.

SALE

SPH, SPL

SDTACK

SDDIR

SDBEN

(see Note A)

212

233

Extended Address

active until the bus master deasserts SAS.

215

goes low.

212

233

218

233a

237R

214

208b

247

†

208a

205

216a

229

206

207a

HI-ZData InAddress

207b

225R

Figure 41. 68xxx Mode DMA Read Timing

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx mode DMA write timing

NO. PARAMETER MIN MAX UNIT

208a 208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle 15 ns 209 Pulse duration, SAS, SUDS, and SLDS high 211 Delay from SBCLK high in T2 cycle to SUDS and SLDS active 25 ns

211a Delay of output data valid to SUDS and SLDS no longer high t 212 Delay from SBCLK low to address valid 25 ns 215 Pulse duration, SALE and SXAL high t 216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SUDS and SAS high t 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns 218 Hold of address valid after SALE, SXAL low t 219 Delay from SBCLK low in T2 cycle to output data and parity valid 39 ns 221 Hold of output data, parity valid after SUDS and SLDS high t 222 Delay from SBCLK high to SAS low 25 ns 223W Delay from SBCLK low to SUDS, SLDS, and SAS high 25 ns 225W Delay from SBCLK high in T4 cycle to SDBEN high 25 ns 225WH Hold of SDBEN low after SUDS and SLDS high t 233 Setup of address valid before SALE or SXAL no longer high t 233a Setup of address valid before SAS no longer high t 237W Delay from SBCLK high in T1 cycle to SDBEN low 25 ns

239 SAS pulse duration

243 Pulse duration, SUDS and SLDS

Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition on this cycle

c(SCK)

w(SCKL)

c(SCK)

w(SCKL)

w(SCKH)

c(SCK)

w(SCKL) w(SCKL) w(SCKL)

c(SCK)

w(SCKH)

c(SCK)

w(SCKH)

15 ns

–25

–15 ns

–25 ns

–15 ns

–25 ns –15 ns –15 ns

–30

–25

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•

SBCLK

SAS

SUDS,

SLDS

SRNW

SXAL

SALE

SADL0–SADH7, SADH0–SADL7,

SPL, SPH

SDTACK

(see Notes A and B)

216

Low

212

PARAMETER MEASUREMENT INFORMATION

217

215

216

233

Extended Address

222

233a

218

215

212

233

211

211a

217

218

219

TWAIT

239

208a

243

Output DataAddress

223W

216a

209

221

TMS380C26

NETWORK COMMPROCESSOR

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T1T4T3T2T1TXT4

SDDIR

SDBEN

NOTES: A. All VSS pins should be routed to minimize inductance to system ground.

B. On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN

becomes no longer active.

237W

Figure 42. 68xxx Mode DMA Write Timing

208b

225W

225WH

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx mode bus arbitration timing, SIF returns control

NO. PARAMETER MIN MAX UNIT

220†Delay from SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS high-impedance, bus release 35 ns 223b†Delay from SBCLK low in I1 cycle to SBHE/SRNW high-impedance 45 ns 224b Delay from SBCLK low in cycle I2 to SOWN high 25 ns 224d Delay from SBCLK low in cycle I2 to SDDIR high 30 ns 230 Delay from SBCLK high to either SHRQ low or SBRQ high 25 ns 240†Setup of SUDS, SLDS, SRNW, and SAS control signals high-impedance before SOWN no longer low 0 ns

†

This specification has been characterized to meet stated value.

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SIF Inputs:

SBCLK

SBGR

SDTACK

PARAMETER MEASUREMENT INFORMATION

TMS380C26

NETWORK COMMPROCESSOR

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UserBus ExchangeSIF Master

T1I2I1T4T3T2

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

•

SIF Outputs:

SBRQ

(see Note A)

SAS

, SUDS,

SLDS

SRNW

SADH0–SADH7,

SADL0–SADL7,

SPH, SPL

SDDIR

SOWN

230

READ

WRITE

SIF

WRITE

READ

220

240

223b

HI-Z

220

HI-Z

224d

224b

NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system

interface deasserts SBRQ

on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.

Figure 43. 68xxx Mode Bus Arbitration Timing, SIF Returns Control

TMS380C26

NETWORK COMMPROCESSOR

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PARAMETER MEASUREMENT INFORMATION

68xxx mode bus release and error timing

NO. PARAMETER MIN MAX UNIT

208a Setup of asynchronous input before SBCLK no longer high to guarantee recognition 15 ns 208b Hold of asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to guarantee recognition 15 ns 208c Hold of SBRLS low after SOWN high 0 ns 236 Setup of SBERR low before SDTACK no longer high if parameter 208a not met 30 ns

T(W or 2) T3 T4 T1 T2

SBCLK

208a

SBRLS

(see Note A)

SOWN

SBERR

(see Note B)

SDTACK

NOTES: A. The System Interface ignores the assertion of SBRLS

the assertion of SBRLS internally started, then the System Interface will release the bus before starting another.

B. If SBERR

of the value of SDTACK Interface will then release control of the system bus. The System Interface ignores the assertion of SBERR a DMA bus cycle on the system bus. When SBERR releases the bus upon completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the System Interface are not defined after a system bus error.

C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer

and whenever the increment of the DMA Address Register carries beyond the least significant 16 bits.

D. SDTACK E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,

the signal is also specified to hold its previous value (including high-impedance) until the start of that SBCLK transition.

is asserted when the System Interface controls the system bus, then the current bus transfer is completed, regardless

is not sampled to verify that it is deasserted.

, it will complete any internally started DMA cycle and relinquish control of the bus. If no DMA transfer has

. If the BERETRY register is non-zero, the cycle will be retried. If the BERETRY register is zero, the System

208b

208a

208b

208c

236

if it does not own the system bus. If it does own the bus, then when it detects

if it is not performing

is properly asserted and BERETRY is zero, however, the System Interface

Figure 44. 68xxx Mode Bus Release and Error Timing

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PARAMETER MEASUREMENT INFORMATION

normal completion with delayed start

T1 T(W or 2) T3 T4

SBCLK

SDTACK

SBERR

SHALT

rerun cycle with delayed start

T1 T2 T3 T4 TH

SBCLK

SDTACK

†

TH T1

SBERR

SHALT

SOWN

†

Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms shown.

Figure 45. 68xxx Bus Halt and Retry Cycle Waveforms

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MECHANICAL DATA

JEDEC plastic leaded quad flat package (PQ suffix)

Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and circuit performance characteristics remain stable when the devices are operated in high-humidity conditions. The packages are intended for surface mounting on solder lands on 0,635 (0.025) centers. Leads require no additional cleaning or processing when used in soldered assembly.

0,635 (0.025) NOM

0,254 (0.010) NOM

4,57 (0.180) 4,06 (0.160)

0,76 (0.030) NOM

JEDEC

OUTLINE

MO–069–AD

MO–069–AE

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NO. OF

TERMINALS

100

132

POST OFFICE BOX 1443 • HOUSTON, TEXAS

MIN MAX

22,28

(0.877)

27,36

(1.077)

77251–1443

(0.883)

(1.083)

22,43

27,50

MIN MAX

18,97

(0.747)

24,05

(0.947)

(0.753)

(0.953)

19,13

24,21

MIN MAX

15,16

(0.597)

20,24

(0.797)

15,32

(0.603)

20,40

(0.803)

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TMS380C26 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual