Texas Instruments TMS370C742ANT, TMS370C742AN2T, TMS370C742AFNT Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS370Cx4x

8-BIT MICROCONTROLLER

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CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High Volume

Production

– One-Time-Programmable (OTP) Devices

for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive

T emperature Ranges

– Clock Options:

– Divide-by-1 (2 MHz–5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK)

– Voltage (V

) 5 V ± 10%

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 4K Bytes or 8K Bytes

– EPROM: 8K Bytes – Data EEPROM: 256 Bytes – Static RAM: 256 Bytes Usable as

Registers

Two 16-Bit General-Purpose Timers – Software Configurable as

Two 16-Bit Event Counters, or

Two 16-Bit Pulse Accumulators, or

Three 16-Bit Input Capture Functions, or

Four Compare Registers, or

Two Self-Contained

Pulse-Width-Modulation (PWM)

Functions

Serial Communications Interface 1 (SCI1) – Asynchronous and Isosynchronous

†

Modes – Full Duplex, Double Buffered RX and TX – Two Multiprocessor Communications

Formats

CMOS/Package/TTL Compatible I/O Pins – All Peripheral Function Pins Software

Configurable for Digital I/O – 40-Pin Plastic and Ceramic Dual-In-Line

Packages/27 Bidirectional, 5 Input Pins – 44-Pin Plastic and Ceramic Leaded Chip

Carrier Packages/27 Bidirectional, 9

Input Pins

On-Chip 24-Bit Watchdog Timer

Eight-Bit ADC1 – Four Channels in 40-Pin Packages – Eight Channels in 44-Pin Packages

Flexible Interrupt Handling

TMS370 Series Compatibility

Workstation/PC-Based Development System – C Compiler Support – Real-Time In-Circuit Emulation – C Source Debug – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – EEPROM/EPROM Programming

JC, JD, N, AND NJ PACKAGES

(TOP VIEW)

FN AND FZ PACKAGES

(TOP VIEW)

T2AEVT

T2AIC2/PWM

T2AIC1/CR

RESET

INT1 INT2 INT3 V

A7 A6

A5 A4 A3 A2 A1 A0 D7 D4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 V

CC3

SS3

AN3 AN2 D6 D3

MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 AN5 AN4 V

SS3

39 38 37 36 35 34 33 32 31 30 29

18 19

7 8 9 10 11 12 13 14 15 16 17

INT1 INT2 INT3 V

CC3

A7 A6

A5 A4 A3

20 21 22 23

SCITXD

SCIRXD

SCICLK

54321644

RESET

T2AIC1/CR

T2AIC2/PWM

T2AEVTB2B1

AN0

AN1

AN2

A2A1A0

D7D4D6

42 41 4043

24 25 26 27 28

AN3

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

†

Isosynchronous = Isochronous

TMS370Cx4x 8-BIT MICROCONTROLLER

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Pin Descriptions

NO.

TYPE

†

DESCRIPTION

DIP (40) LCC (44)

A0 A1 A2 A3 A4 A5 A6 A7

18 17 16 15 14 13 11 10

20 19 18 17 16 15 13 12

I/O Port A pins are general-purpose bidirectional I/O ports.

B0 B1 B2

39 40

1 2

I/O Port B pins are general-purpose bidirectional I/O ports.

D3 D4 D5 D6 D7

21 20 35 22 19

23 22 40 24 21

I/O

Port D pins are general-purpose bidirectional I/O ports. D3 is also configurable as SYSCLK.

AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7

— — 23 24 — — 27 28

25 26 27 28 30 31 32 33

Analog-to-digital converter 1 (ADC1) analog input channels or positive reference pins; any ADC1 channel can be programmed as general-purpose input pin (E port) if not used as an analog input or reference channel.

CC3

SS3

26 25

11 29

ADC1 converter positive supply voltage and optional positive reference input pin ADC1 converter ground supply and low reference input pin

INT1 INT2 INT3

6 7 8

7 8 9

I I/O I/O

External (non-maskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin

T1IC/CR T1PWM T1EVT

31 30 29

36 35 34

I/O

Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin Timer 1 pulse-width-modulation output pin/general-purpose bidirectional pin Timer 1 external event input pin/general-purpose bidirectional pin

T2AIC1/CR T2AIC2/PWM T2AEVT

4 3 2

5 4 3

I/O

Timer 2A input capture/counter reset input pin/general-purpose bidirectional pin Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer 2A external event input pin/general-purpose bidirectional pin

SCITXD SCIRXD SCICLK

38 37 36

43 42 41

I/O

SCI transmit data output pin/general-purpose bidirectional pin

‡

SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

RESET 5 6 I/O

System reset bidirectional pin. As input, RESET initializes microcontroller; as open-drain output, RESET

indicates detection of an internal fault by the watchdog or oscillator fault cir-

cuit.

MC 34 39 I

Mode control input pin; enables the EEPROM write-protection-override (WPO) mode, also EPROM VPP.

XTAL1 XTAL2/CLKIN

32 33

37 38

Internal-oscillator output for crystal Internal-oscillator crystal input/external clock source input

10 14

Positive supply voltage Ground reference

†

I = input, O = output

‡

The three-pin configuration SCI is referred to as SCI1.

TMS370Cx4x

8-BIT MICROCONTROLLER

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functional block diagram

Interrupts

Clock Options Divide-by-4 or

Divide-by-1(PLL)

System Control

INT1

AN0–AN7

INT2 INT3 MC RESET

XTAL1

A-to-D

Converter 1

Timer 2A

Timer 1

Watchdog

Serial

Communications

Interface 1

RAM

256 Bytes

(Usable as Registers)

Program Memory

ROM: 4K or 8K Bytes

EPROM:8K Bytes

Data EEPROM 0 or 256 Bytes

CPU

XTAL2/ CLKIN

SCIRXD SCITXD SCICLK

T2AIC1/CR T2AEVT T2AIC2/PWM

T1IC/CR T1EVT T1PWM

CC3

SS3

Port BPort A Port D

83 5

(40-Pin: 4 CH) (44-Pin: 8 CH)

40-PIN DIP: AN2, AN3,

AN6, AN7

44-PIN PLCC:AN0–AN7

description

The TMS370C040A, TMS370C042A, TMS370C340A, TMS370C342A, TMS370C742A, and SE370C742A devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx4x refers to these devices. TMS370 family provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations.

The TMS370Cx4x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technology. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx4x devices attractive in system designs for automotive electronics, industrial motor, computer peripheral control, telecommunications, and consumer applications.

The TMS370Cx4x devices contain the following on-chip peripheral modules:

Eight-channel (for 44 pin device) or four-channel (for 40-pin device) 8-bit analog-to-digital converter 1 (ADC1)

Serial communications interface 1 (SCI1)

Two 16-bit general-purpose timers (one with an 8-bit prescaler)

TMS370Cx4x 8-BIT MICROCONTROLLER

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description (continued)

One 24-bit general-purpose watchdog timer

Table 1 provides an overview of the various memory configurations of the TMS370Cx4x devices.

Table 1. Memory Configurations

PROGRAM MEMORY (BYTES) DATA MEMORY (BYTES)

PACKAGES

DEVICE

ROM EPROM RAM EEPROM

44 PIN/PLCC/CLCC OR

40 PIN PDIP/CDIP/PSDIP/CSDIP

TMS370C040A 4K — 256 256

FN-PLCC

N-PDIP

NJ-PSDIP

†

TMS370C042A 8K — 256 256

FN-PLCC

N-PDIP

NJ-PSDIP

†

TMS370C340A 4K — 256 —

FN-PLCC

N-PDIP

NJ-PSDIP

†

TMS370C342A 8K — 256 —

FN-PLCC

N-PDIP

NJ-PSDIP

†

TMS370C742A — 8K 256 256

FN-PLCC

N-PDIP

NJ-PSDIP

†

SE370C742A

‡

— 8K 256 256

FZ-CLCC

JD-CDIP

JC-CSDIP

†

The NJ designator for the 40-pin plastic shrink DIP package was known formerly as the N2. The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.

‡

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 (standard oscillator)

Enabled or disabled

Simple

or Divide-by-1 (PLL)

The 4K bytes and 8K bytes of mask-programmable ROM in the TMS370C040A, TMS370C042A, TMS370C340A and TMS370C342A are replaced in the TMS370C742 with 8K bytes of EPROM while all other available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the TMS370C340A and TMS370C342A devices. The OTP (TMS370C742A) device and the reprogrammable device (SE370C742A) are available.

TMS370C742A (OTP) devices are available in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx4x family or for low-volume production runs when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

TMS370Cx4x

8-BIT MICROCONTROLLER

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description (continued)

The SE370C742A has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development/prototyping phase of design. The SE370C742A device allows quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx4x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx4x features advanced register-to-register architecture that allows arithmetic and logical operations without requiring an accumulator (e.g., ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx4x family is fully instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family.

The TMS370Cx4x family offers an 8-channel ADC1 with 8-bit accuracy for the 44-pin PLCC packages and also offers a 4-channel ADC1 for the 40-pin DIP packages. The 33-µs conversion time at 5-MHz SYSCLK and the variable sample period, combined with selectable positive reference voltage sources, turn analog signals into digital data.

The serial communications interface 1 (SCI1) module is a built-in serial interface that can be programmed to be asynchronous or isosynchronous to give two methods of serial communications. The SCI allows standard RS-232-C communications with other common data transmission equipment. The CPU takes no part in serial communications except to write data to be transmitted to a register and to read data received from a register.

The TMS370Cx4x family provides the system designer with very economical, efficient solutions to real-time control applications. The TMS370 family extended development system (XDS) and compact development tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx4x into an ever-increasing number of complex applications. The application source code can be written in assembly and C languages, and the output code can be generated by the linker. The TMS370 family XDS communicates through a standard RS-232-C interface with a personal computer, allowing use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation, as well as reduced time-to-market cycle.

The TMS370Cx4x family together with the TMS370 family XDS, CDT370, starter kit, software tools, the SE370C742A reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution for the needs of the system designer.

XDS and CDT are trademarks of Texas Instruments Incorporated.

TMS370Cx4x 8-BIT MICROCONTROLLER

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central processing unit (CPU)

The CPU used on the TMS370Cx4x device is the high-performance 8-bit TMS370 CPU module. The ’x4x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x4x instruction map is shown in T able 17 in the TMS370Cx4x instruction set overview section.

The ’370Cx4x CPU architecture provides the following components:

CPU registers: – A stack pointer (SP) that points to the last entry in the memory stack – A status register (ST) that monitors the operation of the instructions and contains the

global-interrupt-enable bits

– A program counter (PC) that points to the memory location of the next instruction to be executed

Figure 1 illustrates the CPU registers and memory blocks.

Reserved

†

Peripheral File

Not Available

‡

0FFFh 1000h

1F00h 1FFFh 2000h 5FFFh

6000h

Interrupts and Reset Vectors;

Trap Vectors

10FFh 1100h

1EFFh

Reserved

†

7FFFh

RAM (Includes up to 256-Byte Registers File)

015

Program Counter

Legend:

Z=Zero

IE1=Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 interrupts Enable

IE1IE2ZNC

01234567

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R127

0000h 0001h

0002h

007Fh

R255

0003h

00FFh

256-Byte Data EEPROM

6FFFh 7000h

8K-Byte ROM/EPROM (6000h–6FFFh)

4K-Byte ROM (7000h–7FFFh)

7FC0h

7FBFh

00FFh 0100h

256-Byte RAM (0000h–00FFh)

0000h

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

TMS370Cx4x

8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

A memory map that includes: – 256-byte general-purpose RAM that can be used for data memory storage, program instructions,

general-purpose registers, or the stack

– A peripheral file that provides access to all internal peripheral modules, system-wide control functions

and EEPROM/EPROM programming control

– 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

– 4K- or 8K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. The stack is used typically to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

IE2

IE1 Reserved Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

TMS370Cx4x 8-BIT MICROCONTROLLER

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program counter (PC) (continued)

Memory

Program Counter (PC)

60 00

PCH PCL

60 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx4x family architecture is based on the Von Neumann architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx4x family provides memory-mapped RAM, ROM, data EEPROM, EPROM, input/output pins, peripheral functions, and system interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EPROM and EEPROM memory programming, and system-wide control functions. The peripheral file is located between 1010h and 107Fh and is logically divided into seven peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed.

TMS370Cx4x

8-BIT MICROCONTROLLER

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memory map (continued)

256-Byte RAM (Register File/Stack)

Reserved

Peripheral File

Reserved

256-Byte Data EEPROM

Not Available

8K-Byte ROM or EPROM

(0000h–7FFFh)

7FC0hTrap 15-0 7FE0hReserved 7FECh

Serial Comm I/F RX

7FEEh

Timer 1

7FF0h

Interrupt 3

7FF2h

Interrupt 2

7FF4h

Interrupt 1

7FF8h

Reset

1000hReserved 1010hSystem Control 1020hDigital Port Control 1030h

ADC1 Peripheral Control

1040hTimer 1 Peripheral Control

Vectors

7FDFh 7FEBh 7FEDh 7FEFh 7FF1h 7FF3h 7FF5h

7FF9h

100Fh 101Fh 102Fh 103Fh 104Fh

– – – – –

– – – – – – –

–

4K-Byte ROM

(7000h–7FFFh)

Not Available

Reserved

SCI1 Peripheral Control

Timer 2A Peripheral Control

Reserved

A-D Converter 1

Timer 2A

Serial Comm I/F TX

7FFAh 7FFBh

–

– 7FFCh 7FFDh– 7FFEh 7FFFh

–

1050h 1060h 1070h

105Fh 106Fh 107Fh

–

1080h 10FFh–

0000h

0100h

00FFh

1000h

10FFh

1100h

1EFFh

1F00h

1FFFh

2000h

5FFFh

6000h

6FFFh

7000h

7FBFh 7FC0h

FFFFh

0FFFh

7FFFh

8000h

Interrupts and Reset

Vectors; Trap Vectors

Reserved 7FF6h 7FF7h–

Figure 3. TMS370Cx4x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx4x devices contain 256 bytes of internal RAM memory mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255).

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx4x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 shows the TMS370Cx4x PF address map.

TMS370Cx4x 8-BIT MICROCONTROLLER

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peripheral file (PF) (continued)

Table 4. TMS370Cx4x Peripheral File Address Map

БББББ

ADDRESS RANGE

БББББ

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

DESCRIPTION

1000h–100Fh

P000–P00F Reserved for factory test

1010h–101Fh

P010–P01F

System and EPROM/EEPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

P030–P03F

Reserved

1040h–104Fh

P040–P04F

Timer 1 registers

1050h–105Fh

P050–P05F Serial communications interface 1 registers

1060h–106Fh

P060–P06F

Timer 2A registers

1070h–107Fh

P070–P07F

Analog-to-digital converter 1 registers

1080h–10FFh

P080–P0FF

Reserved

data EEPROM

The TMS370Cx4x devices, containing 256 bytes of data EEPROM, have memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370

Family Data Manual

(literature number SPNS014B). The data EEPROM features include the following:

Programming: – Bit-, byte-, and block-write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A (see Table 5).

– In-circuit programming capability. There is no need to remove the device to program it.

Write protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write protection active. There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

T able 5. Data EEPROM and PROGRAM EPROM Control Register Memory Map

ADDRESS SYMBOL NAME

P01A DEECTL DATA EEPROM Control Register P01B — Reserved P01C EPCTL Program EPROM Control Register

TMS370Cx4x

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program EPROM

The TMS370C742A device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing through location 7FFFh. Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include:

Programming – In-circuit programming capability if VPP is applied to MC – Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01C as shown in Table 5.

Write protection: writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC

program ROM

The program ROM consists of 4K or 8K bytes of mask-programmable read-only memory . The program ROM is used for permanent storage of data or instructions. Memory addresses 7FE0h through 7FEBh are reserved for TI, and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device fabrication.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx4x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are generated internally , while one (RESET

pin) is controlled externally. These actions are as follows:

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 Family

User’s Guide

(literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the

TMS370 Family User’s Guide

(literature number SPNU127) for more information.

External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide

(literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x4x device to reset external system components. Additionally , if a cold start (V

is off for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag (COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

TI is a trademark of Texas Instruments Incorporated.

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system reset (continued)

Table 6. Reset Sources

ADDRESS

BIT NO.

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

COLD START

Cold (power-up)

SCCR0

1010h

P010

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.

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interrupts

The TMS370 family software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be independently enabled by the global-interrupt enable bits (IE1 and IE2) of the status register.

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

T2A PRI

Priority

Overflow

Compare1 Ext Edge

Compare2 Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A/D

TIMER 1

T1 PRI

Overflow

Compare1 Ext Edge

Compare2 Input Capture 1

Watchdog

SCI INT

BRKDT

RXRDY

TXRDY

TXPRI

RXPRI

Figure 4. Interrupt Control

Each system interrupt is configured independently on either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion to future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx4x has eight hardware system interrupts (plus RESET

) as shown in Table 7. Each system interrupt has a dedicated interrupt vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXNT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt.

Five of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software-configurable for input polarity (rising or falling) for ease of system interface. External interrupt INT1 is software-configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the interrupt function is not required (INT1 can be configured similarly as an input pin).

T able 7. Hardware System Interrupts

INTERRUPT SOURCE INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY

†

External RESET Watchdog Overflow Oscillator Fault Detect

COLD START WD OVRFL INT FLAG OSC FLT FLAG

RESET

‡

7FFEh, 7FFFh 1

External INT1 INT1 FLAG INT1

‡

7FFCh, 7FFDh 2

External INT2 INT2 FLAG INT2

‡

7FFAh, 7FFBh 3

External INT3 INT3 FLAG INT3

†

7FF8h, 7FF9h 4

Timer 1 Overflow Timer 1 Compare 1 Timer 1 Compare 2 Timer 1 External Edge Timer 1 Input Capture Watchdog Overflow

T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC INT FLAG WD OVRFL INT FLAG

T1INT

7FF4h, 7FF5h 5

SCI RX Data Register Full SCI RX Break Detect

RXRDY FLAG BRKDT FLAG

RXINT

‡

7FF2h, 7FF3h 6

SCI TX Data Register Empty TXRDY FLAG TXINT 7FF0h, 7FF1h 7 Timer 2A Overflow

Timer 2A Compare 1 Timer 2A Compare 2 Timer 2A External Edge Timer 2A Input Capture 1 Timer 2A Input Capture 2

T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG

T2AINT 7FEEh, 7FEFh 8

A-D Conversion Complete AD INT FLAG ADINT 7FECh, 7FEDh 9

†

Relative priority within an interrupt level.

‡

Releases microcontroller from STANDBY and HALT low-power modes.

Releases microcontroller from STANDBY low-power mode.

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privileged operation and EEPROM write-protection override

The TMS370Cx4x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once defined for an end application. Following a hardware reset, the TMS370Cx4x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1, entering the nonprivileged mode and disabling write operations to specific configuration control bits within the peripheral file. The system-configuration bits listed in T able 8 are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

Table 8. Privilege Bits

†

NAME LOCATION

CONTROL BIT

SCCR0

P010.5 P010.6

PF AUTO WAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

SCCR2

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

SCIPRI

P05F.4 P05F.5 P05F.6 P05F.7

SCI ESPEN SCI RX PRIORITY SCI TX PRIORITY SCI STEST

T1PRI

P04F.6 P04F.7

T1 PRIORITY T1 STEST

T2APRI

P06F.6 P06F.7

T2A PRIORITY T2A STEST

ADPRI

P07F.5 P07F.6 P07F.7

AD ESPEN AD PRIORITY AD STEST

†

The privileged bits are shown in a bold typeface in the peripheral file frames of the following sections.

The WPO mode provides an external hardware method for overriding the write protection registers (WPR) of data EEPROM on the TMS370Cx4x. Applying a 12-V input to the MC pin after the RESET pin input goes high causes the device to enter WPO mode. The high voltage on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the content of data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx4x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time the mask is manufactured.

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low-power and IDLE modes (continued)

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

In the ST ANDBY mode (HAL T/ST ANDBY = 0 ), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, Timer 1, and the receive start-bit-detection circuit of the SCI1 remain active. System processing is suspended until a qualified interrupt (hardware RESET

, external interrupt on INT1, INT2, INT3, Timer 1 interrupt, or a low level on the receive pin of the serial communications interface 1) is detected.

In the HALT mode (HALT/STANDBY=1 ), the TMS370Cx4x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET

external interrupt on INT1, INT2, INT3, or low level on

the receive pin of the SCI1) is detected. The power-down mode selection bits are sumarized in Table 9.

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

1 0 STANDBY 1 1 HALT 0 X IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is always generated, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU-instruction processing is stopped during the STANDBY and HALT modes, the clocking of the WD timer is inhibited.

clock modules

The ’x4x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ’x4x ROM-masked devices of fer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’742A EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency. The divide-by-4 option produces a SYSCLK which is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

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clock modules (continued)

These are formulated as follows:

Divide-by-4 : SYSCLK

external resonator frequency

CLKIN

Divide-by-1 : SYSCLK

external resonator frequency 4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the reduction of EMI. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a steeper decay of emissions produced by the oscillator.

system configuration registers

Table 10 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface.

Table 10. Peripheral File Frame 1: System Configuration Registers

PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

P010

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

—

µP/µC

MODE

SCCR0

P011

—

— —

AUTOWAIT

DISABLE

—

MEMORY DISABLE

— — SCCR1

P012

HALT/

STANDBY

PWRDWN/

IDLE

—

BUS

STEST

CPU

STEST

—

INT1

NMI

PRIVILEGE

DISABLE

SCCR2

P013

P016

Reserved

P017

INT1

FLAG

INT1

PIN DATA

— — —

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

INT1

P018

INT2

FLAG

INT2

PIN DATA

—

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT2

P019

INT3

FLAG

INT3

PIN DATA

—

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

INT3

P01A BUSY — — — — AP W1W0 EXE DEECTL

P01B Reserved P01C BUSY VPPS — — — — W0 EXE EPCTL P01D

P01E

P01F

Reserved

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 and Table 12 detail the specific addresses, registers, and control bits within the peripheral file frame.

Table 11. Peripheral File Frame 2: Digital Port Control Registers

PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

P020 Reserved APORT1 P021 Port A Control Register 2 (must be 0) APORT2 P022 Port A Data ADATA P023 Port A Direction ADIR P024 Reserved BPORT1 P025 — — — — — Port B Control Register 2 (must be 0) BPORT2 P026 — — — — — Port B Data BDATA P027 — — — — — Port B Direction BDIR P028

P02B

Reserved

P02C Port D Control Register 1 (must be 0) — — — DPORT1 P02D Port D Control Register 2 (must be 0)

†

— — — DPORT2 P02E Port D Data — — — DDATA P02F Port D Direction — — — DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 12. Port Configuration Register Setup

PORT PIN

abcd 00q1

abcd 00y0

A 0 – 7 Data Out q Data In y B 0 – 2 Data Out q Data In y

D 3 – 7 Data Out q Data In y

a = Port × Control Register 1

b = Port × Control Register 2

c = Data

d = Direction

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timer 1 module

The programmable Timer 1 (T1) module of the TMS370Cx4x provides the designer with the enhanced timer resources required to perform real-time system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The T1 module includes three external device pins that can be used for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The T1 module block diagram is shown in Figure 5.

T1IC/CR

Edge

Select

16-Bit

Counter

T1EVT

MUX

16-Bit

T1PWM

PWM

Toggle

16-Bit

Watchdog Counter

(Aux. Timer)

Interrupt

Logic

Capt/Comp

16-Bit

Compare

Interrupt

Logic

8-Bit

Prescaler

Figure 5. Timer 1 Block Diagram

Three T1 I/O pins – T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin – T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin – T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin

Two operational modes: – Dual-compare mode: Provides PWM signal – Capture/compare mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a capture or compare register.

One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD feature is not needed.

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

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timer 1 module (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR)

Interrupts that can be generated on the occurrence of: – A capture – A compare equal – A counter overflow – An external edge detection

Sixteen T1 module control registers located in the PF frame, beginning at address P040

The T1 module control registers are illustrated in Table 13.

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timer 1 module (continued)

Table 13. Timer 1 Module Registers Memory Map

†

PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

Modes: Dual-Compare and Capture/Compare

P040 Bit 15 T1 Counter MSB Bit 8 P041 Bit 7 T1 Counter LSB Bit 0

T1CNTR

P042 Bit 15 Compare Register MSB Bit 8 P043 Bit 7 Compare Register LSB Bit 0

T1C

P044 Bit 15 Capture/Compare Register MSB Bit 8 P045 Bit 7 Capture/Compare Register LSB Bit 0

T1CC

P046 Bit 15 Watchdog Counter MSB Bit 8 P047 Bit 7 Watchdog Counter LSB Bit 0

WDCNTR

P048 Bit 7 Watchdog Reset Key Bit 0 WDRST P049

WD OVRFL

TAP SEL

†

WD INPUT SELECT2

†

WD INPUT SELECT1

†

WD INPUT

SELECT0

†

—

T1INPUT

SELECT2

T1INPUT

SELECT1

T1INPUT

SELECT0

T1CTL1

P04A

WD OVRFL

RST ENA

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

— —

T1 SW

RESET

T1CTL2

Mode: Dual-Compare

P04B

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

— —

T1EDGE INT ENA

T1C2

INT ENA

T1C1

INT ENA

T1CTL3

P04C

MODE = 0

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

T1CTL4

Mode: Capture/Compare

P04B

T1EDGE

INT FLAG

—

T1C1

INT FLAG

— —

T1EDGE INT ENA

—

T1C1

INT ENA

T1CTL3

P04C

MODE = 1

T1C1

OUT ENA

—

T1C1

RST ENA

—

T1EDGE

POLARITY

—

T1EDGE

DET ENA

T1CTL4

Modes: Dual-Compare and Capture/Compare

P04D — — — —

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

T1PC1

P04E

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1PC2

P04F

STEST

PRIORITY

— — — — — — T1PRI

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.

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timer 1 module (continued)

Figure 6 shows the T1 dual-compare mode block diagram. The annotations on the diagram identify the register and the bits in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CTL4.1

T1CTL4.4

Prescaler

Clock

Source

16-Bit

Counter

16-Bit

Compare=

Reset

T1C1

RST ENA

T1 SW

RESET

Edge

Select

T1EDGE DET ENA

Output Enable

Capt/Comp

MSB

LSB

MSB

LSB

T1CR OUT ENA

T1IC/CR

T1EDGE POLARITY

Toggle

16-Bit

Compare

MSB

LSB

T1CC.15-0

T1C1 INT FLAG

T1CTL3.0

T1CTL3.5

T1C1 INT ENA

T1C2 INT FLAG

T1CTL3.1

T1CTL3.6

T1C2 INT ENA

T1 OVRFL INT FLAG

T1CTL2.4

T1CTL2.3

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.2

T1CTL3.7

T1EDGE INT ENA

T1 PRIORITY

T1C2 OUT ENA

T1C1 OUT ENA

T1CTL4.3

T1CTL4.6

T1CTL4.5

T1PWM

T1PC2.7-4

T1PRI.6

T1C.15-0

T1CNTR.15-0

T1CTL2.0

T1CR

RST ENA

T1PC2.3-0

T1CTL4.0

T1CTL4.2

Level 1 Int

Level 2 Int

Figure 6. Timer 1: Dual-Compare Mode

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timer 1 module (continued)

Figure 7 shows the T1 capture/compare mode block diagram. The annotations on the diagram identify the register and the bits in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CTL4.2

Compare=

Edge

Select

T1IC/CR

T1EDGE POLARITY

T1EDGE DET ENA

Prescale

Clock

Source

16-Bit

Counter

MSB

LSB

T1CNTR.15-0

Reset

T1C1

RST ENA

T1 SW

RESET

T1CTL2.0

T1CTL4.4

T1PC2.3-0

T1CTL4.0

T1EDGE INT FLAG

T1EDGE INT ENA

T1CTL3.7

T1CTL3.2

T1 OVRFL INT FLAG

T1 OVRFL INT ENA

T1CTL2.3

T1CTL2.4

T1C1 INT FLAG

T1C1 INT ENA

T1CTL3.5

T1CTL3.0

T1C1

OUT ENA

T1PWM

T1CTL4.6

Toggle

T1PC2.7-4

16-Bit

Capt/Comp

MSB

LSB

T1CC.15-0

T1C.15-0

16-Bit

Compare

MSB

LSB

T1 PRIORITY

T1PRI.6

Level 1 Int

Level 2 Int

Figure 7. Timer 1: Capture/Compare Mode

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timer 1 module (continued)

The TMS370Cx4x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be configured as one of three mask options as follows:

Standard WD configuration (see Figure 8) for ’C742A EPROM and mask-ROM devices: – Watchdog mode

– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written

– Generates a system reset if an incorrect value is written to the WD reset key or if the counter

overflows

– A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

– Non-watchdog mode

– Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

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timer 1 module (continued)

Hard watchdog configuration (see Figure 9) for mask-ROM devices only: – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written. – Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows – A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system

reset – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as a nonmaskable interrupt during low power modes.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVRFL

INT FLAG

Figure 9. Hard Watchdog

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

Simple counter configuration (see Figure 10) for mask-ROM devices only – Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVFL INT FLAG

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

Figure 10. Simple Counter

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2A module

The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture register in one mode and as a compare register in the other mode. The T2A module adds an additional timer that provides an event count, input capture, and compare function. The T2A module includes three external device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is shown in Figure 11.

16–Bit

INT

Logic

Capt/Comp

16–Bit

Capture

Edge

Detect

T2AEVT

PWM

Toggle

T2AIC2/PWM

(Dual-Compare Mode)

Edge

Detect

T2AIC1/CR

T2AIC2/PWM

16–Bit

Compare

16–Bit

Counter

Clock

Select

(Dual-Capture Mode)

Figure 11. T imer 2A Module Block Diagram

The T2A module features include the following:

Three T2A I/O pins: – T2AIC1/CR: T2A input-capture 1/counter-reset input pin, or general-purpose bidirectional I/O pin – T2AIC2/PWM: T2A input-capture 2 / pulse-width-modulation (PWM) output pin, or general-purpose

bidirectional I/O pin – T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin

Two operational modes: – Dual-compare mode: Provides PWM signal – Dual-capture mode: Provides input-capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture register with associated capture logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a capture or compare register

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

T2A clock sources can be any of the following: – System clock – No clock (the counter is stopped) – External clock synchronized to the system clock (event counter) – System clock while external input is high (pulse accumulation)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T2AIC1/CR)

Interrupts that can be generated on the occurrence of: – A compare equal to dedicated-compare register – A compare equal to capture-compare register – A counter overflow – An external edge 1 detection – An external edge 2 detection

Fourteen T2A module-control registers: Located in the PF frame beginning at address P060

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A module-control registers are shown in Table 14.

Table 14. T2A Module Register Memory Map

†

PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

Modes: Dual-Compare and Dual-Capture

P060 Bit 15 T2A Counter MSB Bit 8 P061 Bit 7 T2A Counter LSB Bit 0

T2ACNTR

P062 Bit 15 Compare Register MSB Bit 8 P063 Bit 7 Compare Register LSB Bit 0

T2AC

P064 Bit 15 Capture/Compare Register MSB Bit 8 P065 Bit 7 Capture/Compare Register LSB Bit 0

T2ACC

P066 Bit 15 Capture Register 2 MSB Bit 8 P067 Bit 7 Capture Register 2 LSB Bit 0

T2AIC

P068 P069

Reserved

P06A — — —

T2A OVRFL

INT ENA

T2A OVRFL

INT FLAG

T2A INPUT

SELECT1

T2A INPUT

SELECT0

T2A

SW RESET

T2ACTL1

Mode: Dual-Compare

P06B

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

— —

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

T2ACTL2

P06C

T2A

MODE = 0

T2AC1

OUT ENA

T2AC1

OUT ENA

T2AC1

RST ENA

T2AEDGE1

OUT ENA

T2AEDGE1

POLARITY

T2AEDGE1

RST ENA

T2AEDGE1

DET ENA

T2ACTL3

Mode: Dual-Capture

P06B

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

— —

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

T2ACTL2

P06C

T2A

MODE = 1

— —

T2AC1

RST ENA

T2AEDGE2

POLARITY

T2AEDGE1

POLARITY

T2AEDGE2

DET ENA

T2AEDGE1

DET ENA

T2ACTL3

Modes: Dual-Compare and Dual-Capture

P06D — — — —

T2AEVT DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

T2APC1

P06E

T2AIC2/PWM

DATA IN

T2AIC2/PWM

DATA OUT

T2AIC2/PWM

FUNCTION

T2AIC2/PWM

DATA DIR

T2AIC1/CR

DATA IN

T2AIC1/CR

DATA OUT

T2AIC1/CR FUNCTION

T2AIC1/CR

DATA DIR

T2APC2

P06F

T2A

STEST

T2A

PRIORITY

— — — — — — T2APRI

†

Privileged bits are shown in bold typeface.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register.

T2AC.15-0

T2ACTL2.1

T2ACTL3.2

T2ACTL3.1

T2ACTL3.5

T2ACTL3.3

Clock

Source

16-Bit

Counter

16-Bit

Compare=

Reset

T2AC1

RST ENA

T2A SW

RESET

Edge 1

Select

T2AEDGE1 DET ENA

Output Enable

Capt/Comp

MSB

LSB

MSB

LSB

T2AEDGE1 OUT ENA

T2AIC1/CR

T2AEDGE1 POLARITY

Toggle

16-Bit

Compare

MSB

LSB

T2ACC.15-0

T2AC1 INT FLAG

T2ACTL2.0

T2ACTL2.5

T2AC1 INT ENA

T2AC2 INT FLAG

T2ACTL2.6

T2AC2 INT ENA

T2A OVRFL INT FLAG

T2ACTL1.4

T2ACTL1.3

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2ACTL2.2

T2ACTL2.7

T2AEDGE1 INT ENA

T2A PRIORITY

T2AC2 OUT ENA

T2AC1 OUT ENA

T2ACTL3.6

T2AIC2/PWM

T2APC2.7-4

T2APRI.6

T2ACNTR.15-0

T2ACTL1.0

T2ACTL3.4

T2AEDGE1

RST ENA

T2APC2.3-0

T2ACTL3.0

Level 1 Int Level 2 Int

0 1

Figure 12. Timer 2A: Dual-Compare Mode

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register.

Capt/Comp

T2APC2.3–0

Compare =

Clock

Source

16-Bit

Counter

MSB

LSB

T2ACNTR.15–0

Reset

T2AC1

RST ENA

T2ACTL1.0

T2ACTL3.4

T2ACTL2.6

T2ACTL2.1

T2ACTL2.7

T2ACTL2.2

T2ACTL2.5

T2ACTL2.0

16-Bit

MSB

LSB

T2ACC.15–0

T2AC.15–0

16-Bit

Compare

MSB

LSB

T2A PRIORITY

Level 1 Int

Level 2 Int

T2ACTL1.3

T2ACTL1.4

16-Bit

Capture

MSB

LSB

T2AIC.15–0

Edge 2

Select

T2AIC2/PWM

T2APC2.7–4

T2ACTL3.1

Edge1 Select

T2AIC1/CR

T2ACTL3.3

T2ACTL3.2

T2ACTL3.0

T2AEDGE1 POLARITY

T2AEDGE1 DET ENA

T2AEDGE2 DET ENA

T2AEDGE2 POLARITY

T2AC1 INT FLAG

T2AC1 INT ENA

T2A OVRFL INT FLAG

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2AEDGE1 INT ENA

T2AEDGE2 INT ENA

T2AEDGE2 INT FLAG

T2APRI.6

T2A SW

RESET

Figure 13. Timer 2A: Dual-Capture Mode

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1)

The TMS370Cx4x devices include a serial communications interface 1 (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals and uses the standard non return-to-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing errors. The bit rate (baud) is programmable to over 65,000 different rates through a 16-bit baud-select register.

Features of the SCI1 module include:

Three external pins: – SCITXD: SCI transmit-output pin or general purpose bidirectional I/O pin. – SCIRXD: SCI receive-input pin or general purpose bidirectional I/O pin.

– SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin.

Two communications modes: asynchronous and isosynchronous

Baud rate: 64K different programmable rates – Asynchronous mode: 3 bps to 156K bps at 5 MHz SYSCLK

Asynchronous Baud

SYSCLK

(BAUD REG)1) 32

– Isosynchronous mode: 39 bps to 2.5 Mbps at 5 MHz SYSCLK

Isosynchronous Baud

SYSCLK

(BAUD REG)1) 2

Data word format: – One start bit – Data word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: Idle-line and address bit

Half or full-duplex operation

Double-buffered receiver and transmitter operations

Transmitter and receiver operations can be accomplished through either interrupt-driven or polled-algorithms with status flags:

– Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (Transmitter shift register is empty)

– Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions – Separate enable bits for transmitter and receiver interrupts – NRZ (non return-to-zero) format

Eleven SCI1 module control registers, located in control register frame beginning at address P050h

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) (continued)

Table 15 lists the SCI1 module control registers.

Table 15. SCI1 Module Control Register Memory Map

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P050

ÁÁ

STOP BITS

ÁÁÁ

EVEN/ODD

PARITY

ÁÁ

PARITY

ENABLE

ÁÁ

ASYNC/

ISOSYNC

ÁÁÁ

ADDRESS/

IDLE WUP

ÁÁ

SCI CHAR2

ÁÁ

SCI CHAR1

ÁÁÁ

SCI CHAR0

ÁÁ

SCICCR

P051

ÁÁ

—

ÁÁÁ

—

ÁÁ

SCI SW

RESET

ÁÁ

CLOCK

ÁÁÁ

TXWAKE

ÁÁ

SLEEP

ÁÁ

TXENA

ÁÁÁ

RXENA

ÁÁ

SCICTL

P052

BAUDF

(MSB)

BAUDE

BAUDD

BAUDC

BAUDB

BAUDA

BAUD9

BAUD8

BAUD MSB

P053

ÁÁ

BAUD7

ÁÁÁ

BAUD6

ÁÁ

BAUD5

ÁÁ

BAUD4

ÁÁÁ

BAUD3

ÁÁ

BAUD2

ÁÁ

BAUD1

ÁÁÁ

BAUD0

(LSB)

ÁÁ

BAUD LSB

P054

TXRDY

TX EMPTY

—

SCI TX

INT ENA

TXCTL

P055

ÁÁ

ERROR

ÁÁÁ

RXRDY

ÁÁ

BRKDT

ÁÁ

ÁÁÁ

ÁÁ

RXWAKE

ÁÁÁ

SCI RX

INT ENA

ÁÁ

RXCTL

P056

Reserved

P057

RXDT7

RXDT6

RXDT5

RXDT4

RXDT3

RXDT2

RXDT1

RXDT0

RXBUF

P058

RESERVED

P059

TXDT7

TXDT6

TXDT5

TXDT4

TXDT3

TXDT2

TXDT1

TXDT0

TXBUF

P05A P05B P05C

ББББББББББББББББББББББББББ

Reserved

ÁÁ

P05D

ÁÁ

—

ÁÁÁ

—

ÁÁ

—

ÁÁ

—

ÁÁÁ

SCICLK

DATA IN

ÁÁ

SCICLK

DATA OUT

ÁÁ

SCICLK

FUNCTION

ÁÁÁ

SCICLK

DATA DIR

ÁÁ

SCIPC1

P05E

ÁÁ

SCITXD

DATA IN

ÁÁÁ

SCITXD

DATA OUT

ÁÁ

SCITXD

FUNCTION

ÁÁ

SCITXD

DATA DIR

ÁÁÁ

SCIRXD DATA IN

ÁÁ

SCIRXD

DATA OUT

ÁÁ

SCIRXD

FUNCTION

ÁÁÁ

SCIRXD

DATA DIR

ÁÁ

SCIPC2

P05F SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

—

SCIPRI

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) (continued)

Figure 14 shows the SCI1 module block diagram.

RXCTL.4–2

FE OE PE

RX ERROR

SCICTL.3

TXWAKE

SCICCR.6 SCICCR.5

EVEN/ODD ENABLE

PARITY

Frame Format and Mode

WUT

TXBUF.7 – 0

Transmit Data

Buffer Reg.

TXSHF Reg.

TXCTL.7

TXCTL.6

TXRDY

TX EMPTY

SCI TX Interrupt

TXCTL.0

TXENA

SCICTL.4

BAUD MSB. 7–0

Baud Rate

MSbyte Reg.

BAUD LSB. 7–0

Baud Rate

LSbyte Reg.

CLOCK

SCICTL.1

SCITXD

SCI TX INT ENA

RXCTL.7

ERR

RXSHF Reg.

RXCTL.1

Receive Data

Buffer Reg.

RXBUF.7 – 0

RXENA

RXCTL.6

RXCTL.5

RXRDY

BRKDT

SCI RX Interrupt

RXCTL.0

SCI RX INT ENA

SCIPRI.6

SCIPRI.5

Level 1 INT Level 2 INT

Level 1 INT

Level 2 INT

SCITX PRIORITY

SCIRX PRIORITY

SCITXD

SCIPC2.7–4

SCICLK

SCIPC1.3–0

SCIRXD

SCIPC2.3–0

SCICTL.0

RXWAKE

SYSCLK

Figure 14. SCI1 Block Diagram

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry . The module has eight multiplexed analog input channels for the 44-pin device and four multiplexed analog input channels for the 40-pin device that allow the processor to convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

Minimum conversion time: 32.8 µs at 5-MHz SYSCLK

Up to ten external pins: – Four (AN2, AN3, AN6, AN7) or eight (AN0-AN7) analog input channels, any of which can be software

configured as digital inputs (E2, E3, E6, E7) or (E0–E7), respectively , if not needed as analog channels – AN1–AN7 can also be configured as positive-input voltage reference. –V

CC3

: ADC1 module high-voltage reference input

–V

SS3

: ADC1 module low-voltage reference input

The ADDATA register, which contains the digital result of the last A/D conversion

A/D operations can be accomplished through either interrupt driven or polled algorithms.

Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.

The ADC1 module control registers are illustrated in Table 16.

Table 16. ADC1 Module Control Register Memory Map

†

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P070

ÁÁÁ

CONVERT

START

ÁÁ

SAMPLE

START

ÁÁ

REF VOLT

SELECT2

ÁÁÁ

REF VOLT

SELECT1

ÁÁ

REF VOLT

SELECT0

ÁÁ

AD INPUT

SELECT2

ÁÁÁ

AD INPUT

SELECT1

ÁÁ

AD INPUT

SELECT0

ÁÁ

ADCTL

P071

—

AD READY

AD INT

FLAG

AD INT

ENA

ADSTAT

P072

A-to-D Conversion Data Register

ADDATA

P073

P07C

ББББББББББББББББББББББББББ

Reserved

ÁÁ

P07D

Port E Data Input Register

ADIN

P07E

Port E Input Enable Register

ADENA

P07F AD STEST

PRIORITY

AD ESPEN

ÁÁÁ

—

ÁÁ

—

ÁÁ

—

ÁÁÁ

—

ÁÁ

—

ÁÁ

ADPRI

†

Privileged bits are shown in bold typeface.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module (continued)

The ADC1 module block diagram is illustrated in Figure 15.

ADCTL.5–3

5 4 3

ADENA.0

REF VOLTS SELECT

ADCTL.2–0

2 1 0

AD INPUT SELECT

ADIN.0

Port E Input

ENA 0

Port E Data

AN 0

AN0

ADENA.1

ADIN.1

Port E Input

ENA 1

Port E Data

AN 1

AN1

ADENA.2

ADIN.2

Port E Input

ENA 2

Port E Data

AN 2

AN2

ADENA.3

ADIN.3

Port E Input

ENA 3

Port E Data

AN 3

AN3

ADENA.4

ADIN.4

Port E Input

ENA 4

Port E Data

AN 4

AN4

ADENA.5

ADIN.5

Port E Input

ENA 5

Port E Data

AN 5

AN5

ADENA.6

ADIN.6

Port E Input

ENA 6

Port E Data

AN 6

AN6

ADENA.7

ADIN.7

Port E Input

ENA 7

Port E Data

AN 7

AN7

CC3

SS3

ADCTL.6

SAMPLE

START

ADCTL.7

CONVERT

START

ADDATA.7–0

A-to-D

Conversion

Data Register

ADSTAT.2

AD READY

AD PRIORITY

ADPRI.6

Level 1 INT

Level 2 INT

AD INT FLAG

ADSTAT.1

AD INT ENA

ADSTAT.0

A/D

Figure 15. ADC1 Converter Block Diagram

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

instruction set overview

Table 17 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx4x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instructions for these two opcode nibbles contain the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

Template Release Date: 7–11–94

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

Table 17. TMS370 Family Opcode/Instruction Map

†

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

JMP

#ra 2/7

INCW

#ra,Rd

3/11

MOV Ps,A

2/8

CLRC /

TST A

1/9

MOV

A,B

1/9

MOV A,Rd

2/7

TRAP

1/14

LDST

2/6

1JNra

2/5

MOV A,Pd

2/8

MOV B,Pd

2/8

MOV

Rs,Pd

3/10

MOV

Ps,B

2/7

MOV B,Rd

2/7

TRAP

1/14

MOV

#ra[SP],A

2/7

2JZra

2/5

MOV Rs,A

2/7

MOV #n,A

2/6

MOV Rs,B

2/7

MOV

Rs,Rd

3/9

MOV #n,B

2/6

MOV

B,A

1/8

MOV

#n,Rd

3/8

MOV

Ps,Rd

3/10

DEC

1/8

DEC

1/8

DEC

Rd 2/6

TRAP

1/14

MOV

A,*ra[SP]

2/7

3JCra

2/5

AND Rs,A

2/7

AND #n,A

2/6

AND Rs,B

2/7

AND

Rs,Rd

3/9

AND #n,B

2/6

AND

B,A

1/8

AND

#n,Rd

3/8

AND A,Pd

2/9

AND B,Pd

2/9

AND

#n,Pd

3/10

INC

1/8

INC

1/8

INC Rd 2/6

TRAP

1/14

CMP

*n[SP],A

2/8

4JPra

2/5

Rs,A

2/7

#n,A

2/6

Rs,B

2/7

Rs,Rd

3/9

#n,B

2/6

OR B,A

1/8

#n,Rd

3/8

A,Pd

2/9

B,Pd

2/9

#n,Pd

3/10

INV

1/8

INV

1/8

INV Rd 2/6

TRAP

1/14

extend

inst,2

opcodes

L S

JPZ

2/5

XOR Rs,A

2/7

XOR #n,A

2/6

XOR Rs,B

2/7

XOR

Rs,Rd

3/9

XOR #n,B

2/6

XOR

B,A

1/8

XOR

#n,Rd

3/8

XOR A,Pd

2/9

XOR B,Pd

2/9

XOR

#n,Pd

3/10

CLR

1/8

CLR

1/8

CLR

Rn 2/6

TRAP

1/14

JNZ

2/5

BTJO

Rs,A,ra

3/9

BTJO

#n,A,ra

3/8

BTJO

Rs,B,ra

3/9

BTJO

Rs,Rd,ra

4/11

BTJO

#n,B,ra

3/8

BTJO

B,A,ra

2/10

BTJO

#n,Rd,ra

4/10

BTJO

A,Pd,ra

3/11

BTJO

B,Pd,ra

3/10

BTJO

#n,Pd,ra

4/11

XCHB

1/10

XCHB A /

TST B

1/10

XCHB

Rn 2/8

TRAP

1/14

IDLE

1/6

JNC

2/5

BTJZ

Rs.,A,ra

3/9

BTJZ

#n,A,ra

3/8

BTJZ

Rs,B,ra

3/9

BTJZ

Rs,Rd,ra

4/11

BTJZ

#n,B,ra

3/8

BTJZ

B,A,ra

2/10

BTJZ

#n,Rd,ra

4/10

BTJZ

A,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

BTJZ

#n,Pd,ra

4/11

SWAP

1/11

SWAP

1/11

SWAP

Rn 2/9

TRAP

1/14

MOV

#n,Pd

3/10

8JVra

2/5

ADD Rs,A

2/7

ADD #n,A

2/6

ADD Rs,B

2/7

ADD

Rs,Rd

3/9

ADD #n,B

2/6

ADD

B,A

1/8

ADD

#n,Rd

3/8

MOVW #16,Rd

4/13

MOVW

Rs,Rd

3/12

MOVW

#16[B],Rpd

4/15

PUSH

1/9

PUSH

1/9

PUSH

Rd 2/7

TRAP

1/14

SETC

1/7

9JLra

2/5

ADC Rs,A

2/7

ADC #n,A

2/6

ADC Rs,B

2/7

ADC

Rs,Rd

3/9

ADC #n,B

2/6

ADC

B,A

1/8

ADC

#n,Rd

3/8

JMPL

lab 3/9

JMPL

*Rp 2/8

JMPL

*lab[B]

3/11

POP

1/9

POP

1/9

POP

Rd 2/7

TRAP

1/14

RTS

1/9

JLE

2/5

SUB Rs,A

2/7

SUB #n,A

2/6

SUB

Rs,B

2/7

SUB

Rs,Rd

3/9

SUB #n,B

2/6

SUB

B,A

1/8

SUB

#n,Rd

3/8

MOV

& lab,A

3/10

MOV

*Rp,A

2/9

MOV

*lab[B],A

3/12

DJNZ A,#ra

2/10

DJNZ B,#ra

2/10

DJNZ Rd,#ra

3/8

TRAP

1/14

RTI

1/12

JHS

2/5

SBB Rs,A

2/7

SBB #n,A

2/6

SBB

Rs,B

2/7

SBB

Rs,Rd

3/9

SBB

#n,B

2/6

SBB

B,A

1/8

SBB

#n,Rd

3/8

MOV

A, & lab

3/10

MOV

A, *Rp

2/9

MOV

A,*lab[B]

3/12

COMPL

1/8

COMPL

1/8

COMPL

Rd 2/6

TRAP

1/14

PUSH

ST 1/8

†

All conditional jumps (opcodes 01– 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 39

Table 17. TMS370 Family Opcode/Instruction Map† (Continued)

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

JNV

2/5

MPY Rs,A 2/46

MPY #n,A 2/45

MPY Rs,B 2/46

MPY

Rs,Rd

3/48

MPY

#n,B 2/45

MPY

B,A 1/47

MPY

#n,Rs

3/47

BR lab 3/9

*Rp

2/8

*lab[B]

3/11

1/8

RR Rd 2/6

TRAP

1/14

POP

ST 1/8

JGE

2/5

CMP Rs,A

2/7

CMP #n,A

2/6

CMP Rs,B

2/7

CMP

Rs,Rd

3/9

CMP

#n,B

2/6

CMP

B,A

1/8

CMP

#n,Rd

3/8

CMP

& lab,A

3/11

CMP

*Rp,A

2/10

CMP

*lab[B],A

3/13

RRC

1/8

RRC

1/8

RRC

Rd 2/6

TRAP

1/14

LDSP

1/7

EJGra

2/5

DAC Rs,A

2/9

DAC #n,A

2/8

DAC Rs,B

2/9

DAC

Rs,Rd

3/11

DAC

#n,B

2/8

DAC

B,A 1/10

DAC

#n,Rd

3/10

CALL

lab

3/13

CALL

*Rp 2/12

CALL

*lab[B]

3/15

1/8

RL Rd 2/6

TRAP

1/14

STSP

1/8

JLO

2/5

DSB Rs,A

2/9

DSB #n,A

2/8

DSB Rs,B

2/9

DSB

Rs,Rd

3/11

DSB

#n,B

2/8

DSB

B,A 1/10

DSB

#n,Rd

3/10

CALLR

lab

3/15

CALLR

*Rp 2/14

CALLR

*lab[B]

3/17

RLC

1/8

RLC

1/8

RLC

Rd 2/6

TRAP

1/14

NOP

1/7

Second byte of two-byte instructions (F4xx): F4 8

MOVW

*n[Rn]

4/15

DIV

Rn.A

3/14-63

F4 9

JMPL *n[Rn]

4/16

Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix

F4 A

MOV

*n[Rn],A

4/17

# = immediate operand #16 = immediate 16-bit number lab = 16-label

F4 B

MOV

A,*n[Rn]

4/16 n = immediate 8-bit number Pd = Peripheral register containing destination type Pn = Peripheral register

F4 C

*n[Rn]

4/16

Ps=Peri heral register containing source byte

ra = Relative address Rd = Register containing destination type Rn = Re

ister file

F4 D

CMP

*n[Rn],A

4/18

Rn Register file

Rp = Register pair Rpd= Destination register pair Rps = Source Register pair

F4 E

CALL

*n[Rn]

4/20 Rs = Register containing source byte

F4 F

CALLR

*n[Rn]

4/22

†

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit emulator (XDS/22), compact development tool (CDT) and an EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850-02 for PC) — Includes extensive macro capability — Provides high-speed operation

— Offers format conversion utilities available for popular formats

ANSI C compiler (Part No. TMDS3740855-02 for PC, Part No. TMDS3740555-09 for HP700, Sun-3 or Sun-4)

— Generates assembly code of the TMS370 that can be inspected easily — Improves code execution speed and reduces code size with optional optimizer pass — Enables the user to directly reference the TMS370’s port registers by using a naming convention — Provides flexibility in specifying the storage for data objects — Interfaces C functions and assembly functions easily — Includes assembler and linker

CDT370 (compact development tool) real-time in-circuit emulation – Base (Part Number EDSCDT370 – for PC, requires cable)

– Cable for 44-pin PLCC (Part No. EDSTRG44PLCC) – Cable for 40-pin DIP (Part No. EDSTRG40DIL)

– Cable for 40-pin SDIP (Part No. EDSTRG40SDIL) – Provides EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Allows uploading anddownloading of program and data memory – Provides capability to execute programs and software routines – Includes 1024-sample trace buffer – Includes single-step executable instructions – Allows uses of software breakpoints to halt program execution at selected address

XDS/22 (extended development support) in-circuit emulator — Base (Part No. TMDS3762210 For PC, requires cable)

– Cable for 44-pin PLCC, 40-pin DIP, or shrink DIP (Part No. TMDS3788844) — Contains all the features of the CDT370 described above but does not have the capability to program

the data EEPROM and program EPROM — Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace

samples with symbolic disassembly — Allows breakpoints to be qualified by address and/or data on any type of memory acquisition. Up to four

levels of events can be combined to cause a breakpoint.

HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

development system support (continued)

— Provides timers for analyzing total and average time in routines — Contains an eight-line logic probe for adding external signal visibility to the breakpoint qualifier and

to the trace display

Microcontroller programmer — Base (Part No. TMDS3760500A – For PC, requires programming head)

– Single unit head for 44-pin PLCC (Part No. TMDS3780510A) – Single unit head for 40-pin DIP or shrink DIP (Part No. TMDS3780511A)

— PC-based, window/function-key oriented user interface for ease of use and a rapid learning

environment

Starter kit (Part No. TMDS37000 – For PC) – Includes TMS370 Assembler diskette and documentation – Includes TMS370 Simulator – Includes programming adapter board and programming software – Does not include – (to be supplied by the user):

– + 5 V power supply

ZIF sockets 9-pin RS-232 cable

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device numbering conventions

Figure 16 illustrates the numbering and symbol nomenclature for the TMS370Cx4x family.

3370 4 0C

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology: C = CMOS

Program Memory Types: 0 = Mask ROM

3 = Mask ROM, No Data EEPROM 7 = EPROM

Device Type: 4 = x4x devices containing the following modules:

– Timer 1 – Timer 2A – Serial Communications Interface 1 – Analog-to-Digital Converter 1

Memory Size: 0 = 4K bytes

2 = 8K bytes

Temperature Ranges: A = –40°Cto 85°C

L= 0°Cto 70°C T=–40°Cto 105°C

Packages: FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier JC = Ceramic Shrink Dual-In-Line JD = Ceramic Dual-In-Line

N = Plastic Dual-In-Line

NJ = Plastic Shrink Dual-In-Line

ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog – A hard watchdog – A simple watchdog

The clock can be either:

– Divide-by-4 clock – Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled – Disabled

A = For EPROM device, a standard watchdog, a divide-by-4

clock, and low-power modes are enabled

TMS

AFNL

Figure 16. TMS370Cx4x Family Nomenclature

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device part numbers

Table 18 lists all the ‘x4x devices available at present. The device part-number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. Each device can have only one of the possible three watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

T able 18. Device Part Numbers

DEVICE PART NUMBERS

FOR 44 PINS (LCC)

DEVICE PART NUMBERS

FOR 40 PINS (DIP)

DEVICE PART NUMBERS

FOR 40 PINS (SDIP)

TMS370C040AFNA TMS370C040AFNL TMS370C040AFNT

TMS370C040ANA TMS370C040ANL TMS370C040ANT

TMS370C040ANJA

†

TMS370C040ANJL

†

TMS370C040ANJT

†

TMS370C042AFNA TMS370C042AFNL TMS370C042AFNT

TMS370C042ANA TMS370C042ANL TMS370C042ANT

TMS370C042ANJA

†

TMS370C042ANJL

†

TMS370C042ANJT

†

TMS370C340AFNA TMS370C340AFNL TMS370C340AFNT

TMS370C340ANA TMS370C340ANL TMS370C340ANT

TMS370C340ANJA

†

TMS370C340ANJL

†

TMS370C340ANJT

†

TMS370C342AFNA TMS370C342AFNL TMS370C342AFNT

TMS370C342ANA TMS370C342ANL TMS370C342ANT

TMS370C342ANJA

†

TMS370C342ANJL

†

TMS370C342ANJT

†

TMS370C742AFNT TMS370C742ANT TMS370C742ANJT

†

SE370C742AFZT

‡

SE370C742AJDT

‡

SE370C742AJCT

‡

†

The NJ designator for the 40-pin plastic shrink DIP package was known formerly as the N2. The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.

‡

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

new code release form

Figure 17 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

TMS370 MICROCONTROLLER PRODUCTS

DATE:

T o release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name: Street Address: Street Address: City: State Zip

Contact Mr./Ms.: Phone: ( ) Ext.:

Customer Purchase Order Number:

Customer Part Number: Customer Application:

Customer Print Number *Yes: #

No: (Std. spec to be followed) *If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM code processing starts.

TMS370 Device: TI Customer ROM Number:

(provided by T exas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLAT OR FREQUENCY

MIN TYP MAX [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator

Low Power Modes [] Enabled [] Disabled

Watchdog counter [] Standard [] Hard Enabled [] Simple Counter

Clock Type [] Standard (/4) [] PLL (/1)

[] Supply Voltage MIN: MAX: (std range: 4.5V to 5.5V)

NOTE: Non ’A’ version ROM devices of the TMS370 microcontrollers will have the “Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog options. See the

TMS370 Family User’s Guide

(literature number SPNU127)

or the

TMS370 Family Data Manual

(literature number SPNS014B).

TEMPERATURE RANGE

[] ’L’: 0° to 70°C (standard) [] ’A’: –40° to 85°C [] ’T’: –40° to 105°C

PACKAGE TYPE

[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP [] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZA TION BUS EXP ANSION

[] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization

(per attached spec, subject to approval)

[] YES [] NO

NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the TI part number.

RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer.

1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:

Figure 17. Sample New Code Release Form

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 19 is a collection of all the peripheral file frames using the ’Cx4x (provided for a quick reference).

Table 19. Peripheral File Frame Compilation

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SYSTEM CONFIGURATION REGISTERS

P010

ÁÁ

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁ

OSC FLT

FLAG

ÁÁ

MC PIN

WPO

ÁÁÁ

MC PIN

DATA

ÁÁ

—

ÁÁÁ

µP/µC MODE

ÁÁ

SCCR0

P011

—

AUTOWAIT

DISABLE

—

MEMORY DISABLE

—

SCCR1

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁÁ

—

BUS

STEST

CPU

STEST

ÁÁÁ

—

INT1

NMI

PRIVILEGE

DISABLE

ÁÁ

SCCR2

P013

P016

Reserved

P017

ÁÁ

INT1

FLAG

ÁÁ

INT1

PIN DATA

ÁÁÁ

—

ÁÁ

—

ÁÁ

—

ÁÁÁ

INT1

POLARITY

ÁÁ

INT1

PRIORITY

ÁÁÁ

INT1

ENABLE

ÁÁ

INT1

P018

INT2

FLAG

INT2

PIN DATA

—

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT2

P019

ÁÁ

INT3

FLAG

ÁÁ

INT3

PIN DATA

ÁÁÁ

—

ÁÁ

INT3

DATA DIR

ÁÁ

INT3

DATA OUT

ÁÁÁ

INT3

POLARITY

ÁÁ

INT3

PRIORITY

ÁÁÁ

INT3

ENABLE

ÁÁ

INT3

P01A

BUSY

—

W1W0

EXE

DEECTL P01B Reserved P01C

BUSY

VPPS

—

EXE

EPCTL

P01D

P01F

Reserved

ÁÁ

DIGITAL PORT CONTROL REGISTERS

P020 Reserved APORT1 P021 Port A Control Register 2 (must be 0) APORT2 P022 Port A Data ADATA P023 Port A Direction ADIR

P024 Reserved BPORT1 P025 — — — — — Port B Control Register 2 (must be 0) BPORT2 P026 — — — — — Port B Data BDATA P027 — — — — — Port B Direction BDIR P028

P02B

Reserved

P02C Port D Control Register 1 (must be 0) — — — DPORT1 P02D Port D Control Register 2 (must be 0)

†

— — — DPORT2

P02E Port D Data — — — DDATA

P02F Port D Direction — — — DDIR

TIMER 1 MODULE REGISTER

Modes: Dual-Compare and Capture/Compare

P040

Bit 15

T1 Counter MSbyte

Bit 8

T1CNTR

P041

Bit 7

T1 Counter LSbyte

Bit 0

P042

Bit 15

Compare-Register MSbyte

Bit 8

T1C

P043

Bit 7

Compare-Register LSbyte

Bit 0

†

To configure pin D3 as CLKOUT, set port D control register 2 = 08h.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 19. Peripheral File Frame Compilation (Continued)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

TIMER 1 MODULE REGISTER (CONTINUED)

P044

Bit 15

Capture/Compare-Register MSbyte

Bit 8

T1CC

P045

Bit 7

Capture/Compare-Register LSbyte

Bit 0

P046

Bit 15

Watchdog-Counter MSbyte

Bit 8

WDCNTR

P047

Bit 7

Watchdog-Counter LSbyte

Bit 0

P048

Bit 7

Watchdog-Reset Key

Bit 0

WDRST

P049

WD OVRFL

TAP SEL

†

INPUT

SELECT2

†

INPUT

SELECT1

†

INPUT

SELECT0

†

ÁÁ

—

ÁÁÁ

INPUT

SELECT2

ÁÁ

INPUT

SELECT1

ÁÁÁ

T1 INPUT SELECT0

ÁÁ

T1CTL1

P04A

WD OVRFL

RST ENA

†

ÁÁ

WD OVRFL

INT ENA

ÁÁÁ

WD OVRFL

INT FLAG

ÁÁ

T1 OVRFL

INT ENA

ÁÁ

T1 OVRFL

INT FLAG

ÁÁÁ

—

ÁÁ

—

ÁÁÁ

T1 SW

RESET

ÁÁ

T1CTL2

Mode: Dual-Compare

P04B

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

—

T1EDGE INT ENA

T1C2

INT ENA

T1C1

INT ENA

T1CTL3

P04C

ÁÁÁ

MODE = 0

ÁÁ

T1C1

OUT ENA

ÁÁÁ

T1C2

OUT ENA

ÁÁ

T1C1

RST ENA

ÁÁ

T1CR

OUT ENA

ÁÁÁ

T1EDGE

POLARITY

ÁÁ

T1CR

RST ENA

ÁÁÁ

T1EDGE

DET ENA

ÁÁ

T1CTL4

Mode: Capture/Compare

P04B

T1EDGE

INT FLAG

—

T1C1

INT FLAG

—

T1EDGE INT ENA

—

T1C1

INT ENA

T1CTL3

P04C

ÁÁÁ

MODE = 1

ÁÁ

T1C1

OUT ENA

ÁÁÁ

—

ÁÁ

T1C1

RST ENA

ÁÁ

—

ÁÁÁ

T1EDGE

POLARITY

ÁÁ

—

ÁÁÁ

T1EDGE

DET ENA

ÁÁ

T1CTL4

Modes: Dual-Compare and Capture/Compare

P04D

—

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT DATA

DIR

T1PC1

P04E

ÁÁÁ

T1PWM

DATA IN

ÁÁ

T1PWM

DATA OUT

ÁÁÁ

T1PWM

FUNCTION

ÁÁ

T1PWM

DATA DIR

ÁÁ

T1IC/CR DATA IN

ÁÁÁ

T1IC/CR

DATA OUT

ÁÁ

T1IC/CR

FUNCTION

ÁÁÁ

T1IC/CR DATA

DIR

ÁÁ

T1PC2

P04F T1 STEST

PRIORITY

—

T1PRI

SCI1 MODULE CONTROL REGISTER

P050

STOP BITS

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

SCI CHAR2

SCI CHAR1

SCI CHAR0

SCICCR

P051

ÁÁÁ

—

ÁÁ

—

ÁÁÁ

SCI SW RE-

SET

ÁÁ

CLOCK

ÁÁ

TXWAKE

ÁÁÁ

SLEEP

ÁÁ

TXENA

ÁÁÁ

RXENA

ÁÁ

SCICTL

P052

BAUDF

(MSB)

BAUDE

BAUDD

BAUDC

BAUDB

BAUDA

BAUD9

BAUD8

BAUD MSB

P053

ÁÁÁ

BAUD7

ÁÁ

BAUD6

ÁÁÁ

BAUD5

ÁÁ

BAUD4

ÁÁ

BAUD3

ÁÁÁ

BAUD2

ÁÁ

BAUD1

ÁÁÁ

BAUD0

(LSB)

ÁÁ

BAUD LSB

P054

TXRDY

TX EMPTY

—

SCI TX

INT ENA

TXCTL

P055

ÁÁÁ

ERROR

ÁÁ

RXRDY

ÁÁÁ

BRKDT

ÁÁ

ÁÁÁ

ÁÁ

RXWAKE

ÁÁÁ

SCI RX

INT ENA

ÁÁ

RXCTL

P056

Reserved

P057

RXDT7

RXDT6

RXDT5

RXDT4

RXDT3

RXDT2

RXDT1

RXDT0

RXBUF

P058

Reserved

P059

TXDT7

TXDT6

TXDT5

TXDT4

TXDT3

TXDT2

TXDT1

TXDT0

TXBUF

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until after a full power-down cycle has been completed.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 19. Peripheral File Frame Compilation (Continued)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SCI1 MODULE CONTROL REGISTER (CONTINUED)

P05A P05B P05C

БББББББББББББББББББББББББББ

Reserved

P05D

—

SCICLK

DATA IN

SCICLK

DATA OUT

SCICLK

FUNCTION

SCICLK

DATA DIR

SCIPC1

P05E

ÁÁ

SCITXD

DATA IN

ÁÁÁ

SCITXD

DATA OUT

ÁÁÁ

SCITXD

FUNCTION

ÁÁ

SCITXD

DATA DIR

ÁÁÁ

SCIRXD DATA IN

ÁÁ

SCIRXD

DATA OUT

ÁÁ

SCIRXD

FUNCTION

ÁÁÁ

SCIRXD

DATA DIR

SCIPC2

P05F SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

—

SCIPRI

T2A MODULE REGISTER

Modes: Dual-Capture and Dual-Compare

P060

Bit 15

T2A Counter MSbyte

Bit 8

P061

Bit 7

T2A Counter LSbyte

Bit 0

T2ACNTR

P062

Bit 15

Compare Register MSbyte

Bit 8

P063

Bit 7

Compare Register LSbyte

Bit 0

T2AC

P064

Bit 15

Capture/Compare Register MSbyte

Bit 8

P065

Bit 7

Capture/Compare Register LSbyte

Bit 0

T2ACC

P066

Bit 15

Capture Register 2 MSbyte

Bit 8

P067

Bit 7

Capture Register 2 LSbyte

Bit 0

T2AIC

P068 P069

ÁÁÁББББББББББББББББББББ

Reserved

ÁÁÁÁÁ

P06A

ÁÁ

—

ÁÁÁ

—

ÁÁÁ

—

ÁÁ

T2A OVRFL-

INT ENA

ÁÁÁ

T2A OVRFL

INT FLAG

ÁÁ

T2A

INPUT

SELECT1

ÁÁ

T2A INPUT

SELECT0

ÁÁÁ

T2A SW

RESET

T2ACTL1

Mode: Dual-Compare

P06B

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

—

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

T2ACTL2

P06C

ÁÁ

T2A

MODE = 0

ÁÁÁ

T2AC1

OUT ENA

ÁÁÁ

T2AC2

OUT ENA

ÁÁ

T2AC1

RST ENA

ÁÁÁ

T2AEDGE1

OUT ENA

ÁÁ

T2AEDGE1

POLARITY

ÁÁ

T2AEDGE1

RST ENA

ÁÁÁ

T2AEDGE1

DET ENA

T2ACTL3

Mode: Dual-Capture

P06B

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

—

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

T2ACTL2

P06C

ÁÁ

T2A

MODE = 1

ÁÁÁ

—

ÁÁÁ

—

ÁÁ

T2AC1

RST ENA

ÁÁÁ

T2AEDGE2

POLARITY

ÁÁ

T2AEDGE1

POLARITY

ÁÁ

T2AEDGE2

DET ENA

ÁÁÁ

T2AEDGE1

DET ENA

T2ACTL3

Modes: Dual-Capture and Dual-Compare

P06D

—

T2AEVT DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

T2APC1

P06E

ÁÁ

T2AIC2/PWM

DATA IN

ÁÁÁ

T2AIC2/PWM

DATA OUT

ÁÁÁ

T2AIC2/PWM

FUNCTION

ÁÁ

T2AIC2/PWM

DATA DIR

ÁÁÁ

T2AIC1/CR

DATA IN

ÁÁ

T2AIC1/CR

DATA OUT

ÁÁ

T2AIC1/CR

FUNCTION

ÁÁÁ

T2AIC1/CR

DATA DIR

T2APC2

P06F T2A STEST

T2A

PRIORITY

—

T2APRI

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 19. Peripheral File Frame Compilation (Continued)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

ADC1 MODULE CONTROL REGISTER

P070

CONVERT

STAR T

SAMPLE

STAR T

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

ADCTL

P071

ÁÁÁ

—

ÁÁÁ

—

ÁÁ

—

ÁÁÁ

—

ÁÁ

—

ÁÁ

AD READY

ÁÁÁ

AD INT

FLAG

ÁÁ

AD INT ENA

ÁÁ

ADSTAT

P072

A-to-D Conversion Data Register

ADDATA

P073

P07C

БББББББББББББББББББББББББББ

Reserved

ÁÁ

P07D

Port E Data Input Register

ADIN

P07E

Port E Input Enable Register

ADENA

P07F AD STEST

PRIORITY

AD ESPEN

—

ADPRI

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC, VCC3

(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0 or V

> V

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current per buffer, IO (VO = 0 to VCC)‡ ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature, T

: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A version –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T version –40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

Electrical characteristics are specified with all output buffers loaded with the specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers.

NOTE 1: Unless otherwise noted, all voltage values are with respect to VSS.

recommended operating conditions (see Note 1)

MIN NOM MAX UNIT

Supply voltage (see Note 1) 4.5 5 5.5 V

RAM data retention supply voltage (see Note 2) 3 5.5 V

CC3

Analog supply voltage (see Note 1) 4.5 5 5.5 V

SS3

Analog supply ground – 0.3 0 0.3 V

All pins except MC V

0.8

VILLow-level input voltage

MC, normal operation V

0.3

All pins except MC, XTAL2/CLKIN, and RESET 2 V

High-level input voltage

XTAL2/CLKIN

0.8 V

RESET 0.7 V

EEPROM write protect override 11.7 12 13

MC (mode control) voltage

Microcomputer

0.3

V EPROM programming voltage (VPP) 13 13.2 13.5 L version 0 70

Operating free-air temperature

A version

– 40 85

°C

T version – 40 105

NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.

2. RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-level digital output voltage IOL = 1.4 mA 0.4 V

IOH = –50 µA 0.9 V

VOHHigh-level output voltage

IOH = –2 mA 2.4

0 V < VI ≤ 0.3 V 10

0.3 V < VI ≤ 13 650

IIIn ut current

12 V ≤ VI ≤ 13 V

(see Note 3)

50 mA

Input current I/O pins 0 V ≤ VI ≤ V

±10 µA

Low-level output current VOL = 0.4 V 1.4 mA

VOH = 0.9 V

– 50 µA

IOHHigh-level output current

VOH = 2.4 V – 2 mA

SYSCLK = 5 MHz

(see Notes 4 and 5)

30 45

Supply current (Operating mode) OSC POWER bit = 0 (see Note 6)

SYSCLK = 3 MHz

(see Notes 4 and 5)

20 30

SYSCLK = 0.5 MHz

(see Notes 4 and 5)

7 11

SYSCLK = 5 MHz

(see Notes 4 and 5)

10 17

Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 7)

SYSCLK = 3 MHz

(see Notes 4 and 5)

8 11

SYSCLK = 0.5 MHz

(see Notes 4 and 5)

2 3.5

Supply current (STANDBY mode)

SYSCLK = 3 MHz

(see Notes 4 and 5)

6 8.6

y( )

OSC POWER bit = 1 (see Note 8)

SYSCLK = 0.5 MHz

(see Notes 4 and 5)

2 3.0

Supply current (HALT mode)

XTALK2/CLKIN < 0.2 V

(see Note 4)

2 30 µA

NOTES: 3. Microcontroller-single chip mode, ports configured as inputs, or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC –0.2 V.

4. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK this extra current = 0.01 mA × (total load capacitance + crystal capacitance in pF).

5. Maximum operating current = 7.6 (SYSCLK) + 7 mA.

6. Maximum standby current =3 (SYSCLK) + 2 mA. (Osc power bit = 0.)

7. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (Osc power bit = 1 and valid up to 3-MHz SYSCLK.)

8. Input current IPP is a maximum of 50 mA only when EPROM is being programmed.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

RECOMMENDED CRYSTAL/CLOCK CONNECTIONS

External

Clock Signal

XTAL1XTAL2/CLKIN

†

Crystal/Ceramic

Resonator

‡

XTAL1XTAL2/CLKIN

†

The values of C1 and C2 are typically 15 pF and C3 value is typically 50 pF. See the manufacturer’s recommendations for ceramic resonators.

‡

The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

TYPICAL OUTPUT LOAD CIRCUIT

1.2 kΩ

20 pF

Load Voltage

Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1

All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

TYPICAL INPUT BUFFERS

I/O

300 Ω

30 Ω

20 Ω

Pin Data

Output Enable

GND

INT 1

6 kΩ

20 Ω

GND

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

A Address R Read AR Array RXD SCIRXD B Byte SC SYSCLK CI XTAL2/CLKIN SCC SCICLK D Data TXD SCITXD PGM Program W Write

Lowercase subscripts and their meanings are: c cycle time (period) r rise time

d delay time su setup time f fall time v valid time h hold time w pulse duration (width)

The following additional letters are used with these meanings: H High V Valid

L Low Z High Impedance

All timings are measured between high and low measurement points as indicated in the figures below.

General Measurement PointsXTAL2/CLKIN Measurement Points

0.8 V (Low)

2 V (High)

0.8 V (Low)

0.8 VCC V (High)

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

external clocking requirements for clock divided by 4

†

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 9) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns CLKIN Crystal operating frequency 2 20 MHz SYSCLK System clock

‡

0.5 5 MHz

†

For VIL and VIH, refer to recommended operating conditions.

‡

SYSCLK = CLKIN/4

NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 18. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL)

†

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 9) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns CLKIN Crystal operating frequency 2 5 MHz SYSCLK System clock

2 5 MHz

†

For VIL and VIH, refer to recommended operating conditions.

SYSCLK = CLKIN/1

NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 19. External Clock Timing for Divide-by-1

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

switching characteristics and timing requirements (see Note 10 and Figure 20)

NO. PARAMETER MIN MAX UNIT

Divide-by-4 200 2000 ns

tcCycle time, SYSCLK (system clock)

Divide-by-1 200 500 ns

6 t

w(SCL)

Pulse duration, SYSCLK low 0.5 tc–20 0.5 t

7 t

w(SCH)

Pulse duration, SYSCLK high 0.5 tc0.5 tc + 20 ns

NOTE 10: tc = system-clock cycle time = 1/SYSCLK.

SYSCLK

Figure 20. SYSCLK Timing

general-purpose output signal-switching time requirements

MIN TYP MAX UNIT

trRise time 30 ns tfFall time 30 ns

recommended EEPROM timing requirements for programming

MIN MAX UNIT

w(PGM)B

Pulse duration, programming signal to be certain valid data is stored (byte mode) 10 ms

w(PGM)AR

Pulse duration, programming signal to be certain valid data is stored (array mode) 20 ms

recommended EPROM operating conditions for programming

MIN TYP MAX UNIT

Supply voltage 4.75 5.5 6 V

Supply voltage at MC pin 13 13.2 13.5 V

Supply current at MC pin during programming (VPP = 13 V) 30 50 mA

Divide-by-4 0.5 5

SYSCLK

System clock

Divide-by-1 2 5

recommended EPROM timing requirements for programming

MIN TYP MAX UNIT

w(EPGM)

Pulse duration, programming signal (see Note 11) 0.40 0.50 3 ms

NOTE 11: Programming pulse is active when both EXE (EPCTL.0) and V

PPS

(EPCTL.6) are set.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) INTERNAL CLOCK

ISOSYNCHRONOUS MODE I/O TIMING

SCI1 isosynchronous mode timing characteristics and requirements for internal clock (see Note 10 and Figure 21)

NO. PARAMETER MIN MAX UNIT

24 t

c(SCC)

Cycle time, SCICLK 2t

131,072t

25 t

w(SCCL)

Pulse duration, SCICLK low tc– 45 0.5t

c(SCC)

+45 ns

26 t

w(SCCH)

Pulse duration, SCICLK high tc– 45 0.5t

c(SCC)

+45 ns

27 t

d(SCCL-TXDV)

Delay time, SCITXD valid after SCICLK low – 50 60 ns

28 t

v(SCCH-TXD)

Valid time, SCITXD data after SCICLK high t

w(SCCH)

– 50 ns

29 t

su(RXD-SCCH)

Setup time, SCIRXD to SCICLK high 0.25tc + 145 ns

30 t

v(SCCH-RXD)

Valid time, SCIRXD data after SCICLK high 0 ns

NOTE 10: tc = system-clock cycle time = 1/SYSCLK.

Data Valid

SCIRXD

SCITXD

SCICLK

2827

Figure 21. SCI1 Isosynchronous Mode Timing Diagram for Internal Clock

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) EXTERNAL CLOCK

ISOSYNCHRONOUS MODE I/O TIMING

SCI1 isosynchronous mode timing characteristics and requirements for external clock (see Note 10 and Figure 22)

NO. PARAMETER MIN MAX UNIT

31 t

c(SCC)

Cycle time, SCICLK 10t

32 t

w(SCCL)

Pulse duration, SCICLK low 4.25tc + 120 ns

33 t

w(SCCH)

Pulse duration, SCICLK high tc + 120 ns

34 t

d(SCCL-TXDV)

Delay time, SCITXD valid after SCICLK low 4.25tc + 145 ns

35 t

v(SCCH-TXD)

Valid time, SCITXD data after SCICLK high t

w(SCCH)

36 t

su(RXD-SCCH)

Setup time, SCIRXD to SCICLK high 40 ns

37 t

v(SCCH-RXD)

Valid time, SCIRXD data after SCICLK high 2t

NOTE 10: tc = system-clock cycle time = 1/SYSCLK.

SCICLK

SCITXD

SCIRXD

Data Valid

34 35

Figure 22. SCI1 Isosynchronous Mode Timing Diagram for External Clock

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADC1

The ADC1 has a separate power bus for its analog circuitry . These pins are referred to as V

CC3

and V

SS3

. Their purpose is to enhance ADC1 performance by preventing digital switching noise on the logic circuitry that could be present on V

and VCC from coupling into the ADC1 analog stage. All ADC1 specifications are given with

respect to V

SS3

unless otherwise noted.

Resolution 8 bits (256 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monotonic Yes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output conversion code 00h to FFh (00h for V

≤ V

SS3

; FFh for V

≥ V

ref

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conversion time (excluding sample time) 164t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

4.5 5 5.5

CC3

Analog su ly voltage

VCC – 0.3 VCC + 0.3

SS3

Analog ground VSS – 0.3 VSS + 0.3 V

ref

Non-V

CC3

reference

†

2.5 V

CC3VCC3

+ 0.1 V

Analog input for conversion V

SS3

ref

†

ref

must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over ranges of recommended operating conditions

PARAMETER TEST CONDITIONS MIN MAX UNIT

Absolute accuracy (see Note 12) V

CC3

= 5.5 V, V

ref

= 5.1 V +1.5 LSB

Differential/integral linearity error (see Notes 12 and 13) V

CC3

= 5.5 V, V

ref

= 5.1 V ±0.9 LSB

Converting 2 mA

CC3

Analog supply current

Nonconverting 5 µA

Input current, AN0-AN7 0 V ≤ VI ≤ 5.5 V 2 µA V

ref

input charge current 1 mA

SYSCLK ≤ 3 MHz 24 kΩ

ref

Source impedance V

ref

3 MHz < SYSCLK ≤ 5 MHz 10 kΩ

NOTES: 12. Absolute resolution = 20 mV. At V

ref

= 5 V , this is 1 LSB. As V

ref

decreases, LSB size decreases and thus absolute accuracy and

differential / integral linearity errors in terms of LSBs increases.

13. Excluding quantization error of 1/2 LSB.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADC1 (continued)

The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined such that high-impedance sources can be accommodated without penalty to low-impedance sources. The sample period begins when the SAMPLE ST ART bit of the ADC1 control register (ADCTL) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START) of the ADCTL is set to 1. After a hold time, the converter resets the SAMPLE ST ART and CONVERT START bits, signaling that a conversion has started and the analog signal can be removed.

analog timing requirements

MIN MAX UNIT

su(S)

Setup time, analog input to sample command 0 ns

h(AN)

Hold time, analog input from start of conversion 18t

w(S)

Pulse duration, sample time per kilohm of source impedance (see Note 14) 1 µs/kΩ

NOTE 14: The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time

of 1 µs.

Analog Stable

su(S)

h(AN)

w(S)

Analog

Sample

Start

Convert

Start

Figure 23. Analog Timing

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 20 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name.

Table 20. TMS370Cx4x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

TMS370 GENERIC NAME

PKG TYPE NO. AND

MECHANICAL NAME

DEVICE PART NUMBERS

ÁÁÁÁ

FN – 44 pin (50-mil pin spacing)

БББББББББ

PLASTIC LEADED CHIP CARRIER (PLCC)

БББББББББ

FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

ББББББ

TMS370C040AFNA TMS370C040AFNL TMS370C040AFNT TMS370C042AFNA TMS370C042AFNL TMS370C042AFNT TMS370C340AFNA TMS370C340AFNL TMS370C340AFNT TMS370C342AFNA TMS370C342AFNL TMS370C342AFNT TMS370C742AFNT

ÁÁÁÁ

FZ – 44 pin (50-mil pin spacing)

БББББББББ

CERAMIC LEADED CHIP CARRIER (CLCC)

БББББББББ

FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

ББББББ

SE370C742AFZT

JD – 40 pin (100-mil pin spacing)

CERAMIC DUAL-IN-LINE PACKAGE (CDIP)

JD(R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

SE370C742AJDT

ÁÁÁÁ

N – 40 pin (100-mil pin spacing)

БББББББББ

PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

БББББББББ

N(R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

ББББББ

TMS370C040ANA TMS370C040ANL TMS370C040ANT TMS370C042ANA TMS370C042ANL TMS370C042ANT TMS370C340ANA TMS370C340ANL TMS370C340ANT TMS370C342ANA TMS370C342ANL TMS370C342ANT TMS370C742ANT

JC – 40 pin (70-mil pin spacing)

CERAMIC SHRINK DUAL-IN-LINE PACKAGE (CSDIP)

JC(R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

SE370C742AJCT

ÁÁÁÁ

NJ – 40 pin (70-mil pin spacing)

†

БББББББББ

PLASTIC SHRINK DUAL–IN–LINE PACKAGE (PSDIP)

БББББББББ

NJ(R–PDIP–T**) PLASTIC SHRINK DUAL-IN-LINE PACKAGE

ББББББ

TMS370C040ANJA TMS370C040ANJL TMS370C040ANJT TMS370C042ANJA TMS370C042ANJL TMS370C042ANJT TMS370C340ANJA TMS370C340ANJL TMS370C340ANJT TMS370C342ANJA TMS370C342ANJL TMS370C342ANJT TMS370C742ANJT

†

NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

E1E

MINMAXMIN

PINS

20 28 44

0.385 (9,78)

0.485 (12,32)

0.685 (17,40) 52 68 84

1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF

D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

4040219/B 03/95

0.180 (4,57)

0.140 (3,55)

0.020 (0,51)

0.032 (0,81)

A B

0.025 (0,64) R TYP

0.026 (0,66)

0.120 (3,05)

0.155 (3,94)

0.014 (0,36)

0.120 (3,05)

0.040 (1,02) MIN

0.090 (2,29)

0.040 (1,02)  45°

MIN MAX

0.485

(12,32) (12,57)

0.495

0.455

(11,56)(10,92)

0.430

MAXMIN

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

PINS**

NO. OFJEDEC

MO-087AC

MO-087AB

MO-087AA

OUTLINE

28 LEAD SHOWN

Seating Plane

(at Seating

Plane)

1426

0.050 (1,27)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

68MO-087AD

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

JC (R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

4040223-2/B 04/95

0.175 (4,46) TYP

0.020 (0,51)

0.012 (0,31)

0.016 (0,41)

Seating Plane

0.610 (15,49)

0.032 (0,81) TYP

0.009 (0,23)

0.590 (14,99)

1.335 (33,91)

1.325 (33,66)

1.386 (35,20)

1.414 (35,92)

0.600 (15,24)

0.580 (14,73)

0.040 (1,02)

0.060 (1,52)

40 21

0.093 (2,38)

0.077 (1,96)

0.070 (1,78)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

4040087/B 04/95

24 PIN SHOWN

2.650

(67,31)

PINS **

2.050

(52,07)(36,83)

1.450

0.590 (14,99)

0.620 (15,75)

1.250

DIM

A MAX

(31,75)

24 28 40

(61,85)

2.435

0.012 (0,30)

0.008 (0,20)

0.020 (0,51) MIN

Seating Plane

4 Places

0.075 (1,91) MAX

0.045 (1,14)

0.065 (1,65)

0.021 (0,53)

0.015 (0,38)

0.125 (3,18) MIN

0.175 (4,45)

0.140 (3,56)

TYP

0.590 (15,00)

0°–15°

0.100 (2,54)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

TMS370Cx4x 8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

Seating Plane

0.560 (14,22)

0.520 (13,21)

0.610 (15,49)

0.590 (14,99)

524840

0.125 (3,18) MIN

2.390

(60,71)

(62,23)(53,09)

(51,82)

2.040

2.090

2.450 2.650 (67,31)

(65,79)

2.590

0.010 (0,25) NOM

4040053/B 04/95

0.060 (1,52) TYP

322824

1.230

(31,24)

(32,26) (36,83)

(35,81)

1.410

1.450

1.270

PINS **

DIM

0.015 (0,38)

0.021 (0,53)

A MIN

A MAX

1.650

(41,91)

(40,89)

1.610

0.020 (0,51) MIN

0.200 (5,08) MAX

0.100 (2,54)

0.010 (0,25)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-011 D. Falls within JEDEC MS-015 (32 pin only)

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

NJ (R-PDIP-T**) PLASTIC SHRINK DUAL-IN-LINE PACKAGE

4040034/B 04/95

40 PIN SHOWN

2.031

(51,60)

1.425

(36,20)

DIM

A MAX

PINS **

0.200 (5,08) MAX

0.560 (14,22) MAX

0.125 (3,18) MIN

Seating Plane

0.010 (0,25) NOM

0.600 (15,24)

0.048 (1,216)

0.032 (0,816)

0.014 (0,36)

0.022 (0,56)

0.020 (0,51) MIN

0°–15°

0.010 (0,25)

0.070 (1,78)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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Texas Instruments TMS370C742ANT, TMS370C742AN2T, TMS370C742AFNT Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual