Texas Instruments TMS370C742ANT, TMS370C742AN2T, TMS370C742AFNT Datasheet
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
CMOS/EEPROM/EPROM Technologies on a
Single Device
– Mask-ROM Devices for High Volume
Production
– One-Time-Programmable (OTP) Devices
for Low-Volume Production
– Reprogrammable EPROM Devices for
Prototyping Purposes
D
Flexible Operating Features
– Low-Power Modes: STANDBY and HALT
– Commercial, Industrial, and Automotive
T emperature Ranges
– Clock Options:
– Divide-by-1 (2 MHz–5 MHz SYSCLK)
Phase-Locked Loop (PLL)
– Divide-by-4 (0.5 MHz–5 MHz SYSCLK)
– Voltage (V
CC
) 5 V ± 10%
D
Internal System Memory Configurations
– On-Chip Program Memory Versions
– ROM: 4K Bytes or 8K Bytes
– EPROM: 8K Bytes
– Data EEPROM: 256 Bytes
– Static RAM: 256 Bytes Usable as
Registers
D
Two 16-Bit General-Purpose Timers
– Software Configurable as
Two 16-Bit Event Counters, or
Two 16-Bit Pulse Accumulators, or
Three 16-Bit Input Capture Functions, or
Four Compare Registers, or
Two Self-Contained
Pulse-Width-Modulation (PWM)
Functions
D
Serial Communications Interface 1 (SCI1)
– Asynchronous and Isosynchronous
†
Modes
– Full Duplex, Double Buffered RX and TX
– Two Multiprocessor Communications
Formats
D
CMOS/Package/TTL Compatible I/O Pins
– All Peripheral Function Pins Software
Configurable for Digital I/O
– 40-Pin Plastic and Ceramic Dual-In-Line
Packages/27 Bidirectional, 5 Input Pins
– 44-Pin Plastic and Ceramic Leaded Chip
Carrier Packages/27 Bidirectional, 9
Input Pins
D
On-Chip 24-Bit Watchdog Timer
D
Eight-Bit ADC1
– Four Channels in 40-Pin Packages
– Eight Channels in 44-Pin Packages
D
Flexible Interrupt Handling
D
TMS370 Series Compatibility
D
Workstation/PC-Based Development
System
– C Compiler Support
– Real-Time In-Circuit Emulation
– C Source Debug
– Extensive Breakpoint/Trace Capability
– Software Performance Analysis
– Multi-Window User Interface
– EEPROM/EPROM Programming
JC, JD, N, AND NJ PACKAGES
(TOP VIEW)
FN AND FZ PACKAGES
(TOP VIEW)
B2
T2AEVT
T2AIC2/PWM
T2AIC1/CR
RESET
INT1
INT2
INT3
V
CC
A7
A6
V
SS
A5
A4
A3
A2
A1
A0
D7
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B1
B0
SCITXD
SCIRXD
SCICLK
D5
MC
XTAL2/CLKIN
XTAL1
T1IC/CR
T1PWM
T1EVT
AN7
AN6
V
CC3
V
SS3
AN3
AN2
D6
D3
MC
XTAL2/CLKIN
XTAL1
T1IC/CR
T1PWM
T1EVT
AN7
AN6
AN5
AN4
V
SS3
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
INT1
INT2
INT3
V
CC
V
CC3
A7
A6
V
SS
A5
A4
A3
20 21 22 23
SCITXD
SCIRXD
SCICLK
D5
54321644
RESET
T2AIC1/CR
T2AIC2/PWM
T2AEVTB2B1
B0
AN0
AN1
AN2
A2A1A0
D7D4D6
42 41 4043
24 25 26 27 28
AN3
D3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
†
Isosynchronous = Isochronous
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Descriptions
PIN
NO.
TYPE
†
DESCRIPTION
DIP (40) LCC (44)
A0
A1
A2
A3
A4
A5
A6
A7
18
17
16
15
14
13
11
10
20
19
18
17
16
15
13
12
I/O Port A pins are general-purpose bidirectional I/O ports.
B0
B1
B2
39
40
1
44
1
2
I/O Port B pins are general-purpose bidirectional I/O ports.
D3
D4
D5
D6
D7
21
20
35
22
19
23
22
40
24
21
I/O
Port D pins are general-purpose bidirectional I/O ports.
D3 is also configurable as SYSCLK.
AN0/E0
AN1/E1
AN2/E2
AN3/E3
AN4/E4
AN5/E5
AN6/E6
AN7/E7
—
—
23
24
—
—
27
28
25
26
27
28
30
31
32
33
I
Analog-to-digital converter 1 (ADC1) analog input channels or positive reference pins; any
ADC1 channel can be programmed as general-purpose input pin (E port) if not used as an
analog input or reference channel.
V
CC3
V
SS3
26
25
11
29
ADC1 converter positive supply voltage and optional positive reference input pin
ADC1 converter ground supply and low reference input pin
INT1
INT2
INT3
6
7
8
7
8
9
I
I/O
I/O
External (non-maskable or maskable) interrupt/general-purpose input pin
External maskable interrupt input/general-purpose bidirectional pin
External maskable interrupt input/general-purpose bidirectional pin
T1IC/CR
T1PWM
T1EVT
31
30
29
36
35
34
I/O
Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin
Timer 1 pulse-width-modulation output pin/general-purpose bidirectional pin
Timer 1 external event input pin/general-purpose bidirectional pin
T2AIC1/CR
T2AIC2/PWM
T2AEVT
4
3
2
5
4
3
I/O
Timer 2A input capture/counter reset input pin/general-purpose bidirectional pin
Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin
Timer 2A external event input pin/general-purpose bidirectional pin
SCITXD
SCIRXD
SCICLK
38
37
36
43
42
41
I/O
SCI transmit data output pin/general-purpose bidirectional pin
‡
SCI receive data input pin/general-purpose bidirectional pin
SCI bidirectional serial clock pin/general-purpose bidirectional pin
RESET 5 6 I/O
System reset bidirectional pin. As input, RESET initializes microcontroller; as open-drain
output, RESET
indicates detection of an internal fault by the watchdog or oscillator fault cir-
cuit.
MC 34 39 I
Mode control input pin; enables the EEPROM write-protection-override (WPO) mode, also
EPROM VPP.
XTAL1
XTAL2/CLKIN
32
33
37
38
I
O
Internal-oscillator output for crystal
Internal-oscillator crystal input/external clock source input
V
CC
V
SS
9
12
10
14
Positive supply voltage
Ground reference
†
I = input, O = output
‡
The three-pin configuration SCI is referred to as SCI1.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
Interrupts
Clock Options
Divide-by-4 or
Divide-by-1(PLL)
System
Control
INT1
AN0–AN7
INT2 INT3 MC RESET
XTAL1
A-to-D
Converter 1
Timer 2A
Timer 1
Watchdog
Serial
Communications
Interface 1
RAM
256 Bytes
(Usable as Registers)
Program Memory
ROM: 4K or 8K Bytes
EPROM:8K Bytes
Data EEPROM
0 or 256 Bytes
CPU
XTAL2/
CLKIN
SCIRXD
SCITXD
SCICLK
T2AIC1/CR
T2AEVT
T2AIC2/PWM
T1IC/CR
T1EVT
T1PWM
V
CC
V
SS
V
CC3
V
SS3
Port BPort A Port D
83 5
(40-Pin: 4 CH)
(44-Pin: 8 CH)
40-PIN DIP: AN2, AN3,
AN6, AN7
44-PIN PLCC:AN0–AN7
description
The TMS370C040A, TMS370C042A, TMS370C340A, TMS370C342A, TMS370C742A, and SE370C742A
devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the
term TMS370Cx4x refers to these devices. TMS370 family provides cost-effective real-time system control
through integration of advanced peripheral function modules and various on-chip memory configurations.
The TMS370Cx4x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM
technology. The low-operating power, wide-operating temperature range, and noise immunity of CMOS
technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx4x devices attractive in system designs for automotive electronics, industrial motor, computer
peripheral control, telecommunications, and consumer applications.
The TMS370Cx4x devices contain the following on-chip peripheral modules:
D
Eight-channel (for 44 pin device) or four-channel (for 40-pin device) 8-bit analog-to-digital converter 1
(ADC1)
D
Serial communications interface 1 (SCI1)
D
Two 16-bit general-purpose timers (one with an 8-bit prescaler)
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
D
One 24-bit general-purpose watchdog timer
Table 1 provides an overview of the various memory configurations of the TMS370Cx4x devices.
Table 1. Memory Configurations
PROGRAM MEMORY (BYTES) DATA MEMORY (BYTES)
PACKAGES
DEVICE
ROM EPROM RAM EEPROM
44 PIN/PLCC/CLCC OR
40 PIN PDIP/CDIP/PSDIP/CSDIP
TMS370C040A 4K — 256 256
FN-PLCC
N-PDIP
NJ-PSDIP
†
TMS370C042A 8K — 256 256
FN-PLCC
N-PDIP
NJ-PSDIP
†
TMS370C340A 4K — 256 —
FN-PLCC
N-PDIP
NJ-PSDIP
†
TMS370C342A 8K — 256 —
FN-PLCC
N-PDIP
NJ-PSDIP
†
TMS370C742A — 8K 256 256
FN-PLCC
N-PDIP
NJ-PSDIP
†
SE370C742A
‡
— 8K 256 256
FZ-CLCC
JD-CDIP
JC-CSDIP
†
The NJ designator for the 40-pin plastic shrink DIP package was known formerly as the N2. The mechanical drawing of the NJ is identical to the
N2 package and did not need to be requalified.
‡
System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the
configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 2. Suffix Letter Configuration
DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE
EPROM A Standard Divide-by-4 (standard oscillator) Enabled
Standard
ROM A
Hard
Divide-by-4 (standard oscillator)
-
-
Enabled or disabled
Simple
or Divide-by-1 (PLL)
The 4K bytes and 8K bytes of mask-programmable ROM in the TMS370C040A, TMS370C042A,
TMS370C340A and TMS370C342A are replaced in the TMS370C742 with 8K bytes of EPROM while all other
available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the
TMS370C340A and TMS370C342A devices. The OTP (TMS370C742A) device and the reprogrammable
device (SE370C742A) are available.
TMS370C742A (OTP) devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx4x family or for low-volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
The SE370C742A has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development/prototyping phase of design. The SE370C742A device allows quick updates to
breadboards and prototype systems while iterating initial designs.
The TMS370Cx4x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no
instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain
active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral
configuration bits throughout both low-power modes.
The TMS370Cx4x features advanced register-to-register architecture that allows arithmetic and logical
operations without requiring an accumulator (e.g., ADD R24, R47; add the contents of register 24 to the contents
of register 47 and store the result in register 47). The TMS370Cx4x family is fully instruction-set-compatible,
allowing easy transition between members of the TMS370 8-bit microcontroller family.
The TMS370Cx4x family offers an 8-channel ADC1 with 8-bit accuracy for the 44-pin PLCC packages and also
offers a 4-channel ADC1 for the 40-pin DIP packages. The 33-µs conversion time at 5-MHz SYSCLK and the
variable sample period, combined with selectable positive reference voltage sources, turn analog signals into
digital data.
The serial communications interface 1 (SCI1) module is a built-in serial interface that can be programmed to
be asynchronous or isosynchronous to give two methods of serial communications. The SCI allows standard
RS-232-C communications with other common data transmission equipment. The CPU takes no part in serial
communications except to write data to be transmitted to a register and to read data received from a register.
The TMS370Cx4x family provides the system designer with very economical, efficient solutions to real-time
control applications. The TMS370 family extended development system (XDS) and compact development
tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the
TMS370Cx4x into an ever-increasing number of complex applications. The application source code can be
written in assembly and C languages, and the output code can be generated by the linker. The TMS370 family
XDS communicates through a standard RS-232-C interface with a personal computer, allowing use of the
personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS
emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with
minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic
debug and analysis tools ensure efficient software and hardware implementation, as well as reduced
time-to-market cycle.
The TMS370Cx4x family together with the TMS370 family XDS, CDT370, starter kit, software tools, the
SE370C742A reprogrammable devices, comprehensive product documentation, and customer support
provide a complete solution for the needs of the system designer.
XDS and CDT are trademarks of Texas Instruments Incorporated.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
central processing unit (CPU)
The CPU used on the TMS370Cx4x device is the high-performance 8-bit TMS370 CPU module. The ’x4x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x4x instruction map is shown in T able 17 in the TMS370Cx4x instruction set overview
section.
The ’370Cx4x CPU architecture provides the following components:
D
CPU registers:
– A stack pointer (SP) that points to the last entry in the memory stack
– A status register (ST) that monitors the operation of the instructions and contains the
global-interrupt-enable bits
– A program counter (PC) that points to the memory location of the next instruction to be executed
Figure 1 illustrates the CPU registers and memory blocks.
Reserved
†
Peripheral File
Not Available
‡
0FFFh
1000h
1F00h
1FFFh
2000h
5FFFh
6000h
Interrupts and Reset Vectors;
Trap Vectors
10FFh
1100h
1EFFh
Reserved
†
7FFFh
0
RAM (Includes up to 256-Byte Registers File)
015
Program Counter
7
Legend:
Z=Zero
IE1=Level 1 interrupts Enable
C=Carry
V=Overflow
N=Negative
IE2=Level 2 interrupts Enable
IE1IE2ZNC
01234567
V
Status Register (ST)
Stack Pointer (SP)
R0(A)
R1(B)
R3
R127
0000h
0001h
0002h
007Fh
R255
0003h
R2
00FFh
256-Byte Data EEPROM
6FFFh
7000h
8K-Byte ROM/EPROM (6000h–6FFFh)
4K-Byte ROM (7000h–7FFFh)
7FC0h
7FBFh
00FFh
0100h
256-Byte RAM (0000h–00FFh)
0000h
†
Reserved means the address space is reserved for future expansion.
‡
Not available means the address space is not accessible.
Figure 1. Programmer’s Model
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
central processing unit (CPU) (continued)
D
A memory map that includes:
– 256-byte general-purpose RAM that can be used for data memory storage, program instructions,
general-purpose registers, or the stack
– A peripheral file that provides access to all internal peripheral modules, system-wide control functions
and EEPROM/EPROM programming control
– 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off
conditions
– 4K- or 8K-byte ROM or 8K-byte EPROM program memory
stack pointer (SP)
The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. The stack is used
typically to store the return address on subroutine calls as well as the status-register contents during interrupt
sequences.
The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM memory.
status register (ST)
The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits:
D
The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional jump instructions) use the status bits to determine program flow.
D
The two interrupt-enable bits control the two interrupt levels.
The ST register, status-bit notation, and status-bit definitions are shown in Table 3.
Table 3. Status Registers
7
6
5
4
3
2
1
0
C
N
Z
V
IE2
IE1 Reserved Reserved
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = read, W = write, 0 = value after reset
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.
The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
program counter (PC) (continued)
Memory
Program Counter (PC)
60 00
PCH PCL
60
00
0000h
7FFEh
7FFFh
Figure 2. Program Counter After Reset
memory map
The TMS370Cx4x family architecture is based on the Von Neumann architecture, where the program memory
and data memory share a common address space. All peripheral input/output is memory mapped in this same
common address space. As shown in Figure 3, the TMS370Cx4x family provides memory-mapped RAM, ROM,
data EEPROM, EPROM, input/output pins, peripheral functions, and system interrupt vectors.
The peripheral file contains all input/output port control, peripheral status and control, EPROM and EEPROM
memory programming, and system-wide control functions. The peripheral file is located between 1010h and
107Fh and is logically divided into seven peripheral file frames of 16 bytes each. Each on-chip peripheral is
assigned to a separate frame through which peripheral control and data information is passed.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map (continued)
256-Byte RAM (Register File/Stack)
Reserved
Peripheral File
Reserved
256-Byte Data EEPROM
Not Available
8K-Byte ROM or EPROM
(0000h–7FFFh)
7FC0hTrap 15-0
7FE0hReserved
7FECh
Serial Comm I/F RX
7FEEh
Timer 1
7FF0h
Interrupt 3
7FF2h
Interrupt 2
7FF4h
Interrupt 1
7FF8h
Reset
1000hReserved
1010hSystem Control
1020hDigital Port Control
1030h
ADC1 Peripheral Control
1040hTimer 1 Peripheral Control
Vectors
7FDFh
7FEBh
7FEDh
7FEFh
7FF1h
7FF3h
7FF5h
7FF9h
100Fh
101Fh
102Fh
103Fh
104Fh
–
–
–
–
–
–
–
–
–
–
–
–
–
4K-Byte ROM
(7000h–7FFFh)
Not Available
Reserved
SCI1 Peripheral Control
Timer 2A Peripheral Control
Reserved
A-D Converter 1
Timer 2A
Serial Comm I/F TX
7FFAh 7FFBh
–
–
7FFCh 7FFDh–
7FFEh 7FFFh
–
–
1050h
1060h
1070h
105Fh
106Fh
107Fh
–
–
–
1080h 10FFh–
0000h
0100h
00FFh
1000h
10FFh
1100h
1EFFh
1F00h
1FFFh
2000h
5FFFh
6000h
6FFFh
7000h
7FBFh
7FC0h
FFFFh
0FFFh
7FFFh
8000h
Interrupts and Reset
Vectors; Trap Vectors
Reserved 7FF6h 7FF7h–
Figure 3. TMS370Cx4x Memory Map
RAM/register file (RF)
Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program
memory, or the stack instructions. The TMS370Cx4x devices contain 256 bytes of internal RAM memory
mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255).
The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF)
The TMS370Cx4x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
shows the TMS370Cx4x PF address map.
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
peripheral file (PF) (continued)
Table 4. TMS370Cx4x Peripheral File Address Map
БББББ
Á
ADDRESS RANGE
БББББ
Á
PERIPHERAL FILE
DESIGNAT OR
БББББББББББББББББББ
Á
DESCRIPTION
1000h–100Fh
P000–P00F Reserved for factory test
1010h–101Fh
P010–P01F
System and EPROM/EEPROM control registers
1020h–102Fh
P020–P02F
Digital I/O port control registers
1030h–103Fh
P030–P03F
Reserved
1040h–104Fh
P040–P04F
Timer 1 registers
1050h–105Fh
P050–P05F Serial communications interface 1 registers
1060h–106Fh
P060–P06F
Timer 2A registers
1070h–107Fh
P070–P07F
Analog-to-digital converter 1 registers
1080h–10FFh
P080–P0FF
Reserved
data EEPROM
The TMS370Cx4x devices, containing 256 bytes of data EEPROM, have memory mapped beginning at location
1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data
EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm
examples are available in the
TMS370 Family User’s Guide
(literature number SPNU127) or the
TMS370
Family Data Manual
(literature number SPNS014B). The data EEPROM features include the following:
D
Programming:
– Bit-, byte-, and block-write/erase modes
– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.
– Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame
beginning at location P01A (see Table 5).
– In-circuit programming capability. There is no need to remove the device to program it.
D
Write protection. Writes to the data EEPROM are disabled during the following conditions.
– Reset. All programming of the data EEPROM module is halted.
– Write protection active. There is one write-protect bit per 32-byte EEPROM block.
– Low-power mode operation
D
Write protection can be overridden by applying 12 V to MC.
T able 5. Data EEPROM and PROGRAM EPROM Control Register Memory Map
ADDRESS SYMBOL NAME
P01A DEECTL DATA EEPROM Control Register
P01B — Reserved
P01C EPCTL Program EPROM Control Register
TMS370Cx4x
8-BIT MICROCONTROLLER
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program EPROM
The TMS370C742A device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing
through location 7FFFh. Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI),
and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used
with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the
program EPROM modules is identical to reading other internal memory . During programming, the EPROM is
controlled by the EPROM control register (EPCTL). The program EPROM module features include:
D
Programming
– In-circuit programming capability if VPP is applied to MC
– Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in
the peripheral file (PF) frame at location P01C as shown in Table 5.
D
Write protection: writes to the program EPROM are disabled under the following conditions:
– Reset: All programming to the EPROM module is halted.
– Low-power modes
– 13 V not applied to MC
program ROM
The program ROM consists of 4K or 8K bytes of mask-programmable read-only memory . The program ROM
is used for permanent storage of data or instructions. Memory addresses 7FE0h through 7FEBh are reserved
for TI, and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors,
used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh.
Programming of the mask ROM is performed at the time of device fabrication.
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx4x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
generated internally , while one (RESET
pin) is controlled externally. These actions are as follows:
D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the
TMS370 Family
User’s Guide
(literature number SPNU127) for more information.
D
Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the
TMS370 Family User’s Guide
(literature number SPNU127) for more information.
D
External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 Family User’s Guide
(literature number SPNU127) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x4x device to reset external system components. Additionally , if a cold start (V
CC
is off
for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag
(COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 lists the reset sources.
TI is a trademark of Texas Instruments Incorporated.
TMS370Cx4x
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system reset (continued)
Table 6. Reset Sources
REGISTER
ADDRESS
PF
BIT NO.
CONTROL BIT
SOURCE OF RESET
SCCR0
1010h
P010
7
COLD START
Cold (power-up)
SCCR0
1010h
P010
4
OSC FLT FLAG
Oscillator out of range
T1CTL2
104Ah
P04A
5
WD OVRFL INT FLAG
Watchdog timer timeout
Once a reset is activated, the following sequence of events occurs:
1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2. Registers A and B are initialized to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.
TMS370Cx4x
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interrupts
The TMS370 family software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be independently enabled by the global-interrupt enable bits (IE1 and IE2)
of the status register.
TIMER 2A
CPU
NMI
Logic
Enable
IE1
IE2
Level 1 INT
Level 2 INT
T2A PRI
Priority
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Input Capture 2
EXT INT 3
INT3 PRI
INT 3
STATUS REG
EXT INT1
INT1 PRI
INT1
EXT INT 2
INT2 PRI
INT 2
AD INT
AD PRI
A/D
TIMER 1
T1 PRI
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Watchdog
SCI INT
RX
BRKDT
RXRDY
TX
TXRDY
TXPRI
RXPRI
Figure 4. Interrupt Control
Each system interrupt is configured independently on either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
TMS370Cx4x
8-BIT MICROCONTROLLER
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interrupts (continued)
chains is performed within the peripheral modules to support interrupt expansion to future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
The TMS370Cx4x has eight hardware system interrupts (plus RESET
) as shown in Table 7. Each system
interrupt has a dedicated interrupt vector located in program memory through which control is passed to the
interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXNT has two
interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in
the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for
determining which interrupt source generated the associated system interrupt.
Five of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are
supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software-configurable for input
polarity (rising or falling) for ease of system interface. External interrupt INT1 is software-configurable as either
a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the
individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the
interrupt function is not required (INT1 can be configured similarly as an input pin).
T able 7. Hardware System Interrupts
INTERRUPT SOURCE INTERRUPT FLAG
SYSTEM
INTERRUPT
VECTOR
ADDRESS
PRIORITY
†
External RESET
Watchdog Overflow
Oscillator Fault Detect
COLD START
WD OVRFL INT FLAG
OSC FLT FLAG
RESET
‡
7FFEh, 7FFFh 1
External INT1 INT1 FLAG INT1
‡
7FFCh, 7FFDh 2
External INT2 INT2 FLAG INT2
‡
7FFAh, 7FFBh 3
External INT3 INT3 FLAG INT3
†
7FF8h, 7FF9h 4
Timer 1 Overflow
Timer 1 Compare 1
Timer 1 Compare 2
Timer 1 External Edge
Timer 1 Input Capture
Watchdog Overflow
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC INT FLAG
WD OVRFL INT FLAG
T1INT
§
7FF4h, 7FF5h 5
SCI RX Data Register Full
SCI RX Break Detect
RXRDY FLAG
BRKDT FLAG
RXINT
‡
7FF2h, 7FF3h 6
SCI TX Data Register Empty TXRDY FLAG TXINT 7FF0h, 7FF1h 7
Timer 2A Overflow
Timer 2A Compare 1
Timer 2A Compare 2
Timer 2A External Edge
Timer 2A Input Capture 1
Timer 2A Input Capture 2
T2A OVRFL INT FLAG
T2AC1 INT FLAG
T2AC2 INT FLAG
T2AEDGE INT FLAG
T2AIC1 INT FLAG
T2AIC2 INT FLAG
T2AINT 7FEEh, 7FEFh 8
A-D Conversion Complete AD INT FLAG ADINT 7FECh, 7FEDh 9
†
Relative priority within an interrupt level.
‡
Releases microcontroller from STANDBY and HALT low-power modes.
§
Releases microcontroller from STANDBY low-power mode.
TMS370Cx4x
8-BIT MICROCONTROLLER
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privileged operation and EEPROM write-protection override
The TMS370Cx4x family has significant flexibility to enable the designer to software-configure the system and
peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation
ensures the integrity of the system configuration, once defined for an end application. Following a hardware
reset, the TMS370Cx4x operates in the privileged mode, where all peripheral file registers have unrestricted
read/write access and the application program configures the system during the initialization sequence
following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1,
entering the nonprivileged mode and disabling write operations to specific configuration control bits within the
peripheral file. The system-configuration bits listed in T able 8 are write-protected during the nonprivileged mode
and must be configured by software prior to exiting the privileged mode.
Table 8. Privilege Bits
REGISTER
†
NAME LOCATION
CONTROL BIT
SCCR0
P010.5
P010.6
PF AUTO WAIT
OSC POWER
SCCR1
P011.2
P011.4
MEMORY DISABLE
AUTOWAIT DISABLE
SCCR2
P012.0
P012.1
P012.3
P012.4
P012.6
P012.7
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY
SCIPRI
P05F.4
P05F.5
P05F.6
P05F.7
SCI ESPEN
SCI RX PRIORITY
SCI TX PRIORITY
SCI STEST
T1PRI
P04F.6
P04F.7
T1 PRIORITY
T1 STEST
T2APRI
P06F.6
P06F.7
T2A PRIORITY
T2A STEST
ADPRI
P07F.5
P07F.6
P07F.7
AD ESPEN
AD PRIORITY
AD STEST
†
The privileged bits are shown in a bold typeface in the peripheral file frames of the
following sections.
The WPO mode provides an external hardware method for overriding the write protection registers (WPR) of
data EEPROM on the TMS370Cx4x. Applying a 12-V input to the MC pin after the RESET pin input goes high
causes the device to enter WPO mode. The high voltage on the MC pin during the WPO mode is not the
programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system level capability to modify the content of data
EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx4x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time the mask is manufactured.
TMS370Cx4x
8-BIT MICROCONTROLLER
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low-power and IDLE modes (continued)
The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.
In the ST ANDBY mode (HAL T/ST ANDBY = 0 ), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, Timer 1, and the receive start-bit-detection circuit of the SCI1 remain
active. System processing is suspended until a qualified interrupt (hardware RESET
, external interrupt on INT1,
INT2, INT3, Timer 1 interrupt, or a low level on the receive pin of the serial communications interface 1) is
detected.
In the HALT mode (HALT/STANDBY=1 ), the TMS370Cx4x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET
external interrupt on INT1, INT2, INT3, or low level on
the receive pin of the SCI1) is detected. The power-down mode selection bits are sumarized in Table 9.
Table 9. Low-Power/Idle Control Bits
POWER-DOWN CONTROL BITS
PWRDWN/IDLE
(SCCR2.6)
HALT/STANDBY
(SCCR2.7)
MODE SELECTED
1 0 STANDBY
1 1 HALT
0 X IDLE
X = don’t care
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is always generated, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU-instruction processing is stopped during the
STANDBY and HALT modes, the clocking of the WD timer is inhibited.
clock modules
The ’x4x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The ’x4x ROM-masked devices of fer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’742A
EPROM has only the divide-by-4.
The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN)
to the internal system clock (SYSCLK) frequency. The divide-by-4 option produces a SYSCLK which is
one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the
external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide
the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.
TMS370Cx4x
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clock modules (continued)
These are formulated as follows:
Divide-by-4 : SYSCLK
+
external resonator frequency
4
+
CLKIN
4
Divide-by-1 : SYSCLK
+
external resonator frequency 4
4
+
CLKIN
The main advantage of choosing a divide-by-1 oscillator is the reduction of EMI. The harmonics of low-speed
resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a steeper
decay of emissions produced by the oscillator.
system configuration registers
Table 10 contains system configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface.
Table 10. Peripheral File Frame 1: System Configuration Registers
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
P010
COLD
START
OSC
POWER
PF AUTO
WAIT
OSC FLT
FLAG
MC PIN
WPO
MC PIN
DATA
—
µP/µC
MODE
SCCR0
P011
—
— —
AUTOWAIT
DISABLE
—
MEMORY
DISABLE
— — SCCR1
P012
HALT/
STANDBY
PWRDWN/
IDLE
—
BUS
STEST
CPU
STEST
—
INT1
NMI
PRIVILEGE
DISABLE
SCCR2
P013
to
P016
Reserved
P017
INT1
FLAG
INT1
PIN DATA
— — —
INT1
POLARITY
INT1
PRIORITY
INT1
ENABLE
INT1
P018
INT2
FLAG
INT2
PIN DATA
—
INT2
DATA DIR
INT2
DATA OUT
INT2
POLARITY
INT2
PRIORITY
INT2
ENABLE
INT2
P019
INT3
FLAG
INT3
PIN DATA
—
INT3
DATA DIR
INT3
DATA OUT
INT3
POLARITY
INT3
PRIORITY
INT3
ENABLE
INT3
P01A BUSY — — — — AP W1W0 EXE DEECTL
P01B Reserved
P01C BUSY VPPS — — — — W0 EXE EPCTL
P01D
P01E
P01F
Reserved
TMS370Cx4x
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digital port control registers
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 and Table 12
detail the specific addresses, registers, and control bits within the peripheral file frame.
Table 11. Peripheral File Frame 2: Digital Port Control Registers
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
P020 Reserved APORT1
P021 Port A Control Register 2 (must be 0) APORT2
P022 Port A Data ADATA
P023 Port A Direction ADIR
P024 Reserved BPORT1
P025 — — — — — Port B Control Register 2 (must be 0) BPORT2
P026 — — — — — Port B Data BDATA
P027 — — — — — Port B Direction BDIR
P028
to
P02B
Reserved
P02C Port D Control Register 1 (must be 0) — — — DPORT1
P02D Port D Control Register 2 (must be 0)
†
— — — DPORT2
P02E Port D Data — — — DDATA
P02F Port D Direction — — — DDIR
†
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 12. Port Configuration Register Setup
PORT PIN
abcd
00q1
abcd
00y0
A 0 – 7 Data Out q Data In y
B 0 – 2 Data Out q Data In y
D 3 – 7 Data Out q Data In y
a = Port × Control Register 1
b = Port × Control Register 2
c = Data
d = Direction
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timer 1 module
The programmable Timer 1 (T1) module of the TMS370Cx4x provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock
sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The T1 module includes three external device pins that can be used
for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The T1
module block diagram is shown in Figure 5.
T1IC/CR
Edge
Select
16-Bit
Counter
T1EVT
MUX
MUX
16-Bit
Register
T1PWM
PWM
Toggle
16
16-Bit
Watchdog Counter
(Aux. Timer)
Interrupt
Logic
Capt/Comp
16-Bit
Register
Compare
Interrupt
Logic
8-Bit
Prescaler
Figure 5. Timer 1 Block Diagram
D
Three T1 I/O pins
– T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin
D
Two operational modes:
– Dual-compare mode: Provides PWM signal
– Capture/compare mode: Provides input capture pin
D
One 16-bit general-purpose resettable counter
D
One 16-bit compare register with associated compare logic
D
One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register.
D
One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD
feature is not needed.
D
Prescaler/clock sources that determine one of eight clock sources for general-purpose timer
TMS370Cx4x
8-BIT MICROCONTROLLER
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timer 1 module (continued)
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR)
D
Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external edge detection
D
Sixteen T1 module control registers located in the PF frame, beginning at address P040
The T1 module control registers are illustrated in Table 13.
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