Texas Instruments TMS370C6C2ANT, TMS370C6C2AFNT, TMS370C3C0ANT, TMS370C3C0ANL, TMS370C3C0ANA Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

CMOS/EEPROM/EPROM Technologies on
a Single Device
– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

D

Internal System Memory Configurations
– On-Chip Program Memory Versions

– ROM: 4K Bytes
– EPROM: 8K Bytes

– Static RAM: 128 Bytes

D

Flexible Operating Features
– Low-Power Modes: STANDBY and HALT
– Commercial, Industrial, and Automotive

T emperature Ranges

– Clock Options

– Divide-by-4 (0.5 to 5 MHz SYSCLK)
– Divide-by-1 (2 to 5 MHz SYSCLK) PLL

– Supply Voltage (V

CC

) 5 V ±10%

D

Four-Channel 8-Bit Analog-to-Digital
Converter 2 (ADC2)

D

16-Bit General-Purpose Timer
– Software Configurable as

a 16-Bit Event Counter, or
a 16-Bit Pulse Accumulator, or
a 16-Bit Input Capture Function, or
T wo Compare Registers, or
a Self-Contained
Pulse-Width-Modulation (PWM) Function

D

On-Chip 24-Bit Watchdog Timer
– EPROM/OTP Devices: Standard

Watchdog

– Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

D

Flexible Interrupt Handling

D

Workstation/Personal Computer-Based
Development System
– C Compiler and C Source Debugger
– Real-Time In-Circuit Emulation
– Extensive Breakpoint/Trace Capability
– Software Performance Analysis
– Multi-Window User Interface
– Microcontroller Programmer

D

Serial Communications Interface 2 (SCI2)
– Asynchronous Mode: 156 Kbps

Maximum at 5 MHz SYSCLK

– Full Duplex, Double-Buffered Receiver

(RX) and Transmitter (TX)

D

TMS370 Series Compatibility
– Register-to-Register Architecture
– 256 General-Purpose Registers
– 14 Powerful Addressing Modes
– Instructions Upwardly Compatible With

All TMS370 Devices

D

CMOS/TTL Compatible I/O Pins/Packages
– All Peripheral Function Pins Software

Configurable for Digital I/O
– 17 Bidirectional Pins, 5 Input Pins
– 28-Pin Plastic and Ceramic Dual-In-Line,

or Leaded Chip Carrier Packages

5
6
7
8
9
10
11

3212827

12 13

25
24
23
22
21
20
19

AN3
AN2
AN1
AN0
SCITXD
SCIRXD
MC

XTAL2/CLKIN

XTAL1

A6
A5
A4
A3
A2

426

14 15 16 1718

A1

A0

INT1

T1EVT

T1PWM

T1IC/CR

A7D6D3/SYSCLKVV

RESET

D4

FZ AND FN PACKAGES

(TOP VIEW)

D7

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

D3/SYSCLK

D6
A7

XTAL2/CLKIN

XTAL1

A6
A5
A4
A3
A2
D7
A1
A0

V

SS

RESET
D4
AN3
AN2
AN1
AN0
SCITXD
SCIRXD
MC
T1IC/CR
T1PWM
T1EVT
INT1

JD AND N PACKAGES

(TOP VIEW)

CC

SS

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

TMS370CxCx
8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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Pin Descriptions

28 PINS

DIP and LCC

I/O

†

DESCRIPTION

NAME NO.

A0
A1
A2
A3
A4
A5
A6
A7

14
13
11
10

9
8
7
4

I/O Port A is a general-purpose bidirectional I/O port.

D3/SYSCLK
D4
D6
D7

2

26

3

12

I/O Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

INT1 15 I External interrupt (non-maskable or maskable)/general-purpose input pin.
AN0/E0

AN1/E1
AN2/E2
AN3/E3

22
23
24
25

I

ADC2 module analog input (AN0–AN3) or positive reference pins (AN1–AN3).

Port E can be individually programmed as general-purpose input pins if not used as ADC2 analog input.

T1IC/CR
T1PWM
T1EVT

18
17
16

I/O

Timer1 input capture/counter reset input pin /general-purpose bidirectional pin.
Timer1 PWM output pin/general-purpose bidirectional pin.
Timer1 external event input pin/general-purpose bidirectional pin.

SCITXD
SCIRXD

21
20

I/O

SCI module transmit data output/general-purpose bidirectional pin. (See Note 1)
SCI module receive data input pin/general-purpose bidirectional pin.

RESET 27 I/O

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,
RESET

indicates that an internal failure was detected by watchdog or oscillator fault circuit.
MC 19 I Mode control input pin; programming EPROM when VPP is applied to MC pin.
XTAL2/CLKIN

XTAL1

5
6

I

O

Internal oscillator crystal input/External clock source input.
Internal oscillator output for crystal.

V

CC

1 Positive supply voltage

V

SS

28 Ground reference

†

I = input, O = output

NOTE 1: The two SCI configuration pins are referenced to as SCI2.

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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functional block diagram

Interrupts

T1IC/CR
T1EVT
T1PWM

V

System
Control

Clock Options:
Divide-By-4 Or

Divide-By-1 (PLL)

RAM

128 Bytes

CPU

Port A Port D

Timer 1

Watchdog

INT1

XTAL1

XTAL2/

CLKIN

MC

SCIRXD
SCITXD

Serial

Communications

Interface 2

RESET

SS

V

CC

Program Memory

ROM: 4K Bytes

EPROM: 8K Bytes

4

A-to-D

Converter 2

E0–E3

or

AN0–AN3

8

description

The TMS370C3C0, TMS370C6C2, and SE370C6C2 devices are members of the TMS370 family of single-chip
8-bit microcontrollers. Unless otherwise noted, the term TMS370CxCx refers to these devices. The TMS370
family provides cost-effective real-time system control through integration of advanced peripheral function
modules and various on-chip memory configurations.

The TMS370CxCx family of devices is implemented using high-performance silicon-gate CMOS EPROM
technologies. Low-operating power, wide-operating temperature range, and noise immunity of CMOS
technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370CxCx devices attractive in system designs for automotive electronics, industrial motors, computer
peripheral controls, telecommunications, and consumer applications.

All TMS370CxCx devices contain the following on-chip peripheral modules:

D

Four-channel, 8-bit analog to digital converter 2 (ADC2)

D

Serial communications interface 2 (SCI2)

D

One 24-bit general-purpose watchdog timer

D

One 16-bit general-purpose timer with an 8-bit prescaler

TMS370CxCx
8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

Table 1 provides a memory configuration overview of the TMS370CxCx devices.

Table 1. Memory Configurations

DEVICES

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

-

ROM EPROM RAM EEPROM

28-PIN LCC OR DIP

TMS370C3C0A 4K — 128 —

FN – PLCC

N – PDIP

TMS370C6C2A — 8K 128 —

FN – PLCC

N – PDIP

SE370C6C2A

†

— 8K 128 —

FZ – CLCC

JD – CDIP

†

System evaluators and development are for use only in prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device name (shown in T able 1) indicates configuration of the device. ROM
or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A
are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 or

-

-

Enabled or disabled

Simple

Divide-by-1 (PLL)

The 4K bytes of mask-programmable ROM in the associated TMS370C3C0A device are replaced in the
TMS370C6C2A with 8K bytes of EPROM while all other available memory and on-chip peripherals are identical.
The one-time programmable (OTP) (TMS370C6C2A) and reprogrammable (SE370C6C2A) devices are
available.

TMS370C6C2A OTP devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370C3C0A or for low-volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C6C2A has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development-prototyping phase of design. The SE370C6C2A devices allow quick updates to
breadboards and prototype systems during initial design iterations.

The TMS370CxCx family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity , that is, no instructions are executed. In the
STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all
device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.

The TMS370CxCx features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370CxCx family is fully instruction-set
compatible, providing easy transition between members of the TMS370 8-bit microcontroller family.

TMS370CxCx

8-BIT MICROCONTROLLER

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description (continued)

The TMS370CxCx device has one operational mode of serial communications provided by the SCI2 module.
The SCI2 allows standard RS-232-C communications with other common data transmission equipment.

The TMS370CxCx family provides the system designer with economical, efficient solutions to real-time control
applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently
developing the software and hardware required to design the TMS370CxCx into an ever-increasing number of
complex applications. The application source code can be written in assembly and C-language, and the output
code can be generated by the linker. The TMS370 family CDT development tool can communicate through a
standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer
editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use
through extensive menus and screen windowing so that a system designer can begin developing software with
minimal training. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure
efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370CxCx family together with the TMS370 family CDT370, software tools, the SE370C6C2A
reprogrammable devices, comprehensive product documentation, and customer support provide a complete
solution to the needs of the system designer.

central processing unit (CPU)

The CPU used on the TMS370CxCx device is the high-performance 8-bit TMS370 CPU module. The ’xCx
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’xCx instruction map is shown in Table 36 in the TMS370CxCx instruction set
overview section.

The ’370CxCx CPU architecture provides the following components:
CPU registers:

D

A stack pointer that points to the last entry in the memory stack.

D

A status register that monitors the operation of the instructions and contains the global-interrupt enable bits.

D

A program counter (PC) that points to the memory location of the next instruction to be executed.

CDT is a trademark of Texas Instruments Incorporated.

TMS370CxCx
8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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central processing unit (CPU) (continued)

Figure 1 illustrates the CPU registers and memory blocks.

0080h
0FFFh

Reserved

†

Peripheral File

Not Available

‡

1FFFh
2000h

5FFFh
6000h

Interrupts and Reset Vectors;

Trap Vectors

107Fh
1080h

Reserved

7FFFh

0

RAM (Includes up to 256-Byte Registers File)

015

Program Counter

7

Legend:

Z=Zero

IE1=Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 interrupts Enable

IE1IE2ZNC

01234567

V

Status Register (ST)

Stack Pointer (SP)

R0(A)
R1(B)

R3

0000h
0001h

0002h

R127

0003h

R2

007Fh

6FFFh
7000h

8K-Byte EPROM (6000h–7FFFh)

4K-Byte ROM (7000h–7FFFh)

7FC0h

7FBFh

128-Byte RAM (0000h–007Fh)

007Fh

1000h

0000h

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

A memory map that includes:

D

128-byte general-purpose RAM that can be used for data memory storage, program instructions,
general-purpose register, or the stack

D

A peripheral file that provides access to all internal peripheral modules, system-wide control functions and
EPROM programming control

D

4K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register that operates as a last-in, first-out, read/write memory. Typically, the stack is
used to store the return address on subroutine calls as well as the status-register contents during interrupt
sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM.

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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central processing unit (CPU) (continued)

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST register
includes four status bits (condition flags) and two interrupt-enable bits:

D

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional jump instructions) use the status bits to determine program flow.

D

The two interrupt-enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Register (ST)

765432 1 0

C

N Z V IE2 IE1 Reserved Reserved

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
7000h as the contents of the reset vector.

Memory

Program Counter (PC)

70 00

PCH PCL

70
00

0000h

7FFEh
7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370CxCx architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input/output is memory mapped in this same common
address space. As shown in Figure 3, the TMS370CxCx provides memory-mapped RAM, ROM, input/output
pins, peripheral functions, and system interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EPROM, and
system-wide control functions. The peripheral file is located from 1000h to 107Fh and is logically divided into
seven peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through
which peripheral control and data information is passed.

TMS370CxCx
8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

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memory map (continued)

128-Byte RAM

(Register File/Stack)

Peripheral File

Reserved

†

Not Available

‡

Reserved

†

System Control

Digital Port Control

Timer 1 Peripheral Control

Vectors

Not Available

‡

Reserved

†

0000h

0080h

007Fh

1000h
107Fh

1080h

1FFFh

2000h

5FFFh

6000h

6FFFh

7000h

FFFFh

0FFFh

4K-Byte ROM

(7000h–7FFFh)

Interrupts and Reset Vectors;

Trap Vectors

7FBFh
7FC0h

7FFFh

8000h

Peripheral File Control Registers

8K-Byte EPROM

(6000h–7FFFh)

1010h–101Fh
1020h–102Fh

1040h–104Fh

1030h–103Fh

SCI2 Peripheral Control 1050h–105Fh

Trap 15–0

7FC0h–7FDFh

Reserved

†

7FE0h–7FEBh

Analog-To-Digital Converter 2 7FECh–7FEDh

Reserved

†

7FEEh–7FEFh

SCI TX

7FF0h–7FF1h

SCI RX

7FF2h–7FF3h

Timer 1 7FF4h–7FF5h

Reserved

†

7FF6h–7FFBh

Interrupt 1 7FFCh–7FFDh

Reset 7FFEh–7FFFh

Reserved

†

1000h–100Fh

Reserved

†

1060h–106Fh

ADC2 Peripheral Control 1070h–107Fh

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

Figure 3. TMS370CxCx Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program
memory, or the stack instructions. The TMS370CxCx devices contain 128 bytes of internal RAM mapped
beginning at location 0000h (R0) and continuing through location 007Fh (R127) which is shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
SP is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370CxCx control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
shows the TMS370CxCx PF address map.

TMS370CxCx

8-BIT MICROCONTROLLER

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peripheral file (PF) (continued)

Table 4. TMS370CxCx Peripheral File Address Map

ADDRESS RANGE

PERIPHERAL FILE

DESIGNAT OR

DESCRIPTION

1000h–100Fh P000–P00F Reserved
1010h–101Fh P010–P01F System and EPROM control registers
1020h–102Fh P020–P02F Digital I/O port control registers
1030h–103Fh P030–P03F Reserved
1040h–104Fh P040–P04F T imer 1 registers
1050h–105Fh P050–P05F Serial communications interface 2 registers
1060h–106Fh P060–P06F Reserved
1070h–107Fh P070–P07F Analog-to-digital converter 2 registers
1080h–1FFFh P080–P0FF Reserved

program EPROM

†

The TMS370C6C2 device contains 8K bytes of EPROM mapped at location 6000h and continuing through
location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading other
internal memory. During programming, the EPROM is controlled by the EPROM control register (EPCTL). The
program EPROM module features include:

D

Programming
– In-circuit programming capability if V

PP

is applied to MC

– Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 5.

D

Write protection: Writes to the program EPROM are disabled under the following conditions:
– Reset halts all programming to the EPROM module.
– Low-power modes
– 13 V not applied to MC

T able 5. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

SYMBOL

NAME

P01A to P01B

—

Reserved

P01C

EPCTL

Program EPROM Control Register

program ROM

†

The program read-only memory (ROM) consists of 4K bytes of mask-programmable ROM. The program ROM
is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time
of device fabrication. Refer to Figure 3 for ROM memory map.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and addresses 7FECh through 7FFFh are reserved for
interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and
7FDFh.

TMS370CxCx
8-BIT MICROCONTROLLER

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system reset

The system reset operation ensures an orderly start-up sequence for the TMS370CxCx CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
internally generated, while one (RESET

pin) is controlled externally. These actions are as follows:

D

External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

D

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 User’s

Guide

(literature number SPNU127) for more information.

D

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven low (active) for a minimum of eight SYSCLK
cycles. This allows the ’xCx device to reset external system components. Additionally , if a cold start (V

CC

is off
for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag
(COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

Table 6. Reset Sources

REGISTER ADDRESS PF BIT NO. CONTROL BIT SOURCE OF RESET

SCCR0 1010h P010 7 COLD START Cold (power-up)
SCCR0 1010h P010 4 OSC FLT FLAG Oscillator out of range

T1CTL2 104Ah P04A 5 WD OVRFL INT FLAG Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.

interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of
the status register.

TMS370CxCx

8-BIT MICROCONTROLLER

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interrupts (continued)

TIMER 1

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT
Level 2 INT

T1 PRI

Priority

Overflow

Compare 1

Ext Edge

Compare 2
Input Capture 1
Watchdog

ADC2 INT

A/D PRI

A/D

STATUS REG

EXT INT 1

INT1 PRI

INT1

SCI2 INT

RX

BRKDT

RXRDY

TX

TXRDY

TXPRI

RXPRI

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is selectively configured on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules.
Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt
mask and priority conditions.

The TMS370CxCx has five hardware system interrupts (plus RESET

) as shown in Table 7. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. A system interrupt may have multiple interrupt sources (for example, SCI RXINT has two
interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in
the associated peripheral file. Each interrupt source FLAG bit is readable individually for software polling or for
determining which interrupt source generated the associated system interrupt.

Four of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is
supported. Software configuration of the external interrupts is performed through the INT1 control register in
peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or
falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable
or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual-

TMS370CxCx
8-BIT MICROCONTROLLER

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interrupts (continued)

or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and therefore should
be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupt
INT1 can be software-configured as a general-purpose input pin if the interrupt function is not required.

T able 7. Hardware System Interrupts

INTERRUPT SOURCE INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY

†

External RESET
Watchdog Overflow
Oscillator Fault Detect

COLD START
WD OVRFL INT FLAG
OSC FLT FLAG

RESET

‡

7FFEh, 7FFFh 1

External INT1 INT1 FLAG INT1

‡

7FFCh, 7FFDh 2

Timer 1 Overflow
Timer 1 Compare 1
Timer 1 Compare 2
Timer 1 External Edge
Timer 1 Input Capture 1
Watchdog Overflow

T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC1 INT FLAG
WD OVRFL INT FLAG

T1INT

§

7FF4h, 7FF5h 3

SCI RX Data Register Full
SCI RX Break Detect

RXRDY FLAG
BRKDT FLAG

RXINT

‡

7FF2h, 7FF3h 4

SCI TX Data Register Empty TXRDY FLAG TXINT 7FF0h, 7FF1h 5
A/D Conversion Complete AD INT FLAG ADINT 7FECh, 7FEDh 6

†

Relative priority within an interrupt level.

‡

Release microcontroller from STANDBY and HALT low-power modes.

§

Release microcontroller from STANDBY low-power mode.

privileged operation and EEPROM write-protection override

The TMS370CxCx family has significant flexibility to enable the designer to software configure the system and
peripherals to meet the requirements of a variety of applications. The non-privileged mode of operation ensures
the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the
TMS370CxCx operates in the privileged mode, where all peripheral file registers have unrestricted read/write
access, and the application program configures the system during the initialization sequence following reset.
As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the
non-privileged mode; thus, disabling write operations to specific configuration control bits within the peripheral
file. T able 8 displays the system configuration bits which are write-protected during the non-privileged mode and
must be configured by software prior to exiting the privileged mode.

TMS370CxCx

8-BIT MICROCONTROLLER

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privileged operation and EEPROM write-protection override (continued)

Table 8. Privilege Bits

REGISTER

†

NAME LOCATION

CONTROL BIT

SCCR0

P010.5
P010.6

PF AUTO WAIT
OSC POWER

SCCR1

P011.2
P011.4

MEMORY DISABLE
AUTOWAIT DISABLE

SCCR2

P012.0
P012.1
P012.3
P012.4
P012.6
P012.7

PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY

T1PRI

P04F.6
P04F.7

T1 PRIORITY
TI STEST

SCIPRI

P05F.4
P05F.5
P05F.6
P05F.7

SCI ESPEN
SCIRX PRIORITY
SCITX PRIORITY
SCI STEST

ADPRI

P07F.5
P07F.6
P07F.7

AD ESPEN
AD PRIORITY
AD STEST

†

The privilege bits are shown in a bold typeface in the peripheral file
frame 1 section.

low-power and IDLE modes

The TMS370CxCx devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops;
however, the oscillator, internal clocks, timer 1, and the receive-start bit detection circuit of the serial
communications interface 2 remain active. System processing is suspended until a qualified interrupt (hardware
RESET

, external interrupt on INT1, timer 1 interrupt, or low level in the receive pin of the SCI2) is detected.

In the HAL T mode (HAL T/STANDBY = 1), the TMS370CxCx is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET , external interrupt on the INT1, or low level on the receive
pin of the serial communications interface 2) is detected. The power-down mode selection bits are summarized
in Table 9.

TMS370CxCx
8-BIT MICROCONTROLLER

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low-power and IDLE modes (continued)

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

1 0 STANDBY
1 1 HALT
0 X

†

IDLE

†

Don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6-7 bits are ignored. In addition, if an idle instruction executes when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI always is generated, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU instruction processing stops during the STANDBY
and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ’xCx family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The ’xCx ROM-masked devices of fer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’6C2A
EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.

The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN)
to the internal system clock (SYSCLK) frequency , whereas the divide-by-4 option produces a SYSCLK which
is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the
external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide
the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

TMS370CxCx

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clock modules (continued)

These are formulated as follows:

Divide-by-4 : SYSCLK

+

external resonator frequency

4

+

CLKIN

4

Divide-by-1 : SYSCLK

+

external resonator frequency 4

4

+

CLKIN

The main advantage of choosing a divide-by-1 oscillator is to reduce EMI. The harmonics of low-speed
resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a steeper
decay of emissions produced by the oscillator.

system configuration registers

Table 10 contains system configuration and control functions. The privileged bits are shown in bold typeface
and shaded areas.

Table 10. System Configuration Registers

PF

BIT 7

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

P010

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

—

µP/µC
MODE

SCCR0

P011 — — —

AUTO

WAIT

DISABLE

—

MEMORY
DISABLE

— — SCCR1

P012

HALT/

STANDBY

PWRDWN/

IDLE

—

BUS

STEST

CPU

STEST

—

INT1

NMI

PRIVILEGE

DISABLE

SCCR2

P013

to

P016

RESERVED

P017

INT1

FLAG

INT1

PIN DATA

— — —

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

INT1

P018

to

P01B

RESERVED

P01C BUSY VPPS — — — — W0 EXE EPCTL
P01D

P01E

P01F

RESERVED

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digital I/O port configuration registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. T able 11 shows the specific
addresses, registers, and control bits within this peripheral file frame. Table 12 shows the port-configuration
register setup.

Table 11. Peripheral File Frame 2: Digital Port-Control Registers

PF

BIT 7

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

P020 Reserved APORT1
P021 Port A Control Register 2 (must be 0) APORT2
P022 Port A Data ADATA
P023 Port A Direction ADIR
P024

to

P02B

Reserved

P02C

Port D Control Register 1

(must be 0)

—

Port D Control Register 1

(must be 0)

— — — DPORT1

P02D

Port D Control Register 2

(must be 0)

†

—

Port D Control Register 2

(must be 0)

†

— — — DPORT2

P02E Port D Data — Port D Data — — — DDATA
P02F Port D Direction — Port D Direction — — — DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 12. Port Configuration Register Set-up

PORT PIN

abcd
00q1

abcd

00y0
A 0 – 7 Data Out q Data In y
D 3, 4, 6, 7 Data Out q Data In y

a = Port x Control Register 1
b = Port x Control Register 2

c = Data

d = Direction

TMS370CxCx

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programmable timer 1

The programmable Timer 1 (T1) module of the TMS370CxCx provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers allow program selection of input clock sources
(real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and compare) for
special timer function control. The T1 module includes three external device pins that can be used for multiple
counter functions (operation mode dependent) or used as general-purpose I/O pins. The T1 module is shown
in Figure 5.

T1IC/CR

Edge

Select

16-Bit

Counter

T1EVT

MUX

MUX

16-Bit

Register

T1PWM

PWM

Toggle

16

16-Bit

Watchdog Counter

(Aux. Timer)

Interrupt

Logic

Capt/Comp

16-Bit

Register

Compare

Interrupt

Logic

8-Bit

Prescaler

Figure 5. Timer 1 Block Diagram

D

Three T1 I/O pins
– T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: T imer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin

D

Two operation modes:
– Dual-compare mode: Provides PWM signal
– Capture/compare mode: Provides input capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register.

D

One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer
if watchdog feature is not needed.

D

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

TMS370CxCx
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programmable timer 1 (continued)

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR)

D

Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external edge detection

D

Sixteen T1 module control registers located in the PF frame beginning at address P040.

TMS370CxCx

8-BIT MICROCONTROLLER

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programmable timer 1 (continued)

The T1 module control registers are listed in Table 13. Privilege bits are shown in bold typeface and shaded.

Table 13. Timer Module Register Memory Map

PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG

Mode: Dual-Compare and Capture/Compare

P040 Bit 15 T1Counter MSbyte Bit 8 T1CNTR
P041 Bit 7 T1 Counter LSbyte Bit 0
P042 Bit 15 Compare Register MSbyte Bit 8 T1C
P043 Bit 7 Compare Register LSbyte Bit 0
P044 Bit 15 Capture/Compare Register MSbyte Bit 8 T1CC
P045 Bit 7 Capture/Compare Register LSbyte Bit 0
P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR
P047 Bit 7 Watchdog Counter LSbyte Bit 0
P048 Bit 7 Watchdog Reset Key Bit 0 WDRST

P049

WD OVRFL

TAP SEL

†

WD INPUT
SELECT2

†

WD INPUT
SELECT1

†

WD INPUT
SELECT0

†

—

T1 INPUT
SELECT2

T1 INPUT
SELECT1

T1 INPUT
SELECT0

T1CTL1

P04A

WD OVRFL

RST ENA

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

— —

T1

SW RESET

T1CTL2

Mode: Dual-Compare

P04B

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

— —

T1EDGE
INT ENA

T1C2

INT ENA

T1C1

INT ENA

T1CTL3

P04C

T1

MODE=0

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

T1CTL4

Mode: Capture/Compare

P04B

T1EDGE

INT FLAG

—

T1C1

INT FLAG

— —

T1EDGE
INT ENA

—

T1C1

INT ENA

T1CTL3

P04C

T1

MODE = 1

T1C1

OUT ENA

—

T1C1

RST ENA

—

T1EDGE

POLARITY

—

T1EDGE

DET ENA

T1CTL4

Mode: Dual-Compare and Capture/Compare

P04D — — — —

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

T1PC1

P04E

T1PWM
DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR
DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1PC2

P04F T1 STEST

T1

PRIORITY

— — — — — — T1PRI

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.