Texas Instruments TMS370C686AFNT Datasheet

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 4K Bytes

– EPROM: 16K Bytes – Data EEPROM: 256 Bytes – Static RAM: 128 or 256 Bytes Usable as

Registers

Flexible Operating Features – Low-Power Modes: STANDBY and HAL T – Commercial, Industrial, and Automotive

T emperature Ranges – Clock Options

– Divide-by-1 (2 MHz–5 MHz SYSCLK) PLL

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK) – Supply Voltage (V

) 5 V ±10%

16-Bit General Purpose Timer – Software Configurable as

a 16-Bit Event Counter, or

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

T wo Compare Registers, or a

Self-Contained Pulse Width Modulation

(PWM) Function

On-Chip 24-Bit Watchdog Timer – EPROM/OTP Device: Standard

Watchdog – Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Flexible Interrupt Handling – Two S/W Programmable Interrupt Levels – Global- and Individual-Interrupt Masking – Programmable Rising- or Falling-Edge

Detect – Individual Interrupt Vectors

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

all TMS370 Devices

CMOS/Package/TTL Compatible I/O Pins – 40-Pin Plastic Dual-In-Line Packages/

32 Bidirectional Pins, 1 Input Pin

– 44-Pin Plastic Leaded Chip Carrier (LCC)

Packages/34 Bidirectional Pins, 1 Input Pin

Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Multi-Window User Interface – Microcontroller Programmer

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

N PACKAGE (TOP VIEW)

FZ AND FN PACKAGES

(TOP VIEW)

MC XTAL2/CLKIN XTAL1 B7 B6 B5 NC B4 C7 C6 NC

39 38 37 36 35 34 33 32 31 30 29

18 19

7 8 9 10 11 12 13 14 15 16 17

INT1 INT2 INT3 V

CC NC

A7 A6

A5 A4 A3

20 21 22 23

B0B1B2

54 3216

RESETC5C4C3C2C1C0

T1EVT

T1PWM

T1IC/CR

A2A1A0

D7D4D3

42 41 4043

24 25 26 27 28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

C2 C3 C4 C5

RESET

INT1 INT2 INT3

A7 A6 A5 A4 A3 A2 A1 A0 D7 D4

C1 C0 B0 B1 B2 B3 MC XTAL2/CLKIN XTAL1 B7 B6 B5 B4 V

T1IC/CR T1PWM T1EVT D5 D6 D3

TMS370Cx8x 8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions

PINS

NAME

PDIP

(40)

LCC

(44)

TYPE†

DESCRIPTION

ÁÁÁ

A0 A1 A2 A3 A4 A5 A6 A7

ÁÁ

18 17 16 15 14 13 12 11

20 19 18 17 16 15 13 12

ÁÁ

I/O

ББББББББББББББББББББ

Port A is a general-purpose bidirectional I/O port.

ÁÁÁ

B0 B1 B2 B3 B4 B5 B6 B7

ÁÁ

38 37 36 35 28 29 30 31

43 42 41 40 32 34 35 36

ÁÁ

I/O

ББББББББББББББББББББ

Port B is a general-purpose bidirectional I/O port.

ÁÁÁ

C0 C1 C2 C3 C4 C5 C6 C7

ÁÁ

39 40

1 2 3

4 — —

1 2 3 4

5 30 31

ÁÁ

I/O

ББББББББББББББББББББ

Port C is a general-purpose bidirectional I/O port.

ÁÁÁ

D3 D4 D5 D6 D7

ÁÁ

21 20 23 22 19

23 22 25 24 21

ÁÁ

I/O

ББББББББББББББББББББ

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

ÁÁÁ

INT1 INT2 INT3

ÁÁ

6 7 8

ÁÁ

I I/O I/O

ББББББББББББББББББББ

External (non-maskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁ

T1IC/CR T1PWM T1EVT

ÁÁ

26 25 24

28 27 26

ÁÁ

I/O

ББББББББББББББББББББ

Timer1 input capture/counter reset input pin /general-purpose bidirectional pin Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

ÁÁÁ

RESET

ÁÁ

I/O

ББББББББББББББББББББ

System reset bidirectional pin: as input pin, RESET initializes the microcontroller; as open-drain output, RESET

indicates that an internal failure was detected by the watchdog or

oscillator fault circuit.

Mode control pin; enables EEPROM write-protection override (WPO) mode, also EPROM V

ÁÁÁ

XTAL2/CLKIN XTAL1

ÁÁ

33 32

38 37

ÁÁ

ББББББББББББББББББББ

Internal oscillator crystal input/external clock source input Internal oscillator output for crystal

Positive supply voltage

Ground reference for digital logic

ÁÁÁ

ÁÁ

11, 29,

ÁÁÁББББББББББББББББББББ

These pins have no connection to the internal die.

†

I = input, O = output

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Interrupts

T1IC/CR T1EVT T1PWM

System Control

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

RAM

128 or 256 Bytes

CPU

Port A Port D

Timer 1

Watchdog

INT1

INT2 INT3 XTAL1

XTAL2/

CLKIN

MC RESET

Program Memory

ROM: 4K Bytes

EPROM: 16K Bytes

Data EEPROM 0 or 256 Bytes

Port B Port C

†

58 8 8/6

†

For the 40-pin devices, there are only six pins for port C.

description

The TMS370C080, TMS370C380, TMS370C686, and SE370C686 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx8x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral-function modules and various on-chip memory configurations.

The TMS370Cx8x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low-operating power , wide operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx8x devices attractive for system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications.

All TMS370Cx8x devices contain the following on-chip peripheral modules:

One 24-bit general-purpose watchdog timer

One 16-bit general-purpose timer with an 8-bit prescaler

TMS370Cx8x 8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx8x devices.

Table 1. Memory Configurations

DEVICE

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

44-PIN PLCC/CLCC,

ROM

EPROM

RAM

EEPROM

OR 40-PIN PDIP

TMS370C080

—

128

256

N – PDIP

TMS370C380A

—

128

—

FN – PLCC

TMS370C686A

—

16K

256

—

FN – PLCC

SE370C686A

†

—

16K

256

—

FZ – CLCC

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of T able 1 and T able 2 indicates the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. For a detailed description of the differences between the TMS370C080 and TMS370Cx8xA contact options (as indicated by the suffix letter nomenclature), refer to Appendix A of the

TMS370 Microcontroller Family User’s

Guide

(literature number SPNU127).

For a detailed description of the differences between the TMS370C080 and the TMS370Cx8xA contact options (as indicated by the suffix letter nomenclature), refer to Appendix A of the

TMS370 Microcontroller Family User’s

Guide

(literature number SPNU127).

Table 2. Suffix Letter Configuration

DEVICE

‡

WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (Standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled

Simple

ROM without A Standard Divide-by-4 (Standard oscillator) Enabled

‡

Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering.

The 4K bytes of mask-programmable ROM in the associated TMS370C380 device is replaced in the TMS370C686 with 16K bytes of EPROM. All other on-chip peripherals are identical. The one-time programmable (OTP) (TMS370C686) device and reprogrammable (SE370C686) device are available. The 4K-byte (TMS370C080) mask-programmable ROM device relies on the 68-pin (TMS370C758) development devices and a converter socket (part # TMDS37788OTP) for prototyping and programming purposes.

TMS370C686 OTP devices are available in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx8x family or for low-volume production runs when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C686 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development/prototyping phase of design. The SE370C686 devices allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx8x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS370Cx8x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx8x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family.

The TMS370Cx8x family provides the system designer with economical, efficient solutions to real-time control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx8x into an ever-increasing number of complex applications. The application source code can be written in assembly and C languages, and the output code can be generated by the linker. The TMS370 family CDT development tool communicates through a standard RS-232-C interface with an existing personal computer. This allows the designer to use familiar personal computer editors and software utilities. Precise real-time, in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reducing the time-to-market cycle.

The TMS370Cx8x family together with the TMS370 family CDT370, software tools, the SE370C686 and SE370C758 (FZ package) reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU on the TMS370Cx8x device is the high-performance 8-bit TMS370 CPU module. The ’x8x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x8x instruction map is shown in Table 15 in the TMS370Cx8x instruction set overview section.

The ’370Cx8x CPU architecture provides the following components:

CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global interrupt-enable

bits

– A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes: – 128- or 256-byte general-purpose RAM that can be used for data memory storage, program

instructions, general purpose register, or the stack

– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

– 256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off

conditions

– 4K-byte ROM or 16K-byte EPROM program memory

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx8x 8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

Figure 1 illustrates the CPU registers and memory blocks.

Reserved

†

Peripheral File

Not Available

‡

OFFFh 1000h

1F00h 1FFFh 2000h 3FFFh

4000h

Interrupts and Reset Vectors;

Trap Vectors

104Fh 1050h

1EFFh

Reserved

†

7FFFh

RAM (Includes up to 256-Byte Registers File)

015

Program Counter

Legend:

Z=Zero

IE1=Level 1 Interrupt Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 Interrupt Enable

IE1IE2ZNC

01234567

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R127

0000h 0001h

0002h

007Fh

R255

0003h

00FFh

256-Byte Data EEPROM

16K-Byte EPROM (4000h–7FFFh)

7FC0h

7FBFh

128-Byte RAM (0000h–007Fh)

007Fh 0080h

00FFh 0100h

256-Byte RAM (0000h–00FFh)

0000h

6FFFh 7000h

4K-Byte ROM (7000h–7FFFh)

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. T ypically, the stack is used to store the return address on subroutine calls as well as the status register (ST) contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

status register

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits.

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

IE2

IE1 Reserved Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH), and the program counter low (PCL). These registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector.

Memory

Program Counter (PC)

60 00

PCH PCL

60 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx8x architecture is based on the Von Neuman architecture, in which the program memory and data memory share a common address space. All peripheral input /output is memory-mapped in this same common address space. As shown in Figure 3, the TMS370Cx8x provides memory-mapped RAM, ROM, data EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh and is divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is

TMS370Cx8x 8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x CPU (continued)

assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx8x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 4, addresses 1010h through 104Fh.

256-Byte RAM

(Register File/Stack)

128-Byte RAM

(Register File/Stack)

Reserved

†

Peripheral File

Reserved

†

256-Byte Data EEPROM

Not Available

‡

7FC0hTrap 15–0 7FE0hReserved 7FF4h

Interrupt 3 Interrupt 2 Interrupt 1

Reset

1010h 1020h

Reserved

†

System Control

1030h

1040h

Reserved

Vectors

7FDFh 7FF3h 7FF5h

101Fh 102Fh

103Fh

104Fh

– –

–

– – –

Not Available

‡

Digital Port Control

Timer 1

Reserved

†

7FFAh 7FFBh– 7FFCh 7FFDh– 7FFEh 7FFFh–

0000h

0080h

007Fh

1000h 104Fh

1050h

1EFFh

1F00h

1FFFh

2000h

3FFFh

4000h

6FFFh

7000h

FFFFh

0FFFh

16K-Byte EPROM

(4000h - 7FFFh)

4K-Byte ROM

(7000h - 7FFFh)

Interrupts and Reset Vectors;

Trap Vectors

7FBFh 7FC0h 7FFFh

8000h

7FF6h 7FF7h–– 7FF8h 7FF9h–

Peripheral File Control Registers

0100h

00FFh

Timer 1

Peripheral Control

1000h 100Fh–

†

Reserved means that the address space is reserved for future expansion, means the address space is not accessible.

‡

Not available means that the address space is not accessible.

Figure 3. TMS370Cx8x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370C080 and TMS370C380 contain 128 bytes of internal RAM memory mapped beginning at location 0000h (R0) and continuing through location 007Fh (R127), which is shown in Table 4 along with ’x86 devices.

Table 4. RAM Memory Map

’x80 ’x86

RAM size 128 bytes 256 bytes

Memory mapped 0000h–007Fh 0000h–00FFh

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction load SP (LDSP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral file (PF)

The TMS370Cx8x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 5 shows the TMS370Cx8x PF address map.

Table 5. TMS370Cx8x Peripheral File Address Map

БББББ

ADDRESS RANGE

БББББББ

БББББ

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

DESCRIPTION

1000h–100Fh

БББББББ

P000–P00F Reserved

1010h–101Fh

БББББББ

P010–P01F

System and EPROM/EEPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

БББББББ

P030–P03F

Reserved

1040h–104Fh

БББББББ

P040–P04F

Timer 1 registers

1050h–10FFh

БББББББ

P050–P0FF Reserved

data EEPROM

The TMS370C080 device, containing 256 bytes of data EEPROM, has a memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B). The data EEPROM features include the following:

Programming: – Bit-, byte-, and block-write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A. See Table 6.

– In-circuit programming capability. There is no need to remove the device to program.

Write-protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write-protection active. There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write-protection can be overridden by applying 12 V to MC.

T able 6. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ADDRESS

SYMBOL

NAME

P01A

DEECTL

Data EEPROM Control Register

P01B

— Reserved

P01C

EPCTL

Program EPROM Control Register

TMS370Cx8x 8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

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program EPROM

†

The TMS370C686 device contains 16K bytes of EPROM memory, mapped beginning at location 4000h and continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include:

Programming – In-circuit programming capability if V

is applied to MC

– Control register EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01C as shown in Table 6.

Write-protection writes to the program EPROM are disabled under the following conditions – Reset all programming to the EPROM module is halted – Low-power modes – 13 V not applied to MC

program ROM

†

The program ROM consists of 4K bytes of mask-programmable read-only memory . The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx8x CPU-based device. There are up to three different actions that can cause the system to reset the device. T wo of these actions are generated internally , while one (RESET pin) is controlled externally. These actions are as follows:

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 User’s

Guide

(literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x8x device to reset external system components. Additionally , if a cold start (V

is off for several hundred milliseconds) condition or oscillator failure occurs, or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag (COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 7 depicts the reset sources.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated, and 7FF4h through 7FF5h along with 7FF8h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

system reset (continued)

Table 7. Reset Sources

ADDRESS

BIT NO.

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

COLD START

Cold (power-up)

SCCR0

1010h

P010

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Register A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode-fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the ST.

TIMER1

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

T1 PRI

Priority

Overflow

Compare1

Ext Edge

Compare2 Input Capture1 Watchdog

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

EXT INT 2

INT2 PRI

INT 2

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high- or low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx8x has four hardware-system interrupts (plus RESET

) as shown in Table 8. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or to determine which interrupt source generated the associated system interrupt.

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interrupts (continued)

One of the system interrupts is generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation. It, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin).

T able 8. Hardware System Interrupts

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY

†

БББББББББ

External RESET Watchdog Overflow Oscillator Fault Detect

БББББББ

COLD START WD OVRFL INT FLAG OSC FLT FLAG

ÁÁÁÁ

RESET

‡

БББББ

7FFEh, 7FFFh

ÁÁ

External INT1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

External INT2

INT2 FLAG

INT2

‡

7FFAh, 7FFBh

External INT3

INT3 FLAG

INT3

‡

7FF8h, 7FF9h

БББББББББ

Timer 1 Overflow Timer 1 Compare 1 Timer 1 Compare 2 Timer 1 External Edge Timer 1 Input Capture 1 Watchdog Overflow

БББББББ

T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG

ÁÁÁÁ

T1INT

БББББ

7FF4h, 7FF5h

ÁÁ

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes

Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx8x family is designed with significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration once it is defined for an application. Following a hardware reset, the TMS370Cx8x operates in the privileged mode, where all peripheral file registers have unrestricted read / write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the nonprivileged mode, thus disabling write operations to specific configuration-control bits within the PF . T able 9 displays the system-configuration bits, which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 9. Privilege Bits

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

SCCRO

ÁÁÁ

P010.5 P010.6

БББББББ

PF AUTO WAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

БББББББ

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

ÁÁÁ

T1PRI

ÁÁÁ

P04F.6 P04F.7

БББББББ

T1 PRIORITY T1 STEST

†

The privilege bits are shown in a bold typeface in the peripheral file frame 1 section.

The WPO mode provides an external hardware method of overriding the write-protection registers (WPRs) of data EEPROM on the TMS370C080. WPO mode is entered by applying a 12-V input to the MC pin after the RESET

pin input goes high (logic 1). The high voltage on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware-system-level capability to modify the content of the data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx8x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the ST ANDBY mode (HAL T/ST ANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, and Timer 1 remain active. System processing is suspended until a qualified interrupt (hardware RESET

, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected.

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx8x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, or INT3) is detected. The power-down mode-selection bits are summarized in Table 10.

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