Texas Instruments TMS370C686AFNT Datasheet

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

CMOS/EEPROM/EPROM Technologies on
a Single Device
– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

D

Internal System Memory Configurations
– On-Chip Program Memory Versions

– ROM: 4K Bytes

– EPROM: 16K Bytes
– Data EEPROM: 256 Bytes
– Static RAM: 128 or 256 Bytes Usable as

Registers

D

Flexible Operating Features
– Low-Power Modes: STANDBY and HAL T
– Commercial, Industrial, and Automotive

T emperature Ranges
– Clock Options

– Divide-by-1 (2 MHz–5 MHz SYSCLK) PLL

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK)
– Supply Voltage (V

CC

) 5 V ±10%

D

16-Bit General Purpose Timer
– Software Configurable as

a 16-Bit Event Counter, or

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

T wo Compare Registers, or a

Self-Contained Pulse Width Modulation

(PWM) Function

D

On-Chip 24-Bit Watchdog Timer
– EPROM/OTP Device: Standard

Watchdog
– Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

D

Flexible Interrupt Handling
– Two S/W Programmable Interrupt Levels
– Global- and Individual-Interrupt Masking
– Programmable Rising- or Falling-Edge

Detect
– Individual Interrupt Vectors

D

TMS370 Series Compatibility
– Register-to-Register Architecture
– 256 General-Purpose Registers
– 14 Powerful Addressing Modes
– Instructions Upwardly Compatible With

all TMS370 Devices

D

CMOS/Package/TTL Compatible I/O Pins
– 40-Pin Plastic Dual-In-Line Packages/

32 Bidirectional Pins, 1 Input Pin

– 44-Pin Plastic Leaded Chip Carrier (LCC)

Packages/34 Bidirectional Pins,
1 Input Pin

D

Workstation/PC-Based Development
System
– C Compiler and C Source Debugger
– Real-Time In-Circuit Emulation
– Extensive Breakpoint/Trace Capability
– Multi-Window User Interface
– Microcontroller Programmer

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

N PACKAGE
(TOP VIEW)

FZ AND FN PACKAGES

(TOP VIEW)

MC
XTAL2/CLKIN
XTAL1
B7
B6
B5
NC
B4
C7
C6
NC

39
38
37
36
35
34
33
32
31
30
29

18 19

7
8
9
10
11
12
13
14
15
16
17

INT1
INT2
INT3
V

CC
NC

A7
A6

V

SS

A5
A4
A3

20 21 22 23

B0B1B2

B3

54 3216

44

RESETC5C4C3C2C1C0

D5

T1EVT

T1PWM

T1IC/CR

A2A1A0

D7D4D3

D6

42 41 4043

24 25 26 27 28

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

C2
C3
C4
C5

RESET

INT1
INT2
INT3

NC

V

CC

A7
A6
A5
A4
A3
A2
A1
A0
D7
D4

C1
C0
B0
B1
B2
B3
MC
XTAL2/CLKIN
XTAL1
B7
B6
B5
B4
V

SS

T1IC/CR
T1PWM
T1EVT
D5
D6
D3

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions

PINS

NAME

PDIP

(40)

LCC

(44)

TYPE†

DESCRIPTION

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

A0
A1
A2
A3
A4
A5
A6
A7

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

18
17
16
15
14
13
12
11

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

20
19
18
17
16
15
13
12

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Port A is a general-purpose bidirectional I/O port.

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

B0
B1
B2
B3
B4
B5
B6
B7

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

38
37
36
35
28
29
30
31

Á

Á

Á

Á

Á

Á

Á

Á

43
42
41
40
32
34
35
36

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Port B is a general-purpose bidirectional I/O port.

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

C0
C1
C2
C3
C4
C5
C6
C7

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

39
40

1
2
3

4
—
—

Á

Á

Á

Á

Á

Á

Á

Á

44

1
2
3
4

5
30
31

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Port C is a general-purpose bidirectional I/O port.

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

D3
D4
D5
D6
D7

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

21
20
23
22
19

Á

Á

Á

Á

Á

Á

23
22
25
24
21

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

ÁÁÁ

Á

INT1
INT2
INT3

ÁÁ

Á

6
7
8

Á

Á

7

8

9

ÁÁ

Á

I
I/O
I/O

ББББББББББББББББББББ

Á

External (non-maskable or maskable) interrupt/general-purpose input pin
External maskable interrupt input/general-purpose bidirectional pin
External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁ

Á

T1IC/CR
T1PWM
T1EVT

ÁÁ

Á

26
25
24

Á

Á

28
27
26

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

Timer1 input capture/counter reset input pin /general-purpose bidirectional pin
Timer1 PWM output pin/general-purpose bidirectional pin
Timer1 external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

RESET

ÁÁ

Á

ÁÁ

Á

5

Á

Á

Á

Á

6

ÁÁ

Á

ÁÁ

Á

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

System reset bidirectional pin: as input pin, RESET initializes the microcontroller; as
open-drain output, RESET

indicates that an internal failure was detected by the watchdog or

oscillator fault circuit.

MC

34

39

I

Mode control pin; enables EEPROM write-protection override (WPO) mode, also EPROM
V

PP

ÁÁÁ

Á

XTAL2/CLKIN
XTAL1

ÁÁ

Á

33
32

Á

Á

38
37

ÁÁ

Á

I

O

ББББББББББББББББББББ

Á

Internal oscillator crystal input/external clock source input
Internal oscillator output for crystal

V

CC

10

10

Positive supply voltage

V

SS

27

14

Ground reference for digital logic

ÁÁÁ

Á

NC

ÁÁ

Á

9

Á

Á

11, 29,

33

ÁÁÁББББББББББББББББББББ

Á

These pins have no connection to the internal die.

†

I = input, O = output

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Interrupts

T1IC/CR
T1EVT
T1PWM

V

System
Control

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

RAM

128 or 256 Bytes

CPU

Port A Port D

Timer 1

Watchdog

INT1

INT2 INT3 XTAL1

XTAL2/

CLKIN

MC RESET

SS

V

CC

Program Memory

ROM: 4K Bytes

EPROM: 16K Bytes

Data EEPROM
0 or 256 Bytes

Port B Port C

†

58 8 8/6

†

For the 40-pin devices, there are only six pins for port C.

description

The TMS370C080, TMS370C380, TMS370C686, and SE370C686 devices are members of the TMS370 family
of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx8x refers to these devices.
The TMS370 family provides cost-effective real-time system control through integration of advanced
peripheral-function modules and various on-chip memory configurations.

The TMS370Cx8x family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. Low-operating power , wide operating temperature range, and noise immunity of CMOS
technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx8x devices attractive for system designs for automotive electronics, industrial motors, computer
peripheral controls, telecommunications, and consumer applications.

All TMS370Cx8x devices contain the following on-chip peripheral modules:

D

One 24-bit general-purpose watchdog timer

D

One 16-bit general-purpose timer with an 8-bit prescaler

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx8x devices.

Table 1. Memory Configurations

DEVICE

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

44-PIN PLCC/CLCC,

ROM

EPROM

RAM

EEPROM

OR 40-PIN PDIP

TMS370C080

4K

—

128

256

N – PDIP

TMS370C380A

4K

—

128

—

FN – PLCC

TMS370C686A

—

16K

256

—

FN – PLCC

SE370C686A

†

—

16K

256

—

FZ – CLCC

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of T able 1 and T able 2 indicates
the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture. For
a detailed description of the differences between the TMS370C080 and TMS370Cx8xA contact options (as
indicated by the suffix letter nomenclature), refer to Appendix A of the

TMS370 Microcontroller Family User’s

Guide

(literature number SPNU127).

For a detailed description of the differences between the TMS370C080 and the TMS370Cx8xA contact options
(as indicated by the suffix letter nomenclature), refer to Appendix A of the

TMS370 Microcontroller Family User’s

Guide

(literature number SPNU127).

Table 2. Suffix Letter Configuration

DEVICE

‡

WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (Standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled

Simple

ROM without A Standard Divide-by-4 (Standard oscillator) Enabled

‡

Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering.

The 4K bytes of mask-programmable ROM in the associated TMS370C380 device is replaced in the
TMS370C686 with 16K bytes of EPROM. All other on-chip peripherals are identical. The one-time
programmable (OTP) (TMS370C686) device and reprogrammable (SE370C686) device are available. The
4K-byte (TMS370C080) mask-programmable ROM device relies on the 68-pin (TMS370C758) development
devices and a converter socket (part # TMDS37788OTP) for prototyping and programming purposes.

TMS370C686 OTP devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx8x family or for low-volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C686 has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development/prototyping phase of design. The SE370C686 devices allow quick updates to
breadboards and prototype systems while iterating initial designs.

The TMS370Cx8x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In
the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,
all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS370Cx8x features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx8x family is fully
instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller
family.

The TMS370Cx8x family provides the system designer with economical, efficient solutions to real-time control
applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently
developing the software and hardware required to design the TMS370Cx8x into an ever-increasing number of
complex applications. The application source code can be written in assembly and C languages, and the output
code can be generated by the linker. The TMS370 family CDT development tool communicates through a
standard RS-232-C interface with an existing personal computer. This allows the designer to use familiar
personal computer editors and software utilities. Precise real-time, in-circuit emulation and extensive symbolic
debug and analysis tools ensure efficient software and hardware implementation as well as reducing the
time-to-market cycle.

The TMS370Cx8x family together with the TMS370 family CDT370, software tools, the SE370C686 and
SE370C758 (FZ package) reprogrammable devices, comprehensive product documentation, and customer
support provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU on the TMS370Cx8x device is the high-performance 8-bit TMS370 CPU module. The ’x8x implements
an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The
complete ’x8x instruction map is shown in Table 15 in the TMS370Cx8x instruction set overview section.

The ’370Cx8x CPU architecture provides the following components:

D

CPU registers:
– A stack pointer that points to the last entry in the memory stack
– A status register that monitors the operation of the instructions and contains the global interrupt-enable

bits

– A program counter (PC) that points to the memory location of the next instruction to be executed

D

A memory map that includes:
– 128- or 256-byte general-purpose RAM that can be used for data memory storage, program

instructions, general purpose register, or the stack

– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

– 256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off

conditions

– 4K-byte ROM or 16K-byte EPROM program memory

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

Figure 1 illustrates the CPU registers and memory blocks.

Reserved

†

Peripheral File

Not Available

‡

OFFFh
1000h

1F00h
1FFFh
2000h
3FFFh

4000h

Interrupts and Reset Vectors;

Trap Vectors

104Fh
1050h

1EFFh

Reserved

†

7FFFh

0

RAM (Includes up to 256-Byte Registers File)

015

Program Counter

7

Legend:

Z=Zero

IE1=Level 1 Interrupt Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 Interrupt Enable

IE1IE2ZNC

01234567

V

Status Register (ST)

Stack Pointer (SP)

R0(A)
R1(B)

R3

R127

0000h
0001h

0002h

007Fh

R255

0003h

R2

00FFh

256-Byte Data EEPROM

16K-Byte EPROM (4000h–7FFFh)

7FC0h

7FBFh

128-Byte RAM (0000h–007Fh)

007Fh
0080h

00FFh
0100h

256-Byte RAM (0000h–00FFh)

0000h

6FFFh
7000h

4K-Byte ROM (7000h–7FFFh)

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. T ypically, the stack
is used to store the return address on subroutine calls as well as the status register (ST) contents during interrupt
sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

status register

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits.

D

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional-jump instructions) use the status bits to determine program flow.

D

The two interrupt-enable bits control the two interrupt levels.

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

7

6

5

4

3

2

1

0

C

N

Z

V

IE2

IE1 Reserved Reserved

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH), and the program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the
PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the
contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the
contents of the reset vector.

Memory

Program Counter (PC)

60 00

PCH PCL

60
00

0000h

7FFEh
7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx8x architecture is based on the Von Neuman architecture, in which the program memory and
data memory share a common address space. All peripheral input /output is memory-mapped in this same
common address space. As shown in Figure 3, the TMS370Cx8x provides memory-mapped RAM, ROM, data
EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and
system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to
10FFh and is divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x CPU (continued)

assigned to a separate frame through which peripheral control and data information is passed. The
TMS370Cx8x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 4,
addresses 1010h through 104Fh.

256-Byte RAM

(Register File/Stack)

128-Byte RAM

(Register File/Stack)

Reserved

†

Peripheral File

Reserved

†

256-Byte Data EEPROM

Not Available

‡

7FC0hTrap 15–0
7FE0hReserved
7FF4h

Interrupt 3
Interrupt 2
Interrupt 1

Reset

1010h
1020h

Reserved

†

System Control

1030h

1040h

Reserved

Vectors

7FDFh
7FF3h
7FF5h

101Fh
102Fh

103Fh

104Fh

–
–

–

–

–
–
–

Not Available

‡

Digital Port Control

Timer 1

Reserved

†

7FFAh 7FFBh–
7FFCh 7FFDh–
7FFEh 7FFFh–

0000h

0080h

007Fh

1000h
104Fh

1050h

1EFFh

1F00h

1FFFh

2000h

3FFFh

4000h

6FFFh

7000h

FFFFh

0FFFh

16K-Byte EPROM

(4000h - 7FFFh)

4K-Byte ROM

(7000h - 7FFFh)

Interrupts and Reset Vectors;

Trap Vectors

7FBFh
7FC0h
7FFFh

8000h

7FF6h 7FF7h––
7FF8h 7FF9h–

Peripheral File Control Registers

0100h

00FFh

Timer 1

Peripheral Control

1000h 100Fh–

†

Reserved means that the address space is reserved for future expansion, means the address space is not accessible.

‡

Not available means that the address space is not accessible.

Figure 3. TMS370Cx8x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program
memory, or the stack instructions. The TMS370C080 and TMS370C380 contain 128 bytes of internal RAM
memory mapped beginning at location 0000h (R0) and continuing through location 007Fh (R127), which is
shown in Table 4 along with ’x86 devices.

Table 4. RAM Memory Map

’x80 ’x86

RAM size 128 bytes 256 bytes

Memory mapped 0000h–007Fh 0000h–00FFh

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction load SP (LDSP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

TMS370Cx8x

8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral file (PF)

The TMS370Cx8x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 5
shows the TMS370Cx8x PF address map.

Table 5. TMS370Cx8x Peripheral File Address Map

БББББ

Á

ADDRESS RANGE

БББББББ

Á

БББББ

Á

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

Á

DESCRIPTION

1000h–100Fh

БББББББ

P000–P00F Reserved

1010h–101Fh

БББББББ

P010–P01F

System and EPROM/EEPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

БББББББ

P030–P03F

Reserved

1040h–104Fh

БББББББ

P040–P04F

Timer 1 registers

1050h–10FFh

БББББББ

P050–P0FF Reserved

data EEPROM

The TMS370C080 device, containing 256 bytes of data EEPROM, has a memory mapped beginning at location
1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data
EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm
examples are available in the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B). The data EEPROM features include the following:

D

Programming:
– Bit-, byte-, and block-write/erase modes
– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.
– Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A. See Table 6.

– In-circuit programming capability. There is no need to remove the device to program.

D

Write-protection. Writes to the data EEPROM are disabled during the following conditions.
– Reset. All programming of the data EEPROM module is halted.
– Write-protection active. There is one write-protect bit per 32-byte EEPROM block.
– Low-power mode operation

D

Write-protection can be overridden by applying 12 V to MC.

T able 6. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ADDRESS

SYMBOL

NAME

P01A

DEECTL

Data EEPROM Control Register

P01B

— Reserved

P01C

EPCTL

Program EPROM Control Register

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

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program EPROM

†

The TMS370C686 device contains 16K bytes of EPROM memory, mapped beginning at location 4000h and
continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical
to reading other internal memory . During programming, the EPROM is controlled by the EPROM control register
(EPCTL). The program EPROM module features include:

D

Programming
– In-circuit programming capability if V

PP

is applied to MC

– Control register EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01C as shown in Table 6.

D

Write-protection writes to the program EPROM are disabled under the following conditions
– Reset all programming to the EPROM module is halted
– Low-power modes
– 13 V not applied to MC

program ROM

†

The program ROM consists of 4K bytes of mask-programmable read-only memory . The program ROM is used
for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device
fabrication.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx8x CPU-based device.
There are up to three different actions that can cause the system to reset the device. T wo of these actions are
generated internally , while one (RESET pin) is controlled externally. These actions are as follows:

D

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 User’s

Guide

(literature number SPNU127) for more information.

D

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

D

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x8x device to reset external system components. Additionally , if a cold start (V

CC

is off
for several hundred milliseconds) condition or oscillator failure occurs, or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag
(COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 7 depicts the reset sources.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated, and 7FF4h through 7FF5h along with 7FF8h
through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between
addresses 7FC0h and 7FDFh.

TMS370Cx8x

8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

system reset (continued)

Table 7. Reset Sources

REGISTER

ADDRESS

PF

BIT NO.

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

7

COLD START

Cold (power-up)

SCCR0

1010h

P010

4

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

5

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Register A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode-fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.

TMS370Cx8x
8-BIT MICROCONTROLLER

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of
the ST.

TIMER1

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT
Level 2 INT

T1 PRI

Priority

Overflow

Compare1

Ext Edge

Compare2
Input Capture1
Watchdog

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

EXT INT 2

INT2 PRI

INT 2

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is selectively configured on either the high- or
low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.

The TMS370Cx8x has four hardware-system interrupts (plus RESET

) as shown in Table 8. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are
individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt
source FLAG bit is individually readable for software polling or to determine which interrupt source generated
the associated system interrupt.

TMS370Cx8x

8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupts (continued)

One of the system interrupts is generated by on-chip peripheral functions, and three external interrupts are
supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input
polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as
either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked
by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation. It,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the
interrupt function is not required (INT1 can be similarly configured as an input pin).

T able 8. Hardware System Interrupts

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY

†

БББББББББ

Á

БББББББББ

Á

External RESET
Watchdog Overflow
Oscillator Fault Detect

БББББББ

Á

БББББББ

Á

COLD START
WD OVRFL INT FLAG
OSC FLT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

RESET

‡

БББББ

Á

БББББ

Á

7FFEh, 7FFFh

ÁÁ

Á

ÁÁ

Á

1

External INT1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

2

External INT2

INT2 FLAG

INT2

‡

7FFAh, 7FFBh

3

External INT3

INT3 FLAG

INT3

‡

7FF8h, 7FF9h

4

БББББББББ

Á

БББББББББ

Á

БББББББББ

Á

Timer 1 Overflow
Timer 1 Compare 1
Timer 1 Compare 2
Timer 1 External Edge
Timer 1 Input Capture 1
Watchdog Overflow

БББББББ

Á

БББББББ

Á

БББББББ

Á

T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC1 INT FLAG
WD OVRFL INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T1INT

§

БББББ

Á

БББББ

Á

БББББ

Á

7FF4h, 7FF5h

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

5

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes

§

Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx8x family is designed with significant flexibility to enable the designer to software-configure the
system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of
operation ensures the integrity of the system configuration once it is defined for an application. Following a
hardware reset, the TMS370Cx8x operates in the privileged mode, where all peripheral file registers have
unrestricted read / write access, and the application program configures the system during the initialization
sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is
set to 1 to enter the nonprivileged mode, thus disabling write operations to specific configuration-control bits
within the PF . T able 9 displays the system-configuration bits, which are write-protected during the nonprivileged
mode and must be configured by software prior to exiting the privileged mode.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write-protection override (continued)

Table 9. Privilege Bits

REGISTER

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

Á

SCCRO

ÁÁÁ

Á

P010.5
P010.6

БББББББ

Á

PF AUTO WAIT
OSC POWER

SCCR1

P011.2
P011.4

MEMORY DISABLE
AUTOWAIT DISABLE

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

SCCR2

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

P012.0
P012.1
P012.3
P012.4
P012.6
P012.7

БББББББ

Á

БББББББ

Á

БББББББ

Á

PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY

ÁÁÁ

Á

T1PRI

ÁÁÁ

Á

P04F.6
P04F.7

БББББББ

Á

T1 PRIORITY
T1 STEST

†

The privilege bits are shown in a bold typeface in the peripheral file
frame 1 section.

The WPO mode provides an external hardware method of overriding the write-protection registers (WPRs) of
data EEPROM on the TMS370C080. WPO mode is entered by applying a 12-V input to the MC pin after the
RESET

pin input goes high (logic 1). The high voltage on the MC pin during the WPO mode is not the
programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware-system-level capability to modify the content of the data
EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx8x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the ST ANDBY mode (HAL T/ST ANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, and Timer 1 remain active. System processing is suspended until a
qualified interrupt (hardware RESET

, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected.

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx8x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, or INT3) is
detected. The power-down mode-selection bits are summarized in Table 10.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

Table 10. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

БББББ

Á

PWRDWN/IDLE

(SCCR2.6)

ÁÁÁÁ

Á

HALT/STANDBY

(SCCR2.7)

БББББ

Á

MODE SELECTED

1

0

STANDBY

1

1

HALT

0

X

†

IDLE

†

Don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.

T o provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (SP , PC, and ST), I/O pin direction and output data, and status registers of all on-chip peripheral
functions. Since all CPU instruction processing is stopped during the ST ANDBY and HAL T modes, the clocking
of the WD timer is inhibited.

clock modules

The ’x8x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The ’x8x masked ROM devices of fer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’686A
EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.

The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system
clock (SYSCLK) frequency, whereas the divide-by-4 option produces a SYSCLK which is one-fourth of the
frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator
is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased
internal system clock signals. The resulting SYSCLK is equal to the resonator frequency . These are formulated
as follows:

Divide-by-4 option : SYSCLK

+

external resonator frequency

4

+

CLKIN

4

Divide-by-1 option : SYSCLK

+

external resonator frequency 4

4

+

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of
low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators.
The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a
steeper decay of emissions produced by the oscillator.

TMS370Cx8x
8-BIT MICROCONTROLLER

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system configuration registers

T able 1 1 contains system-configuration, control functions, and registers for controlling EEPROM programming.
The privileged bits are shown in bold typeface in shaded areas.

Table 11. Peripheral File Frame 1: System-Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

ÁÁ

Á

P010

ÁÁ

Á

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁ

Á

OSC FLT

FLAG

ÁÁÁ

Á

MC PIN

WPO

ÁÁ

Á

MC PIN

DATA

ÁÁ

Á

—

ÁÁÁ

Á

µP/µC
MODE

ÁÁ

Á

SCCR0

ÁÁ

Á

P011

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

AUTO

WAIT

DISABLE

ÁÁÁ

Á

—

MEMORY
DISABLE

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

SCCR1

ÁÁ

Á

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁÁ

Á

—

BUS

STEST

CPU

STEST

ÁÁ

Á

—

INT1

NMI

PRIVILEGE

DISABLE

ÁÁ

Á

SCCR2

ÁÁ

Á

P013

to

P016

Reserved

ÁÁ

Á

ÁÁ

Á

P017

ÁÁ

Á

INT1

FLAG

ÁÁ

Á

INT1

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

INT1

POLARITY

ÁÁ

Á

INT1

PRIORITY

ÁÁÁ

Á

INT1

ENABLE

ÁÁ

Á

INT1

P018

INT2

FLAG

INT2

PIN DATA

—

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT2

ÁÁ

Á

P019

ÁÁ

Á

INT3

FLAG

ÁÁ

Á

INT3

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

INT3

DATA DIR

ÁÁÁ

Á

INT3

DATA OUT

ÁÁ

Á

INT3

POLARITY

ÁÁ

Á

INT3

PRIORITY

ÁÁÁ

Á

INT3

ENABLE

ÁÁ

Á

INT3

P01A

BUSY

—

—

—

—

AP

W1W0

EXE

DEECTL
P01B Reserved
P01C

BUSY

VPPS

—

—

—

—

W0

EXE

EPCTL

ÁÁ

Á

ÁÁ

Á

P01D
P01E
P01F

Reserved

ÁÁ

Á

ÁÁ

Á

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

digital port-control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. T able 12 shows the specific
addresses, registers, and control bits within this peripheral file frame. Table 13 shows the port-configuration
register setup.

Table 12. Peripheral File Frame 2: Digital Port-Control Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

P020 Reserved

APORT1

P021

Port A Control Register 2 (must be 0)

APORT2

P022

Port A Data

ADATA

P023

Port A Direction

ADIR

P024 Reserved

BPORT1

P025 Port B Control Register 2 (must be 0)

BPORT2

P026 Port B Data

BDATA

P027 Port B Direction

BDIR

P028 Reserved

CPORT1

P029 Port C Control Register 2 (must be 0)

CPORT2

P02A Port C Data

CDATA

P02B Port C Direction

CDIR

P02C

Port D Control Register 1 (must be 0)

—

—

—

DPORT1

P02D

Port D Control Register 2 (must be 0)

†

—

—

—

DPORT2

P02E

Port D Data

—

—

—

DDATA

P02F

Port D Direction

—

—

—

DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 13. Port-Configuration Register Setup

БББББББ

Á

PORT

БББББББ

Á

PIN

БББББББ

Á

abcd
00q1

БББББББ

Á

abcd
00y0

A

0 – 7

Data Out q

Data In y

B

0 – 7

Data Out q

Data In y

C

0 – 7

Data Out q

Data In y

D

3 – 7

Data Out q

Data In y

БББББББББББББББББББББББББББББББ

Á

БББББББББББББББББББББББББББББББ

Á

a = Port x Control Register 1
b = Port x Control Register 2

c = Data

d = Direction

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1

The programmable Timer 1 (T1) module of the TMS370Cx8x provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD timer , allow program selection of input
clock sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The Timer 1 module includes three external device pins that can
be used for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The
T1 module block diagram is shown in Figure 5.

T1IC/CR

Edge

Select

16-Bit

Counter

T1EVT

MUX

MUX

16-Bit

Register

T1PWM

PWM

Toggle

16

16-Bit

Watchdog Counter

(Aux. Timer)

Interrupt

Logic

Capt/Comp

16-Bit

Register

Compare

Interrupt

Logic

8-Bit

Prescaler

Figure 5. Timer 1 Block Diagram

D

Three Timer1 I/O pins
– T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin

D

Two operational modes:
– Dual-compare mode: Provides PWM signal
– Capture/compare mode: Provides input capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either
capture or compare registers.

D

One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD
feature is not needed.

D

Prescaler/clock sources that determines one of eight clock sources for general-purpose timer

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

19

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR)

D

Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external-edge detection

D

Sixteen T1 module control registers located in the PF frame beginning at address P040

The T1 module control registers are illustrated in Table 14.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

Table 14. Timer 1 Module Register Memory Map

ÁÁÁÁ

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Mode: Dual-Compare and Capture/Compare

P040

Bit 15 T1Counter MSbyte Bit 8

T1CNTR

P041

Bit 7 T1 Counter LSbyte Bit 0

P042

Bit 15 Compare Register MSbyte Bit 8

T1C

P043

Bit 7 Compare Register LSbyte Bit 0

P044

Bit 15 Capture/Compare Register MSbyte Bit 8

T1CC

P045

Bit 7 Capture/Compare Register LSbyte Bit 0

P046

Bit 15 Watchdog Counter MSbyte Bit 8

WDCNTR

P047

Bit 7 Watchdog Counter LSbyte Bit 0

P048

Bit 7 Watchdog Reset Key Bit 0

WDRST

ÁÁ

Á

P049

ÁÁ

Á

WD OVRFL

TAP SEL

†

ÁÁ

Á

WD INPUT
SELECT2

†

ÁÁÁ

Á

WD INPUT
SELECT1

†

ÁÁ

Á

WD INPUT
SELECT0

†

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

T1 INPUT
SELECT2

ÁÁ

Á

T1 INPUT
SELECT1

ÁÁÁ

Á

T1 INPUT
SELECT0

ÁÁ

Á

T1CTL1

P04A

WD OVRFL

RST ENA

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

ÁÁÁÁ

—

—

T1

SW RESET

T1CTL2

Mode: Dual-Compare

ÁÁ

Á

P04B

ÁÁ

Á

T1EDGE

INT FLAG

ÁÁ

Á

T1C2

INT FLAG

ÁÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

T1EDGE
INT ENA

ÁÁ

Á

T1C2

INT ENA

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

P04C

T1

MODE=0

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

ÁÁÁÁ

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

T1CTL4

Mode: Capture/Compare

ÁÁ

Á

P04B

ÁÁ

Á

T1EDGE

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

T1EDGE
INT ENA

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

P04C

T1

MODE = 1

T1C1

OUT ENA

—

T1C1

RST ENA

—

ÁÁÁÁ

T1EDGE

POLARITY

—

T1EDGE

DET ENA

T1CTL4

Mode: Dual-Compare and Capture/Compare

ÁÁ

Á

P04D

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

T1EVT

DATA IN

ÁÁÁÁ

Á

ÁÁ

Á

T1EVT

DATA OUT

ÁÁ

Á

T1EVT

FUNCTION

ÁÁÁ

Á

T1EVT

DATA DIR

ÁÁ

Á

T1PC1

ÁÁ

Á

P04E

ÁÁ

Á

T1PWM

DATA IN

ÁÁ

Á

T1PWM

DATA OUT

ÁÁÁ

Á

T1PWM

FUNCTION

ÁÁ

Á

T1PWM

DATA DIR

ÁÁÁ

Á

T1IC/CR
DATA IN

ÁÁÁÁ

ÁÁ

Á

T1IC/CR

DATA OUT

ÁÁ

Á

T1IC/CR

FUNCTION

ÁÁÁ

Á

T1IC/CR

DATA DIR

ÁÁ

Á

T1PC2

ÁÁ

Á

P04F T1 STEST

T1

PRIORITY

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T1PRI

ÁÁÁÁ

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

21

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

Figure 6 shows the Timer 1 capture/compare mode block diagram. The annotations on the diagram identify the
register and the bit(s) in the PF. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2
register.

T1CTL4.2

16

Compare=

Edge

Select

T1IC/CR

T1EDGE POLARITY

T1EDGE DET ENA

Prescale

Clock

Source

16-Bit

Counter

MSB

LSB

T1CNTR.15–0

Reset

T1C1

RST ENA

T1 SW
RESET

T1CTL2.0

T1CTL4.4

T1PC2.3-0

T1CTL4.0

T1EDGE INT FLAG

T1EDGE INT ENA

T1CTL3.7

T1CTL3.2

T1 OVRFL INT FLAG

T1 OVRFL INT ENA

T1CTL2.3

T1CTL2.4

T1C1 INT FLAG

T1C1 INT ENA

T1CTL3.5

T1CTL3.0

T1C1

OUT ENA

T1PWM

T1CTL4.6

Toggle

T1PC2.7-4

16-Bit

Capt/Comp

Register

MSB

LSB

T1CC.15-0

T1C.15-0

16-Bit

Compare

MSB

LSB

Register

T1 PRIORITY

T1PRI.6

Level 1 Int
Level 2 Int

0
1

Figure 6. Capture/Compare Mode

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

Figure 7 shows the Timer 1 dual-compare mode block diagram. The annotations on the diagram identify the
register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in
the T1CTL2 register.

T1CTL4.1

T1CTL4.4

Prescaler

Clock

Source

16-Bit

Counter

16-Bit

16

Compare=

Compare=

Reset

T1C1

RST ENA

T1 SW

RESET

Edge

Select

T1EDGE DET ENA

Output
Enable

Capt/Comp

Register

MSB

LSB

MSB

LSB

T1CR OUT ENA

T1IC/CR

T1EDGE POLARITY

Toggle

16-Bit

Compare

MSB

LSB

Register

T1CC.15-0

T1C1 INT FLAG

T1CTL3.0

T1CTL3.5

T1C1 INT ENA

T1C2 INT FLAG

T1CTL3.1

T1CTL3.6

T1C2 INT ENA

T1 OVRFL INT FLAG

T1CTL2.4

T1CTL2.3

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.2

T1CTL3.7

T1EDGE INT ENA

T1 PRIORITY

T1C2 OUT ENA

T1C1 OUT ENA

T1CTL4.3

T1CTL4.6

T1CTL4.5

T1PWM

T1PC2.7-4

T1PRI.6

T1C.15-0

T1CNTR.15-0

T1CTL2.0

T1CR

RST ENA

T1PC2.3-0

T1CTL4.0

T1CTL4.2

Level 1 Int
Level 2 Int

0
1

Figure 7. Dual-Compare Mode

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

The TMS370Cx8x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed
as an event counter, pulse accumulator , or interval timer if the watchdog function is not used. The WD function
is to monitor software and hardware operation and to implement a system reset when the WD counter is not
properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be
configured as one of three mask options as follows: standard watchdog, hard WD, or simple counter.

D

Standard watchdog configuration (see Figure 8) for EPROM and mask-ROM devices:
– Watchdog mode

– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

– Non-watchdog mode

– Watchdog timer can be configured as an event counter, pulse accumulator or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog-Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

D

Hard watchdog configuration (see Figure 9) for mask-ROM devices:
– Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.
– Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows.
– A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system

reset.
– Automatic activation of the WD timer upon power-up reset
– INT1 is enabled as a nonmaskable interrupt during low-power modes.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog-Reset Key

WD OVRFL

TAP SEL

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVRFL

INT FLAG

Figure 9. Hard Watchdog

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

D

Simple counter configuration (see Figure 10) for mask-ROM devices only
– Simple counter can be configured as an event counter, pulse accumulator or an internal timer.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog-Reset Key

WD OVRFL

TAP SEL

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVFL
INT FLAG

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

Figure 10. Simple Counter

instruction set overview

Table 15 provides an opcode-to-instruction cross reference of all 73 instructions and 274 opcodes of the
‘370Cx8x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the
opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction
of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B – DECEMBER 1995 – REVISED FEBRUARY 1997

Template Release Date: 7–11–94

26

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

Table 15. TMS370 Family Opcode/Instruction Map

†

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

0

JMP

#ra
2/7

INCW

#ra,Rd

3/11

MOV
Ps,A

2/8

CLRC /

TST A

1/9

MOV

A,B
1/9

MOV
A,Rd

2/7

TRAP

15

1/14

LDST

n

2/6

1JNra

2/5

MOV
A,Pd

2/8

MOV
B,Pd

2/8

MOV

Rs,Pd

3/10

MOV
Ps,B

2/7

MOV
B,Rd

2/7

TRAP

14

1/14

MOV

#ra[SP],A

2/7

2JZra

2/5

MOV
Rs,A

2/7

MOV
#n,A

2/6

MOV
Rs,B

2/7

MOV

Rs,Rd

3/9

MOV

#n,B

2/6

MOV

B,A
1/8

MOV

#n,Rd

3/8

MOV

Ps,Rd

3/10

DEC

A

1/8

DEC

B

1/8

DEC

Rd
2/6

TRAP

13

1/14

MOV

A,*ra[SP]

2/7

3JCra

2/5

AND
Rs,A

2/7

AND
#n,A

2/6

AND
Rs,B

2/7

AND

Rs,Rd

3/9

AND

#n,B

2/6

AND

B,A
1/8

AND

#n,Rd

3/8

AND
A,Pd

2/9

AND
B,Pd

2/9

AND

#n,Pd

3/10

INC

A

1/8

INC

B

1/8

INC
Rd
2/6

TRAP

12

1/14

CMP

*n[SP],A

2/8

4JPra

2/5

OR

Rs,A

2/7

OR

#n,A

2/6

OR

Rs,B

2/7

OR

Rs,Rd

3/9

OR

#n,B

2/6

OR
B,A
1/8

OR

#n,Rd

3/8

OR

A,Pd

2/9

OR

B,Pd

2/9

OR

#n,Pd

3/10

INV

A

1/8

INV

B

1/8

INV
Rd
2/6

TRAP

11

1/14

extend

inst,2

opcodes

L
S

5

JPZ

ra

2/5

XOR
Rs,A

2/7

XOR
#n,A

2/6

XOR
Rs,B

2/7

XOR

Rs,Rd

3/9

XOR

#n,B

2/6

XOR

B,A
1/8

XOR

#n,Rd

3/8

XOR
A,Pd

2/9

XOR
B,Pd

2/9

XOR

#n,Pd

3/10

CLR

A

1/8

CLR

B

1/8

CLR

Rn
2/6

TRAP

10

1/14

N

6

JNZ

ra

2/5

BTJO

Rs,A,ra

3/9

BTJO

#n,A,ra

3/8

BTJO

Rs,B,ra

3/9

BTJO

Rs,Rd,ra

4/11

BTJO

#n,B,ra

3/8

BTJO
B,A,ra

2/10

BTJO

#n,Rd,ra

4/10

BTJO

A,Pd,ra

3/11

BTJO

B,Pd,ra

3/10

BTJO

#n,Pd,ra

4/11

XCHB

A

1/10

XCHB A /

TST B

1/10

XCHB

Rn
2/8

TRAP

9

1/14

IDLE

1/6

7

JNC

ra

2/5

BTJZ

Rs.,A,ra

3/9

BTJZ

#n,A,ra

3/8

BTJZ

Rs,B,ra

3/9

BTJZ

Rs,Rd,ra

4/11

BTJZ

#n,B,ra

3/8

BTJZ

B,A,ra

2/10

BTJZ

#n,Rd,ra

4/10

BTJZ

A,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

BTJZ

#n,Pd,ra

4/11

SWAP

A

1/11

SWAP

B

1/11

SWAP

Rn
2/9

TRAP

8

1/14

MOV
#n,Pd

3/10

8JVra

2/5

ADD
Rs,A

2/7

ADD
#n,A

2/6

ADD
Rs,B

2/7

ADD

Rs,Rd

3/9

ADD

#n,B

2/6

ADD

B,A
1/8

ADD

#n,Rd

3/8

MOVW
#16,Rd

4/13

MOVW

Rs,Rd

3/12

MOVW

#16[B],Rpd

4/15

PUSH

A

1/9

PUSH

B

1/9

PUSH

Rd
2/7

TRAP

7

1/14

SETC

1/7

9JLra

2/5

ADC
Rs,A

2/7

ADC
#n,A

2/6

ADC
Rs,B

2/7

ADC

Rs,Rd

3/9

ADC

#n,B

2/6

ADC

B,A
1/8

ADC

#n,Rd

3/8

JMPL

lab
3/9

JMPL

*Rp

2/8

JMPL
*lab[B]

3/11

POP

A

1/9

POP

B

1/9

POP

Rd
2/7

TRAP

6

1/14

RTS

1/9

A

JLE

ra

2/5

SUB

Rs,A

2/7

SUB
#n,A

2/6

SUB
Rs,B

2/7

SUB

Rs,Rd

3/9

SUB

#n,B

2/6

SUB

B,A
1/8

SUB

#n,Rd

3/8

MOV

& lab,A

3/10

MOV

*Rp,A

2/9

MOV

*lab[B],A

3/12

DJNZ

A,#ra

2/10

DJNZ
B,#ra

2/10

DJNZ

Rd,#ra

3/8

TRAP

5

1/14

RTI

1/12

B

JHS

ra

2/5

SBB

Rs,A

2/7

SBB
#n,A

2/6

SBB
Rs,B

2/7

SBB

Rs,Rd

3/9

SBB
#n,B

2/6

SBB

B,A
1/8

SBB

#n,Rd

3/8

MOV

A, & lab

3/10

MOV

A, *Rp

2/9

MOV

A,*lab[B]

3/12

COMPL

A

1/8

COMPL

B

1/8

COMPL

Rd
2/6

TRAP

4

1/14

PUSH

ST
1/8

†

All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions
have a relative address as the last operand.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B – DECEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 27

Table 15. TMS370 Family Opcode/Instruction Map† (Continued)

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

C

JNV

ra

2/5

MPY
Rs,A

2/46

MPY
#n,A
2/45

MPY
Rs,B
2/46

MPY

Rs,Rd

3/48

MPY
#n,B
2/45

MPY

B,A

1/47

MPY

#n,Rs

3/47

BR
lab
3/9

BR
*Rp
2/8

BR

*lab[B]

3/11

RR

A

1/8

RR

B

1/8

RR

Rd

2/6

TRAP

3

1/14

POP

ST
1/8

L

D

JGE

ra

2/5

CMP
Rs,A

2/7

CMP

#n,A

2/6

CMP

Rs,B

2/7

CMP

Rs,Rd

3/9

CMP
#n,B

2/6

CMP

B,A
1/8

CMP
#n,Rd

3/8

CMP

& lab,A

3/11

CMP

*Rp,A

2/10

CMP

*lab[B],A

3/13

RRC

A

1/8

RRC

B

1/8

RRC

Rd

2/6

TRAP

2

1/14

LDSP

1/7

S

N

EJGra

2/5

DAC
Rs,A

2/9

DAC
#n,A

2/8

DAC
Rs,B

2/9

DAC

Rs,Rd

3/11

DAC
#n,B

2/8

DAC

B,A

1/10

DAC

#n,Rd

3/10

CALL

lab

3/13

CALL

*Rp

2/12

CALL

*lab[B]

3/15

RL

A

1/8

RL

B

1/8

RL
Rd

2/6

TRAP

1

1/14

STSP

1/8

F

JLO

ra

2/5

DSB
Rs,A

2/9

DSB
#n,A

2/8

DSB
Rs,B

2/9

DSB

Rs,Rd

3/11

DSB
#n,B

2/8

DSB

B,A

1/10

DSB

#n,Rd

3/10

CALLR

lab

3/15

CALLR

*Rp

2/14

CALLR

*lab[B]

3/17

RLC

A

1/8

RLC

B

1/8

RLC

Rd

2/6

TRAP

0

1/14

NOP

1/7

Second byte of two-byte instructions (F4xx): F4 8

MOVW

*n[Rn]

4/15

DIV

Rn.A

3/14-63

F4 9

JMPL
*n[Rn]

4/16

Legend:
* = Indirect addressing operand prefix
& = Direct addressing operand prefix

F4 A

MOV

*n[Rn],A

4/17

# = immediate operand
#16 = immediate 16-bit number
lab = 16-label

F4 B

MOV

A,*n[Rn]

4/16
n = immediate 8-bit number
Pd = Peripheral register containing destination type
Pn = Peripheral register

p

F4 C

BR

*n[Rn]

4/16

Ps=Peri heral register containing source byte

ra = Relative address
Rd = Register containing destination type
Rn = Re

g

ister file

F4 D

CMP

*n[Rn],A

4/18

Rn Register file

Rp = Register pair
Rpd= Destination register pair
Rps = Source Register pair

F4 E

CALL
*n[Rn]

4/20
Rs = Register containing source byte

F4 F

CALLR

*n[Rn]

4/22

†

All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions
have a relative address as the last operand.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, CDT and an
EEPROM/UVEPROM programmer.

D

Assembler/linker (Part No. TMDS3740850–02 for PC)
– Includes extensive macro capability
– Provides high-speed operation
– Includes format conversion utilities for popular formats

D

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3
or Sun-4)

– Generates assembly code for the TMS370 that can be inspected easily
– Improves code execution speed and reduces code size with optional optimizer pass
– Enables direct reference to the TMS370’s port registers by using a naming convention
– Provides flexibility in specifying the storage for data objects
– Interfaces C functions and assembly functions easily
– Includes assembler and linker

D

CDT370 (Compact Development Tool) real-time in-circuit emulation
– Base (Part Number EDSCDT370 – for PC, requires cable)

– Cable for 40-pin DIP (Part No. EDSTRG40DIL8X)

– Cable for 44-pin PLCC (Part No. EDSTRG44PLCC8X)
– Provides EEPROM and EPROM programming support
– Allows inspection and modification of memory locations
– Includes compatibility to upload/download program and data memory
– Executes programs and software routines
– Includes 1024-sample trace buffer
– Includes single-step executable instructions
– Uses software breakpoints to halt program execution at selected address
– Provides timers for analyzing total and average time in routines
– Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and

to trace display

D

Microcontroller programmer
– Base (Part No. TMDS3760500A – for PC, requires programmer head)

– Single unit head for 44-pin PLCC (Part No. TMDS3780510A)

– Single unit head for 40-pin DIP (Part No. TMDS3780511A)
– PC-based, window/function-key-oriented user interface for ease of use and rapid learning environment

D

Converter Socket (Part No. TMDS37788OTP)

HP700 is a trademark of Hewlett-Packard Company.
Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device numbering conventions

Figure 11 illustrates the numbering and symbol nomenclature for the TMS370Cx8x family .

6370 8 6C

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology: C = CMOS

Program Memory Types: 0 = Mask ROM

3 = Mask ROM, No Data EEPROM
6 = EPROM, No Data EEPROM

Device Type: 8 = ’x8x device containing a Timer1 module

Memory Size: 0 = 4K bytes

6 = 16K bytes

Temperature Ranges: A = –40°C to 85°C

L = 0°C to 70°C
T = –40°C to 105°C

Packages: FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

N = Plastic Dual-In-Line

ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog
– A hard watchdog
– A simple watchdog

The clock can be either:

– Divide-by-4 clock
– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled
– Disabled

Without A = For ROM device, a standard watchdog,

a divide-by-4 clock, and low-power modes are enabled

A = For EPROM device, a standard watchdog,

a divide-by-4 clock, and low-power modes are enabled

TMS

AFNL

Figure 11. TMS370Cx8x Family Nomenclature

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device part numbers

T able 16 provides all of the ’x8x devices available. The device part number nomenclature is designed to assist
ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and
watchdog timer options desired. Each device can have only one of the three possible watchdog timer options
and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

T able 16. Device Part Numbers

DEVICES PART NUMBERS

FOR 44 PINS (LCC)

DEVICES PART NUMBERS

FOR 40 PINS (PDIP)

TMS370C380AFNA

TMS370C380AFNL

TMS370C380AFNT

TMS370C080NA
TMS370C080NL
TMS370C080NT

TMS370C686AFNT —

SE370C686AFZT

†

—

†

System evaluators are for use in prototype environment and their
reliability has not been characterized.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

new code release form

Figure 12 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

TMS370 MICROCONTROLLER PRODUCTS

DATE:

T o release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:
Street Address:
Street Address:
City: State Zip

Contact Mr./Ms.:
Phone: ( ) Ext.:

Customer Purchase Order Number:

Customer Part Number:
Customer Application:

Customer Print Number *Yes: #

No: (Std. spec to be followed)
*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM
code processing starts.

TMS370 Device:
TI Customer ROM Number:

(provided by T exas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLAT OR FREQUENCY

MIN TYP MAX
[] External Drive (CLKIN)
[] Crystal
[] Ceramic Resonator

Low Power Modes
[] Enabled
[] Disabled

Watchdog counter
[] Standard
[] Hard Enabled
[] Simple Counter

Clock Type
[] Standard (/4)
[] PLL (/1)

[] Supply Voltage MIN: MAX:
(std range: 4.5V to 5.5V)

NOTE:
Non ’A’ version ROM devices of the TMS370 microcontrollers will have the
“Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog
options. See the

TMS370 Family User’s Guide

(literature number SPNU127)

or the

TMS370 Family Data Manual

(literature number SPNS014B).

TEMPERATURE RANGE

[] ’L’: 0° to 70°C (standard)
[] ’A’: –40° to 85°C
[] ’T’: –40° to 105°C

PACKAGE TYPE

[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC
[] “FN” 28-pin PLCC [] “FN” 68-pin PLCC
[] “N” 40-pin PDIP [] “NM” 64-pin PSDIP
[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZA TION BUS EXPANSION

[] TI standard symbolization
[] TI standard w/customer part number
[] Customer symbolization

(per attached spec, subject to approval)

[] YES [] NO

NON-STANDARD SPECIFICATIONS:
ALL NON-STANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the
TI part number.

RELEASE AUTHORIZATION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.

1. Customer: Date: 2. TI: Field Sales:
Marketing:
Prod. Eng.:
Proto. Release:

Figure 12. Sample New Code Release Form

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 17 is a collection of all the peripheral file frames used in the ’Cx8x (provided for a quick reference).

Table 17. Peripheral File Frame Compilation

System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

ÁÁ

Á

P010

ÁÁ

Á

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁ

Á

OSC FLT

FLAG

ÁÁÁ

Á

MC PIN

WPO

ÁÁ

Á

MC PIN

DATA

ÁÁ

Á

—

ÁÁÁ

Á

µP/µC

MODE

ÁÁ

Á

SCCR0

ÁÁ

Á

P011

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

AUTO

WAIT

DISABLE

ÁÁÁ

Á

—

MEMORY
DISABLE

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

SCCR1

ÁÁ

Á

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁÁ

Á

—

BUS

STEST

CPU

STEST

ÁÁ

Á

—

INT1

NMI

PRIVILEGE

DISABLE

ÁÁ

Á

SCCR2

ÁÁ

Á

ÁÁ

Á

P013

to

P016

Reserved

ÁÁ

Á

ÁÁ

Á

P017

INT1

FLAG

INT1

PIN DATA

—

—

—

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

INT1

ÁÁ

Á

P018

ÁÁ

Á

INT2

FLAG

ÁÁ

Á

INT2

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

INT2

DATA DIR

ÁÁÁ

Á

INT2

DATA OUT

ÁÁ

Á

INT2

POLARITY

ÁÁ

Á

INT2

PRIORITY

ÁÁÁ

Á

INT2

ENABLE

ÁÁ

Á

INT2

P019

INT3

FLAG

INT3

PIN DATA

—

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

INT3

P01A

BUSY

—

—

—

—

AP

W1W0

EXE

DEECTL
P01B Reserved
P01C

BUSY

VPPS

—

—

—

—

W0

EXE

EPCTL

ÁÁ

Á

P01D
P01E

P01F

Reserved

ÁÁ

Á

Digital Port Control Registers

P020 Reserved

APORT1

P021

Port A Control Register 2 (must be 0)

APORT2

P022

Port A Data

ADATA

P023

Port A Direction

ADIR

P024 Reserved

BPORT1

P025 Port B Control Register 2 (must be 0)

BPORT2

P026 Port B Data

BDATA

P027 Port B Direction

BDIR

P028 Reserved

CPORT1

P029 Port C Control Register 2 (must be 0)

CPORT2
P02A Port C Data

CDATA
P02B Port C Direction

CDIR
P02C

Port D Control Register 1 (must be 0)

—

—

—

DPORT1
P02D

Port D Control Register 2 (must be 0)

†

—

—

—

DPORT2
P02E

Port D Data

—

—

—

DDATA

P02F

Port D Direction

—

—

—

DDIR

Timer1 Module Register Memory Map

Modes: Dual-Compare and Capture/Compare

P040

Bit 15 T1Counter MSbyte Bit 8

T1CNTR

P041

Bit 7 T1 Counter LSbyte Bit 0

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 17. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

ÁÁÁÁ

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare (Continued)

P042

Bit 15 Compare Register MSbyte Bit 8

T1C

P043

Bit 7 Compare Register LSbyte Bit 0

P044

Bit 15 Capture/Compare Register MSbyte Bit 8

T1CC

P045

Bit 7 Capture/Compare Register LSbyte Bit 0

P046

Bit 15 Watchdog Counter MSbyte Bit 8

WDCNTR

P047

Bit 7 Watchdog Counter LSbyte Bit 0

P048

Bit 7 W atchdog Reset Key Bit 0

WDRST

P049

WD OVRFL

TAP SEL

†

WD INPUT

SELECT2

†

WD INPUT
SELECT1

†

WD INPUT
SELECT0

†

ÁÁÁÁ

—

T1 INPUT
SELECT2

T1 INPUT
SELECT1

T1 INPUT
SELECT0

T1CTL1

Á

Á

P04A

ÁÁ

Á

WD OVRFL

RST ENA

†

ÁÁÁ

Á

WD OVRFL

INT ENA

ÁÁ

Á

WD OVRFL

INT FLAG

ÁÁÁ

Á

T1 OVRFL

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

T1 OVRFL

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T1

SW RESET

ÁÁ

Á

T1CTL2

Mode: Dual-Compare

P04B

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

—

ÁÁÁÁ

—

T1EDGE
INT ENA

T1C2

INT ENA

T1C1

INT ENA

T1CTL3

Á

Á

P04C

ÁÁ

Á

T1 MODE=0

ÁÁÁ

Á

T1C1

OUT ENA

ÁÁ

Á

T1C2

OUT ENA

ÁÁÁ

Á

T1C1

RST ENA

ÁÁÁÁ

Á

ÁÁ

Á

T1CR

OUT ENA

ÁÁ

Á

T1EDGE

POLARITY

ÁÁÁ

Á

T1CR

RST ENA

ÁÁ

Á

T1EDGE

DET ENA

ÁÁ

Á

T1CTL4

Mode: Capture/Compare

P04B

T1EDGE

INT FLAG

—

T1C1

INT FLAG

—

ÁÁÁÁ

—

T1EDGE
INT ENA

—

T1C1

INT ENA

T1CTL3

Á

Á

P04C

ÁÁ

Á

T1

MODE = 1

ÁÁÁ

Á

T1C1

OUT ENA

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

RST ENA

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

T1EDGE

POLARITY

ÁÁÁ

Á

—

ÁÁ

Á

T1EDGE

DET ENA

ÁÁ

Á

T1CTL4

Modes: Dual-Compare and Capture/Compare

P04D

—

—

—

—

ÁÁÁÁ

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

T1PC1

Á

Á

P04E

ÁÁ

Á

T1PWM

DATA IN

ÁÁÁ

Á

T1PWM

DATA OUT

ÁÁ

Á

T1PWM

FUNCTION

ÁÁÁ

Á

T1PWM

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

T1IC/CR
DATA IN

ÁÁ

Á

T1IC/CR

DATA OUT

ÁÁÁ

Á

T1IC/CR

FUNCTION

ÁÁ

Á

T1IC/CR DATA

DIR

ÁÁ

Á

T1PC2

P04F T1 STEST

T1

PRIORITY

—

—

ÁÁÁÁ

—

—

—

—

T1PRI

ÁÁÁÁ

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter . In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range,VCC (see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (V

I

< 0 or V

I

> V

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current per buffer, IO (VO = 0 to V

CC)

) (see Note 2) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

CC

current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

SS

current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A version – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T version – 40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.

2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in
any buffer can affect the levels on other buffers.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage (see Note 1) 4.5 5 5.5 V

V

CC

RAM data-retention supply voltage (see Note 3) 3 5.5 V

p

All pins except MC V

SS

0.8

VILLow-level input voltage

MC, normal operation V

SS

0.3

V

All pins except MC, XTAL2/CLKIN, and
RESET

2 V

CC

V

IH

High-level input voltage

XTAL2/CLKIN

0.8 V

CC

V

CC

V

RESET 0.7 V

CC

V

CC

EEPROM write protect override (WPO) 11.7 12 13

V

MC

MC (mode control) voltage

EPROM programming voltage (VPP)

13 13.2 13.5

V

Microcomputer V

SS

0.3

L version 0 70

T

A

Operating free-air temperature

A version

– 40 85

°C

T version – 40 105

NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.

3. RESET

must be externally activated when VCC or SYSCLK is not within the recommended operating range.

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OL

Low-level output voltage IOL = 1.4 mA 0.4 V

p

IOH = –50 µA 0.9 V

CC

VOHHigh-level output voltage

IOH = –2 mA 2.4

V

0 V < VI ≤ 0.3 V 10

0.3 V < VI ≤ 13 V 650

µ

A

I

I

Input current

MC

See Note 4
12 V ≤ VI ≤ 13 V

50 mA

I/O pins 0 V ≤ VI ≤ V

CC

± 10 µA

I

OL

Low-level output current VOL = 0.4 V 1.4 mA

p

VOH = 0.9 V

CC

– 50 µA

IOHHigh-level output current

VOH = 2.4 V – 2 mA
See Notes 5 and 6

SYSCLK = 5 MHz

30 45

Supply current (operating mode)
OSC POWER bit = 0 (see Note 7)

See Notes 5 and 6
SYSCLK = 3 MHz

20 30

mA

See Notes 5 and 6
SYSCLK = 0.5 MHz

7 11

See Notes 5 and 6
SYSCLK = 5 MHz

10 17

I

CC

Supply current (STANDBY mode)
OSC POWER bit = 0 (see Note 8)

See Notes 5 and 6
SYSCLK = 3 MHz

8 11

mA

See Notes 5 and 6
SYSCLK = 0.5 MHz

2 3.5

Supply current (STANDBY mode)

See Notes 5 and 6
SYSCLK = 3 MHz

6 8.6

y( )

OSC POWER bit = 1 (see Note 9)

See Notes 5 and 6
SYSCLK = 0.5 MHz

2 3.0

mA

Supply current (HALT mode)

See Note 5
XTAL2/CLKIN < 0.2 V

2 30 µA

NOTES: 4. Input current IPP is a maximum of 50 mA only when you are programming EPROM.

5. Single-chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2V .

6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current
can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance
in pF).

7. Maximum operating current = 7.6 (SYSCLK) + 7 mA.

8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz SYSCLK).

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

External

Clock Signal

XTAL1XTAL2/CLKIN

C2
(see Note B)

C1

(see Note B)

Crystal/Ceramic

Resonator

(see Note A)

XTAL1XTAL2/CLKIN

C3
(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and the value of C3 is typically 50 pF. See the manufacturer’s recommendations for

ceramic resonators.

Figure 13. Recommended Crystal/Clock Connections

1.2 kΩ

20 pF

V

O

Load Voltage

Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V
Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 14. Typical Output Load Circuit (See Note A)

V

CC

GND

300 Ω

20 Ω

I/O

Pin Data
Output

Enable

V

CC

GND

INT1

6 kΩ

20 Ω

30 Ω

Figure 15. T ypical Buffer Circuitry

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:

AR Array CI XTAL2/CLKIN
B Byte SC SYSCLK

Lowercase subscripts and their meanings are:

c cycle time (period) su setup time
d delay time v valid time
f fall time w pulse duration (width)
r rise time

The following additional letters are used with these meanings:

H High
L Low
V Valid

All timings are measured between high and low measurement points as indicated in Figure 16 and Figure 17.

0.8 V (Low)

2 V (High)

0.8 V (Low)

0.8 VCC V (High)

Figure 16. XTAL2/CLKIN Measurement Points Figure 17. General Measurement Points

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

external clocking requirements for clock divided by 4 (see Note 10 and Figure 18)

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns
CLKIN Crystal operating frequency 2 20 MHz
SYSCLK Internal system clock operating frequency

†

0.5 5 MHz

†

SYSCLK = CLKIN/4

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

11. This pulse may be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

3

2

1

4

SYSCLK

Figure 18. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL) (see Note 10 and Figure 19)

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns
CLKIN Crystal operating frequency 2 5 MHz
SYSCLK Internal system clock operating frequency

‡

2 5 MHz

‡

SYSCLK = CLKIN/1

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

4

32

1

XTAL2/CLKIN

SYSCLK

Figure 19. External Clock Timing for Divide-by-1

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

switching characteristics and timing requirements (see Note 12)

NO. PARAMETER MIN MAX UNIT

Divide-by-4 200 2000

5

tcCycle time, SYSCLK (system clock)

Divide-by-1 200 500

ns

6 t

w(SCL)

Pulse duration, SYSCLK low 0.5 tc–20 0.5 t

c

ns

7 t

w(SCH)

Pulse duration, SYSCLK high 0.5 t

c

0.5 tc + 20 ns

NOTE 12: tc = system-clock cycle time = 1/SYSCLK

SYSCLK

5

6

7

Figure 20. SYSCLK Timing

general purpose output signal switching time requirements

MIN NOM MAX UNIT

trRise time 30 ns
tfFall time 30 ns

t

f

t

r

Figure 21. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN MAX UNIT

t

w(PGM)B

Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms

t

w(PGM)AR

Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms

recommended EPROM operating conditions for programming

MIN NOM MAX UNIT

V

CC

Supply voltage 4.75 5.5 6 V

V

PP

Supply voltage at MC pin 13 13.2 13.5 V

I

PP

Supply current at MC pin during programming (VPP = 13 V) 30 50 mA

Divide-by-4 0.5 5

SYSCLK

System clock

Divide-by-1 2 5

MH

z

recommended EPROM timing requirements for programming

MIN NOM MAX UNIT

t

w(EPGM)

Pulse duration, programming signal (see Note 13) 0.40 0.50 3 ms

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.

Table 18. TMS370Cx8x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

TMS370 GENERIC NAME

PKG TYPE NO. AND

MECHANICAL NAME

DEVICE PART NUMBERS

БББББ

Á

БББББ

Á

FN – 44 pin
(50-mil pin spacing)

ББББББББ

Á

ББББББББ

Á

PLASTIC LEADED CHIP CARRIER
(PLCC)

ББББББББББ

Á

ББББББББББ

Á

FN(S-PQCC-J**) PLASTIC J-LEADED
CHIP CARRIER

ББББББ

Á

ББББББ

Á

TMS370C380AFNA
TMS370C380AFNL
TMS370C380AFNT
TMS370C686AFNT

БББББ

Á

FZ – 44 pin
(50-mil pin spacing)

ББББББББ

Á

CERAMIC LEADED CHIP CARRIER
(CLCC)

ББББББББББ

Á

FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER

ББББББ

Á

SE370C686AFZT

БББББ

Á

N – 40 pin
(100-mil pin spacing)

ББББББББ

Á

PLASTIC DUAL-IN-LINE PACKAGE
(PDIP)

ББББББББББ

Á

N(R-PDIP-T**) PLASTIC DUAL-IN-LINE
PACKAGE

ББББББ

Á

TMS370C080NA
TMS370C080NL
TMS370C080NT

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

12

Seating Plane

0.560 (14,22)

0.520 (13,21)

13

0.610 (15,49)

0.590 (14,99)

524840

0.125 (3,18) MIN

2.390

(60,71)

(62,23)(53,09)

(51,82)

2.040

2.090

2.450 2.650
(67,31)

(65,79)

2.590

0.010 (0,25) NOM

4040053/B 04/95

A

0.060 (1,52) TYP

1

24

322824

1.230

(31,24)

(32,26) (36,83)

(35,81)

1.410

1.450

1.270

PINS **

DIM

0.015 (0,38)

0.021 (0,53)

A MIN

A MAX

1.650

(41,91)

(40,89)

1.610

0.020 (0,51) MIN

0.200 (5,08) MAX

0.100 (2,54)

M

0.010 (0,25)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)

TMS370Cx8x
8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

18

19

14

13

D

D1

13

9

E1E

4

8

MINMAXMIN

PINS

**

20
28
44

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)
52
68
84

1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF

D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

M

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

4040219/B 03/95

0.180 (4,57)

0.140 (3,55)

C

0.020 (0,51)

0.032 (0,81)

A B

A

B

0.025 (0,64) R TYP

0.026 (0,66)

0.120 (3,05)

0.155 (3,94)

0.014 (0,36)

0.120 (3,05)

0.040 (1,02) MIN

0.090 (2,29)

0.040 (1,02)  45°

A

MIN MAX

0.485

(12,32) (12,57)

0.495

0.455

(11,56)(10,92)

0.430

MAXMIN

BC

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

PINS**

28

44

52

NO. OFJEDEC

MO-087AC

MO-087AB

MO-087AA

OUTLINE

28 LEAD SHOWN

Seating Plane

(at Seating

Plane)

1426

25

19

18

12

11

5

0.050 (1,27)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

68MO-087AD

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

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