TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
Copyright 1990, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• TTL-Compatible Inputs
• CCD-Compatible Outputs
• Variable-Output Slew Rates With External
Resistor Control
• Full-Frame Operation
• Frame-Transfer Operation
• Solid-State Reliability
• Adjustable Clock Levels
description
The TMS3473B is a monolithic CMOS integrated
circuit designed to drive the parallel image-area
gate (IAG), parallel storage-area gate (SAG), and
antiblooming gate (ABG) inputs of the Texas Instruments (TI) virtual-phase CCD image sensors. The
TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL-input signals
from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor.
The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When
the TMS3473B I
/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I/N is
connected to V
CC
, the noninterlace mode is selected (see Figure 2).
ABOUT follows ABIN and switches between V
ABG+
and V
ABG–
. IAOUT and SAOUT follow IAIN and SAIN,
respectively , and switch between V
CC
and VSS. Additionally , ABOUT and IAOUT can each be made to output
midlevel voltages. DC inputs to ABL VL and IALVL determine the midlevel voltages that can be output on ABOUT
and IAOUT , respectively . A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic
level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected.
Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to V
CC
and ABSR to V
ABG+
through external resistors. The larger the resistor values, the longer the rise and fall times are.
A low-logic level on PD
causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT
and SAOUT to V
SS
, ABOUT to V
ABG–
).
The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from
–20°C to 45°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.
Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices and Assemblies
available from Texas Instruments.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IAL VL
I
/N
IAIN
ABIN
MIDSEL
SAIN
PD
GND
V
ABG+
V
SS
V
SS
IASR
ABSR
V
CC
ABLVL
IAOUT
ABOUT
SAOUT
V
CC
V
ABG–
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TI is a trademark of Texas Instruments Incorporated.
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
TTL/CCD
ABOUT
14
4
ABIN
16
ABLVL
18
ABSR
3
IAIN
1
IALVL
19
IASR
6
SAIN
IAOUT
15
SAOUT
13
NONINT
2
TMS3473B
Φ
INT/M1
PWR DWN
7
ABOUT to midlevel
5
MIDSEL
1(IAOUT to midlevel)
I/N
PD
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
ABIN 4 I Antiblooming in
ABLVL 16 I DC antiblooming midlevel voltage
ABOUT 14 O Antiblooming out
ABSR 18 I Antiblooming slew rate
GND 8 Ground
IAIN 3 I Parallel-image-area in
IALVL 1 I DC parallel-image-area midlevel voltage
IAOUT 15 O Parallel-image-area out
IASR 19 I Parallel-image-area slew rate
I/N 2 I Interlace/noninterlace select
MIDSEL 5 I IAOUT/ABOUT midlevel voltage select
PD 7 I Power down
SAIN 6 I Parallel storage area in
SAOUT 13 O Parallel storage area out
V
ABG+
9 I Positive ABG supply voltage
V
ABG–
11 I Negative ABG supply voltage
V
CC
†
12 I Positive supply voltage
V
CC
†
17 I Positive supply voltage
V
SS
†
10 I Negative supply voltage
V
SS
†
20 I Negative supply voltage
†
All terminals of the same name should be connected together externally.
IAIN
ABIN
MIDSEL
IAOUT
ABOUT
I
/N
Integrate
Readout
or
Transfer to
Memory
‡
ABOUT
IAOUT
MIDSEL
ABIN
IAIN
I
/N
TV Field BTV Field A
Integrate
Readout
or
Transfer to
Memory
‡
–9 V
5 V
0 V
5 V
0 V
5 V
0 V
1.5 V
–9 V
–3 V
3 V
–8 V
–2.5 V
2 V
5 V
0 V
5 V
0 V
5 V
0 V
1.5 V
–9 V
3 V
–8 V
–2.5 V
Figure 1. Parallel-Driver Timing Diagram
(interlace mode)
Figure 2. Parallel-Driver Timing Diagram
(noninterlace mode)
‡
A readout occurs if the TMS3473B is driving a full-frame CCD image sensor; a transfer to memory occurs if the TMS3473B is driving a
frame-transfer CCD image sensor.
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Positive supply voltage, V
CC
(see Note 1) 4.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative supply voltage, V
SS
(see Note 2) –11.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive ABG supply voltage, V
ABG+
5.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative ABG supply voltage, V
ABG–
–8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABG supply voltage differential (V
ABG+
– VSS) 15.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below), T
A
≤ 25°C:
Unmounted device (see Figure 3) 825 mW. . . . . . . . . . . . . .
Mounted device (see Figure 3) 1150 mW. . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –20°C to 45°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
STG
–55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
voltage levels only.
010203040506070
0
500
1000
1500
P
D
– Power Dissipation – mW
TA – Free-Air Temperature – °C
Mounted Device
(see Note A)
Unmounted Device
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
100
200
300
400
600
700
800
900
1100
1200
1300
1400
Figure 3
NOTE A: The mounted-device derating curve in Figure 3 is obtained under the following conditions:
The board is 50 mm by 50 mm by 1.6 mm thick.
The board material is glass epoxy.
The copper thickness of all the etch runs is 35 microns.
Etch run dimensions – DW package – All 20 etch runs are 0.4 mm by 22 mm.
Each chip is soldered to the board.
An aluminum cooling fin 10 mm by 10 mm by 1 mm thick is coupled to the chip with thermal paste.
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
Positive supply voltage, V
CC
†
0 1 4.4 V
Negative supply voltage, V
SS
†
–11.1 –10 –9.7 V
Positive ABG supply voltage, V
ABG+
†
1 3.5 4.4 V
Negative ABG supply voltage, V
ABG–
†
–11.1 –7 –6.2 V
Power supply voltage differential (VCC – VSS) 15.5 V
DC parallel image area midlevel voltage, IALVL
‡
Z < 5 kΩ –6 –5 –2 V
DC antiblooming midlevel voltage, ABLVL Z < 2.5 kΩ –3.5 –2.5 1 V
p
ABIN, MIDSEL, PD, IAIN, or SAIN 2.5 5
High-level input voltage, V
IH
I/N VCC – 0.4
V
p
ABIN, MIDSEL, PD, IAIN, or SAIN 0 0.9
Low-level input voltage, V
IL
I/N VSS + 0.4
V
p
ABLVL –3.5 1
Input voltage, V
I
IALVL –6 –2
V
IAIN, SAIN
§
3.58
Frequenc
y,
f
clock
ABIN
§
2
MH
z
Input resistance, R
i
IALVL, ABLVL 2.5 kΩ
Slope-resistance bias 10 50 kΩ
Input capacitance, C
i
ABLVL 1 µF
Operating free-air temperature, T
A
–20 45 °C
†
VCC, VSS, V
ABG+
, and V
ABG–
have 100-mA current limits. Adequate decoupling capacitors are required from these terminals to ground.
‡
Proper adjustment is required for interlace-mode operation.
§
Different CCD image sensors have different maximum clock rates. See the individual CCD image sensor data sheets for these rates.
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 2)
PARAMETER TEST CONDITIONS
†
MIN MAX UNIT
High-level output
ABOUT IOH = 180 mA (peak) V
ABG+
– 0.2 V
ABG+
+ 0.2
V
OH
g
voltage
IAOUT, SAOUT
IOH = 730 mA (peak) VCC – 0.5 VCC + 0.5
V
Low-level output
ABOUT IOL = 180 mA (peak) V
ABG–
– 0.3 V
ABG–
+ 0.3
V
OL
voltage
IAOUT, SAOUT
IOL = 730 mA (peak) VSS – 0.6 VSS + 0.8
V
High-level input
ABIN, IAIN, SAIN, MIDSEL, PD VIH = 5 V 0 –50
I
IH
†
g
current
I
/N VIH = VCC = 2 V ±10
µ
A
Low-level input
ABIN, IAIN, SAIN, MIDSEL, PD VIL = 0 V ±10
I
IL
†
current
I
/N VIL = VSS = –10 V ±10
µ
A
I
AB
Antiblooming current Average load, See Note 3 20 mA
pp
No load, PD = 0 V 1.5
ISSSupply current
Average load, See Note 4 25
mA
†
These parameters are measured with VSS = –10.3 V , VCC = 2.1 V , V
ABG+
= 4.3 V , V
ABG–
= –7 V , and with IASR connected to VCC and ABSR
connected to V
ABG+,
both through 22-kΩ resistors.
NOTES: 2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
voltage levels only.
3. The load consists of a TC241 CCD image sensor with ABG clocked at 2 MHz using ABG mode 3 (see the TMS3471C data sheet
for details on mode 3).
4. The load consists of a TC241 CCD image sensor with IAG and SAG clocked at 2.1 MHz.
switching characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
ABOUT 60 140
trRise time
IAOUT, SAOUT
V
= 2.1 V, V
= 4.3 V, V
–
= –7 V,
40
180
ns
ABOUT
CC
,
TA = 25°C,
ABG+
,
VSS = –10.3 V ,
ABG
,
See Note 5
45
100
tfFall time
IAOUT, SAOUT 30 110
ns
NOTE 5: IASR is connected to VCC and ABSR is connected to V
ABG+
, both through 22-kΩ resistors. The load consists of a TC241 CCD image
sensor with ABG clocked at 2 MHz using ABG mode 3 (see the TMS3471C data sheet for details on mode 3).
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DW/R-PDSO-G** PLASTIC WIDE-BODY SMALL-OUTLINE PACKAGE
20 PIN SHOWN
0.419 (10,65)
0.400 (10,15)
0.293 (7,45)
0.299 (7,59)
0.093 (2,35)
0.104 (2,65)
0.012 (0,30)
0.004 (0,10)
0.009 (0,23)
0.012 (0,30)
0.050 (1,27)
0.016 (0,40)
0.020 (0,51)
0.014 (0,35)
16
0.400
(10,16)
A MIN
A MAX
(10,41)
0.410
0.510
(12,95)
(12,70)
0.500
20
0.610
(15,49)
(15,24)
0.600
24
0.710
(18,03)
(17,78)
0.700
28
DIM
PINS**
4040000/A–10/93
20 11
1
10
0.338 (8,58)
0.364 (9,24)
A
Seating Plane
0.004 (0,10)
0°–8°
M
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
SOCS022B – NOVEMBER 1990
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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