Texas Instruments TMS3472ADW, TMS3472A Datasheet
TMS3472A
SERIAL DRIVER
SOCS025B – FEBRUARY 1991
PD
SSR
V
SS
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
1PC2
1PC1
V
CC
SRG3OUT
SRG2OUT
SRG1OUT
TRGOUT
V
CC
TSR
• TTL-Compatible Inputs
• CCD-Compatible Outputs
• Variable-Output Slew Rates With External
Resistor Control
• Frame-Transfer Operation
• Solid-State Reliability
• Adjustable Clock Levels
description
The TMS3472A serial driver is a monolithic
CMOS integrated circuit designed to drive the
serial-register gate (SRGn) and transfer-gate
DLADJ
GND
SRG2,3IN
SRG1IN
TRGIN
2,3PC1
2,3PC2
(TRG) inputs of the Texas Instruments (TI)
TC241 (monochrome) CCD image sensor. The TMS3472A interfaces the TI TMS3471C or a user-defined
timing generator to the TC241; it receives TTL signals from the timing generator and outputs level-shifted and
slew-rate-adjusted signals to the image sensor. The TMS3472A contains three noninverting serial drivers and
one noninverting transfer driver as well as circuitry for slew-rate adjustment.
The voltage levels on SRG1OUT , SRG2OUT , SRG3OUT , and TRGOUT are controlled by the levels on V
V
. DLADJ, PD, SRG1IN, SRG2,3IN, and TRGIN are TTL compatible. A high level on PD allows the TMS3472
CC
to operate normally with the level-shifted and slew-rate-adjusted outputs following the inputs. When PD
the device is in a low power-consumption mode and all outputs are at V
CC
.
The slew rate of SRG1OUT , SRG2OUT , and SRG3OUT is controlled by connecting a resistor between V
SSR. The TRGOUT slew rate is controlled by connecting a resistor between V
and TSR. The larger the
CC
resistor values, the longer the rise and fall times are.
and
SS
is low,
and
CC
The TMS3472A is available in a 20-pin surface-mount package (DW) and is characterized for operation from
–20°C to 45°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.
Specific guidelines for handling devices of this type are contained in the publication
(ESDS) Devices and Assemblies
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
Guidelines for Handling Electrostatic-Discharge-Sensitive
available from Texas Instruments.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
1
TMS3472A
SERIAL DRIVER
SOCS025B – FEBRUARY 1991
functional block diagram
PD
1PC1
1PC2
DLADJ
SRG1IN
SSR
2,3PC1
2,3PC2
POWER DOWN
PLL1
Phase Control
Phase Control
Delay Adjust
TTL/CCD
S1
SR
PLL2,3
Phase Control
Phase Control
Delay Adjust
TTL/CCD
S2
SR
SRG1OUT
SRG2OUT
SRG2,3IN
TRGIN
TSR
SR
SR
TTL/CCD
S3
SRG3OUT
TTL/CCD
T
TRGOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TMS3472A
I/O
DESCRIPTION
Phase-adjust control for SRG2OUT, SRG3OUT
Phase-adjust control for SRG1OUT
Positive suppl
oltage
Negative suppl
oltage
SERIAL DRIVER
SOCS025B – FEBRUARY 1991
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984.
†
3
PD
SSR
DLADJ
1PC1
1PC2
SRG1IN
2,3PC1
2,3PC2
SRG2,3IN
TRGIN
TSR
9
1
18
19
5
7
8
4
6
11
Pwr Dwn
Ser Slew
Ser Delay Adj
Slew
Phase
Phase
CCD Driver
PLL1
TTL/CCD
[S1]
PLL2,3
TTL/CCD
[S2]
TTL/CCD
[S3]
TTL/CCD
[T]
14
15
16
13
SRG1OUT
SRG2OUT
SRG3OUT
TRGOUT
Terminal Functions
TERMINAL
NAME NO.
DLADJ 1 I Delay adjust for all serial-register gates
GND 2 Ground
‡
2,3PC1
‡
2,3PC2
‡
1PC1
‡
1PC2
PD 3 I Power down
SRG1IN 5 I Serial-register gate 2 and 3 in
SRG2,3IN 4 I Serial-register gate 1 in
SRG1OUT 14 O Serial-register gate 1 out
SRG2OUT 15 O Serial-register gate 2 out
SRG3OUT 16 O Serial-register gate 3 out
SSR 9 I Serial-register gate out slew-rate adjust
TRGIN 6 I Transfer gate in
TRGOUT 13 O Transfer gate out
TSR 11 I Transfer gate out slew-rate adjust
§
V
CC
§
V
CC
§
V
SS
§
V
SS
‡
A 270-pF capacitor should be connected between terminals 7 and 8 and between
terminals 18 and 19.
§
All terminals of the same name should be connected together externally.
7 I
8 I
18 I
19 I
12 I
17 I
10 I
20 I
pp
pp
y v
y v
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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