TMS320 x2833x, 2823x System Control and
Interrupts
Reference Guide
Literature Number: SPRUFB0C
September 2007 – Revised May 2009
2 SPRUFB0C – September 2007 – Revised May 2009
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Contents
Preface .............................................................................................................................. 11
1 Flash and OTP Memory Blocks .................................................................................. 15
1.1 Flash and OTP Memory ................................................................................................... 16
1.1.1 Flash Memory ...................................................................................................... 16
1.1.2 OTP Memory ....................................................................................................... 16
1.2 Flash and OTP Power Modes ............................................................................................ 16
1.2.1 Flash and OTP Performance ................................................................................... 18
1.2.2 Flash Pipeline Mode .............................................................................................. 18
1.2.3 Reserved Locations Within Flash and OTP ................................................................... 19
1.2.4 Procedure to Change the Flash Configuration Registers .................................................... 20
1.3 Flash and OTP Registers ................................................................................................. 21
2 Code Security Module (CSM) ..................................................................................... 27
2.1 Functional Description ..................................................................................................... 28
2.2 CSM Impact on Other On-Chip Resources ............................................................................. 30
2.3 Incorporating Code Security in User Applications ..................................................................... 31
2.3.1 Environments That Require Security Unlocking .............................................................. 32
2.3.2 Password Match Flow ........................................................................................... 33
2.3.3 Unsecuring Considerations for Devices With/Without Code Security ...................................... 34
2.4 Do's and Don'ts to Protect Security Logic ............................................................................... 36
2.4.1 Do's ................................................................................................................. 36
2.4.2 Don'ts .............................................................................................................. 36
2.5 CSM Features - Summary ................................................................................................ 36
3 Clocking .................................................................................................................. 37
3.1 Clocking and System Control ............................................................................................. 38
3.2 OSC and PLL Block ........................................................................................................ 45
3.2.1 PLL-Based Clock Module ........................................................................................ 45
3.2.2 Main Oscillator Fail Detection.................................................................................... 46
3.2.3 XCLKOUT Generation ............................................................................................ 48
3.2.4 PLL Control (PLLCR) Register .................................................................................. 49
3.2.5 PLL Control, Status and XCLKOUT Register Descriptions .................................................. 51
3.2.6 External Reference Oscillator Clock Option ................................................................... 52
3.3 Low-Power Modes Block .................................................................................................. 53
3.4 Watchdog Block ............................................................................................................ 55
3.4.1 Servicing The Watchdog Timer .................................................................................. 56
3.4.2 Watchdog Reset or Watchdog Interrupt Mode ................................................................ 56
3.4.3 Watchdog Operation in Low Power Modes .................................................................... 57
3.4.4 Emulation Considerations ........................................................................................ 57
3.4.5 Watchdog Registers .............................................................................................. 58
3.5 32-Bit CPU Timers 0/1/2 .................................................................................................. 60
4 General-Purpose Input/Output (GPIO) ......................................................................... 65
SPRUFB0C – September 2007 – Revised May 2009 Contents 3
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4.1 GPIO Module Overview ................................................................................................... 66
4.2 Configuration Overview .................................................................................................... 71
4.3 Digital General Purpose I/O Control ..................................................................................... 72
4.4 Input Qualification .......................................................................................................... 74
4.4.1 No Synchronization (asynchronous input) ..................................................................... 74
4.4.2 Synchronization to SYSCLKOUT Only ......................................................................... 74
4.4.3 Qualification Using a Sampling Window ....................................................................... 74
4.5 GPIO and Peripheral Multiplexing (MUX) ............................................................................... 78
4.6 Register Bit Definitions .................................................................................................... 83
5 Peripheral Frames ................................................................................................... 109
5.1 Peripheral Frame Registers ............................................................................................. 110
5.2 EALLOW-Protected Registers .......................................................................................... 112
5.3 Device Emulation Registers ............................................................................................. 116
5.4 Write-Followed-by-Read Protection .................................................................................... 118
6 Peripheral Interrupt Expansion (PIE) ......................................................................... 121
6.1 Overview of the PIE Controller .......................................................................................... 122
6.1.1 Interrupt Operation Sequence .................................................................................. 122
6.2 Vector Table Mapping .................................................................................................... 125
6.3 Interrupt Sources.......................................................................................................... 127
6.3.1 Procedure for Handling Multiplexed Interrupts ............................................................... 129
6.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts ............................... 130
6.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU ................................. 131
6.3.4 The PIE Vector Table ........................................................................................... 132
6.4 PIE Configuration Registers ............................................................................................. 139
6.5 PIE Interrupt Registers ................................................................................................... 140
6.5.1 PIE Interrupt Flag Registers .................................................................................... 141
6.5.2 PIE Interrupt Enable Registers ................................................................................. 141
6.5.3 CPU Interrupt Flag Register (IFR) ............................................................................. 142
6.5.4 Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER) ...................... 144
6.6 External Interrupt Control Registers ................................................................................... 148
A Revision History ..................................................................................................... 151
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List of Figures
1-1 Flash Power Mode State Diagram ....................................................................................... 17
1-2 Flash Pipeline ............................................................................................................... 19
1-3 Flash Configuration Access Flow Diagram ............................................................................. 20
1-4 Flash Options Register (FOPT) .......................................................................................... 22
1-5 Flash Power Register (FPWR) ........................................................................................... 22
1-6 Flash Status Register (FSTATUS) ....................................................................................... 23
1-7 Flash Standby Wait Register (FSTDBYWAIT) ......................................................................... 24
1-8 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) .................................................. 24
1-9 Flash Wait-State Register (FBANKWAIT) .............................................................................. 25
1-10 OTP Wait-State Register (FOTPWAIT) ................................................................................. 26
2-1 CSM Status and Control Register (CSMSCR) ......................................................................... 32
2-2 Password Match Flow (PMF) ............................................................................................ 33
3-1 Clock and Reset Domains ................................................................................................ 38
3-2 Peripheral Clock Control 0 Register (PCLKCR0) ...................................................................... 39
3-3 Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 40
3-4 Peripheral Clock Control 3 Register (PCLKCR3) ...................................................................... 43
3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Register ......................................................... 44
3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) ......................................................... 44
3-7 OSC and PLL Block ........................................................................................................ 45
3-8 Oscillator Fail-Detection Logic Diagram ................................................................................. 46
3-9 XCLKOUT Generation ..................................................................................................... 48
3-10 PLLCR Change Procedure Flow Chart .................................................................................. 50
3-11 PLLCR Register Layout ................................................................................................... 51
3-12 PLL Status Register (PLLSTS) ........................................................................................... 51
3-13 Low Power Mode Control 0 Register (LPMCR0) ....................................................................... 54
3-14 Watchdog Module .......................................................................................................... 55
3-15 System Control and Status Register (SCSR) .......................................................................... 58
3-16 Watchdog Counter Register (WDCNTR) ................................................................................ 59
3-17 Watchdog Reset Key Register (WDKEY) ............................................................................... 59
3-18 Watchdog Control Register (WDCR) .................................................................................... 59
3-19 CPU-Timers ................................................................................................................. 60
3-20 CPU-Timer Interrupts Signals and Output Signal ...................................................................... 61
3-21 TIMERxTIM Register (x = 0, 1, 2) ........................................................................................ 62
3-22 TIMERxTIMH Register (x = 0, 1, 2) ...................................................................................... 62
3-23 TIMERxPRD Register (x = 0, 1, 2) ....................................................................................... 62
3-24 TIMERxPRDH Register (x = 0, 1, 2) ..................................................................................... 62
3-25 TIMERxTCR Register (x = 0, 1, 2) ....................................................................................... 63
3-26 TIMERxTPR Register (x = 0, 1, 2) ....................................................................................... 64
3-27 TIMERxTPRH Register (x = 0, 1, 2) .................................................................................... 64
4-1 GPIO0 to GPIO27 Multiplexing Diagram ................................................................................ 66
4-2 GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 67
4-3 GPIO32, GPIO33 Multiplexing Diagram ................................................................................. 68
4-4 GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 69
4-5 GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification) ................................ 70
4-6 Input Qualification Using a Sampling Window .......................................................................... 74
4-7 Input Qualifier Clock Cycles .............................................................................................. 77
4-8 GPIO Port A MUX 1 (GPAMUX1) Register ............................................................................. 83
4-9 GPIO Port A MUX 2 (GPAMUX2) Register ............................................................................. 85
4-10 GPIO Port B MUX 1 (GPBMUX1) Register ............................................................................. 87
4-11 GPIO Port B MUX 2 (GPBMUX2) Register ............................................................................. 89
4-12 GPIO Port C MUX 1 (GPCMUX1) Register ............................................................................. 91
4-13 GPIO Port C MUX 2 (GPCMUX2) Register ............................................................................. 92
SPRUFB0C – September 2007 – Revised May 2009 List of Figures 5
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4-14 GPIO Port A Qualification Control (GPACTRL) Register ............................................................ 94
4-15 GPIO Port B Qualification Control (GPBCTRL) Register ............................................................ 95
4-16 GPIO Port A Qualification Select 1 (GPAQSEL1) Register........................................................... 96
4-17 GPIO Port A Qualification Select 2 (GPAQSEL2) Register........................................................... 96
4-18 GPIO Port B Qualification Select 1 (GPBQSEL1) Register........................................................... 97
4-19 GPIO Port B Qualification Select 2 (GPBQSEL2) Register........................................................... 97
4-20 GPIO Port A Direction (GPADIR) Register ............................................................................. 98
4-21 GPIO Port B Direction (GPBDIR) Register ............................................................................. 98
4-22 GPIO Port C Direction (GPCDIR) Register ............................................................................ 99
4-23 GPIO Port A Pullup Disable (GPAPUD) Registers .................................................................. 100
4-24 GPIO Port B Pullup Disable (GPBPUD) Registers .................................................................. 100
4-25 GPIO Port C Pullup Disable (GPCPUD) Registers .................................................................. 101
4-26 GPIO Port A Data (GPADAT) Register ............................................................................... 101
4-27 GPIO Port B Data (GPBDAT) Register ............................................................................... 102
4-28 GPIO Port C Data (GPCDAT) Register ............................................................................... 103
4-29 GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers ....................... 104
4-30 GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers ....................... 105
4-31 GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers ...................... 106
4-32 GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers ............................. 107
4-33 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register ................................................ 108
5-1 Device Configuration (DEVICECNF) Register ........................................................................ 116
5-2 Part ID Register ........................................................................................................... 117
5-3 CLASSID Register ........................................................................................................ 117
5-4 REVID Register ........................................................................................................... 117
6-1 Overview: Multiplexing of Interrupts Using the PIE Block ........................................................... 122
6-2 Typical PIE/CPU Interrupt Response - INTx.y ........................................................................ 124
6-3 Reset Flow Diagram ...................................................................................................... 126
6-4 PIE Interrupt Sources and External Interrupts XINT1/XINT2 ....................................................... 127
6-5 PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) ................................................... 128
6-6 Multiplexed Interrupt Request Flow Diagram ......................................................................... 131
6-7 PIECTRL Register (Address CE0) ..................................................................................... 140
6-8 PIE Interrupt Acknowledge Register (PIEACK) Register (Address CE1) ......................................... 140
6-9 PIEIFRx Register (x = 1 to 12) .......................................................................................... 141
6-10 PIEIERx Register (x = 1 to 12) .......................................................................................... 141
6-11 Interrupt Flag Register (IFR) — CPU Register ....................................................................... 143
6-12 Interrupt Enable Register (IER) — CPU Register .................................................................... 145
6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register ..................................................... 146
6-14 External Interrupt n Control Register (XINT nCR) .................................................................... 148
6-15 External NMI Interrupt Control Register (XNMICR) — Address 7077h ............................................ 148
6-16 External Interrupt 1 Counter (XINT1CTR) (Address 7078h) ........................................................ 149
6-17 External Interrupt 2 Counter (XINT2CTR) (Address 7079h) ........................................................ 149
6-18 External NMI Interrupt Counter (XNMICTR) (Address 707Fh) ..................................................... 150
List of Figures6 SPRUFB0C – September 2007 – Revised May 2009
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List of Tables
1-1 Flash/OTP Configuration Registers ...................................................................................... 21
1-2 Flash Options Register (FOPT) Field Descriptions .................................................................... 22
1-3 Flash Power Register (FPWR) Field Descriptions ..................................................................... 22
1-4 Flash Status Register (FSTATUS) Field Descriptions ................................................................. 23
1-5 Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 24
1-6 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions ............................. 24
1-7 Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 25
1-8 OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 26
2-1 Security Levels ............................................................................................................. 28
2-2 Resources Affected by the CSM ......................................................................................... 30
2-3 Resources Not Affected by the CSM .................................................................................... 30
2-4 Code Security Module (CSM) Registers ................................................................................ 31
2-5 CSM Status and Control Register (CSMSCR) Field Descriptions ................................................... 32
3-1 PLL, Clocking, Watchdog, and Low-Power Mode Registers ........................................................ 39
3-2 Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions ................................................ 39
3-3 Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 41
3-4 Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions ................................................ 43
3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions .............................................. 44
3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions ................................... 44
3-7 Possible PLL Configuration Modes ...................................................................................... 46
3-8 PLLCR Bit Descriptions ................................................................................................... 51
3-9 PLL Status Register (PLLSTS) Field Descriptions ..................................................................... 51
3-10 Low-Power Mode Summary .............................................................................................. 53
3-11 Low Power Modes ......................................................................................................... 53
3-12 Low Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 54
3-13 Example Watchdog Key Sequences ..................................................................................... 56
3-14 System Control and Status Register (SCSR) Field Descriptions .................................................... 58
3-15 Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 59
3-16 Watchdog Reset Key Register (WDKEY) Field Descriptions ......................................................... 59
3-17 Watchdog Control Register (WDCR) Field Descriptions .............................................................. 59
3-18 CPU-Timers 0, 1, 2 Configuration and Control Registers ............................................................. 61
3-19 TIMERxTIM Register Field Descriptions ................................................................................ 62
3-20 TIMERxTIMH Register Field Descriptions .............................................................................. 62
3-21 TIMERxPRD Register Field Descriptions ............................................................................... 62
3-22 TIMERxPRDH Register Field Descriptions ............................................................................. 63
3-23 TIMERxTCR Register Field Descriptions ............................................................................... 63
3-24 TIMERxTPR Register Field Descriptions ............................................................................... 64
3-25 TIMERxTPRH Register Field Descriptions.............................................................................. 64
4-1 GPIO Control Registers ................................................................................................... 71
4-2 GPIO Interrupt and Low Power Mode Select Registers ............................................................... 71
4-3 GPIO Data Registers ...................................................................................................... 73
4-4 Sampling Period ............................................................................................................ 75
4-5 Sampling Frequency ....................................................................................................... 75
4-6 Case 1: Three-Sample Sampling Window Width ...................................................................... 76
4-7 Case 2: Six-Sample Sampling Window Width .......................................................................... 76
4-8 Default State of Peripheral Input ......................................................................................... 79
4-9 GPIOA MUX ................................................................................................................ 80
4-10 GPIOB MUX ................................................................................................................ 81
4-11 GPIOC MUX ................................................................................................................ 82
SPRUFB0C – September 2007 – Revised May 2009 List of Tables 7
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4-12 GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions .............................................. 83
4-13 GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ....................................................... 85
4-14 GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ....................................................... 87
4-15 GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions ....................................................... 89
4-16 GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions ...................................................... 91
4-17 GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions ...................................................... 92
4-18 GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions ....................................... 94
4-19 GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions ....................................... 95
4-20 GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions .................................... 96
4-21 GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions .................................... 96
4-22 GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions .................................... 97
4-23 GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions .................................... 97
4-24 GPIO Port A Direction (GPADIR) Register Field Descriptions ....................................................... 98
4-25 GPIO Port B Direction (GPBDIR) Register Field Descriptions ....................................................... 99
4-26 GPIO Port C Direction (GPCDIR) Register Field Descriptions ....................................................... 99
4-27 GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 100
4-28 GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 100
4-29 GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions .................................... 101
4-30 GPIO Port A Data (GPADAT) Register Field Descriptions .......................................................... 102
4-31 GPIO Port B Data (GPBDAT) Register Field Descriptions .......................................................... 102
4-32 GPIO Port C Data (GPCDAT) Register Field Descriptions ......................................................... 103
4-33 GPIO Port A Set (GPASET) Register Field Descriptions ............................................................ 104
4-34 GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 104
4-35 GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 104
4-36 GPIO Port B Set (GPBSET) Register Field Descriptions ............................................................ 105
4-37 GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 105
4-38 GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 105
4-39 GPIO Port C Set (GPCSET) Register Field Descriptions ........................................................... 106
4-40 GPIO Port C Clear (GPCCLEAR) Register Field Descriptions ..................................................... 106
4-41 GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions ................................................. 106
4-42 GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions ..................................... 107
4-43 XINT1/XINT2 Interrupt Select and Configuration Registers ......................................................... 107
4-44 GPIO XINT3 - XINT7 Interrupt Select (GPIOXINTnSEL) Register Field Descriptions .......................... 107
4-45 XINT3 - XINT7 Interrupt Select and Configuration Registers ....................................................... 107
4-46 GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions ...................................... 108
4-47 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions .......................... 108
5-1 Peripheral Frame 0 Registers .......................................................................................... 110
5-2 Peripheral Frame 1 Registers ........................................................................................... 110
5-3 Peripheral Frame 2 Registers ........................................................................................... 111
5-4 Peripheral Frame 3 Registers ........................................................................................... 111
5-5 Access to EALLOW-Protected Registers .............................................................................. 112
5-6 EALLOW-Protected Device Emulation Registers..................................................................... 112
5-7 EALLOW-Protected Flash/OTP Configuration Registers ............................................................ 112
5-8 EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 113
5-9 EALLOW-Protected PIE Vector Table ................................................................................. 113
5-10 EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 114
5-11 EALLOW-Protected GPIO MUX Registers ........................................................................... 114
5-12 EALLOW-Protected eCAN Registers .................................................................................. 115
5-13 EALLOW-Protected ePWM1 - ePWM 6 Registers .................................................................... 115
5-14 XINTF Registers ......................................................................................................... 115
5-15 Device Emulation Registers ............................................................................................. 116
8 List of Tables SPRUFB0C – September 2007 – Revised May 2009
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5-16 DEVICECNF Register Field Descriptions.............................................................................. 116
5-17 PARTID Register Field Descriptions ................................................................................... 117
5-18 CLASSID Register Description .......................................................................................... 117
5-19 REVID Register Field Descriptions ..................................................................................... 118
5-20 PROTSTART and PROTRANGE Registers........................................................................... 118
5-21 PROTSTART Valid Values ............................................................................................. 118
5-22 PROTRANGE Valid Values ............................................................................................. 119
6-1 Enabling Interrupt ......................................................................................................... 124
6-2 Interrupt Vector Table Mapping ........................................................................................ 125
6-3 Vector Table Mapping After Reset Operation ........................................................................ 125
6-4 PIE MUXed Peripheral Interrupt Vector Table ........................................................................ 133
6-5 PIE Vector Table .......................................................................................................... 134
6-6 PIE Configuration and Control Registers .............................................................................. 139
6-7 PIECTRL Register Address Field Descriptions ....................................................................... 140
6-8 PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions ................................................. 140
6-9 PIEIFRx Register Field Descriptions ................................................................................... 141
6-10 PIEIERx Register (x = 1 to 12) Field Descriptions ................................................................... 142
6-11 Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 143
6-12 Interrupt Enable Register (IER) — CPU Register Field Descriptions .............................................. 145
6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 146
6-14 External Interrupt n Control Register (XINT nCR) Field Descriptions .............................................. 148
6-15 External NMI Interrupt Control Register (XNMICR) Field Descriptions ............................................ 148
6-16 XNMICR Register Settings and Interrupt Sources ................................................................... 149
6-17 External Interrupt 1 Counter (XINT1CTR) Field Descriptions ....................................................... 149
6-18 External Interrupt 2 Counter (XINT2CTR) Field Descriptions ....................................................... 150
6-19 External NMI Interrupt Counter (XNMICTR) Field Descriptions .................................................... 150
A-1 Changes Made in This Revision ........................................................................................ 151
SPRUFB0C – September 2007 – Revised May 2009 List of Tables 9
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List of Tables10 SPRUFB0C – September 2007 – Revised May 2009
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About This Manual
Notational Conventions
Preface
SPRUFB0C – September 2007 – Revised May 2009
Read This First
This reference guide is applicable for the systems control and interrupts found on the
TMS320F2833x/TMS320F2823x Delfino digital signal controllers (DSCs).
This guide describes how various 2833x/2823x DSC system controls and interrupts work. It includes
information on the:
• Flash and one-time programmable (OTP) memories
• Code security module (CSM), which is a security feature incorporated in TMS320C28x™ devices.
• Clocking mechanisms including the oscillator, PLL, XCLKOUT, watchdog module, and the low-power
modes. In addition, the 32-bit CPU-Timers are also described.
• GPIO multiplexing (MUX) registers used to select the operation of shared pins on the device.
• Accessing the peripheral frames to write to and read from various peripheral registers on the device.
• Interrupt sources both external and the peripheral interrupt expansion (PIE) block that multiplexes
numerous interrupt sources into a smaller set of interrupt inputs.
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following books describe the 2833x and related support tools that are available on the TI website:
Data Manual and Errata—
SPRS439— TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234,
TMS320F28232 Digital Signal Controllers (DSCs) Data Manual contains the pinout, signal
descriptions, as well as electrical and timing specifications for the F2833x/2823x devices.
SPRZ272— TMS320F28335, F28334, F28332, TMS320F28235, F28234, F28232 Digital Signal
Controllers (DSCs) Silicon Errata describes the advisories and usage notes for different versions of
silicon.
CPU User's Guides—
SPRU430 — TMS320C28x CPU and Instruction Set Reference Guide describes the central processing
unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal
processors (DSPs). It also describes emulation features available on these DSPs.
SPRUEO2 — TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes the
floating-point unit and includes the instructions for the FPU.
Peripheral Guides—
SPRUFB0C – September 2007 – Revised May 2009 Read This First 11
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Related Documentation From Texas Instruments
SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRUFB0 — TMS320x2833x, 2823x System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 2833x and 2823x digital signal controllers
(DSCs).
SPRU812 — TMS320x2833x, 2823x Analog-to-Digital Converter (ADC) Reference Guide describes
how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
SPRU949 — TMS320x2833x, 2823x DSC External Interface (XINTF) Reference Guide describes the
XINTF, which is a nonmultiplexed asynchronous bus, as it is used on the 2833x and 2823x devices.
SPRU963 — TMS320x2833x, 2823x Boot ROM Reference Guide describes the purpose and features of
the bootloader (factory-programmed boot-loading software) and provides examples of code. It also
describes other contents of the device on-chip boot ROM and identifies where all of the information
is located within that memory.
SPRUFB7 — TMS320x2833x, 2823x Multichannel Buffered Serial Port (McBSP) Reference Guide
describes the McBSP available on the 2833x and 2823x devices. The McBSPs allow direct
interface between a DSP and other devices in a system.
SPRUFB8 — TMS320x2833x, 2823x Direct Memory Access (DMA) Module Reference Guide
describes the DMA on the 2833x and 2823x devices.
SPRUG04 — TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) Module Reference
Guide describes the main areas of the enhanced pulse width modulator that include digital motor
control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of
power conversion.
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SPRUG02 — TMS320x2833x, 2823x High-Resolution Pulse Width Modulator (HRPWM) Reference
Guide describes the operation of the high-resolution extension to the pulse width modulator
(HRPWM).
SPRUFG4 — TMS320x2833x, 2823x Enhanced Capture (eCAP) Module Reference Guide describes
the enhanced capture module. It includes the module description and registers.
SPRUG05 — TMS320x2833x, 2823x Enhanced Quadrature Encoder Pulse (eQEP) Module Reference
Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental
encoder to get position, direction, and speed information from a rotating machine in
high-performance motion and position control systems. It includes the module description and
registers.
SPRUEU1 — TMS320x2833x, 2823x Enhanced Controller Area Network (eCAN) Reference Guide
describes the eCAN that uses established protocol to communicate serially with other controllers in
electrically noisy environments.
SPRUFZ5 — TMS320x2833x, 2823x Serial Communications Interface (SCI) Reference Guide
describes the SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The
SCI modules support digital communications between the CPU and other asynchronous peripherals
that use the standard non-return-to-zero (NRZ) format.
SPRUEU3 — TMS320x2833x, 2823x DSC Serial Peripheral Interface (SPI) Reference Guide describes
the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed
bit-transfer rate.
SPRUG03 — TMS320x2833x, 2823x Inter-Integrated Circuit (I2C) Module Reference Guide describes
the features and operation of the inter-integrated circuit (I2C) module.
Tools Guides—
12 Read This First SPRUFB0C – September 2007 – Revised May 2009
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Related Documentation From Texas Instruments
SPRU513 — TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly
language tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514 — TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the
TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and
produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction
set of the C28x™ core.
SPRU625 — TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS.
Trademarks
TMS320C28x, C28x, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
SPRUFB0C – September 2007 – Revised May 2009 Read This First 13
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Chapter 1
SPRUFB0C – September 2007 – Revised May 2009
Flash and OTP Memory Blocks
This chapter describes the proper sequence to configure the wait states and operating mode of flash and
one-time programmable (OTP) memories. It also includes information on flash and OTP power modes and
how to improve flash performance by enabling the flash pipeline mode.
Topic .................................................................................................. Page
1.1 Flash and OTP Memory .............................................................. 16
1.2 Flash and OTP Power Modes ...................................................... 16
1.3 Flash and OTP Registers ........................................................... 21
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Flash and OTP Memory
1.1 Flash and OTP Memory
This section describes how to configure flash and one-time programmable (OTP) memory.
1.1.1 Flash Memory
The on-chip flash is uniformly mapped in both program and data memory space. This flash memory is
always enabled and features:
• Multiple sectors
The minimum amount of flash memory that can be erased is a sector. Having multiple sectors provides
the option of leaving some sectors programmed and only erasing specific sectors.
• Code security
The flash is protected by the Code Security Module (CSM). By programming a password into the flash,
the user can prevent access to the flash by unauthorized persons. See Chapter 2 for information in
using the Code Security Module.
• Low power modes
To save power when the flash is not in use, two levels of low power modes are available. See
Section 1.2 for more information on the available flash power modes.
• Configurable wait states
Configurable wait states can be adjusted based on CPU frequency to give the best performance for a
given execution speed.
• Enhanced performance
A flash pipeline mode is provided to improve performance of linear code execution.
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1.1.2 OTP Memory
The 1K x 16 block of one-time programmable (OTP) memory is uniformly mapped in both program and
data memory space. Thus, the OTP can be used to program data or code. This block, unlike flash, can be
programmed only one time and cannot be erased.
1.2 Flash and OTP Power Modes
The following operating states apply to the flash and OTP memory:
• Reset or Sleep State
This is the state after a device reset. In this state, the bank and pump are in a sleep state (lowest
power). When the flash is in the sleep state, a CPU data read or opcode fetch to the flash or OTP
memory map area will automatically initiate a change in power modes to the standby state and then to
the active state. During this transition time to the active state, the CPU will automatically be stalled.
Once the transition to the active state is completed, the CPU access will complete as normal.
• Standby State
In this state, the bank and pump are in standby power mode state. This state uses more power then
the sleep state, but takes a shorter time to transition to the active or read state. When the flash is in
the standby state, a CPU data read or opcode fetch to the flash or OTP memory map area will
automatically initiate a change in power modes to the active state. During this transition time to the
active state, the CPU will automatically be stalled. Once the flash/OTP has reached the active state,
the CPU access will complete as normal.
• Active or Read State
In this state, the bank and pump are in active power mode state (highest power). The CPU read or
fetch access wait states to the flash/OTP memory map area is controlled by the FBANKWAIT and
FOTPWAIT registers. A prefetch mechanism called flash pipeline can also be enabled to improve fetch
performance for linear code execution.
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Active
state
state
Standby
state
Sleep
Delay
FACTIVEWAIT
cycles
Delay
FSTDBYWAIT
cycles
FSTDBYWAIT
cycles
FACTIVEWAIT
Delay
cycles
Delay
Highest
power
Lowest power
Longest
Wake up time
PWR=0,1
PWR=0,0
PWR=0,0
PWR=1,1
or access to
the Flash/OTP
PWR=0,1
PWR=1,1
or access to
the Flash/OTP
Reset
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Note: During the boot process, the Boot ROM performs a dummy read of the Code Security
Module (CSM) password locations located in the flash. This read is performed to unlock a
new or erased device that has no password stored in it so that flash programming or loading
of code into CSM protected SARAM can be performed. On devices with a password stored,
this read has no affect and the CSM remains locked (see Chapter 2 for information on the
CSM). One effect of this read is that the flash will transition from the sleep (reset) state to the
active state.
Flash and OTP Power Modes
The flash/OTP bank and pump are always in the same power mode. See Figure 1-1 for a graphic
depiction of the available power states. You can change the current flash/OTP memory power state as
follows:
• To move to a lower power state
Change the PWR mode bits from a higher power mode to a lower power mode. This change
instantaneously moves the flash/OTP bank to the lower power state. This register should be accessed
only by code running outside the flash/OTP memory.
• To move to a higher power state
To move from a lower power state to a higher power state, there are two options.
1. Change the FPWR register from a lower state to a higher state. This access brings the flash/OTP
memory to the higher state.
2. Access the flash or OTP memory by a read access or program opcode fetch access. This access
automatically brings the flash/OTP memory to the active state.
There is a delay when moving from a lower power state to a higher one. See Figure 1-1 . This delay is
required to allow the flash to stabilize at the higher power mode. If any access to the flash/OTP memory
occurs during this delay the CPU automatically stalls until the delay is complete.
Figure 1-1. Flash Power Mode State Diagram
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Flash and OTP Power Modes
The duration of the delay is determined by the FSTDBYWAIT and FACTIVEWAIT registers. Moving from
the sleep state to a standby state is delayed by a count determined by the FSTDBYWAIT register. Moving
from the standby state to the active state is delayed by a count determined by the FACTIVEWAIT register.
Moving from the sleep mode (lowest power) to the active mode (highest power) is delayed by
FSTDBYWAIT + FACTIVEWAIT. These registers should be left in their default state.
1.2.1 Flash and OTP Performance
CPU read or data fetch operations to the flash/OTP can take one of the following forms:
• 32-bit instruction fetch
• 16-bit or 32-bit data space read
• 16-bit program space read
Once flash is in the active power state, then a read or fetch access to the bank memory map area can be
classified as a flash access or an OTP access.
The main flash array is organized into rows and columns. The rows contain 2048 bits of information.
Accesses to flash and OTP are one of three types:
1. Flash Memory Random Access
The first access to a 2048 bit row is considered a random access.
2. Flash Memory Paged Access
While the first access to a row is considered a random access, subsequent accesses within the same
row are termed paged accesses.
The number of wait states for both a random and a paged access can be configured by programming
the FBANKWAIT register. The number of wait states used by a random access is controlled by the
RANDWAIT bits and the number of wait states used by a paged access is controlled by the
PAGEWAIT bits. The FBANKWAIT register defaults to a worst-case wait state count and, thus, needs
to be initialized for the appropriate number of wait states to improve performance based on the CPU
clock rate and the access time of the flash. The flash supports 0-wait accesses when the PAGEWAIT
bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access
time. To determine the random and paged access time requirements, refer to the Data Manual for your
particular device.
3. OTP Access
Read or fetch accesses to the OTP are controlled by the OTPWAIT bits in the FOTPWAIT register.
Accesses to the OTP take longer than the flash and there is no paged mode. To determine OTP
access time requirements, see the data manual for your particular device.
Some other points to keep in mind when working with flash:
• CPU writes to the flash or OTP memory map area are ignored. They complete in a single cycle.
• When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
• Reads of the CSM password locations are hardwired for 16 wait-states. The PAGEWAIT and
RANDOMWAIT bits have no effect on these locations. See Chapter 2 for more information on the
CSM.
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1.2.2 Flash Pipeline Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash pipeline mode has been
implemented. The flash pipeline feature is disabled by default. Setting the ENPIPE bit in the FOPT register
enables this mode. The flash pipeline mode is independent of the CPU pipeline.
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Flash Pipeline
CPU
32 bits
M
U
X
Data read from either program or data memory
Instruction Fetch (64 bits)
Flash or OTP
Read
16 bits
Flash and OTP
Instruction buffer
64-bit
Buffer
64-bit
Buffer
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Flash and OTP Power Modes
An instruction fetch from the flash or OTP reads out 64 bits per access. The starting address of the access
from flash is automatically aligned to a 64-bit boundary such that the instruction location is within the 64
bits to be fetched. With flash pipeline mode enabled (see Figure 1-2 ), the 64 bits read from the instruction
fetch are stored in a 64-bit wide by 2-level deep instruction pre-fetch buffer. The contents of this pre-fetch
buffer are then sent to the CPU for processing as required.
Up to two 32-bit instructions or up to four 16-bit instructions can reside within a single 64-bit access. The
majority of C28x instructions are 16 bits, so for every 64-bit instruction fetch from the flash bank it is likely
that there are up to four instructions in the pre-fetch buffer ready to process through the CPU. During the
time it takes to process these instructions, the flash pipeline automatically initiates another access to the
flash bank to pre-fetch the next 64 bits. In this manner, the flash pipeline mode works in the background to
keep the instruction pre-fetch buffers as full as possible. Using this technique, the overall efficiency of
sequential code execution from flash or OTP is improved significantly.
Figure 1-2. Flash Pipeline
The flash pipeline pre-fetch is aborted only on a PC discontinuity caused by executing an instruction such
as a branch, BANZ, call, or loop. When this occurs, the pre-fetch is aborted and the contents of the
pre-fetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the flash or OTP, the pre-fetch aborts and then resumes at the
destination address.
2. If the destination address is outside of the flash and OTP, the pre-fetch is aborted and begins again
only when a branch is made back into the flash or OTP. The flash pipeline pre-fetch mechanism only
applies to instruction fetches from program space. Data reads from data memory and from program
memory do not utilize the pre-fetch buffer capability and thus bypass the pre-fetch buffer. For example,
instructions such as MAC, DMAC, and PREAD read a data value from program memory. When this
read happens, the pre-fetch buffer is bypassed but the buffer is not flushed. If an instruction pre-fetch
is already in progress when a data read operation is initiated, then the data read will be stalled until the
pre-fetch completes.
1.2.3 Reserved Locations Within Flash and OTP
When allocating code and data to flash and OTP memory, keep the following in mind:
1. Address locations 0x33 FFF6 and 0x33 FFF7 are reserved for an "entry into flash" branch instruction.
When the "boot to flash" boot option is used, the boot ROM will jump to address 0x33 FFF6. If you
program a branch instruction here that will then re-direct code execution to the entry point of the
application.
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Wait eight cycles to let the write instructions
propagate through the CPU pipeline. This
must be done before the return-from-function
call is made.
Write instructions to FOPT, FBANKWAIT,
etc.
The function that changes the configuration
cannot execute from the Flash or OTP.
Branch or call is required to properly flush the
CPU pipeline before the configuration
change.
Wait 8 cycles (8 NOPs)
Return to calling function
Continue execution
SARAM, Flash,
or OTP
Flash configuration
change
Do not execute from
Flash/OTP
SARAM
Begin Flash configuration
change
SARAM, Flash, OTP
Branch or call to
configuration code
Flash and OTP Power Modes
2. For code security operation, all addresses between 0x33 FF80 and 0x33 FFF5 cannot be used for
program code or data, but must be programmed to 0x0000 when the Code Security Password is
programmed. If security is not a concern, addresses 0x33 FF80 through 0x33 FFF5 may be used for
code or data. See Chapter 2 for information in using the Code Security Module.
3. Addresses from 0x33 FFF0 to 0x33 FFF5 are reserved for data variables and should not contain
program code.
1.2.4 Procedure to Change the Flash Configuration Registers
During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions
still in the CPU pipeline, data reads, and instruction pre-fetch operations. To be sure that no access takes
place during the configuration change, you should follow the procedure shown in Figure 1-3 for any code
that modifies the FOPT, FPWR, FBANKWAIT, or FOTPWAIT registers.
Figure 1-3. Flash Configuration Access Flow Diagram
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1.3 Flash and OTP Registers
The flash and OTP memory can be configured by the registers shown in Table 1-1 . The configuration
registers are all EALLOW protected. The bit descriptions are in Figure 1-4 through Figure 1-10 .
Name
FOPT 0x0A80 1 Flash Option Register Figure 1-4
Reserved 0x0A81 1 Reserved
FPWR 0x0A82 1 Flash Power Modes Register Figure 1-5
FSTATUS 0x0A83 1 Status Register Figure 1-6
FSTDBYWAIT
FACTIVEWAIT
FBANKWAIT 0x0A86 1 Flash Read Access Wait State Register Figure 1-9
FOTPWAIT 0x0A87 1 OTP Read Access Wait State Register Figure 1-10
(1)
These registers are EALLOW protected. See Section 5.2 for information.
(2)
These registers are protected by the Code Security Module (CSM). See Chapter 2 for more information.
(3)
These registers should be left in their default state.
Note: The flash configuration registers should not be written to by code that is running from OTP or
Table 1-1. Flash/OTP Configuration Registers
(1) (2)
(3)
flash memory or while an access to flash or OTP may be in progress. All register accesses
to the flash registers should be made from code executing outside of flash/OTP memory and
an access should not be attempted until all activity on the flash/OTP has completed. No
hardware is included to protect against this.
To summarize, you can read the flash registers from code executing in flash/OTP; however,
do not write to the registers.
Address Size (x16) Description Bit Description
0x0A84 1 Flash Sleep To Standby Wait Register Figure 1-7
(3)
0x0A85 1 Flash Standby To Active Wait Register Figure 1-8
Flash and OTP Registers
CPU write access to the flash configuration registers can be enabled only by executing the EALLOW
instruction. Write access is disabled when the EDIS instruction is executed. This protects the registers
from spurious accesses. Read access is always available. The registers can be accessed through the
JTAG port without the need to execute EALLOW. See Section 5.2 for information on EALLOW protection.
These registers support both 16-bit and 32-bit accesses.
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Flash and OTP Registers
Figure 1-4. Flash Options Register (FOPT)
15 1 0
Reserved ENPIPE
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-2. Flash Options Register (FOPT) Field Descriptions
Bit Field Value Description
15-1 Reserved
0 ENPIPE Enable Flash Pipeline Mode Bit. Flash pipeline mode is active when this bit is set. The pipeline
mode improves performance of instruction fetches by pre-fetching instructions. See Section 1.2.2
for more information.
When pipeline mode is enabled, the flash wait states (paged and random) must be greater than
zero.
On flash devices, ENPIPE affects fetches from flash and OTP.
0 Flash Pipeline mode is not active. (default)
1 Flash Pipeline mode is active.
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(3)
When writing to this register, follow the procedure described in Section 1.2.4 .
(1) (2) (3)
Figure 1-5. Flash Power Register (FPWR)
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15 2 1 0
Reserved PWR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-3. Flash Power Register (FPWR) Field Descriptions
Bit Field Value Description
15-2 Reserved
1-0 PWR Flash Power Mode Bits. Writing to these bits changes the current power mode of the flash bank
and pump. See section Section 1.2 for more information on changing the flash bank power mode.
00 Pump and bank sleep (lowest power)
01 Pump and bank standby
10 Reserved (no effect)
11 Pump and bank active (highest power)
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(1) (2)
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Flash and OTP Registers
Figure 1-6. Flash Status Register (FSTATUS)
15 9 8
Reserved 3VSTAT
R-0 R/W1C-0
7 4 3 2 1 0
Reserved ACTIVEWAITS STDBYWAITS PWRS
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; - n = value after reset
Table 1-4. Flash Status Register (FSTATUS) Field Descriptions
Bit Field Value Description
15-9 Reserved Reserved
8 3VSTAT Flash Voltage (V
the pump module went to a high level. This signal indicates that the flash 3.3-V supply went out of
) Status Latch Bit. When set, this bit indicates that the 3VSTAT signal from
DD3VFL
the allowable range.
0 Writes of 0 are ignored.
1 When this bit reads 1, it indicates that the flash 3.3-V supply went out of the allowable range.
Clear this bit by writing a 1.
7-4 Reserved Reserved
3 ACTIVEWAITS Bank and Pump Standby To Active Wait Counter Status Bit. This bit indicates whether the
respective wait counter is timing out an access.
0 The counter is not counting.
1 The counter is counting.
2 STDBYWAITS Bank and Pump Sleep To Standby Wait Counter Status Bit. This bit indicates whether the
respective wait counter is timing out an access.
0 The counter is not counting.
1 The counter is counting.
1-0 PWRS Power Modes Status Bits. These bits indicate which power mode the flash/OTP is currently in.
The PWRS bits are set to the new power mode only after the appropriate timing delays have
expired.
00 Pump and bank in sleep mode (lowest power)
01 Pump and bank in standby mode
10 Reserved
11 Pump and bank active and in read mode (highest power)
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(1) (2)
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Flash and OTP Registers
Figure 1-7. Flash Standby Wait Register (FSTDBYWAIT)
15 9 8 0
Reserved STDBYWAIT
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions
Bit Field Value Description
15-9 Reserved 0 Reserved
8-0 STDBYWAIT This register should be left in its default state.
Bank and Pump Sleep To Standby Wait Count.
111111111 511 SYSCLKOUT cycles (default)
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(1) (2)
Figure 1-8. Flash Standby to Active Wait Counter Register (FACTIVEWAIT)
7 9 8 0
Reserved ACTIVEWAIT
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
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Table 1-6. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions
Bits Field Value Description
15-9 Reserved 0 Reserved
8-0 ACTIVEWAIT This register should be left in its default state.
Bank and Pump Standby To Active Wait Count:
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
111111111 511 SYSCLKOUT cycles (default)
(1) (2)
Flash and OTP Memory Blocks24 SPRUFB0C – September 2007 – Revised May 2009
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Flash and OTP Registers
Figure 1-9. Flash Wait-State Register (FBANKWAIT)
15 12 11 8 7 4 3 0
Reserved PAGEWAIT Reserved RANDWAIT
R-0 R/W-1 R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions
Bits Field Value Description
15-12 Reserved Reserved
11-8 PAGEWAIT Flash Paged Read Wait States. These register bits specify the number of wait states for a paged
read operation in CPU clock cycles (0..15 SYSCLKOUT cycles) to the flash bank. See Section 1.2.1
for more information.
See the device-specific data manual for the minimum time required for a PAGED flash access.
You must set RANDWAIT to a value greater than or equal to the PAGEWAIT setting. No hardware is
provided to detect a PAGEWAIT value that is greater then RANDWAIT.
0000 Illegal value. PAGEWAIT must be set greater then 0.
0001 One wait state per paged flash access or a total of two SYSCLKOUT cycles per access.
0010 Two wait states per paged flash access or a total of three SYSCLKOUT cycles per access.
0011 Three wait states per paged flash access or a total of four SYSCLKOUT cycles per access.
. . . . . .
1111 15 wait states per paged flash access or a total of 16 SYSCLKOUT cycles per access. (default)
7-4 Reserved Reserved
3-0 RANDWAIT Flash Random Read Wait States. These register bits specify the number of wait states for a random
read operation in CPU clock cycles (1..15 SYSCLKOUT cycles) to the flash bank. See Section 1.2.1
for more information.
See the device-specific data manual for the minimum time required for a RANDOM flash access.
RANDWAIT must be set greater than 0. That is, at least 1 random wait state must be used. In
addition, you must set RANDWAIT to a value greater than or equal to the PAGEWAIT setting. The
device will not detect and correct a PAGEWAIT value that is greater then RANDWAIT.
0000 Illegal value. RANDWAIT must be set greater then 0.
0001 One wait state per random flash access or a total of two SYSCLKOUT cycles per access.
0010 Two wait states per random flash access or a total of three SYSCLKOUT cycles per access.
0011 Three wait states per random flash access or a total of four SYSCLKOUT cycles per access.
. . . . . .
1111 15 wait states per random flash access or a total of 16 SYSCLKOUT cycles per access. (default)
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(3)
When writing to this register, follow the procedure described in Section 1.2.4 .
(1) (2) (3)
SPRUFB0C – September 2007 – Revised May 2009 Flash and OTP Memory Blocks 25
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Flash and OTP Registers
Figure 1-10. OTP Wait-State Register (FOTPWAIT)
15 5 4 0
Reserved OTPWAIT
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions
Bit(s) Field Value Description
15-5 Reserved 0 Reserved
4-0 OTPWAIT OTP Read Wait States. These register bits specify the number of wait states for a read operation in
CPU clock cycles (1..31 SYSCLKOUT cycles) to the OTP. See CPU Read Or Fetch Access From
flash/OTP section for details. There is no PAGE mode in the OTP.
OTPWAIT must be set greater than 0. That is, a minimum of 1 wait state must be used. See the
device-specific data manual for the minimum time required for an OTP access.
00000 Illegal value. OTPWAIT must be set to 1 or greater.
00001 One wait state will be used each OTP access for a total of two SYSCLKOUT cycles per access.
00010 Two wait states will be used for each OTP access for a total of three SYSCLKOUT cycles per access.
00011 Three wait states will be used for each OTP access for a total of four SYSCLKOUT cycles per access.
. . . . . .
11111 31 wait states will be used for an OTP access for a total of 32 SYSCLKOUT cycles per access.
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(3)
When writing to this register, follow the procedure described in Section 1.2.4 .
(1) (2) (3)
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Chapter 2
SPRUFB0C – September 2007 – Revised May 2009
Code Security Module (CSM)
The code security module (CSM) is a security feature incorporated in 28x devices. It prevents
access/visibility to on-chip memory to unauthorized persons—i.e., it prevents duplication/reverse
engineering of proprietary code.
The word secure means access to on-chip memory is protected. The word unsecure means access to
on-chip secure memory is not protected — i.e., the contents of the memory could be read by any means
(through a debugging tool such as Code Composer Studio™, for example).
Topic .................................................................................................. Page
2.1 Functional Description............................................................... 28
2.2 CSM Impact on Other On-Chip Resources ................................... 30
2.3 Incorporating Code Security in User Applications ......................... 31
2.4 Do's and Don'ts to Protect Security Logic .................................... 36
2.5 CSM Features - Summary ........................................................... 36
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Functional Description
2.1 Functional Description
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The security module restricts the CPU access to certain on-chip memory without interrupting or stalling
CPU execution. When a read occurs to a protected memory location, the read returns a zero value and
CPU execution continues with the next instruction. This, in effect, blocks read and write access to various
memories through the JTAG port or external peripherals. Security is defined with respect to the access of
on-chip memory and prevents unauthorized copying of proprietary code or data.
The device is secure when CPU access to the on-chip secure memory locations is restricted. When
secure, two levels of protection are possible, depending on where the program counter is currently
pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked
(i.e., through the emulator). This allows secure code to access secure data. Conversely, if code is running
from nonsecure memory, all accesses to secure memories are blocked. User code can dynamically jump
in and out of secure memory, thereby allowing secure function calls from nonsecure memory. Similarly,
interrupt service routines can be placed in secure memory, even if the main program loop is run from
nonsecure memory.
Security is protected by a password of 128-bits of data (eight 16-bit words) that is used to secure or
unsecure the device. This password is stored at the end of flash in 8 words referred to as the password
locations.
The device is unsecured by executing the password match flow (PMF), described Section 2.3.2 . Table 2-1
shows the levels of security.
Table 2-1. Security Levels
PMF Executed Operating Mode Program Fetch Security Description
With Correct Location
Password?
No Secure Outside secure memory Only instruction fetches by the CPU are allowed to secure
memory. In other words, code can still be executed, but not
read
No Secure Inside secure memory CPU has full access.
JTAG port cannot read the secured memory contents.
Yes Not Secure Anywhere Full access for CPU and JTAG port to secure memory
The password is stored in code security password locations (PWL) in flash memory (0x33 FFF8 0x33 FFFF). These locations store the password predetermined by the system designer.
If the password locations have all 128 bits as ones, the device is labeled unsecure. Since new flash
devices have erased flash (all ones), only a read of the password locations is required to bring the device
into unsecure mode. If the password locations have all 128 bits as zeros, the device is secure, regardless
of the contents of the KEY registers. Do not use all zeros as a password or reset the device during an
erase of the flash. Resetting the device during an erase routine can result in either an all zero or unknown
password. If a device is reset when the password locations are all zeros, the device cannot be unlocked
by the password match flow described in Section 2.3.2 . Using a password of all zeros will seriously limit
your ability to debug secure code or reprogram the flash.
Note: If a device is reset while the password locations are all zero or an unknown value, the device
will be permanently locked unless a method to run the flash erase routine from secure
SARAM is embedded into the flash or OTP. Care must be taken when implementing this
procedure to avoid introducing a security hole.
User accessible registers (eight 16-bit words) that are used to unsecure the device are referred to as key
registers. These registers are mapped in the memory space at addresses 0x00 0AE0 - 0x00 0AE7 and
are EALLOW protected.
28 Code Security Module (CSM) SPRUFB0C – September 2007 – Revised May 2009
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Functional Description
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, L0,
L1, L2 or L3 memory while the emulator is connected will trip the ECSL and break the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure
memory reads, you must write the correct value into the lower 64 bits of the KEY register, which matches
the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of
all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password
locations are all ones (unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (i.e., secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will
trip and cause the emulator connection to be cut. Two solutions to this problem exist:
1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the
emulator takes control. The emulator must support this mode for this option.
2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and
continuously poll the boot mode select pins. You can select this boot mode and then exit this mode
once the emulator is connected by re-mapping the PC to another address or by changing the boot
mode selection pin to the desired boot mode.
Note: Reserved Flash Locations When Using Code Security
For code security operation, all addresses between 0x33 FF80 and 0x33 FFF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code
Security Password is programmed. If security is not a concern, addresses 0x33 FF80
through 0x33 FFF5 may be used for code or data. The 128-bit password (at
0x33 FFF8 - 0x33 FFFF) must not be programmed to zeros. Doing so would permanently
lock the device.
Addresses 0x33 FFF0 through 0x33 FFF5 are reserved for data variables and should not
contain program code.
Disclaimer: Code Security Module Disclaimer
The Code Security Module ("CSM") included on this device was designed to password
protect the data stored in the associated memory and is warranted by Texas Instruments
(TI), in accordance with its standard terms and conditions, to conform to TI's published
specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
SPRUFB0C – September 2007 – Revised May 2009 Code Security Module (CSM) 29
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CSM Impact on Other On-Chip Resources
2.2 CSM Impact on Other On-Chip Resources
The CSM affects access to the on-chip resources listed in Table 2-2 :
Address Block
0x00 0A80 - 0x00 0A87 Flash Configuration Registers
0x00 8000 - 0x00 8FFF L0 SARAM (4K X 16)
0x00 9000 - 0x00 9FFF L1 SARAM (4K X 16)
0x00 A000 - 0x00 AFFF L2 SARAM (4K X 16)
0x00 B000 - 0x00 BFFF L3 SARAM (4K X 16)
0x30 0000 - 0x33 FFFF Flash (64K X 16, 32 X 16, or 16 X 16)
0x38 0000 - 0x38 03FF TI One-Time Programmable (OTP)
0x38 0400 - 0x38 07FF User One-Time Programmable (OTP) (1K X 16)
0x3F 8000 - 0x3F 8FFF L0 SARAM (4K X 16), mirror
0x3F 9000 - 0x3F 9FFF L1 SARAM (4K X 16), mirror
0x3F A000 - 0x3F AFFF L2 SARAM (4K X 16), mirror
0x3F B000 - 0x3F BFFF L3 SARAM (4K X 16), mirror
(1)
Not affected by ECSL
The Code Security Module has no impact whatsoever on the following on-chip resources:
• Single-access RAM (SARAM) blocks not designated as secure - These memory blocks can be freely
accessed and code run from them, whether the device is in secure or unsecure mode.
• Boot ROM contents - Visibility to the boot ROM contents is not impacted by the CSM.
• On-chip peripheral registers - The peripheral registers can be initialized by code running from on-chip
or off-chip memory, whether the device is in secure or unsecure mode.
• PIE Vector Table - Vector tables can be read and written regardless of whether the device is in secure
or unsecure mode. Table 2-2 and Table 2-3 show which on-chip resources are affected (or are not
affected) by the CSM.
Table 2-2. Resources Affected by the CSM
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(1)
(1K X 16)
Table 2-3. Resources Not Affected by the CSM
Address Block
0x00 0000 - 0x00 03FF M0 SARAM (1K X 16)
0x00 0400 - 0x00 07FF M1 SARAM (1K X16)
0x00 0800 - 0x00 0CFF Peripheral Frame 0 (2K X 16)
0x00 0D00 - 0x00 0FFF PIE Vector RAM (256 X 16)
0x00 6000 - 0x00 6FFF Peripheral Frame 1 (4K X 16)
0x00 7000 - 0x00 7FFF Peripheral Frame 2 (4K X 16)
0x00 C000 - 0x00 CFFF L4 SARAM (4K X 16)
0x00 D000 - 0x00 DFFF L5 SARAM (4K X 16)
0x00 E000 - 0x00 EFFF L6 SARAM (4K X 16)
0x00 F000 - 0x00 FFFF L7 SARAM (4K X 16)
0x3F F000 - 0x3F FFFF Boot ROM (4K X 16)
To summarize, it is possible to load code onto the unprotected on-chip program SARAM shown in
Table 2-3 via the JTAG connector without any impact from the Code Security Module. The code can be
debugged and the peripheral registers initialized, independent of whether the device is in secure or
unsecure mode.
Code Security Module (CSM)30 SPRUFB0C – September 2007 – Revised May 2009
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