Texas Instruments TMS320TCI6486 User Manual

TMS320C6472/TMS320TCI6486 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module

User's Guide

Literature Number: SPRUEF8F

March 2006–Revised November 2010

SPRUEF8F–March 2006–Revised November 2010

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Preface ...................................................................................................................................... 10

1 Introduction ...................................................................................................................... 11

1.1 Purpose of the Peripheral ............................................................................................. 11

1.2 Features ................................................................................................................. 11

1.3 Functional Block Diagram ............................................................................................. 12

1.4 Industry Standard(s) Compliance Statement ....................................................................... 14

2 EMAC Functional Architecture ............................................................................................ 15

2.1 Clock Control ........................................................................................................... 15

2.2 Memory Map ............................................................................................................ 16

2.3 System-Level Connections ........................................................................................... 17

2.4 Ethernet Protocol Overview .......................................................................................... 29

2.5 Programming Interface ................................................................................................ 31

2.6 Communications Port Programming Interface (CPPI) ............................................................ 40

2.7 Ethernet Multicore Interrupt Combiner (EMIC) Module ........................................................... 40

2.8 Management Data Input/Output (MDIO) Module .................................................................. 47

2.9 EMAC Module .......................................................................................................... 52

2.10 Media Independent Interfaces ........................................................................................ 54

2.11 Packet Receive Operation ............................................................................................ 58

2.12 Packet Transmit Operation ........................................................................................... 62

2.13 Receive and Transmit Latency ....................................................................................... 63

2.14 Transfer Node Priority ................................................................................................. 63

2.15 Reset Considerations .................................................................................................. 64

2.16 Initialization ............................................................................................................. 65

2.17 Interrupt Support ....................................................................................................... 67

2.18 Power Management ................................................................................................... 69

2.19 Emulation Considerations ............................................................................................. 69

3 EMIC Module Registers ...................................................................................................... 71

3.1 EW_INTCTL Registers ................................................................................................ 71

3.2 RPIC Registers ......................................................................................................... 71

3.3 TPIC Registers ......................................................................................................... 74

3.4 Prescalar Configuration Register (PSCFG) ........................................................................ 75

4 MDIO Registers ................................................................................................................. 76

4.1 Introduction ............................................................................................................. 76

4.2 MDIO Version Register (VERSION) ................................................................................. 77

4.3 MDIO Control Register (CONTROL) ................................................................................ 78

4.4 PHY Acknowledge Status Register (ALIVE) ....................................................................... 79

4.5 PHY Link Status Register (LINK) .................................................................................... 80

4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ................................... 81

4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .................................. 82

4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .......................... 83

4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ......................... 84

4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ....................... 85

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4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86

4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87

4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 88

4.14 MDIO User Access Register 1 (USERACCESS1) ................................................................ 89

4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................ 90

5 EMAC Port Registers ......................................................................................................... 91

5.1 Transmit Identification and Version Register (TXIDVER) ........................................................ 95

5.2 Transmit Control Register (TXCONTROL) ......................................................................... 96

5.3 Transmit Teardown Register (TXTEARDOWN) ................................................................... 97

5.4 Receive Identification and Version Register (RXIDVER) ......................................................... 98

5.5 Receive Control Register (RXCONTROL) .......................................................................... 99

5.6 Receive Teardown Register (RXTEARDOWN) .................................................................. 100

5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .......................................... 101

5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ........................................ 102

5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ...................................................... 103

5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ................................................ 104

5.11 MAC Input Vector Register (MACINVECTOR) ................................................................... 105

5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) .................................................... 106

5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ........................................... 107

5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ......................................... 108

5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ....................................................... 109

5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ................................................. 110

5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ............................................ 111

5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .......................................... 112

5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ........................................................ 113

5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .................................................. 114

5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .................. 115

5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ...................................................... 118

5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ......................................................... 119

5.24 Receive Maximum Length Register (RXMAXLEN) .............................................................. 120

5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) ......................................................... 121

5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ......................... 122

5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) .............................. 123

5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) ..................................... 124

5.29 MAC Control Register (MACCONTROL) .......................................................................... 125

5.30 MAC Status Register (MACSTATUS) ............................................................................. 127

5.31 Emulation Control Register (EMCONTROL) ...................................................................... 129

5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 130

5.33 MAC Configuration Register (MACCONFIG) ..................................................................... 131

5.34 Soft Reset Register (SOFTRESET) ................................................................................ 132

5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 133

5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 134

5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 135

5.38 MAC Hash Address Register 2 (MACHASH2) ................................................................... 136

5.39 Back Off Test Register (BOFFTEST) .............................................................................. 137

5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ....................................................... 138

5.41 Receive Pause Timer Register (RXPAUSE) ...................................................................... 139

5.42 Transmit Pause Timer Register (TXPAUSE) ..................................................................... 140

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5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 141

5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142

5.45 MAC Index Register (MACINDEX) ................................................................................. 143

5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) ................................... 144

5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) .................................... 145

5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) .................................................. 146

5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) .................................................. 147

5.50 Network Statistics Registers ........................................................................................ 148

Appendix A Glossary ............................................................................................................... 157

Appendix B Revision History ..................................................................................................... 159

SPRUEF8F–March 2006–Revised November 2010 Contents

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List of Figures

1 EMAC and MDIO Block Diagram........................................................................................ 12

2 Ethernet Configuration with MII Interface .............................................................................. 18

3 Ethernet Configuration with RMII Interface ............................................................................ 20

4 Ethernet Configuration with GMII Interface ............................................................................ 21

5 Ethernet Configuration with RGMII Interface .......................................................................... 23

6 Ethernet Configuration with S3MII Interface ........................................................................... 25

7 S3MII Multi-PHY Configuration .......................................................................................... 27

8 S3MII Switch Configuration .............................................................................................. 28

9 Ethernet Frame............................................................................................................ 29

10 Basic Descriptor Format.................................................................................................. 31

11 Typical Descriptor Linked List............................................................................................ 32

12 Transmit Descriptor Format .............................................................................................. 34

13 Receive Descriptor Format............................................................................................... 37

14 EMIC Block Diagram...................................................................................................... 41

15 Pacing Block ............................................................................................................... 42

16 TDSM State Transition Diagram......................................................................................... 43

17 DSM State Transition Diagram .......................................................................................... 44

18 Transmit Pacer and Interrupt Combiner................................................................................ 45

19 Receive Pacer and Interrupt Combiner................................................................................. 46

20 Common Interrupt Combiner............................................................................................. 47

21 MDIO Module Block Diagram............................................................................................ 48

22 EMAC Module Block Diagram........................................................................................... 52

23 EW_INTCTL Register..................................................................................................... 71

24 RPCFG Register........................................................................................................... 72

25 RPSTAT Register ......................................................................................................... 73

26 TPCFG Register........................................................................................................... 74

27 TPSTAT Register.......................................................................................................... 75

28 Prescalar Configuration Register (PSCFG)............................................................................ 75

29 MDIO Version Register (VERSION) .................................................................................... 77

30 MDIO Control Register (CONTROL).................................................................................... 78

31 PHY Acknowledge Status Register (ALIVE)........................................................................... 79

32 PHY Link Status Register (LINK)........................................................................................ 80

33 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)....................................... 81

34 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..................................... 82

35 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).............................. 83

36 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................ 84

37 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)........................... 85

38 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .................... 86

39 MDIO User Access Register 0 (USERACCESS0) .................................................................... 87

40 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................... 88

41 MDIO User Access Register 1 (USERACCESS1) .................................................................... 89

42 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................... 90

43 Transmit Identification and Version Register (TXIDVER) ............................................................ 95

44 Transmit Control Register (TXCONTROL)............................................................................. 96

45 Transmit Teardown Register (TXTEARDOWN)....................................................................... 97

46 Receive Identification and Version Register (RXIDVER)............................................................. 98

47 Receive Control Register (RXCONTROL) ............................................................................. 99

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48 Receive Teardown Register (RXTEARDOWN)...................................................................... 100

49 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW).............................................. 101

50 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................ 102

51 Transmit Interrupt Mask Set Register (TXINTMASKSET).......................................................... 103

52 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR).................................................... 104

53 MAC Input Vector Register (MACINVECTOR)....................................................................... 105

54 MAC End-of-Interrupt Vector Register (MACEOIVECTOR)........................................................ 106

55 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) .............................................. 107

56 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)............................................. 108

57 Receive Interrupt Mask Set Register (RXINTMASKSET) .......................................................... 109

58 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .................................................... 110

59 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)................................................ 111

60 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .............................................. 112

61 MAC Interrupt Mask Set Register (MACINTMASKSET)............................................................ 113

62 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)...................................................... 114

63 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ..................... 115

64 Receive Unicast Enable Set Register (RXUNICASTSET).......................................................... 118

65 Receive Unicast Clear Register (RXUNICASTCLEAR)............................................................. 119

66 Receive Maximum Length Register (RXMAXLEN).................................................................. 120

67 Receive Buffer Offset Register (RXBUFFEROFFSET)............................................................. 121

68 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)............................. 122

69 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH).................................... 123

70 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ........................................... 124

71 MAC Control Register (MACCONTROL) ............................................................................. 125

72 MAC Status Register (MACSTATUS)................................................................................. 127

73 Emulation Control Register (EMCONTROL) ......................................................................... 129

74 FIFO Control Register (FIFOCONTROL)............................................................................. 130

75 MAC Configuration Register (MACCONFIG)......................................................................... 131

76 Soft Reset Register (SOFTRESET)................................................................................... 132

77 MAC Source Address Low Bytes Register (MACSRCADDRLO).................................................. 133

78 MAC Source Address High Bytes Register (MACSRCADDRHI) .................................................. 134

79 MAC Hash Address Register 1 (MACHASH1)....................................................................... 135

80 MAC Hash Address Register 2 (MACHASH2)....................................................................... 136

81 Back Off Test Register (BOFFTEST) ................................................................................. 137

82 Transmit Pacing Algorithm Test Register (TPACETEST) .......................................................... 138

83 Receive Pause Timer Register (RXPAUSE) ......................................................................... 139

84 Transmit Pause Timer Register (TXPAUSE)......................................................................... 140

85 MAC Address Low Bytes Register (MACADDRLO)................................................................. 141

86 MAC Address High Bytes Register (MACADDRHI) ................................................................. 142

87 MAC Index Register (MACINDEX) .................................................................................... 143

88 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ......................................... 144

89 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP).......................................... 145

90 Transmit Channel n Completion Pointer Register (TXnCP)........................................................ 146

91 Receive Channel n Completion Pointer Register (RXnCP) ........................................................ 147

92 Statistics Register........................................................................................................ 148

SPRUEF8F–March 2006–Revised November 2010 List of Figures

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List of Tables

1 Serial Management Interface Pins...................................................................................... 13

2 EMAC1_EN Pin Description ............................................................................................. 13

3 EMAC Clock Specifications .............................................................................................. 15

4 EMAC0 Interface Selection Pins ........................................................................................ 17

5 EMAC1 Interface Selection Pins ........................................................................................ 17

6 MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding ........................................................ 17

7 EMAC and MDIO Signals for MII Interface............................................................................. 19

8 EMAC and MDIO Signals for RMII Interface........................................................................... 20

9 EMAC and MDIO Signals for GMII Interface .......................................................................... 22

10 EMAC and MDIO Signals for RGMII Interface ........................................................................ 23

11 EMAC and MDIO Signals for S3MII Interface ......................................................................... 26

12 Ethernet Frame Description.............................................................................................. 29

13 Basic Descriptors.......................................................................................................... 31

14 Receive Frame Treatment Summary................................................................................... 61

15 Middle-of-Frame Overrun Treatment.................................................................................... 62

16 Emulation Control ......................................................................................................... 70

17 RPCFG Register Field Descriptions .................................................................................... 72

18 RPSTAT Register Field Descriptions................................................................................... 73

19 TPCFG Register Field Descriptions..................................................................................... 74

20 TPSTAT Register Field Descriptions ................................................................................... 75

21 Management Data Input/Output (MDIO) Registers ................................................................... 76

22 MDIO Version Register (VERSION) Field Descriptions .............................................................. 77

23 MDIO Control Register (CONTROL) Field Descriptions ............................................................. 78

24 PHY Acknowledge Status Register (ALIVE) Field Descriptions..................................................... 79

25 PHY Link Status Register (LINK) Field Descriptions ................................................................. 80

26 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions................. 81

27 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ............... 82

28 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions........ 83

29 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions...... 84

30 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .... 85

31 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field

Descriptions ................................................................................................................ 86

32 MDIO User Access Register 0 (USERACCESS0) Field Descriptions.............................................. 87

33 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions......................................... 88

34 MDIO User Access Register 1 (USERACCESS1) Field Descriptions.............................................. 89

35 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions......................................... 90

36 Ethernet Media Access Controller (EMAC) Registers ................................................................ 91

37 Transmit Identification and Version Register (TXIDVER) Field Descriptions...................................... 95

38 Transmit Control Register (TXCONTROL) Field Descriptions....................................................... 96

39 Transmit Teardown Register (TXTEARDOWN) Field Descriptions................................................. 97

40 Receive Identification and Version Register (RXIDVER) Field Descriptions ...................................... 98

41 Receive Control Register (RXCONTROL) Field Descriptions ....................................................... 99

42 Receive Teardown Register (RXTEARDOWN) Field Descriptions................................................ 100

43 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ....................... 101

44 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions...................... 102

45 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions.................................... 103

46 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................. 104

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47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 105

48 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions.................................. 106

49 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions........................ 107

50 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ...................... 108

51 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions.................................... 109

52 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions.............................. 110

53 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......................... 111

54 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions........................ 112

55 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ..................................... 113

56 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ............................... 114

57 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field

58 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ................................... 118

59 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 119

60 Receive Maximum Length Register (RXMAXLEN) Field Descriptions............................................ 120

61 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions....................................... 121

62 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ...... 122

63 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions.............. 123

64 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ..................... 124

65 MAC Control Register (MACCONTROL) Field Descriptions ....................................................... 125

66 MAC Status Register (MACSTATUS) Field Descriptions........................................................... 127

67 Emulation Control Register (EMCONTROL) Field Descriptions................................................... 129

68 FIFO Control Register (FIFOCONTROL) Field Descriptions....................................................... 130

69 MAC Configuration Register (MACCONFIG) Field Descriptions .................................................. 131

70 Soft Reset Register (SOFTRESET) Field Descriptions............................................................. 132

71 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ........................... 133

72 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................ 134

73 MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................. 135

74 MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................. 136

75 Back Off Test Register (BOFFTEST) Field Descriptions ........................................................... 137

76 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions.................................... 138

77 Receive Pause Timer Register (RXPAUSE) Field Descriptions ................................................... 139

78 Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................. 140

79 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .......................................... 141

80 MAC Address High Bytes Register (MACADDRHI) Field Descriptions........................................... 142

81 MAC Index Register (MACINDEX) Field Descriptions .............................................................. 143

82 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions................... 144

83 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ................... 145

84 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions.................................. 146

85 Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions.................................. 147

86 Statistics Register Field Descriptions.................................................................................. 148

87 EMAC/MDIO Revision History.......................................................................................... 159

Descriptions............................................................................................................... 115

SPRUEF8F–March 2006–Revised November 2010 List of Tables

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About This Manual

This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions for each module.

Notational Conventions

This document uses the following conventions.

• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40

hexadecimal (decimal 64): 40h.

• Registers in this document are shown in figures and described in tables.

– Each register figure shows a rectangle divided into fields that represent the fields of the register.

Each field is labeled with its bit name, its beginning and ending bit numbers above, and its

read/write properties below. A legend explains the notation used for the properties.

– Reserved bits in a register figure designate a bit that is used for future device expansion.

Preface

SPRUEF8F–March 2006–Revised November 2010

Read This First

Related Documentation From Texas Instruments

The following documents describe the C6000™ devices and related support tools. Copies of these documents are available on the Internet. Tip: Enter the literature number in the search box provided at

www.ti.com. SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors

(DSPs).

SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for

the TMS320C6000™ DSPs and includes application program examples.

SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™

integrated development environment and software tools.

SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.

Describes the Code Composer Studio™ application programming interface (API), which allows you

to program custom plug-ins for Code Composer.

SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal

processor (DSP) megamodule. Included is a discussion on the internal direct memory access

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management, and the memory and cache.

C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

Preface SPRUEF8F–March 2006–Revised November 2010

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1 Introduction

The EMAC controls the flow of packet data from the processor to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the DSP through EMIC modules and CPPI buffer managers that allow efficient data transmission and reception. These two modules are considered integral to the EMAC/MDIO peripheral.

1.1 Purpose of the Peripheral

The EMAC module is used on TMS320TCI6486/TMS320C6472 devices to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol.

User's Guide

SPRUEF8F–March 2006–Revised November 2010

C6472/TCI6486 EMAC/MDIO

1.2 Features

Two EMAC modules are integrated with the TCI6486/C6472 device. The basic feature set of the integrated EMAC modules is:

• Synchronous 10/100/1000-Mbps operation.

• Full duplex Gigabit operation (half duplex gigabit is not supported).

• Little endian and big endian support.

• Both EMAC modules support three types of interfaces to the physical layer device (PHY): reduced

pin-count media independent interface (RMII), reduced pin-count gigabit media independent interface (RGMII), and source synchronous serial independent interface (S3MII).

• In addition to above four EMAC0 natively supports an additional two interfaces: standard media

independent interface (MII) and standard gigabit media independent interface (GMII).

• EMAC acts as DMA master to either internal or external device memory space.

• Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.

• Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.

• Ether-stats and 802.3-stats statistics gathering.

• Transmit CRC generation selectable on a per-channel basis.

• Broadcast frames selection for reception on a single channel.

• Multicast frames selection for reception on a single channel.

• Promiscuous receive mode frames selection for reception on a single channel (all frames, all good

frames, short frames, error frames).

• Hardware flow control.

• CPPI 3.0 compliant.

• TI adaptive performance optimization for improved half duplex performance.

• Ethernet Multicore Interrupt Combiner (EMIC) for EMAC and MDIO interrupts.

• Programmable interrupt logic permits the software driver to restrict the generation of back-to-back

interrupts, thus, allowing more work to be performed in a single call to the interrupt service routine.

SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO

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EMIC0

CPPIbuffer

manager+

CPPIRAM0

EMAC0

DMA

memory

transfercontrol

Peripheral

bus

MDIO

EMAC1

CPPIbuffer

manager+

CPPIRAM1

EMIC1

ToGEMs

MII0/GMII0

RGMII0

RMII0

S3MII0

ToPHYs

RGMII1

RMII1

S3MII1

DMA

memory

transfercontrol

EMAC Control0 Module

EMAC Control1 Module

Introduction

• Single MDIO, shared by both EMAC modules.

1.3 Functional Block Diagram

Figure 1 shows the functional block diagram of the EMAC peripherals used in the TCI6486/C6472 device.

It consists mainly of:

• EMAC0

• EMAC1

• CPPI buffer manager per EMAC

• EMIC per EMAC

• MDIO

Figure 1. EMAC and MDIO Block Diagram

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The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (100 Mbits/sec) in either half- or full-duplex mode, and 1000Base-T (1000 Mbits/sec) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

Each EMAC module has a communications port programming interface (CPPI) buffer manager to manage 8K of CPPI RAM. The EMAC uses four 32-bit words as buffer descriptors that point to different buffers in the DSP memory. The CPUs create and maintain these buffer descriptors. The EMAC reads from and writes to these buffer descriptors as it transfers data to or from the buffers.

The EMIC module associated with each EMAC takes a single set of interrupts from respective EMAC and common MDIO and creates six different sets of TX, RX, and common interrupts to six cores of the TCI6486/C6472 device. In addition, this module implements the interrupt pacing operation.

The control registers of the EMAC and MDIO modules are memory mapped into device memory space via the device configuration bus.

The MDIO module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHYs connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. A single MDIO is shared by both EMACs.

MACSEL0[2:0] and MACSEL1[1:0] are device configuration pins used to select the MII interface for EMAC0 and EMAC1, respectively.

The MDIO communicates to PHY through two signals: MDCLK (output clock) and MDIO (bi-directional data). For details of MDIO operation and signals, see Section 2.8. The device has two serial management interfaces, although only one is used based on the interface selection of EMAC0. Table 1 shows the two sets of pins associated with serial management interface. One serial management interface is for RGMII (needed at 1.8-V HSTL buffer) and the other serial management interface is for non-RGMII interfaces (needed at 3.3-V LVCMOS buffers).

Introduction

Table 1. Serial Management Interface Pins

Signal Description

GMDCLK MII/GMII/RMII/S3MII management clock. Available on 3.3-V LVCMOS buffers. GMDIO MII/GMII/RMII/S3MII management data. Available on 3.3-V LVCMOS buffers. RGMDCLK RGMII management clock. Available on 1.8-V HSTL buffers. RGMDIO RGMII management data. Available on 1.8-V HSTL buffers.

As mentioned above, the management interface selection is based on the interface selection for EMAC0. If MACSEL0 is programmed to select RGMII0, the 1.8-V serial management interface is selected (RGMDIO, RGMDCLK), otherwise, the 3.3-V (GMDIO, GMDCLK) management interface is selected. Due to this programmed selection, in some cases level shifters may have to be used for the management interface. As an example, if the RGMII0 interface is selected for EMAC0 and the S3MII1 interface is selected for EMAC1, the 1.8-V serial management interface (RGMDCLK and RGMDIO) is used. Since S3MII PHY needs the 3.3-V management interface, level shifters have to be used to level translate these HSTL pins.

Also note that EMAC1 can be enabled or disabled using the EMAC1_EN internal pulldown pin that controls the I/O signals of EMAC1. The EMAC1_EN is also latched into the bit 12 of the DEVCTL register.

Table 2 describes the EMAC1_EN pin.

Table 2. EMAC1_EN Pin Description

Value Description

0 EMAC1 is disabled or not used.

Pulls on EMAC1 I/O are enabled (except RGMII pins) and the corresponding I/O buffers are powered down.

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Table 2. EMAC1_EN Pin Description (continued)

Value Description

1 EMAC1 is enabled and used.

Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins.

NOTE: RGMII buffers are HSTL buffers with no internal pulls. RGMII output only pins will always

be powered down even when the module is enabled.

EMAC1_EN is also software programmable through the DEVCTL register. A write to the DEVCTL register is key-protected by the DEVCTL_KEY register. For details of MACSEL0, MACSEL1, and EMAC1_EN decoding, see Section 2.3.

1.4 Industry Standard(s) Compliance Statement

The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. ISO/IEC has also

adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E). In difference from this standard, the EMAC peripheral integrated with the TCI6486/C6472 device does not

use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC intentionally generates an incorrect check sum by inverting the frame CRC so that the network detects the transmitted frame as an error.

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2 EMAC Functional Architecture

This section discusses the architecture and basic function of the EMAC peripheral.

2.1 Clock Control

The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification, as shown below:

• 2.5 MHz at 10 Mbps

• 25 MHz at 100 Mbps

• 125 MHz at 1000 Mbps All clock sources, with the exception of the EMAC peripheral bus clock, are sourced from the PLL2

controller. The PLL2 controller has 3 clocks for EMAC0: SYSCLK13, SYSCLK14, and SYSCLK15. For EMAC0 operation, the SYSCLK14 divider is programmable and other clocks are fixed. The PLL multiplier value of the PLL2 controller is also fixed. The PLL2 controller has 3 clocks for EMAC1: SYSCLK16, SYSCLK17, and SYSCLK18. These clocks should remain fixed.

Table 3. EMAC Clock Specifications

Clock Divider Frequency Purpose

SYSCLK13 /2 250 MHz Used for RGMII0 only SYSCLK14 SYSCLK15 /100 5 MHz Used for RGMII0 only

SYSCLK16 /2 250 MHz Used for RGMII1 only SYSCLK17 /10 50 MHz Used for RGMII1 (default) SYSCLK18 /100 5 MHz Used for RGMII1 only

/10 or 50 or 50 MHz used for RGMII (default

/4 125 MHz 125 MHz used for GMII

EMAC Functional Architecture

2.1.1 MII Clocking

The MII interface is supported by EMAC0 only. When MACSEL0 is set to zero (000b), the transmit and receive clock sources are provided from an external PHY via the MTCLK and MRCLK pins. These clocks are inputs to the EMAC module and operate at 2.5 MHz in 10-Mbps mode and at 25 MHz in 100-MHz mode. The MII clocking interface is not used in 1000-Mbps mode. For timing purposes, data is transmitted and received with reference to MTCLK and MRCLK, respectively.

2.1.2 RMII Clocking

The RMII interface is selected when MACSEL0 is set to 1 (001b) or MACSEL1 is set to 3 (11b). RMII requires two clock sources, the peripheral bus clock and the reference clock (REF_CLK), input to the RMII gasket. A 50-MHz clock from device input pin REFCLKx is supplied to the REF_CLK input of the RMII gasket. The EMAC clocks the transmit and receive operations from the reference clock. The MTCLK and MRCLK device pins are not used for this interface. The RMII protocol turns one data phase of an MII transfer into two data phases at double the clock frequency. This is the driving factor for the 50-MHz reference clock. Data at the I/O pins are running at 5 MHz in 10-Mbps mode and at 50 MHz in 100-Mbps mode.

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EMAC Functional Architecture

2.1.3 GMII Clocking

The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for this interface to provide a 125-MHz clock to the RFTCLK input of EMAC. The GMII interface is selected by programming MACSEL0 to 2 (010b). Transmit and receive clock sources for 10/100-Mbps modes are provided from an external PHY via the MTCLK and MRCLK pins. For 1000-Mbps mode, the receive clock is provided by an external PHY via the MRCLK pin. For transmit in 1000-Mbps mode, the clock is sourced synchronous with the data, and is provided by the EMAC to be output on the GMTCLK pin.

For timing purposes, data in 10/100-Mbps mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000-Mbps mode, receive timing is the same, but transmit is relative to GMTCLK.

2.1.4 RGMII Clocking

The RGMII interface is selected by programming MACSEL0 to 3 (011b) and MACSEL1 to 2 (10b). RGMII requires 4 internally generated clocks; peripheral bus clock and three reference clocks. The EMAC drives the transmit clock, while an external PHY generates the receive clock. The reference clock drives the device pin that gives the 125-MHz clock to the PHY; this enables the PHY to generate the receive clock that is sent to EMAC.

The RGMII protocol takes a GMII data stream and turns it into an interface with half of the data bus width and sends the same amount of data with a reduced pinout. The RGMII protocol also allows for dynamic switching of the mode between 10/100/1000-Mbps modes. This negotiation data is embedded in the incoming data stream from the external PHY. For timing purposes, data is transmitted and received with respect to MTCLK and MRCLK, respectively.

The RGMII interface has separate I/O pins from the other EMAC pins because the interface voltage is different from the other interfaces.

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2.1.5 S3MII Clocking

S3MII mode is selected by programming MACSEL0 to 5 (101b) and MACSEL1 to 1 (01b). The S3MII gasket needs a 125-MHz continuous clock (125_CLK) supplied by an external source. It also needs a peripheral bus clock as input. MTCLK and MRCLK are fixed at 125 MHz.

2.2 Memory Map

The EMAC includes an internal memory that holds information about the Ethernet packets that are received or transmitted. This internal RAM is 2K x 32 bits in size. The data can be written to and read from the EMAC internal memory via either the EMAC or the CPU. It stores buffer descriptors that are 4 words (16 bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention.

The packet buffer descriptors can be put in internal processor memory (L2) on the TCI6486/C6472 device. There are some trade-offs in terms of cache performance and throughput when the descriptors are put in L2 versus when they are put in EMAC internal memory. The cache performance improves when the buffer descriptors are put in the internal memory. However, the EMAC throughput is better when the descriptors are put in the local EMAC RAM.

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2.3 System-Level Connections

On the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types of interfaces to physical layer devices (PHYs) or switches. Each EMAC can be configured to only one interface at any given time. EMAC0 interface is selected by programming MACSEL0 [2:0] pins (see Table 4) and EMAC1 interface is selected by programming MACSEL1 [1:0] pins (see Table 5).

Table 4. EMAC0 Interface Selection Pins

MACSEL0 [2:0] Interface

Table 5. EMAC1 Interface Selection Pins

MACSEL1 [1:0] Interface

EMAC Functional Architecture

000 MII 001 RMII 010 GMII 011 RGMII 100 Not used 101 S3MII 110 Not used 111 Not used

00 Not used 01 S3MII 10 RGMII 11 RMII

Table 6 explains the decoding of MACSEL0 [2:0], MACSEL1[1:0], and EMAC1_EN of the DEVCTL

Table 6. MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding

MACSEL02 MACSEL01 MACSEL00 MACSEL11 MACSEL10 EMAC_EN EMAC0 EMAC1

0 0 0 X X 0 MII None 0 0 0 0 X 1 MII None 0 0 0 1 0 1 MII RGMII 0 1 0 X X 0 GMII None 0 1 0 0 X 1 GMII None 0 1 0 1 0 1 GMII RGMII 0 0 1 X X 0 RMII None 0 1 1 X X 0 RGMII None 1 0 0 X X 0 None None 1 0 1 X X 0 S3MII None 0 0 1 0 0 1 RMII None 0 0 1 0 1 1 RMII S3MII 0 0 1 1 0 1 RMII RGMII 0 0 1 1 1 1 RMII RMII 0 1 1 0 0 1 RGMII None 0 1 1 0 1 1 RGMII S3MII 0 1 1 1 0 1 RGMII RGMII 0 1 1 1 1 1 RGMII RMII 1 0 0 0 0 1 None None 1 0 0 0 1 1 None S3MII 1 0 0 1 0 1 None RGMII

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MTCLK

MTXD[3−0]

MTXEN

MCOL

MCRS

MRCLK

MRXD[3−0]

MRXDV

MRXER

MDCLK

MDIO

2.5 MHZ or

25 MHz

Physical

layer

device

(PHY)

System

core

EMAC

MDIO

Transformer

RJ-45

EMAC Functional Architecture

Table 6. MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding (continued)

MACSEL02 MACSEL01 MACSEL00 MACSEL11 MACSEL10 EMAC_EN EMAC0 EMAC1

1 0 0 1 1 1 None RMII 1 0 1 0 0 1 S3MII None 1 0 1 0 1 1 S3MII S3MII 1 0 1 1 0 1 S3MII RGMII 1 0 1 1 1 1 S3MII RMII 1 1 1 X X 0 None None 1 1 1 0 0 1 None None 1 1 1 0 1 1 None S3MII 1 1 1 1 0 1 None RGMII 1 1 1 1 1 1 None RMII

2.3.1 Media Independent Interface (MII) Connections

Figure 2 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an

MII connection. This interface is only available in 10 Mbps and 100 Mbps modes.

Figure 2. Ethernet Configuration with MII Interface

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Table 7 summarizes the individual EMAC and MDIO signals for the MII interface. For more information,

refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC

inversion is used to negate the validity of the transmitted frame.

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EMAC Functional Architecture

Table 7. EMAC and MDIO Signals for MII Interface

Signal Name I/O Description

MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference

for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation.

MTXD[3:0] O Transmit data (MTXD). The transmit data pins are a collection of 4 data signals comprising 4 bits of

data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK and valid only when MTXEN is asserted.

MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generating

nibble data for use by the PHY. It is driven synchronously to MTCLK.

MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on the

network. It remains asserted while the collision condition persists. This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either

transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK or MRCLK. This pin is used in half-duplex operation only.

MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing reference

for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation.

MRXD[3:0] I Receive data (MRXD). The receive data pins are a collection of 4 data signals comprising 4 bits of

data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MRCLK and valid only when MRXDV is asserted.

MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are

generating nibble data for use by the EMAC. It is driven synchronously to MRCLK.

MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods to

indicate that an error was detected in the received frame. This is meaningful only during data reception when MRXDV is active.

MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the

system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of

the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address, register address, and data bit cycles. The MDIO pin acts as an output for everything except the data bit cycles, when the pin acts as an input for read operations.

When the device is interfaced to an Ethernet switch via an MII interface, the carrier sense (MCRS) and collision (MCOL) signals are not necessary since full-duplex operation is forced.

On the TCI6486/C6472 device, the MII Ethernet interface is available only on EMAC0. MII0 pins are multiplexed with other non-RGMII pins (RMII1, S3MII1). due to this multiplexing, when the MII0 interface is selected on EMAC0, except for RGMII1, no Ethernet interface is available on EMAC1.

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MDCLK

MDIO

RMTXD[1−0]

RMTXEN

RMCRSDV

RMRXD[1−0]

RMRXER

Physical

layer device (PHY)

EMAC

MDIO

System

core

RMREFCLK RMREFCLK

50-MHz

zero-delay

clock buffer

50-MHz

EMAC Functional Architecture

2.3.2 Reduced Media Independent Interface (RMII) Connections

Figure 3 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an

RMII connection. This interface is available only in 10-Mbps and 100-Mbps modes.

Figure 3. Ethernet Configuration with RMII Interface

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The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. Table 8 summarizes the individual EMAC and MDIO signals for the RMII interface.

The RMII interface does not include an MCOL signal. A collision is detected from the receive and transmit data delimiters. The data signals are 2 bits wide, and a single reference clock must be provided to the MAC, operating at 50 MHz to sustain the same data rate as MII.

Signal Name I/O Description

RMTXD[1-0] O Transmit data (RMTXD). The transmit data pins are a collection of 2 data signals comprising 2 bits

RMTXEN O Transmit enable (RMTXEN). The transmit enable signal indicates that the RMTXD pins are

RMCRSDV I Carrier sense/receive data valid (RMCRSDV). The RMCRSDV pin is asserted by the PHY when the

RMREFCLK I Reference clock (RMREFCLK). A 50-MHz clock must be provided through this pin for RMII

RMRXD[1-0] I Receive data (RMRXD). The receive data pins are a collection of 2 data signals comprising 2 bits of

Table 8. EMAC and MDIO Signals for RMII Interface

of data. RMTDX0 is the least-significant bit (LSB). The signals are synchronized to the RMII reference clock and valid only when RMTXEN is asserted.

generating nibble data for use by the PHY. It is driven synchronously to the RMII reference clock.

network is not idle in either transmit or receive. The data on RMRXD is considered valid once the RMCRSDV signal is asserted. The pin is de-asserted when both transmit and receive are idle. The assertion of this signal is asynchronous to the RMII reference clock.

operation.

data. RMRDX0 is the least-significant bit (LSB). The signals are synchronized to the RMII reference clock and valid only when RMCRSDV is asserted. In 10-Mbps operation, RMRXD is sampled every tenth cycle of the RMII reference clock.

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MTCLK

MTXD[7−0]

MTXEN

MCOL

MCRS

MRCLK

MRXD[7−0]

MRXDV

MRXER

MDCLK

MDIO

Physical

layer

device

(PHY)

System

core

Transformer

2.5 MHz, 25 MHz,

or 125 MHz

RJ−45

EMAC

MDIO

GMTCLK

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The 50-MHz reference clock (RMREFCLK) for the RMII gasket is sourced externally through a zero-delay clock buffer. If multiple RMII PHY ports are used, all device RMII reference clocks must come from same zero-delay clock buffer.

On the TCI6486/C6472 device, RMII pins are multiplexed with other non-RGMII pins. When using the RMII0 port on EMAC0, there are no restrictions on the available EMAC1 Ethernet interfaces (RMII1, S3MII1, and RGMII1 are useable). When using the RMII1 port on EMAC1, the EMAC0 Ethernet interfaces not available due to pin multiplexing are GMII0/MII0. The RMII0, S3MII0, and RGMII0 ports are available on EMAC0 Ethernet interfaces when using the RMII1 port on EMAC1.

If the device is interfaced to an Ethernet switch through the RMII interface, all device RMII reference clocks should be externally sourced from the same zero-delay clock buffer.

EMAC Functional Architecture

Table 8. EMAC and MDIO Signals for RMII Interface (continued)

Signal Name I/O Description

RMRXER I Receive error (RMRXER). The receive error signal is asserted for one or more reference clock

periods to indicate that an error was detected in the received frame. This is meaningful only during data reception when RMCRSDV is active. It is driven synchronously to the RMII reference clock.

MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the

system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of

2.3.3 Gigabit Media Independent Interface (GMII) Connections

Figure 4 shows a device with integrated EMAC and MDIO interfaced to the PHY via a GMII connection.

This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.

Figure 4. Ethernet Configuration with GMII Interface

The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface, and only the lower 4 bits of data are transferred for each of the data buses.

Table 9 summarizes the individual EMAC and MDIO signals for the GMII interface.

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EMAC Functional Architecture

Signal Name I/O Description

MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference

GMTCLK O GMII source synchronous transmit clock (GMTCLK). This clock is used in 1000 Mbps mode only,

MTXD[7-0] O Transmit data (MTXD). The transmit data pins are a collection of 8 data signals comprising 8 bits of

MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generating

MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on the

MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either

MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing reference

MRXD[7-0] I Receive data (MRXD). The receive data pins are a collection of 8 data signals comprising 8 bits of

MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are

MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods to

MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the

MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of

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Table 9. EMAC and MDIO Signals for GMII Interface

for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clock when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation, and 25 MHz at 100-Mbps operation.

providing a continuous 125 MHz frequency for transmit operations. The MTXD and MTXEN signals are tied to this clock when in Gigabit mode. The clock is generated by the EMAC and is 125 MHz.

data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK in 10/100 Mbps mode, and by GMTCLK in Gigabit mode, and valid only when MTXEN is asserted.

nibble data for use by the PHY. It is driven synchronously to MTCLK in 10/100 Mbps mode, and to GMTCLK in Gigabit mode.

network. It remains asserted while the collision condition persists. This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation, 25 MHz at 100-Mbps operation and 125 MHz at 1000-Mbps operation.

data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MRCLK and valid only when MRXDV is asserted.

generating nibble data for use by the EMAC. It is driven synchronously to M RCLK.

indicate that an error was detected in the received frame. This is meaningful only during data reception when MRXDV is active.

system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

When the TCI6486/C6472 device is interfaced to an Ethernet switch via the GMII interface, the carrier sense (MCRS) and collision (MCOL) signals are not necessary since full-duplex operation is forced.

On the device, the GMII Ethernet interface is available only on EMAC0 of the device. GMII0 pins are multiplexed with other non-RGMII pins (RMII1, S3MII1). Due to this multiplexing, when the MII0 interface is selected on EMAC0, except for RGMII1, no Ethernet interface is available on EMAC1.

2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections

Figure 5 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an

RGMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.

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RGTXC

RGTXD[3−0]

RGTXCTL

RGREFCLK

RGRXC

RGRXD[3−0]

RGRXCTL

RGMDCLK

RGMDIO

Physical

layer

device

(PHY)

System

core

Transformer

2.5 MHz 25 MHz,

or 125 MHz

RJ−45

EMAC

MDIO

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The RGMII interface is a reduced pin alternative to the GMII interface. The data paths are reduced, control signals are multiplexed together, and both edges of the clock are used.

The RGMII interface does not include a MCOL and a MCRS signal for half-duplex mode (only available in 10/100 Mbps mode).

Carrier sense (MCRS) is indicated by one of the following cases instead:

• MRXDV signal (multiplexed in the RGRXCTL signal) is true

• MRXDV is false, MRXERR (multiplexed in the RGRXCTL signal) is true, and a value of FFh exists on

Table 10 summarizes the individual EMAC and MDIO signals for the RGMII interface.

EMAC Functional Architecture

Figure 5. Ethernet Configuration with RGMII Interface

the RGRXD[3:0] simultaneously

Table 10. EMAC and MDIO Signals for RGMII Interface

Signal Name I/O Description

RGTXC O Transmit clock (RGTXC). The transmit clock is a continuous clock that provides the timing reference

RGTXD[3-0] O Transmit data (RGTXD). The transmit data pins are a collection of 4 data signals comprising 4 bits of

RGTXCTL O Transmit enable (RGTXCTL). The transmit enable signal indicates that the RGTXD pins are

RGREFCLK O Reference clock (RGREFCLK). This 125-MHz reference clock is provided as a convenience. It can

RGRXC I Receive clock (RGRXC). The receive clock is a continuous clock that provides the timing reference

RGRXD[3-0] I Receive data (RGRXD). The receive data pins are a collection of 4 data signals comprising 4 bits of

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for transmit operations. The RGTXD and RGTXCTL signals are tied to this clock. The clock is driven by the EMAC and is 2.5 MHz at 10-Mbps operation, 25 MHz at 100-Mbps operation, and 125 MHz at 1000-Mbps operation.

data. RGTDX0 is the least-significant bit (LSB). The signals are synchronized by RGTXC and valid only when RGTXCTL is asserted. The lower 4 bits of data are transmitted on the rising edge of the clock, and the higher 4 bits of data are transmitted on the falling edge of the RGTXC.

generating nibble data for use by the PHY. It is driven synchronously to RGTXC.

be used as a clock source to the PHY, so that the PHY may generate the RGRXC clock to be sent to EMAC. This clock is stopped while the device is in reset.

for receive operations. The RGRXD, and RGRXCTL signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation, 25 MHz at 100-Mbps operation, and 125 MHz at 1000-Mbps operation.

data. RGRDX0 is the least-significant bit (LSB). The signals are synchronized by RGRXC and valid only when RGRXCTL is asserted. The lower 4 bits of data are received on the rising edge of the clock, and the higher 4 bits of data are received on the falling edge of the RGRXC.

EMAC Functional Architecture

Table 10. EMAC and MDIO Signals for RGMII Interface (continued)

Signal Name I/O Description

RGRXCTL I Receive control (RGRXCTL). The receive control data has the receive data valid (MRXDV) signal on

RGMDCLK O Management data clock (RGMDCLK). The RGMDIO data clock is sourced by the MDIO module. It

RGMDIO I/O Management data input output (RGMDIO). The RGMDIO pin drives PHY management data into and

RGMII pins are not multiplexed with other interfaces and are HSTL I/O having voltages different than other interfaces. (RGMII pins are 1.5-V/1.8-V HSTL I/O, whereas other interfaces are 3.3-V LVCMOS I/O). The unused pins of the RGMII PHY should be pulled down to avoid floating inputs.

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the rising edge of the receive clock, and a derivative of receive data valid and receive error (MRXER) on the falling edge of RGRXC. When receiving a valid frame with no errors, MRXDV = TRUE is generated as a logic high on the rising edge on RGRXC and MRXER = FALSE is generated as a logic high on the falling edge of RGRXC. When no frame is being received, MRXDV = FALSE is generated as a logic low on the rising edge of RGRXC and MRXER = FALSE is generated as a logic low on the falling edge of RGRXC. When receiving a valid frame with errors, MRXDV = TRUE is generated as a logic high on the rising edge of RGRXC and MRXER = TRUE is generated as a logic low on the falling edge of RGRXC.

synchronizes MDIO data access operations done on the RGMDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

out of the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address, register address, and data bit cycles. The RGMDIO pin acts as an output for everything except the data bit cycles, when the pin acts as an input for read operations.

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TX_CLK

TXD

TX_SYNC

RX_CLK

RXD

RX_SYNC

MDCLK

MDIO

EMAC

MDIO

System

core

Physical

layer

device

(PHY)

MHZ_125_CLK

125-MHz

zero-delay

clockbuffer

125-MHz

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EMAC Functional Architecture

2.3.5 Source Synchronous Serial Media Independent Interface (S3MII) Connections

Figure 6 shows a TCI6486/C6472 device with an integrated EMAC and MDIO interface via S3MII

connections connected to a PHY. The S3MII interface supports source synchronous 10-Mbps and 100-Mbps operations with full- and half-duplex support.

Figure 6. Ethernet Configuration with S3MII Interface

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EMAC Functional Architecture

Table 11 summarizes the individual EMAC and MDIO signals for the S3MII interface.

Signal Name I/O Description

TX_CLK O Transmit clock. The transmit clock is a continuous clock that provides the timing reference for

TX_SYNC O Transmit Synchronization. The TX_SYNC signal is used to synchronize the TXD data signal. This

TXD O Transmit Data. The transmit data is synchronized with a transmit clock and a transmit

RX_CLK I Transmit clock. The transmit clock is a continuous clock that provides the timing reference for

RX_SYNC I Receive Synchronization. The RX_SYNC signal is used to synchronize the RXD data signal. This

RXD I Receive Data. The receive data is synchronized with a receive clock and a receive synchronization

MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module. It

MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of

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Table 11. EMAC and MDIO Signals for S3MII Interface

transmit operations. The TXD and TX_SYNC signals are tied to this clock. This clock is 125 MHz at 10- and 100-Mbps operations.

signal is synchronized with a 125-MHz clock.

synchronization signal.

transmit operations. The RXD and RX_SYNC signals are tied to this clock. This clock is 125 MHz at 10- and 100-Mbps operations.

signal is synchronized with a 125-MHz clock.

signal.

synchronizes MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

the PHY via an access frame consisting of start-of-frame, read/write indication, PHY address, register address, and data-bit cycles. The MDIO pin acts as an output for everything except the data-bit cycles, when the pin acts as an input for read operations.

The TCI6486/C6472 device S3MII pins are multiplexed with other non-RGMII pins. When using the S3MII0 port on EMAC0, there are no restrictions on the available EMAC1 Ethernet interfaces (RMII1, S3MII1, and RGMII1 are useable). When using the S3MII1 port on EMAC1, the EMAC0 Ethernet interfaces not available due to pin multiplexing are GMII0/MII0. The RMII0, S3MII0, and RGMII0 ports are available on EMAC0 Ethernet interfaces.

In a multi-PHY situation, where PHY has only one TX_SYNC for all ports, external logic is needed to synchronize the TX_SYNC signals from multiple ports or TCI6486/C6472 devices. The TXD signal from the multiple ports should also be synchronized using external logic since the clock-phase relation of different TCI6486/C6472 devices can be different. Figure 7 demonstrates the example mutli-PHY configuration for S3MII.

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TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #1

TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #2

TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #n

125-MHz

zero-delay

clock buffer

125-MHz

Low-skew

buffer

Zero-delay

clock buffer

External

logic

element

S3MII

multi-PHY

TX_CLK

TX_SYNC

P0_TXD

P0_RXD

P1_TXD

P1_RXD

Pn_TXD

Pn_RXD

RX_SYNC

RX_CLK

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EMAC Functional Architecture

Figure 7. S3MII Multi-PHY Configuration

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TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #1

TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #2

TXD

TX_SYNC

TX_CLK

RXD

RX_SYNC

RX_CLK

MHZ_125_CLK

Device #n

125-MHz

zero-delay

clock buffer

125-MHz

Low-skew

buffer

Zero-delay

clock buffer

External

logic

element

S3MII

switch

TX_CLK

TX_SYNC

P0_TXD

P0_RXD

P1_TXD

P1_RXD

Pn_TXD

Pn_RXD

RX_SYNC

RX_CLK

EMAC Functional Architecture

In the case of the S3MII switch, where the switch has only one TX_SYNC for all ports, external logic is needed to synchronize the TX_SYNC signals from multiple ports or TCI6486/C6472 devices. The TXD signal from the multiple ports should also be synchronized using external logic since the clock-phase relation of different TCI6486/C6472 devices can be different. Figure 8 demonstrates the example mutli-PHY configuration for S3MII.

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Figure 8. S3MII Switch Configuration

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Preamble

SFD

Destination

Source

Len Data

7 1 6 6 2 46 − (RXMAXLEN - 18) 4

FCS

Number of bytes

Legend: SFD = Start Frame Delimiter; FCS = Frame Check Sequence (CRC)

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2.4 Ethernet Protocol Overview

Ethernet provides a reliable, connectionless service to a networking application. A brief overview of the ethernet protocol follows. For more information on the carrier sense multiple access with collision detection (CSMA/CD) access method (ethernet's multiple access protocol), see the IEEE 802.3 standard document.

2.4.1 Ethernet Frame Format

All the ethernet technologies use the same frame structure. The format of an ethernet frame is shown in

Figure 9 and described in Table 12. The ethernet packet is the collection of bytes representing the data

portion of a single ethernet frame on the wire (shown outlined in bold in Figure 9). The ethernet frames are of variable lengths, with no frame smaller than 64 bytes or larger than

RXMAXLEN bytes (header, data, and CRC).

EMAC Functional Architecture

Figure 9. Ethernet Frame

Table 12. Ethernet Frame Description

Field Bytes Description

Preamble 7 These 7 bytes have a fixed value of 55h. They wake up the receiving EMAC ports and

Start-of-Frame 1 This field with a value of 5Dh immediately follows the preamble pattern and indicates Delimiter the start of important data.

Destination 6 This field contains the Ethernet MAC address of the intended EMAC port for the frame. address It may be an individual or multicast (including broadcast) address. If the destination

Source 6 This field contains the MAC address of the Ethernet port that transmits the frame to the address Local Area Network.

Len 2 The length field indicates the number of EMAC client data bytes contained in the

Data 46 to (RXMAXLEN - 18) This field carries the datagram containing the upper layer protocol frame (the IP layer

Frame Check 4 A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to Sequence generate a CRC value for the FCS field. The frame check sequence covers the 60 to

synchronize their clocks to that of the sender's clock.

EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses, and no promiscuous, multicast or broadcast channel is enabled, it discards the frame.

subsequent data field of the frame. This field can also be used to identify the data type carried by the frame.

datagram). The maximum transfer unit (MTU) of Ethernet is (RXMAXLEN - 18) bytes. Therefore, if the upper layer protocol datagram exceeds (RXMAXLEN - 18) bytes, the host must fragment the datagram and send it in multiple Ethernet packets. The minimum size of the data field is 46 bytes. Thus, if the upper layer datagram is less then 46 bytes, the data field must be extended to 46 bytes by appending extra bits after the data field, but prior to calculating and appending the FCS.

(RXMAXLEN - 4) bytes of the packet data. Note that the 4-byte FCS field may not be included as part of the packet data, depending on the EMAC configuration.

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EMAC Functional Architecture

2.4.2 Multiple Access Protocol

Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium, because there are exactly two ports on the local network.

Each port runs the CSMA/CD protocol without explicit coordination with the other ports on the ethernet network.

Within a specific port, the CSMA/CD protocol is as follows:

1. The port obtains data from upper layer protocols at its node, prepares an ethernet frame, and puts the frame in a buffer.

2. If the port senses that the medium is idle, it starts to transmit the frame. If the port senses that the transmission medium is busy, it waits until it senses no signal energy (plus an inter-packet gap time) and then starts to transmit the frame.

3. While transmitting, the port monitors for the presence of signal energy coming from other ports. If the port transmits the entire frame without detecting signal energy from other ethernet devices, the port is finished with the frame.

4. If the port detects signal energy from other ports while transmitting, it stops transmitting its frame and instead transmits a 48-bit jam signal.

5. After transmitting the jam signal, the port enters an exponential back off phase. Specifically, when transmitting a given frame, after experiencing a number of collisions in a row for the frame, the port chooses a random value that is dependent on the number of collisions. The port then waits an amount of time which is multiple of this random value, and returns to Step 1.

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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010

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+ 130 hidden pages

Texas Instruments TMS320TCI6486 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SPRUEF8F–March 2006–Revised November 2010 Table of Contents

Preface

1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

1.3 Functional Block Diagram

1.4 Industry Standard(s) Compliance Statement

2 EMAC Functional Architecture

2.1 Clock Control

2.1.1 MII Clocking

2.1.2 RMII Clocking

2.1.3 GMII Clocking

2.1.4 RGMII Clocking

2.1.5 S3MII Clocking

2.2 Memory Map

2.3 System-Level Connections

2.3.1 Media Independent Interface (MII) Connections

2.3.2 Reduced Media Independent Interface (RMII) Connections

2.3.3 Gigabit Media Independent Interface (GMII) Connections

2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections

2.3.5 Source Synchronous Serial Media Independent Interface (S3MII) Connections

2.4 Ethernet Protocol Overview

2.4.1 Ethernet Frame Format

2.4.2 Multiple Access Protocol