Texas Instruments TMS320F2802 User Manual

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

Digital Signal Processors

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS230N

October 2003–Revised May 2012

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Contents

1 F280x, F2801x, C280x DSPs .................................................................................................. 8

1.1 Features ...................................................................................................................... 8

1.2 Getting Started .............................................................................................................. 9

2 Introduction ...................................................................................................................... 10

2.1 Pin Assignments ........................................................................................................... 13

2.2 Signal Descriptions ........................................................................................................ 18

3 Functional Overview .......................................................................................................... 24

3.1 Memory Maps .............................................................................................................. 25

3.2 Brief Descriptions .......................................................................................................... 33

3.2.1 C28x CPU ....................................................................................................... 33

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 33

3.2.3 Peripheral Bus .................................................................................................. 33

3.2.4 Real-Time JTAG and Analysis ................................................................................ 34

3.2.5 Flash ............................................................................................................. 34

3.2.6 ROM .............................................................................................................. 34

3.2.7 M0, M1 SARAMs ............................................................................................... 34

3.2.8 L0, L1, H0 SARAMs ............................................................................................ 35

3.2.9 Boot ROM ....................................................................................................... 35

3.2.10 Security .......................................................................................................... 36

3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 37

3.2.12 External Interrupts (XINT1, XINT2, XNMI) .................................................................. 37

3.2.13 Oscillator and PLL .............................................................................................. 37

3.2.14 Watchdog ........................................................................................................ 37

3.2.15 Peripheral Clocking ............................................................................................. 37

3.2.16 Low-Power Modes .............................................................................................. 37

3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 38

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 38

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 38

3.2.20 Control Peripherals ............................................................................................. 38

3.2.21 Serial Port Peripherals ......................................................................................... 39

3.3 Register Map ............................................................................................................... 39

3.4 Device Emulation Registers .............................................................................................. 41

3.5 Interrupts .................................................................................................................... 41

3.5.1 External Interrupts .............................................................................................. 44

3.6 System Control ............................................................................................................ 45

3.6.1 OSC and PLL Block ............................................................................................ 46

3.6.1.1 External Reference Oscillator Clock Option .................................................... 47

3.6.1.2 PLL-Based Clock Module ......................................................................... 48

3.6.1.3 Loss of Input Clock ................................................................................ 49

3.6.2 Watchdog Block ................................................................................................. 50

3.7 Low-Power Modes Block ................................................................................................. 51

4 Peripherals ....................................................................................................................... 52

4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 52

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 54

4.3 Hi-Resolution PWM (HRPWM) .......................................................................................... 57

4.4 Enhanced CAP Modules (eCAP1/2/3/4) ............................................................................... 57

4.5 Enhanced QEP Modules (eQEP1/2) .................................................................................... 60

4.6 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 62

4.6.1 ADC Connections if the ADC Is Not Used .................................................................. 65

4.6.2 ADC Registers .................................................................................................. 66

4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 67

2 Contents Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) ................................................... 72

4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) .......................................... 75

4.10 Inter-Integrated Circuit (I2C) ............................................................................................. 79

4.11 GPIO MUX ................................................................................................................. 81

5 Device Support ................................................................................................................. 85

5.1 Device and Development Support Tool Nomenclature ............................................................... 85

5.2 Documentation Support .................................................................................................. 87

5.3 Community Resources .................................................................................................... 92

6 Electrical Specifications ..................................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .................................................................................. 94

6.3 Electrical Characteristics ................................................................................................. 94

6.4 Current Consumption ..................................................................................................... 95

6.4.1 Reducing Current Consumption .............................................................................. 99

6.4.2 Current Consumption Graphs ............................................................................... 100

6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 102

6.6 Timing Parameter Symbology .......................................................................................... 103

6.6.1 General Notes on Timing Parameters ...................................................................... 103

6.6.2 Test Load Circuit .............................................................................................. 103

6.6.3 Device Clock Table ........................................................................................... 104

6.7 Clock Requirements and Characteristics ............................................................................. 105

6.8 Power Sequencing ....................................................................................................... 106

6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 106

6.9 General-Purpose Input/Output (GPIO) ................................................................................ 109

6.9.1 GPIO - Output Timing ........................................................................................ 109

6.9.2 GPIO - Input Timing .......................................................................................... 110

6.9.3 Sampling Window Width for Input Signals ................................................................. 111

6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 112

6.10 Enhanced Control Peripherals ......................................................................................... 115

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 115

6.10.2 Trip-Zone Input Timing ....................................................................................... 115

6.10.3 External Interrupt Timing ..................................................................................... 117

6.10.4 I2C Electrical Specification and Timing .................................................................... 118

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing ................................................... 118

6.10.6 SPI Slave Mode Timing ...................................................................................... 123

6.10.7 On-Chip Analog-to-Digital Converter ....................................................................... 125

6.10.7.1 ADC Power-Up Control Bit Timing ............................................................. 126

6.10.7.2 Definitions ......................................................................................... 127

6.10.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................... 128

6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .............................. 129

6.11 Detailed Descriptions .................................................................................................... 130

6.12 Flash Timing .............................................................................................................. 131

6.13 ROM Timing (C280x only) .............................................................................................. 133

7 Migrating From F280x Devices to C280x Devices ................................................................. 134

7.1 Migration Issues .......................................................................................................... 134

8 Revision History .............................................................................................................. 135

9 Mechanical Data .............................................................................................................. 136

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Copyright © 2003–2012, Texas Instruments Incorporated Contents 3

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

List of Figures

2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................ 14

2-2 TMS320F2806 100-Pin PZ LQFP (Top View)................................................................................ 15

2-3 TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View) ..................... 16

2-4 TMS320F2801x 100-Pin PZ LQFP (Top View) .............................................................................. 17

2-5 TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801

100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)................................................................. 17

3-1 Functional Block Diagram....................................................................................................... 25

3-2 F2809 Memory Map.............................................................................................................. 26

3-3 F2808 Memory Map.............................................................................................................. 27

3-4 F2806 Memory Map.............................................................................................................. 28

3-5 F2802, C2802 Memory Map .................................................................................................... 29

3-6 F2801, F28015, F28016, C2801 Memory Map............................................................................... 29

3-7 External and PIE Interrupt Sources............................................................................................ 43

3-8 Multiplexing of Interrupts Using the PIE Block ............................................................................... 43

3-9 Clock and Reset Domains ...................................................................................................... 45

3-10 OSC and PLL Block Diagram................................................................................................... 46

3-11 Using a 3.3-V External Oscillator............................................................................................... 47

3-12 Using a 1.8-V External Oscillator............................................................................................... 47

3-13 Using the Internal Oscillator .................................................................................................... 47

3-14 Watchdog Module................................................................................................................ 50

4-1 CPU-Timers....................................................................................................................... 52

4-2 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 53

4-3 Multiple PWM Modules in a 280x System .................................................................................... 54

4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections.................................................. 56

4-5 eCAP Functional Block Diagram ............................................................................................... 58

4-6 eQEP Functional Block Diagram............................................................................................... 60

4-7 Block Diagram of the ADC Module ............................................................................................ 63

4-8 ADC Pin Connections With Internal Reference .............................................................................. 64

4-9 ADC Pin Connections With External Reference ............................................................................. 65

4-10 eCAN Block Diagram and Interface Circuit ................................................................................... 68

4-11 eCAN-A Memory Map ........................................................................................................... 69

4-12 eCAN-B Memory Map ........................................................................................................... 70

4-13 Serial Communications Interface (SCI) Module Block Diagram............................................................ 74

4-14 SPI Module Block Diagram (Slave Mode) .................................................................................... 78

4-15 I2C Peripheral Module Interfaces .............................................................................................. 80

4-16 GPIO MUX Block Diagram...................................................................................................... 81

4-17 Qualification Using Sampling Window......................................................................................... 84

5-1 Example of TMS320x280x/2801x Device Nomenclature ................................................................... 86

6-1 Typical Operational Current Versus Frequency (F2808) .................................................................. 100

6-2 Typical Operational Power Versus Frequency (F2808).................................................................... 100

6-3 Typical Operational Current Versus Frequency (C280x).................................................................. 101

6-4 Typical Operational Power Versus Frequency (C280x) ................................................................... 101

6-5 Emulator Connection Without Signal Buffering for the DSP .............................................................. 102

6-6 3.3-V Test Load Circuit......................................................................................................... 103

6-7 Clock Timing..................................................................................................................... 106

6-8 Power-on Reset ................................................................................................................. 107

4 List of Figures Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

6-9 Warm Reset ..................................................................................................................... 108

6-10 Example of Effect of Writing Into PLLCR Register......................................................................... 109

6-11 General-Purpose Output Timing.............................................................................................. 110

6-12 Sampling Mode ................................................................................................................. 110

6-13 General-Purpose Input Timing................................................................................................ 111

6-14 IDLE Entry and Exit Timing.................................................................................................... 112

6-15 STANDBY Entry and Exit Timing Diagram.................................................................................. 113

6-16 HALT Wake-Up Using GPIOn................................................................................................. 114

6-17 PWM Hi-Z Characteristics..................................................................................................... 115

6-18 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 117

6-19 External Interrupt Timing....................................................................................................... 117

6-20 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 120

6-21 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 122

6-22 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 124

6-23 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125

6-24 ADC Power-Up Control Bit Timing ........................................................................................... 126

6-25 ADC Analog Input Impedance Model ........................................................................................ 127

6-26 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 128

6-27 Simultaneous Sampling Mode Timing ....................................................................................... 129

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Copyright © 2003–2012, Texas Instruments Incorporated List of Figures 5

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

List of Tables

2-1 Hardware Features (100-MHz Devices)....................................................................................... 11

2-2 Hardware Features (60-MHz Devices) ........................................................................................ 12

2-3 Signal Descriptions............................................................................................................... 18

3-1 Addresses of Flash Sectors in F2809 ......................................................................................... 30

3-2 Addresses of Flash Sectors in F2808 ......................................................................................... 30

3-3 Addresses of Flash Sectors in F2806, F2802................................................................................ 30

3-4 Addresses of Flash Sectors in F2801, F28015, F28016.................................................................... 31

3-5 Impact of Using the Code Security Module................................................................................... 31

3-6 Wait-states ........................................................................................................................ 32

3-7 Boot Mode Selection............................................................................................................. 35

3-8 Peripheral Frame 0 Registers .................................................................................................. 40

3-9 Peripheral Frame 1 Registers .................................................................................................. 40

3-10 Peripheral Frame 2 Registers .................................................................................................. 41

3-11 Device Emulation Registers..................................................................................................... 41

3-12 PIE Peripheral Interrupts ....................................................................................................... 43

3-13 PIE Configuration and Control Registers...................................................................................... 44

3-14 External Interrupt Registers..................................................................................................... 44

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 46

3-16 PLLCR Register Bit Definitions................................................................................................. 48

3-17 Possible PLL Configuration Modes ............................................................................................ 49

3-18 Low-Power Modes ............................................................................................................... 51

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 53

4-2 ePWM Control and Status Registers .......................................................................................... 55

4-3 eCAP Control and Status Registers ........................................................................................... 59

4-4 eQEP Control and Status Registers ........................................................................................... 61

4-5 ADC Registers ................................................................................................................... 66

4-6 3.3-V eCAN Transceivers ...................................................................................................... 68

4-7 CAN Register Map .............................................................................................................. 71

4-8 SCI-A Registers .................................................................................................................. 73

4-9 SCI-B Registers .................................................................................................................. 73

4-10 SPI-A Registers................................................................................................................... 76

4-11 SPI-B Registers................................................................................................................... 76

4-12 SPI-C Registers .................................................................................................................. 77

4-13 SPI-D Registers .................................................................................................................. 77

4-14 I2C-A Registers................................................................................................................... 80

4-15 GPIO Registers .................................................................................................................. 82

4-16 F2808 GPIO MUX Table ........................................................................................................ 83

5-1 TMS320x280x, 2801x Peripheral Selection Guide .......................................................................... 87

6-1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT........... 95

6-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............................. 96

6-3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT........... 97

6-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .......... 98

6-5 Typical Current Consumption by Various Peripherals (at 100 MHz) ..................................................... 99

6-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)..................................................... 104

6-7 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices) .............................................. 104

6-8 Input Clock Frequency ......................................................................................................... 105

6-9 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 105

6 List of Tables Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

6-10 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 105

6-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 105

6-12 Power Management and Supervisory Circuit Solutions ................................................................... 106

6-13 Reset (XRS) Timing Requirements .......................................................................................... 108

6-14 General-Purpose Output Switching Characteristics........................................................................ 109

6-15 General-Purpose Input Timing Requirements .............................................................................. 110

6-16 IDLE Mode Timing Requirements ........................................................................................... 112

6-17 IDLE Mode Switching Characteristics ....................................................................................... 112

6-18 STANDBY Mode Timing Requirements ..................................................................................... 113

6-19 STANDBY Mode Switching Characteristics ................................................................................ 113

6-20 HALT Mode Timing Requirements ........................................................................................... 114

6-21 HALT Mode Switching Characteristics ...................................................................................... 114

6-22 ePWM Timing Requirements ................................................................................................. 115

6-23 ePWM Switching Characteristics ............................................................................................ 115

6-24 Trip-Zone input Timing Requirements ....................................................................................... 115

6-25 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz ................................................ 116

6-26 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 116

6-27 eCAP Switching Characteristics ............................................................................................. 116

6-28 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 116

6-29 eQEP Switching Characteristics ............................................................................................. 116

6-30 External ADC Start-of-Conversion Switching Characteristics............................................................. 117

6-31 External Interrupt Timing Requirements .................................................................................... 117

6-32 External Interrupt Switching Characteristics ................................................................................ 117

6-33 I2C Timing ...................................................................................................................... 118

6-34 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 119

6-35 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 121

6-36 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 123

6-37 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 124

6-38 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 125

6-39 ADC Power-Up Delays......................................................................................................... 126

6-40 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) ..................................... 126

6-41 Sequential Sampling Mode Timing ........................................................................................... 128

6-42 Simultaneous Sampling Mode Timing ....................................................................................... 129

6-43 Flash Endurance for A and S Temperature Material ...................................................................... 131

6-44 Flash Endurance for Q Temperature Material .............................................................................. 131

6-45 Flash Parameters at 100-MHz SYSCLKOUT............................................................................... 131

6-46 Flash/OTP Access Timing .................................................................................................... 132

6-47 Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 132

6-48 ROM/OTP Access Timing .................................................................................................... 133

6-49 ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies..................................... 133

9-1 F280x Thermal Model 100-pin GGM Results............................................................................... 136

9-2 F280x Thermal Model 100-pin PZ Results.................................................................................. 136

9-3 C280x Thermal Model 100-pin GGM Results............................................................................... 136

9-4 C280x Thermal Model 100-pin PZ Results.................................................................................. 136

9-5 F2809 Thermal Model 100-pin GGM Results .............................................................................. 136

9-6 F2809 Thermal Model 100-pin PZ Results ................................................................................. 137

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Copyright © 2003–2012, Texas Instruments Incorporated List of Tables 7

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Digital Signal Processors

Check for Samples: TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,

1 F280x, F2801x, C280x DSPs

1.1 Features

1234

• High-Performance Static CMOS Technology • 128-Bit Security Key/Lock

– 100 MHz (10-ns Cycle Time) – Protects Flash/OTP/L0/L1 Blocks
– 60 MHz (16.67-ns Cycle Time) – Prevents Firmware Reverse Engineering
– Low-Power (1.8-V Core, 3.3-V I/O) Design • Three 32-Bit CPU Timers

• JTAG Boundary Scan Support

• High-Performance 32-Bit CPU ( TMS320C28x™) – Up to 16 PWM Outputs

– 16 x 16 and 32 x 32 MAC Operations – Up to 6 HRPWM Outputs With 150-ps MEP
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)

• On-Chip Memory

– F2809: 128K x 16 Flash, 18K x 16 SARAM

F2808: 64K x 16 Flash, 18K x 16 SARAM – One Inter-Integrated-Circuit (I2C) Bus
F2806: 32K x 16 Flash, 10K x 16 SARAM
F2802: 32K x 16 Flash, 6K x 16 SARAM
F2801: 16K x 16 Flash, 6K x 16 SARAM

F2801x: 16K x 16 Flash, 6K x 16 SARAM
– 1K x 16 OTP ROM (Flash Devices Only)
– C2802: 32K x 16 ROM, 6K x 16 SARAM

C2801: 16K x 16 ROM, 6K x 16 SARAM

• Boot ROM (4K x 16)
– With Software Boot Modes (via SCI, SPI,

CAN, I2C, and Parallel I/O)

– Standard Math Tables

• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module

• Any GPIO A Pin Can Be Connected to One of
the Three External Core Interrupts

• Peripheral Interrupt Expansion (PIE) Block That
Supports All 43 Peripheral Interrupts

• Endianness: Little Endian

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320C28x, Code Composer Studio, DSP/BIOS, MicroStar BGA, C28x, TI, TMS320C2000 are trademarks of Texas

Instruments.

3eZdsp is a trademark of Spectrum Digital.
4All other trademarks are the property of their respective owners.

Copyright © 2003–2012, Texas Instruments Incorporated

TMS320C2801, TMS320F28016, TMS320F28015

(1)

• Enhanced Control Peripherals

Resolution
– Up to Four Capture Inputs
– Up to Two Quadrature Encoder Interfaces
– Up to Six 32-bit/Six 16-bit Timers

• Serial Port Peripherals
– Up to 4 SPI Modules
– Up to 2 SCI (UART) Modules
– Up to 2 CAN Modules

• 12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Fast Conversion Rate:

80 ns - 12.5 MSPS (F2809 only)
160 ns - 6.25 MSPS (280x)
267 ns - 3.75 MSPS (F2801x)

– Internal or External Reference

• Up to 35 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering

• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware

• Development Support Includes
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– Digital Motor Control and Digital Power

Software Libraries

• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks

PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

• Package Options • Temperature Options
– Thin Quad Flatpack (PZ) – A: –40°C to 85°C (PZ, GGM, ZGM)
– MicroStar BGA™ (GGM, ZGM) – S: –40°C to 125°C (PZ, GGM, ZGM)

– Q: –40°C to 125°C (PZ)

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x™ device. For
more detail on each of these steps, see the following:

• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

Step 1. Acquire the appropriate development tools

The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial
development, which, in one package, includes:

• On-board JTAG emulation via USB or parallel port

• Appropriate emulation driver

• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own

hardware, purchase Code Composer Studio™ IDE separately for software development and
a JTAG emulation tool to get started on your project.

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Step 2. Download starter software

To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.

After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software

• The Quick Start Readme in the /doc directory to run your first application.

• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report
(literature number SPRAA85)

Step 3. Download flash programming software

Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.

• Flash Tools: C28x Flash Tools

• TMS320F281x™ Flash Programming Solutions (literature number SPRB169)

• Running an Application from Internal Flash Memory on the TMS320F28xxx DSP
(literature number SPRA958)

Step 4. Move on to more advanced topics

For more application software and other advanced topics, visit the TI™ website at

http://www.ti.com or http://www.ti.com/c2000getstarted.

Copyright © 2003–2012, Texas Instruments Incorporated F280x, F2801x, C280x DSPs 9

Submit Documentation Feedback

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

2 Introduction

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,
TMS320F28016, TMS320C2802, and TMS320C2801 devices, members of the TMS320C28x™ DSP
generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802,
TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS320F28016 are abbreviated as
F2809, F2808, F2806, F2802, F2801, C2802, C2801, F28015, and F28016, respectively. TMS320F28015
and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for each
device.

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 2-1. Hardware Features (100-MHz Devices)

FEATURE TYPE

Instruction cycle (at 100 MHz) – 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

Single-access RAM (SARAM) (16-bit word) – (L0, L1, M0, M1, (L0, L1, M0, M1,

3.3-V on-chip flash (16-bit word) – 128K 64K 32K 32K 16K – –
On-chip ROM (16-bit word) – – – – – – 32K 16K
Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes Yes Yes Yes
Boot ROM (4K x 16) – Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM

(16-bit word)
PWM outputs 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3

HRPWM channels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A
32-bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2

32-bit QEP channels (four inputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes
12-Bit, 16-channel ADC conversion time 1 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns
32-Bit CPU timers – 3 3 3 3 3 3 3
Serial Peripheral Interface (SPI) 0 SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B
Serial Communications Interface (SCI) 0 SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) 0 eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A
Inter-Integrated Circuit (I2C) 0 I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) – 35 35 35 35 35 35 35
External interrupts – 3 3 3 3 3 3 3
Supply voltage 1.8-V Core, 3.3-V I/O – Yes Yes Yes Yes Yes Yes Yes

Packaging

Temperature options S: –40°C to 125°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Product status

(2)

100-Pin PZ – Yes Yes Yes Yes Yes Yes Yes
100-Ball GGM, ZGM – Yes Yes Yes Yes Yes Yes Yes
A: –40°C to 85°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: –40°C to 125°C – (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ)

(1)

– 1K 1K 1K 1K 1K – –

– TMS TMS TMS TMS TMS TMS TMS

F2809 F2808 F2806 F2802 F2801 C2802 C2801

18K 18K
H0) H0)

ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/

4A/5A/6A 3A/4A 3A/4A

10K 6K 6K 6K 6K

(L0, L1, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.

(2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

Copyright © 2003–2012, Texas Instruments Incorporated Introduction 11

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 2-2. Hardware Features (60-MHz Devices)

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FEATURE TYPE

Instruction cycle (at 60 MHz) – 16.67 ns 16.67 ns 16.67 ns 16.67 ns
Single-access RAM (SARAM) (16-bit word) –

3.3-V on-chip flash (16-bit word) – 32K 16K 16K 16K
On-chip ROM (16-bit word) – – – – –
Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes
Boot ROM (4K x 16) – Yes Yes Yes Yes
One-time programmable (OTP) ROM

(16-bit word)
PWM outputs 0 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4
HRPWM channels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A
32-bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2
32-bit QEP channels (four inputs/channel) 0 eQEP1 eQEP1 - ­Watchdog timer – Yes Yes Yes Yes

No. of channels 16 16 16 16

12-Bit ADC MSPS 1 3.75 3.75 3.75 3.75

Conversion time 267 ns 267 ns 267 ns 267 ns
32-Bit CPU timers – 3 3 3 3
Serial Peripheral Interface (SPI) 0 SPI-A/B SPI-A/B SPI-A SPI-A
Serial Communications Interface (SCI) 0 SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) 0 eCAN-A eCAN-A eCAN-A ­Inter-Integrated Circuit (I2C) 0 I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) – 35 35 35 35
External interrupts – 3 3 3 3

Supply voltage –

Packaging

Temperature options S: –40°C to 125°C – (PZ GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Product status

(2)

100-Pin PZ – Yes Yes Yes Yes

100-Ball GGM, ZGM – Yes Yes Yes Yes

A: –40°C to 85°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: –40°C to 125°C – (PZ) (PZ) (PZ) (PZ)

(1)

– 1K 1K 1K 1K

– TMS TMS TMS TMS

F2802-60 F2801-60 F28016 F28015

6K 6K 6K 6K

(L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,

3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.

(2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

12 Introduction Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

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GPIO0/EPWM1A

XRS

TRST

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO13/ /CANRXB/SPISOMIBTZ2

V

DD3VFL

V

DD

V

DD

V

DDIO

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

EMU1

EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

TCK

GPIO12/ /CANTXB/SPISIMOBTZ1

GPIO14/ /SCITXDB/SPICLKBTZ3

GPIO15/ /SCIRXDB/SPISTEBTZ4

GPIO30/CANRXA

ADCINA3

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA2

ADCINA1

ADCINA0

ADCLO

GPIO31/CANTXA

GPIO29/SCITXDA//TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO4/EPWM3A

GPIO17/SPISOMIA/CANRXB/TZ6

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO18/SPICLKA/SCITXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO19/SPISTEA/SCIRXDB

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO20/EQEP1A/SPISIMOC/CANTXB

GPIO10/EPWM6A/CANRXB/ADCSOCBO

GPIO8/EPWM5A/CANTXB/ADCSOCAO

XCLKOUT

GPIO21/EQEP1B/SPISOMIC/CANRXB

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS1AGND

V

SSA2

V

SSAIO

V

DD

V

DDA2

V

DD1A18

V

DDIO

V

DD

V

DD

V

DDIO

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO22/EQEP1S/SPICLKC/SCITXDB

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B/SPISIMOD

GPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID

GPIO16/SPISIMOA/CANTXB/TZ5

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO28/SCIRXDA/TZ5

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2.1 Pin Assignments

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4. The 100-ball GGM and ZGM
ball grid array (BGA) terminal assignments are shown in Figure 2-5. Table 2-3 describes the function(s) of
each pin.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)

Copyright © 2003–2012, Texas Instruments Incorporated Introduction 13

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TMS320C2801 TMS320F28016 TMS320F28015

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100

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3

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21

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25

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GPIO0/EPWM1A

XRS

TRST

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO13/ /SPISOMIBTZ2

V

DD3VFL

V

DD

V

DD

V

DDIO

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

EMU1

EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

TCK

GPIO12/ /SPISIMOBTZ1

GPIO14/ /SCITXDB/SPICLKBTZ3

GPIO15/ /SCIRXDB/SPISTEBTZ4

GPIO30/CANRXA

ADCINA3

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA2

ADCINA1

ADCINA0

ADCLO

GPIO31/CANTXA

GPIO29/SCITXDA//TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO4/EPWM3A

GPIO17/SPISOMIA/TZ6

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO18/SPICLKA/SCITXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO19/SPISTEA/SCIRXDB

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO20/EQEP1A/SPISIMOC

GPIO10/EPWM6A/ADCSOCBO

GPIO8/EPWM5A/ADCSOCAO

XCLKOUT

GPIO21/EQEP1B/SPISOMIC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS1AGND

V

SSA2

V

SSAIO

V

DD

V

DDA2

V

DD1A18

V

DDIO

V

DD

V

DD

V

DDIO

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO22/EQEP1S/SPICLKC/SCITXDB

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B/SPISIMOD

GPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID

GPIO16/SPISIMOA/TZ5

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO28/SCIRXDA/TZ5

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)

14 Introduction Copyright © 2003–2012, Texas Instruments Incorporated

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GPIO0/EPWM1A

XRS

TRST

V

DD2A18

V

SS2AGND

V

DDAIO

SPISOMIB/GPIO13/TZ2

V

DD3VFL

(A)

V

DD

V

DD

V

DDIO

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

SPICLKB/GPIO26

TEST2

TEST1

GPIO25/ECAP2/SPISOMIB

XCLKIN

X1

X2

EMU1

EMU0

SPISIMOB/GPIO24/ECAP1

SPISTEB/GPIO27

TDO

TCK

SPISIMOB/GPIO12/TZ1

SPICLKB/GPIO14/TZ3

SPISTEB/GPIO15/TZ4

GPIO30/CANRXA

ADCINA3

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA2

ADCINA1

ADCINA0

ADCLO

GPIO31/CANTXA

GPIO29/SCITXDA//TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO4/EPWM3A

GPIO17/SPISOMIA/TZ6

GPIO5/EPWM3B/ECAP1

GPIO18/SPICLKA

GPIO6/EPWMSYNCI/EPWMSYNCO

GPIO19/SPISTEA

GPIO7/ECAP2

GPIO9

GPIO20/EQEP1A

GPIO10/ADCSOCBO

GPIO8/ADCSOCAO

XCLKOUT

GPIO21/EQEP1B

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS1AGND

V

SSA2

V

SSAIO

V

DD

V

DDA2

V

DD1A18

V

DDIO

V

DD

V

DD

V

DDIO

GPIO11

GPIO22/EQEP1S

TMS

TDI

GPIO23/EQEP1I

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B

GPIO2/EPWM2A

GPIO3/EPWM2B

GPIO16/SPISIMOA/TZ5

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO28/SCIRXDA/TZ5

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. On the C280x devices, the V

Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)

DD3VFL

pin is V

DDIO

.

Copyright © 2003–2012, Texas Instruments Incorporated Introduction 15

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GPIO0/EPWM1A

XRS

TRST

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO13/TZ2

V

DD3VFL

V

DD

V

DD

V

DDIO

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

GPIO26

TEST2

TEST1

GPIO25/ECAP2

XCLKIN

X1

X2

EMU1

EMU0

GPIO24/ECAP1

GPIO27

TDO

TCK

GPIO12/TZ1

GPIO14/TZ3

GPIO15/TZ4

GPIO30/CANRXA

(A)

ADCINA3

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA2

ADCINA1

ADCINA0

ADCLO

GPIO31/CANTXA

(A)

GPIO29/SCITXDA//TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO4/EPWM3A

GPIO17/SPISOMIA/TZ6

GPIO5/EPWM3B/ECAP1

GPIO18/SPICLKA

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO19/SPISTEA

GPIO7/EPWM4B/ECAP2

GPIO9

GPIO20

GPIO10/ADCSOCBO

GPIO8/ADCSOCAO

XCLKOUT

GPIO21

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS1AGND

V

SSA2

V

SSAIO

V

DD

V

DDA2

V

DD1A18

V

DDIO

V

DD

V

DD

V

DDIO

GPIO11

GPIO22

TMS

TDI

GPIO23

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B

GPIO2/EPWM2A

GPIO3/EPWM2B

GPIO16/SPISIMOA/TZ5

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO28/SCIRXDA/TZ5

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.

Figure 2-4. TMS320F2801x 100-Pin PZ LQFP (Top View)

16 Introduction Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

4

C

B

A

D

E

21

3

K

F

G

H

J

5

7

6

98

10

Bottom View

TRST

TCK

TDI

TDO

TMS

EMU0

EMU1

V

DD3VFL

TEST1

TEST2

XCLKOUT

XCLKIN

X1

X2

XRS

GPIO0GPIO1

GPIO2 GPIO3 GPIO4

GPIO5

GPIO6GPIO7

GPIO9 GPIO8

GPIO10

GPIO11

GPIO12 GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23GPIO24GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30GPIO31

GPIO32

GPIO33

GPIO34

V

DDA2

V

DD1A18

V

SS1AGND

V

SSAIO

V

DDAIO

V

SSA2

ADCINA7

V

SS2AGND

V

DD2A18

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

ADCINB2

ADCINA6

ADCINA5ADCINA4 ADCINA3 ADCINA2

ADCINA1 ADCINA0

ADCINB7

ADCINB1

ADCINB0

ADCLO

ADCRESEXT

ADCREFIN

ADCREFP

ADCREFM

ADCINB3 ADCINB5

ADCINB4

ADCINB6

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801

100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

Copyright © 2003–2012, Texas Instruments Incorporated Introduction 17

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

Submit Documentation Feedback

TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

2.2 Signal Descriptions

Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-3. Signal Descriptions

PIN NO.

NAME DESCRIPTION

PIN #

TRST 84 A6 high test pin and must be maintained low at all times during normal device operation. An external

TCK 75 A10 JTAG test clock with internal pullup (I, ↑)
TMS 74 B10

TDI 73 C9

TDO 76 B9

EMU0 80 A8 (I/O/Z, 8 mA drive ↑)

EMU1 81 B7 (I/O/Z, 8 mA drive ↑)

V

DD3VFL

TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal

XCLKIN 90 B5 case, tie the X1 pin to GND. Alternately, when a crystal/resonator is used (or if an external 1.8-V

GGM/

PZ

96 C4

ZGM

BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active

pulldown resistor is required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it is recommended that each target board be validated
for proper operation of the debugger and the application. (I, ↓)

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to V

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is used to feed a clock from an external 3.3-V oscillator. In this
oscillator is fed into the X1 pin), tie the XCLKIN pin to GND. (I)

DDIO

(1)

.

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(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
18 Introduction Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

X2 86 C6

XRS 78 B8

ADCINA7 16 F3 ADC Group A, Channel 7 input (I)
ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)
ADCINA4 19 G1 ADC Group A, Channel 4 input (I)
ADCINA3 20 G2 ADC Group A, Channel 3 input (I)
ADCINA2 21 G3 ADC Group A, Channel 2 input (I)
ADCINA1 22 H1 ADC Group A, Channel 1 input (I)
ADCINA0 23 H2 ADC Group A, Channel 0 input (I)
ADCINB7 34 K5 ADC Group B, Channel 7 input (I)
ADCINB6 33 H4 ADC Group B, Channel 6 input (I)
ADCINB5 32 K4 ADC Group B, Channel 5 input (I)
ADCINB4 31 J4 ADC Group B, Channel 4 input (I)
ADCINB3 30 K3 ADC Group B, Channel 3 input (I)
ADCINB2 29 H3 ADC Group B, Channel 2 input (I)
ADCINB1 28 J3 ADC Group B, Channel 1 input (I)
ADCINB0 27 K2 ADC Group B, Channel 0 input (I)
ADCLO 24 J1 Low Reference (connect to analog ground) (I)
ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN 35 J5 External reference input (I)

ADCREFP 37 G5

ADCREFM 36 H5

PZ

GGM/

ZGM

BALL #

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.

ADC SIGNALS

Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of

2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.

Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of

2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.

SPRS230N –OCTOBER 2003–REVISED MAY 2012

(1)

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

PZ

GGM/

ZGM

BALL #

CPU AND I/O POWER PINS

V

DDA2

V

SSA2

V

DDAIO

V

SSAIO

V

DD1A18

V

SS1AGND

V

DD2A18

V

SS2AGND

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

GPIO0 General-purpose input/output 0 (I/O/Z)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

15 F2 ADC Analog Power Pin (3.3 V)
14 F1 ADC Analog Ground Pin
26 J2 ADC Analog I/O Power Pin (3.3 V)
25 K1 ADC Analog I/O Ground Pin
12 E4 ADC Analog Power Pin (1.8 V)
13 E5 ADC Analog Ground Pin
40 J6 ADC Analog Power Pin (1.8 V)
39 K6 ADC Analog Ground Pin
10 E2
42 G6
59 F10
68 D7

CPU and Logic Digital Power Pins (1.8 V)

85 B6
93 D4

3 C2
46 H7
65 E9

Digital I/O Power Pin (3.3 V)

82 A7

2 B1
11 E3
41 H6
49 K9
55 H10
62 F7 Digital Ground Pins
69 D10
77 A9
87 D6
89 A5
94 A4

GPIOA AND PERIPHERAL SIGNALS

47 K8

(1) (2)

(3)

- ­GPIO1 General-purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O)
SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801, 2802)

44 K7

(3)

- ­GPIO2 General-purpose input/output 2 (I/O/Z)

EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

45 J7

(3)

- -

(1) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.

(3) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

(1)

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO3 General-purpose input/output 3 (I/O/Z)
EPWM2B Enhanced PWM2 Output B (O)
SPISOMID SPI-D slave out, master in (I/O) (not available on 2801, 2802)

- ­GPIO4 General-purpose input/output 4 (I/O/Z)

EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- ­GPIO5 General-purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O)
SPICLKD SPI-D clock (I/O) (not available on 2801, 2802)
ECAP1 Enhanced capture input/output 1 (I/O)

GPIO6 General-purpose input/output 6 (I/O/Z)
EPWM4A Enhanced PWM4 output A and HRPWM channel (O) (not available on 2801, 2802)
EPWMSYNCI External ePWM sync pulse input (I)
EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General-purpose input/output 7 (I/O/Z)
EPWM4B Enhanced PWM4 output B (O) (not available on 2801, 2802)
SPISTED SPI-D slave transmit enable (I/O) (not available on 2801, 2802)
ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General-purpose input/output 8 (I/O/Z)
EPWM5A Enhanced PWM5 output A and HRPWM channel (O) (not available on 2801, 2802)
CANTXB Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General-purpose input/output 9 (I/O/Z)
EPWM5B Enhanced PWM5 output B (O) (not available on 2801, 2802)
SCITXDB SCI-B transmit data (O) (not available on 2801, 2802)
ECAP3 Enhanced capture input/output 3 (I/O) (not available on 2801, 2802)

GPIO10 General-purpose input/output 10 (I/O/Z)
EPWM6A Enhanced PWM6 output A and HRPWM channel (O) (not available on 2801, 2802)
CANRXB Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General-purpose input/output 11 (I/O/Z)
EPWM6B Enhanced PWM6 output B (O) (not available on 2801, 2802)
SCIRXDB SCI-B receive data (I) (not available on 2801, 2802)
ECAP4 Enhanced CAP Input/Output 4 (I/O) (not available on 2801, 2802)

GPIO12 General-purpose input/output 12 (I/O/Z)
TZ1 Trip Zone input 1 (I)
CANTXB Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
SPISIMOB SPI-B Slave in, Master out (I/O)

GPIO13 General-purpose input/output 13 (I/O/Z)
TZ2 Trip zone input 2 (I)
CANRXB Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
SPISOMIB SPI-B slave out, master in (I/O)

GPIO14 General-purpose input/output 14 (I/O/Z)
TZ3 Trip zone input 3 (I)
SCITXDB SCI-B transmit (O) (not available on 2801, 2802)
SPICLKB SPI-B clock input/output (I/O)

GPIO15 General-purpose input/output 15 (I/O/Z)
TZ4 Trip zone input 4 (I)
SCIRXDB SCI-B receive (I) (not available on 2801, 2802)
SPISTEB SPI-B slave transmit enable (I/O)

GPIO16 General-purpose input/output 16 (I/O/Z)
SPISIMOA SPI-A slave in, master out (I/O)
CANTXB Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
TZ5 Trip zone input 5 (I)

(1) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
(2) The pullups on GPIO12-GPIO34 are enabled upon reset.

GGM/

PZ

ZGM

BALL #

48 J8

51 J9

53 H9

56 G9

58 G8

60 F9

61 F8

64 E10

70 D9

1 B2

95 B4

8 D3

9 E1

50 K10

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(2)

(2)

(2)

(2)

(2)

SPRS230N –OCTOBER 2003–REVISED MAY 2012

(1)

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO17 General-purpose input/output 17 (I/O/Z)
SPISOMIA SPI-A slave out, master in (I/O)
CANRXB Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)

GGM/

PZ

ZGM

BALL #

52 J10

(1)

TZ6 Trip zone input 6 (I)
GPIO18 General-purpose input/output 18 (I/O/Z)

(1)

SPICLKA SPI-A clock input/output (I/O)
SCITXDB 54 H8 SCI-B transmit (O) (not available on 2801, 2802)

- -

- ­GPIO19 General-purpose input/output 19 (I/O/Z)

(1)

SPISTEA SPI-A slave transmit enable input/output (I/O)
SCIRXDB 57 G10 SCI-B receive (I) (not available on 2801, 2802)

- -

- ­GPIO20 General-purpose input/output 20 (I/O/Z)

EQEP1A Enhanced QEP1 input A (I)
SPISIMOC SPI-C slave in, master out (I/O) (not available on 2801, 2802)

63 F6

(1)

CANTXB Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
GPIO21 General-purpose input/output 21 (I/O/Z)

EQEP1B Enhanced QEP1 input A (I)
SPISOMIC SPI-C master in, slave out (I/O) (not available on 2801, 2802)

67 E7

(1)

CANRXB Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
GPIO22 General-purpose input/output 22 (I/O/Z)

EQEP1S Enhanced QEP1 strobe (I/O)
SPICLKC SPI-C clock (I/O) (not available on 2801, 2802)

71 D8

(1)

SCITXDB SCI-B transmit (O) (not available on 2801, 2802)
GPIO23 General-purpose input/output 23 (I/O/Z)

EQEP1I Enhanced QEP1 index (I/O)
SPISTEC SPI-C slave transmit enable (I/O) (not available on 2801, 2802)

72 C10

(1)

SCIRXDB SCI-B receive (I) (not available on 2801, 2802)
GPIO24 General-purpose input/output 24 (I/O/Z)

ECAP1 Enhanced capture 1 (I/O)
EQEP2A Enhanced QEP2 input A (I) (not available on 2801, 2802)

83 C7

(1)

SPISIMOB SPI-B slave in, master out (I/O)
GPIO25 General-purpose input/output 25 (I/O/Z)

ECAP2 Enhanced capture 2 (I/O)
EQEP2B Enhanced QEP2 input B (I) (not available on 2801, 2802)

91 C5

(1)

SPISOMIB SPI-B master in, slave out (I/O)
GPIO26 General-purpose input/output 26 (I/O/Z)

ECAP3 Enhanced capture 3 (I/O) (not available on 2801, 2802)
EQEP2I Enhanced QEP2 index (I/O) (not available on 2801, 2802)

99 A2

(1)

SPICLKB SPI-B clock (I/O)
GPIO27 General-purpose input/output 27 (I/O/Z)

ECAP4 Enhanced capture 4 (I/O) (not available on 2801, 2802)
EQEP2S Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)

79 C8

(1)

SPISTEB SPI-B slave transmit enable (I/O)
GPIO28 General-purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCIRXDA SCI receive data (I)

- -

92 D5

TZ5 Trip zone input 5 (I)
GPIO29 General-purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCITXDA SCI transmit data (O)

- -

4 C3

TZ6 Trip zone 6 input (I)

(1) The pullups on GPIO12-GPIO34 are enabled upon reset.

(1)

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(1)

(1)

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO30 General-purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)
CANRXA Enhanced CAN-A receive data (I)

- -

- ­GPIO31 General-purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)

CANTXA Enhanced CAN-A transmit data (O)

- -

- ­GPIO32 General-purpose input/output 32 (I/O/Z)

SDAA I2C data open-drain bidirectional port (I/OD)
EPWMSYNCI Enhanced PWM external sync pulse input (I)
ADCSOCAO ADC start-of-conversion (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z)
SCLA I2C clock open-drain bidirectional port (I/OD)
EPWMSYNCO Enhanced PWM external synch pulse output (O)
ADCSOCBO ADC start-of-conversion (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z)

- -

- -

- -

(1) The pullups on GPIO12-GPIO34 are enabled upon reset.

100 A1

GGM/

PZ

43 G7

ZGM

BALL #

6 D2

7 D1

5 C1

(1)

(1)

(1)

SPRS230N –OCTOBER 2003–REVISED MAY 2012

(1)

(1)

(1)

NOTE

Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2
for details.

Copyright © 2003–2012, Texas Instruments Incorporated Introduction 23

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TMS320C2801 TMS320F28016 TMS320F28015

INT[12:1]

Real-Time JTAG

(TDI, TDO, , TCK,

TMS, EMU0, EMU1)

TRST

C28x CPU
(100 MHz)

NMI, INT13

Memory Bus

INT14

SYSCLKOUT

RS

CLKIN

12-Bit ADC

ADCSOCA/B

SOCA/B

16 Channels

12

6

32

XCLKOUT

XRS

XCLKIN

X1

X2

32

System Control

(Oscillator, PLL,

Peripheral Clocking,

Low-Power Modes,

Watchdog)

ePWM1/2/3/4/5/6

(12 PWM Outputs,

6 Trip Zones,

6 16-bit Timers)

eCAP1/2/3/4

(4 32-bit Timers)

eQEP1/2

eCAN-A/B (32 mbox)

External Interrupt

Control

PIE

(96 Interrupts)

(A)

FIFO

FIFO

FIFO

SCI-A/B

GPIO MUX

I2C-A

SPI-A/B/C/D

4

8

4

2

16

4

GPIOs

(35)

TINT0

TINT1

TINT2

7

Peripheral Bus

M0 SARAM

1K x 16

M1 SARAM

1K x 16

Boot ROM

4K x 16

(1-wait state)

L0 SARAM

4K x 16
(0-wait)

L1 SARAM

4K x 16
(0-wait)

(B)

H0 SARAM

8K x 16
(0-wait)

(C)

ROM
32K x 16 (C2802)
16K x 16 (C2801)

FLASH

128K x 16 (F2809)

64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)

16K x 16 (F2801x)

OTP

1K x 16

(D)

Protected by the code-security module.

32-bit CPU TIMER 0

32-bit CPU TIMER 1

32-bit CPU TIMER 2

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3 Functional Overview

www.ti.com

A. 43 of the possible 96 interrupts are used on the devices.
B. Not available in F2802, F2801, C2802, and C2801.
C. Not available in F2806, F2802, F2801, C2802, and C2801.
D. The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.

Figure 3-1. Functional Block Diagram

24 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

0x00 0000

Block Start

Address

Data Space

Prog Space

M0 Vector − RAM (32 x 32)

(Enabled if VMAP = 0)

M1 SARAM (1K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x00 8000

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x00 9000

H0 SARAM (0-wait)

(8K y 16, Dual-Mapped)

0x00 A000

0x00 C000

OTP

(1K y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(128K y 16, Secure Zone)

0x3D 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8K y 16, Dual-Mapped)

0x3F A000

0x3F F000

Boot ROM (4K y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

Reserved

Reserved

Reserved

Reserved

Reserved

M0 SARAM (1K y 16)

0x00 0040

Reserved

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3.1 Memory Maps

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 25

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

Figure 3-2. F2809 Memory Map

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TMS320C2801 TMS320F28016 TMS320F28015

0x00 0000

Block Start

Address

Data Space

Prog Space

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x00 8000

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x00 9000

H0 SARAM (0-wait)

(8K y 16, Dual-Mapped)

0x00 A000

0x00 C000

OTP

(1K y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(64K y 16, Secure Zone)

0x3E 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8K y 16, Dual-Mapped)

0x3F A000

0x3F F000

Boot ROM (4K y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

M0 Vector − RAM (32 x 32)

(Enabled if VMAP = 0)

0x00 0040

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

26 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

A. Memory blocks are not to scale.

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

User program cannot access these memory maps in program space.

Figure 3-3. F2808 Memory Map

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TMS320C2801 TMS320F28016 TMS320F28015

0x00 0000

Block Start

Address

Data Space

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8
0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP

(1K y 16, Secure Zone)

FLASH

(32K y 16, Secure Zone)

Boot ROM (4K y 16)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

M1 SARAM (1K y 16)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

L1 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

128-bit Password

0x3F 0000

Prog Space

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

M0 SARAM (1K y 16)

M0 Vector − RAM (32 x 32)

(Enabled if VMAP = 0)

0x00 0040

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 27

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

Figure 3-4. F2806 Memory Map

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TMS320C2801 TMS320F28016 TMS320F28015

0x00 0000

Block Start

Address

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x3D 7800

0x3F 0000

0x3F 7FF8

0x3F 8000

0x3F 9000

0x3F F000

0x3F FFC0

OTP (F2802 Only)

(A)

(1K y 16, Secure Zone)

FLASH (F2802) or ROM (C2802)

(32K y 16, Secure Zone)

L0 (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

Boot ROM (4K y 16)

128-bit Password

Data Space Prog Space

0x3D 7C00

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

0x00 0040

M0 Vector − RAM (32 x 32)

(Enabled if VMAP = 0)

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 3-5 for more information.

28 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

User program cannot access these memory maps in program space.

Figure 3-5. F2802, C2802 Memory Map

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TMS320C2801 TMS320F28016 TMS320F28015

0x00 0000

Block Start

Address

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x3D 7800

0x3F 4000

0x3F 7FF8

0x3F 8000

0x3F 9000

0x3F F000

0x3F FFC0

OTP (F2801/F2801x Only)

(A)

(1K y 16, Secure Zone)

FLASH (F2801) or ROM (C2801)

(16K y 16, Secure Zone)

L0 (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

Boot ROM (4K y 16)

128-bit Password

Data Space Prog Space

0x3D 7C00

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

M1 SARAM (1K y 16)

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual-Mapped)

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

ЙЙЙЙЙ

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

Reserved

Reserved

Reserved

M0 SARAM (1K y 16)

M0 Vector − RAM (32 x 32)

(Enabled if VMAP = 0)

0x00 0040

Reserved

Reserved

Reserved

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 3-5 for more information.

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 29

User program cannot access these memory maps in program space.

Figure 3-6. F2801, F28015, F28016, C2801 Memory Map

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-1. Addresses of Flash Sectors in F2809

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000 – 0x3D BFFF Sector H (16K x 16)

0x3D C000 – 0x3D FFFF Sector G (16K x 16)

0x3E 0000 – 0x3E 3FFF Sector F (16K x 16)
0x3E 4000 – 0x3E 7FFF Sector E (16K x 16)
0x3E 8000 – 0x3E BFFF Sector D (16K x 16)

0x3E C000 – 0x3E FFFF Sector C (16K x 16)

0x3F 0000 – 0x3F 3FFF Sector B (16K x 16)
0x3F 4000 – 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

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Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 3-2. Addresses of Flash Sectors in F2808

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3E 8000 – 0x3E BFFF Sector D (16K x 16)

0x3E C000 – 0x3E FFFF Sector C (16K x 16)

0x3F 0000 – 0x3F 3FFF Sector B (16K x 16)
0x3F 4000 – 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 3-3. Addresses of Flash Sectors in F2806, F2802

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3F 0000 – 0x3F 1FFF Sector D (8K x 16)
0x3F 2000 – 0x3F 3FFF Sector C (8K x 16)
0x3F 4000 – 0x3F 5FFF Sector B (8K x 16)
0x3F 6000 – 0x3F 7F7F Sector A (8K x 16)

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

30 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-4. Addresses of Flash Sectors in F2801, F28015, F28016

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3F 4000 – 0x3F 4FFF Sector D (4K x 16)
0x3F 5000 – 0x3F 5FFF Sector C (4K x 16)
0x3F 6000 – 0x3F 6FFF Sector B (4K x 16)
0x3F 7000 – 0x3F 7F7F Sector A (4K x 16)
0x3F 7F80 – 0x3F 7FF5 Program to 0x0000 when using the

Code Security Module

0x3F 7FF6 – 0x3F 7FF7 Boot-to-Flash Entry Point

(program branch instruction here)

0x3F 7FF8 – 0x3F 7FFF Security Password (128-Bit)

(Do not program to all zeros)

NOTE

• When the code-security passwords are programmed, all addresses between 0x3F7F80
and 0x3F7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.

• If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be
used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and
should not contain program code.

• On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are
reserved for TI, irrespective of whether code security has been used or not. User
application should not use these locations in any way.

Table 3-5 shows how to handle these memory locations.

Table 3-5. Impact of Using the Code Security Module

ADDRESS

0x3F 7F80 – 0x3F 7FEF Application code and data Fill with 0x0000 Application code and data
0x3F 7FF0 – 0x3F 7FF5 Reserved for data only

0x3D 7BFC – 0x3D 7BFF Application code and data

Code security enabled Code security disabled Code security enabled Code security disabled

Fill with 0x0000

FLASH ROM

Reserved for TI. Do not use.

Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 31

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The wait-states for the various spaces in the memory map area are listed in Table 3-6.

Table 3-6. Wait-states

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed
Peripheral Frame 1

Peripheral Frame 2 Fixed

L0 and L1 SARAMs 0-wait

OTP is possible at a reduced CPU frequency. See Section 3.2.5

Flash

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

0-wait (writes) Fixed. The eCAN peripheral can extend a cycle as needed.
2-wait (reads) Back-to-back writes will introduce a 1-cycle delay.

0-wait (writes)
2-wait (reads)

Programmable,

1-wait minimum

Programmable, is possible at reduced CPU frequency. The CSM password

0-wait minimum locations are hardwired for 16 wait-states. See

Programmed via the Flash registers. 1-wait-state operation
for more information.

Programmed via the Flash registers. 0-wait-state operation

Section 3.2.5 for more information.

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32 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

www.ti.com

3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a
very efficient C/C++ engine, enabling users to develop not only their system control software in a high­level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in
DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of
the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical
resolution problems that would otherwise demand a more expensive floating-point processor solution. Add
to this the fast interrupt response with automatic context save of critical registers, resulting in a device that
is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep
protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high
speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Highest: Data Writes (Simultaneous data and program writes cannot occur on the

Program Writes (Simultaneous data and program writes cannot occur on the

Data Reads
Program (Simultaneous program reads and fetches cannot occur on the

Reads memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the
280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of
16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral
bus are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2).
The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

memory bus.)

memory bus.)

memory bus.)

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.2.4 Real-Time JTAG and Analysis

The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time
mode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time critical code while enabling time-critical interrupts to be serviced without interference.
The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the
280x, no software monitor is required. Additionally, special analysis hardware is provided which allows the
user to set hardware breakpoint or data/address watch-points and generate various user-selectable break
events when a match occurs.

3.2.5 Flash

The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The
F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K x 16 sectors. The F2806
and F2802 have 32K x 16 of embedded flash, segregated into four 8K x 16 sectors. The F2801 device
contains 16K x 16 of embedded flash, segregated into four 4K x 16 sectors. All five devices also contain a
single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables and
should not contain program code.

www.ti.com

The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by the
application. This allows applications running at slower frequencies to configure the flash to
use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide
(literature number SPRU712).

3.2.6 ROM

The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.

3.2.7 M0, M1 SARAMs

All 280x devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to
execute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.

NOTE

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3.2.8 L0, L1, H0 SARAMs

The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into three
blocks (L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided
into two blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16
of single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline
stalls. Each block is mapped to both program and data space.

3.2.9 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-7. Boot Mode Selection

MODE DESCRIPTION SPICLKA GPIO34

GPIO18

SCITXDB

Boot to Flash/ROM Jump to Flash/ROM address 0x3F 7FF6 1 1 1

You must have programmed a branch instruction here prior

to reset to redirect code execution as desired.
SCI-A Boot Load a data stream from SCI-A 1 1 0
SPI-A Boot Load from an external serial SPI EEPROM on SPI-A 1 0 1
I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 0

the I2C bus
eCAN-A Boot Call CAN_Boot to load from eCAN-A mailbox 1. 0 1 1
Boot to M0 SARAM Jump to M0 SARAM address 0x00 0000. 0 1 0
Boot to OTP Jump to OTP address 0x3D 7800 0 0 1
Parallel I/O Boot Load data from GPIO0 - GPIO15 0 0 0

GPIO29

SCITXDA

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.2.10 Security

The 280x devices support high levels of security to protect the user firmware from being reverse
engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1
SARAM blocks. The security feature prevents unauthorized users from examining the memory contents
via the JTAG port, executing code from external memory or trying to boot-load some undesirable software
that would export the secure memory contents. To enable access to the secure blocks, the user must
write the correct 128-bit KEY value, which matches the value stored in the password locations within the
Flash.

The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing
so would permanently lock the device.

disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

www.ti.com

NOTE

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3.2.11 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.12 External Interrupts (XINT1, XINT2, XNMI)

The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be
configured to trigger any external interrupt.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.2.13 Oscillator and PLL

The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.14 Watchdog

The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.

3.2.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.

3.2.16 Low-Power Modes

The 280x devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event

HALT: Turns off the internal oscillator. This mode basically shuts down the device and

places it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.2.17 Peripheral Frames 0, 1, 2 (PFn)

The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Control, Programming, Erase, Verify Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers (dual-mapped)

PF1: eCAN: eCAN Mailbox and Control Registers

GPIO: GPIO MUX Configuration and Control Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Result Register
I2C: Inter-Integrated Circuit Module and Registers

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3.2.18 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.

3.2.19 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not
being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.20 Control Peripherals

The 280x devices support the following peripherals which are used for embedded control and
communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM
features.

eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.

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eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed

measurement using capture unit and high-speed measurement using a 32-bit unit
timer.
This peripheral has a watchdog timer to detect motor stall and input error detection
logic to identify simultaneous edge transition in QEP signals.

ADC: The ADC block is a 12-bit converter, single-ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

3.2.21 Serial Port Peripherals

The 280x devices support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. On the 280x, the SPI contains a
16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. On the 280x, the SCI contains a 16-level receive and
transmit FIFO for reducing interrupt servicing overhead.

I2C: The inter-integrated circuit (I2C) module provides an interface between a DSP and

other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the
DSP through the I2C module. On the 280x, the I2C contains a 16-level receive and
transmit FIFO for reducing interrupt servicing overhead.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.3 Register Map

The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:

Peripheral These are peripherals that are mapped directly to the CPU memory bus.
Frame 0: See Table 3-8.

Peripheral These are peripherals that are mapped to the 32-bit peripheral bus.
Frame 1 See Table 3-9.

Peripheral These are peripherals that are mapped to the 16-bit peripheral bus.
Frame 2: See Table 3-10.

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

www.ti.com

Table 3-8. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Device Emulation Registers 0x0880 – 0x09FF 384 EALLOW protected
FLASH Registers
Code Security Module Registers 0x0AE0 – 0x0AEF 16 EALLOW protected

ADC Result Registers (dual-mapped) 0x0B00 – 0x0B0F 16 Not EALLOW protected
CPU-TIMER0/1/2 Registers 0x0C00 – 0x0C3F 64 Not EALLOW protected
PIE Registers 0x0CE0 – 0x0CFF 32 Not EALLOW protected
PIE Vector Table 0x0D00 – 0x0DFF 256 EALLOW protected

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(4) The Flash Registers are also protected by the Code Security Module (CSM).

(4)

0x0A80 – 0x0ADF 96

Table 3-9. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

eCANA Registers 0x6000 – 0x60FF 256 bits in other eCAN control registers) are

eCANA Mailbox RAM 0x6100 – 0x61FF 256 Not EALLOW-protected

eCANB Registers 0x6200 – 0x62FF 256 bits in other eCAN control registers) are

eCANB Mailbox RAM 0x6300 – 0x63FF 256 Not EALLOW-protected
ePWM1 Registers 0x6800 – 0x683F 64
ePWM2 Registers 0x6840 – 0x687F 64
ePWM3 Registers 0x6880 – 0x68BF 64
ePWM4 Registers 0x68C0 – 0x68FF 64
ePWM5 Registers 0x6900 – 0x693F 64
ePWM6 Registers 0x6940 – 0x697F 64
eCAP1 Registers 0x6A00 – 0x6A1F 32
eCAP2 Registers 0x6A20 – 0x6A3F 32
eCAP3 Registers 0x6A40 – 0x6A5F 32
eCAP4 Registers 0x6A60 – 0x6A7F 32
eQEP1 Registers 0x6B00 – 0x6B3F 64
eQEP2 Registers 0x6B40 – 0x6B7F 64
GPIO Control Registers 0x6F80 – 0x6FBF 128 EALLOW protected
GPIO Data Registers 0x6FC0 – 0x6FDF 32 Not EALLOW protected
GPIO Interrupt and LPM Select Registers 0x6FE0 – 0x6FFF 32 EALLOW protected

(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.

(1) (2)

(3)

EALLOW protected
CSM Protected

(1) (2)

Some eCAN control registers (and selected
EALLOW-protected.

Some eCAN control registers (and selected
EALLOW-protected.

Some ePWM registers are EALLOW
protected. See Table 4-2.

Not EALLOW protected

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-10. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

System Control Registers 0x7010 – 0x702F 32 EALLOW Protected
SPI-A Registers 0x7040 – 0x704F 16
SCI-A Registers 0x7050 – 0x705F 16
External Interrupt Registers 0x7070 – 0x707F 16
ADC Registers 0x7100 – 0x711F 32
SPI-B Registers 0x7740 – 0x774F 16 Not EALLOW Protected
SCI-B Registers 0x7750 – 0x775F 16
SPI-C Registers 0x7760 – 0x776F 16
SPI-D Registers 0x7780 – 0x778F 16
I2C Registers 0x7900 – 0x792F 48

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
(2) Missing segments of memory space are reserved and should not be used in applications.

(1) (2)

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-11.

Table 3-11. Device Emulation Registers

NAME SIZE (x16) DESCRIPTION

DEVICECNF 2 Device Configuration Register
PARTID 0x0882 1 Part ID Register 0x002C

REVID 0x0883 1 Revision ID Register 0x0000 – Silicon Rev. 0 – TMX

PROTSTART 0x0884 1 Block Protection Start Address Register
PROTRANGE 0x0885 1 Block Protection Range Address Register

(1) The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.

ADDRESS

RANGE

0x0880
0x0881

(1)

0x0024 – F2802
0x0034 – F2806
0x003C – F2808
0x00FE – F2809
0x0014 – F28016
0x001C – F28015
0xFF2C – C2801
0xFF24 – C2802

0x0001 – Silicon Rev. A – TMX
0x0002 – Silicon Rev. B – TMS
0x0003 – Silicon Rev. C – TMS

Revision ID Register 0x0000 – Silicon rev. 0 – TMS (F2809 only)

- F2801

3.5 Interrupts

Figure 3-7 shows how the various interrupt sources are multiplexed within the 280x devices.

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as
shown in Table 3-12.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

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XINT2

C28x

CPU

CPU TIMER 2 (Reserved for DSP/BIOS)

CPU TIMER 0

Watchdog

Peripherals

(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)

TINT0

Interrupt Control

XNMICR(15:0)

XINT1

MUX

MUX

MUX

MUX

MUX

Interrupt Control

XINT1

XINT1CR(15:0)

Interrupt Control

XINT2

96 Interrupts

PIE

XINT2CR(15:0)

GPIO

MUX

WDINT

INT1

to

INT12

INT13

INT14

NMI

XINT1CTR(15:0)

XINT2CTR(15:0)

XNMICTR(15:0)

CPU TIMER 1

TINT2

Low-Power Modes

LPMINT

WAKEINT

TINT1

int13_select

XNMI_XINT13

GPIO0.int

GPIO31.int

ADC

XINT2SOC

GPIOXINT1SEL(4:0)

GPIOXINT2SEL(4:0)

GPIOXNMISEL(4:0)

nmi_select

1

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

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42 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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Figure 3-7. External and PIE Interrupt Sources

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TMS320C2801 TMS320F28016 TMS320F28015

INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx[8:1] PIEIFRx[8:1]

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals

or

External

Interrupts

(Enable) (Flag)

IER[12:1]IFR[12:1]

Global

Enable

INTM

1

0

PIEACKx

(Enable/Flag)

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 3-8. Multiplexing of Interrupts Using the PIE Block

Table 3-12. PIE Peripheral Interrupts

CPU

INTERRUPTS

INT1 XINT2 XINT1 Reserved

INT2 Reserved Reserved

INT3 Reserved Reserved

INT4 Reserved Reserved Reserved Reserved

INT5 Reserved Reserved Reserved Reserved Reserved Reserved

INT6
INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT8 Reserved Reserved Reserved Reserved Reserved Reserved

INT9

INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT SEQ2INT SEQ1INT

(LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)

EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA

(SPI-D) (SPI-D) (SPI-C) (SPI-C) (SPI-B) (SPI-B) (SPI-A) (SPI-A)

ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

1) No peripheral within the group is asserting interrupts.

2) No peripheral interrupts are assigned to the group (example PIE group 12).

PIE INTERRUPTS

ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT

(eCAP4) (eCAP3) (eCAP2) (eCAP1)

(1)

EQEP2_INT EQEP1_INT

(eQEP2) (eQEP1)

I2CINT2A I2CINT1A

(I2C-A) (I2C-A)

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 43

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-13. PIE Configuration and Control Registers

www.ti.com

NAME ADDRESS SIZE (x16) DESCRIPTION

PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA – 6 Reserved

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

(1)

3.5.1 External Interrupts

Table 3-14. External Interrupt Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XINT1CR 0x7070 1 XINT1 control register
XINT2CR 0x7071 1 XINT2 control register
Reserved 0x7072 – 0x7076 5 Reserved
XNMICR 0x7077 1 XNMI control register
XINT1CTR 0x7078 1 XINT1 counter register
XINT2CTR 0x7079 1 XINT2 counter register
Reserved 0x707A – 0x707E 5 Reserved
XNMICTR 0x707F 1 XNMI counter register

44 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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PLL

X1

X2

Power
Modes

Control

Watchdog

Block

28x

CPU

Peripheral Bus

High-Speed Prescaler

Low-Speed Prescaler

Clock Enables

GPIO

MUX

XCLKIN

16 ADC Inputs

LSPCLK

I/O

Peripheral Reset

SYSCLKOUT

(A)

XRS

Reset

GPIOs

I/O

OSC

CLKIN

(A)

HSPCLK

I/O

Peripheral

Registers

CPU

Timers

System
Control

Registers

Peripheral

Registers

ePWM 1/2/3/4/5/6

eCAP 1/2/3/4 eQEP 1/2

ADC

Registers

12-Bit ADC

Peripheral

Registers

Low-Speed Peripherals

SCI-A/B, SPI-A/B/C/D

Peripheral

Registers

eCAN-A/B

I2C-A

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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP System Control and
Interrupts Reference Guide (literature number SPRU712).

3.6 System Control

This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-9 shows the various clock and reset domains in the 280x devices that will be
discussed.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT).

Figure 3-9. Clock and Reset Domains

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 45

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X1

XCLKIN

(3.3-V Clock Input)

On-Chip

Oscillator

X2

XOR

PLLSTS[OSCOFF]

OSCCLK

PLL

VCOCLK

OSCCLK

or

VCOCLK

CLKIN

OSCCLK

0

PLLSTS[PLLOFF]

n

/2

PLLSTS[CLKINDIV]

n

0

4-bit PLL Select

(PLLCR)

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15.

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Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XCLK 0x7010 1 XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLLSTS 0x7011 1 PLL Status Register
Reserved 0x7012 – 0x7019 8 Reserved
HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
LOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
PCLKCR0 0x701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x701D 1 Peripheral Clock Control Register 1
LPMCR0 0x701E 1 Low-Power Mode Control Register 0
Reserved 0x701F – 0x7020 1 Reserved
PLLCR 0x7021 1 PLL Control Register
SCSR 0x7022 1 System Control and Status Register
WDCNTR 0x7023 1 Watchdog Counter Register
Reserved 0x7024 1 Reserved
WDKEY 0x7025 1 Watchdog Reset Key Register
Reserved 0x7026 – 0x7028 3 Reserved
WDCR 0x7029 1 Watchdog Control Register
Reserved 0x702A – 0x702F 6 Reserved

(1) All of the registers in this table are EALLOW protected.

(1)

3.6.1 OSC and PLL Block

Figure 3-10 shows the OSC and PLL block on the 280x.

Figure 3-10. OSC and PLL Block Diagram

The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:

.

DDIO

1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V

2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.

46 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated

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C

L1

X2X1

Crystal

C

L2

XCLKIN

External Clock Signal

(Toggling 0-V )

DD

XCLKIN

X2

NC

X1

External Clock Signal

(Toggling 0-V )

DDIO

XCLKIN

X2

NC

X1

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The three possible input-clock configurations are shown in Figure 3-11 through Figure 3-13.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 3-11. Using a 3.3-V External Oscillator

Figure 3-12. Using a 1.8-V External Oscillator

Figure 3-13. Using the Internal Oscillator

3.6.1.1 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:

• Fundamental mode, parallel resonant

• CL(load capacitance) = 12 pF

• CL1= CL2= 24 pF

• C

shunt

= 6 pF

• ESR range = 30 to 60 Ω

TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.

Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 47

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.6.1.2 PLL-Based Clock Module

The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.

Table 3-16. PLLCR Register Bit Definitions

www.ti.com

PLLCR[DIV]

0000 (PLL bypass) OSCCLK/n

1011–1111 Reserved

(1) This register is EALLOW protected.
(2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output

clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.

(1)

0001 (OSCCLK*1)/n
0010 (OSCCLK*2)/n
0011 (OSCCLK*3)/n
0100 (OSCCLK*4)/n
0101 (OSCCLK*5)/n
0110 (OSCCLK*6)/n
0111 (OSCCLK*7)/n
1000 (OSCCLK*8)/n
1001 (OSCCLK*9)/n
1010 (OSCCLK*10)/n

SYSCLKOUT

(CLKIN)

(2)

NOTE

PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to
the core. This bit must be 0 before writing to the PLLCR and must only be set after
PLLSTS[PLLLOCKS] = 1.

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.

• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-17. Possible PLL Configuration Modes

PLL MODE REMARKS PLLSTS[CLKINDIV]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block 0 OSCCLK/2

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

PLL Bypass

PLL Enable 0 OSCCLK*n/2

is disabled in this mode. This can be useful to reduce system noise and for low
before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external 0 OSCCLK/2

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.

1 OSCCLK

1 OSCCLK

SYSCLKOUT

(CLKIN)

3.6.1.3 Loss of Input Clock

In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1–5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock). In addition to
this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions
could be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory and the V

DD3VFL

rail.

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/512

OSCCLK

WDCR (WDPS[2:0])

WDCLK

WDCNTR[7:0]

WDKEY[7:0]

Good Key

1

0

1

WDCR (WDCHK[2:0])

Bad

WDCHK

Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

3.6.2 Watchdog Block

The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the software
must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the
watchdog counter. Figure 3-14 shows the various functional blocks within the watchdog module.

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A. TheWDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-14. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7, Low-Power
Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.

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3.7 Low-Power Modes Block

The low-power modes on the 280x are similar to the 240x devices. Table 3-18 summarizes the various
modes.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 3-18. Low-Power Modes

(3)

, XNMI

(1)

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

IDLE 00 On On On

STANDBY 01 Off Off

HALT 1X (oscillator and PLL turned off, Off Off

(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will

exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(watchdog still running) signal, debugger

watchdog not functional)

On XRS, Watchdog interrupt, GPIO Port A

Off

(2)

XRS, Watchdog interrupt, any enabled
interrupt, XNMI

XRS, GPIO Port A signal, XNMI,
debugger

(3)

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized

by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.

HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the

device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide
(literature number SPRU712) for more details.

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Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

4 Peripherals

The integrated peripherals of the 280x are described in the following subsections:

• Three 32-bit CPU-Timers

• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)

• Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)

• Up to two enhanced QEP modules (eQEP1, eQEP2)

• Enhanced analog-to-digital converter (ADC) module

• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)

• Up to two serial communications interface modules (SCI-A, SCI-B)

• Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)

• Inter-integrated circuit module (I2C)

• Digital I/O and shared pin functions

4.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS™.

These timers are different from the timers that are present in the ePWM modules.

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NOTE

If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

Figure 4-1. CPU-Timers

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INT1

to

INT12

INT14

C28x

TINT2

TINT0

PIE

CPU-TIMER 2
(Reserved for

DSP/BIOS)

INT13

TINT1

XINT13

CPU-TIMER 0

CPU-TIMER 1

TMS320C2801, TMS320F28016, TMS320F28015

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In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in

Figure 4-2.

A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-2. CPU-Timer Interrupt Signals and Output Signal

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x,
2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712).

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register
TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High
TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register
TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High
TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register
Reserved 0x0C05 1 Reserved
TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register
TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High
TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register
TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High
TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register
TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High
TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register
Reserved 0x0C0D 1 Reserved
TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register
TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High
TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register
TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High
TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register
TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High
TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register

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PIE

Peripheral Bus

ePWM1 Module

ePWM2 Module

ePWMx Module

EPWM1SYNCI

EPWM2SYNCI

EPWM2SYNCO

EPWMxSYNCI

EPWMxSYNCO

ADC

GPIO

MUX

EPWM1SYNCI

EPWM1SYNCO

ADCSOCx0

EPWMxA

EPWMxB

EPWM2A

EPWM2B

EPWM1A

EPWM1B

EPWM1INT

EPWM1SOC

EPWM2INT

EPWM2SOC

EPWMxINT

EPWMxSOC

To eCAP1

Module

(Sync in)

TZ1 to TZ6

TZ1 to TZ6

TZ1 to TZ6

EPWM1SYNCO

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

Reserved 0x0C15 1 Reserved
TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register
TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High

Reserved 40 Reserved

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)

The 280x device contains up to six enhanced PWM modules (ePWM). Figure 4-3 shows a block diagram
of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the

TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide

(literature number SPRU791) for more details.

0x0C18 –

0x0C3F

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Table 4-2 shows the complete ePWM register set per module.

Figure 4-3. Multiple PWM Modules in a 280x System

54 Peripherals Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-2. ePWM Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 ePWM5 ePWM6 DESCRIPTION

TBCTL 0x6800 0x6840 0x6880 0x68C0 0x6900 0x6940 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1 / 0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 N/A N/A 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 / 1 Time Base Period Register Set
CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 / 0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 N/A N/A 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 0x690B 0x694B 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 0x690E 0x694E 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 / 0 Trip Zone Select Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1 / 0 Trip Zone Control Register
TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1 / 0 Trip Zone Enable Interrupt Register
TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1 / 0 Trip Zone Flag Register
TZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1 / 0 Trip Zone Clear Register
TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1 / 0 Trip Zone Force Register
ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1 / 0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 0x691E 0x695E 1 / 0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 0x6920

(1) Registers that are EALLOW protected.
(2) Applicable to F2809 only

(2)

0x6960

(2)

SIZE (x16) /

#SHADOW

1 / 0 HRPWM Configuration Register

(1)

(1)

(1)

(1)

(1)

(1)

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CTR = PRD

TBPRD Shadow (16)

TBPRD Active (16)

Counter

Up/Down

(16-Bit)

TBCNT

Active (16)

TBCTL[PHSEN]

TBCTL[SWFSYNC]

(Software-Forced Sync)

EPWMxSYNCI

CTR = ZERO

CTR_Dir

CTR = CMPB

Disabled

Sync

In/Out

Select

Mux

TBCTL[SYNCOSEL]

EPWMxSYNCO

TBPHS Active (24)

16

8

TBPHSHR (8)

Phase

Control

Time-Base (TB)

CTR = CMPA

CMPA Active (24)

16

CMPA Shadow (24)

Action

Qualifier

(AQ)

8

16

Counter Compare (CC)

CMPB Active (16)

CTR = CMPB

CMPB Shadow (16)

CMPAHR (8)

EPWMA

EPWMB

Dead
Band

(DB)

PWM

Chopper

(PC)

Trip

Zone

(TZ)

CTR = ZERO

EPWMxAO

EPWMxBO

EPWMxTZINT

TZ1 to TZ6

HiRes PWM (HRPWM)

CTR = PRD

CTR = ZERO

CTR = CMPB

CTR = CMPA

CTR_Dir

Event

Trigger

and

Interrupt

(ET)

EPWMxINT

EPWMxSOCA

EPWMxSOCB

CTR = ZERO

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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56 Peripherals Copyright © 2003–2012, Texas Instruments Incorporated

Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

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4.3 Hi-Resolution PWM (HRPWM)

The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can
be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module
are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM

• Typically used when effective PWM resolution falls below ~ 9–10 bits. This occurs at PWM frequencies
greater than ~200 kHz when using a CPU/System clock of 100 MHz.

• This capability can be utilized in both duty cycle and phase-shift control methods.

• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.

• HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the
EPWMxA output). EPWMxB output has conventional PWM capabilities.

4.4 Enhanced CAP Modules (eCAP1/2/3/4)

The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functional
block diagram of a module. See the TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) Module
Reference Guide (literature number SPRU807) for more details.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP

modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.

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TSCTR

(Counter - 32-bit)

RST

CAP1

(APRD Active)

LD

CAP2

(ACMP Active)

LD

CAP3

(APRD Shadow)

LD

CAP4

(ACMP Shadow)

LD

Continuous/

One-Shot

Capture Control

LD1

LD2

LD3

LD4

32

PRD [0-31]

CTR [0-31]

eCAPx

MODE SELECT

Interrupt

Trigger

and

Flag

Control

to PIE

CTR=CMP

32

32

32

ACMP

Shadow

Event

Prescale

CTRPHS

(Phase Register - 32-bit)

SYNCOut

SYNCIn

SYNC

Event

Qualifier

Polarity

Select

Polarity

Select

Polarity

Select

Polarity

Select

CTR=PRD

CTR_OVF

4

PWM

Compare

Logic

CTR [0-31]

PRD [0-31]

CMP [0-31]

CTR=CMP

CTR=PRD

CTR_OVF

OVF

APWM Mode

Delta Mode

4

Capture Events

CEVT[1:4]

APRD

Shadow

32

32

32

32

32

CMP [0-31]

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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Figure 4-5. eCAP Functional Block Diagram

58 Peripherals Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-3. eCAP Control and Status Registers

NAME eCAP1 eCAP2 eCAP3 eCAP4 DESCRIPTION

TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 2 Time-Stamp Counter

CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 2 Counter Phase Offset Value Register

CAP1 0x6A04 0x6A24 0x6A44 0x6A64 2 Capture 1 Register
CAP2 0x6A06 0x6A26 0x6A46 0x6A66 2 Capture 2 Register
CAP3 0x6A08 0x6A28 0x6A48 0x6A68 2 Capture 3 Register
CAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 2 Capture 4 Register

Reserved 0x6A0C – 0x6A2C – 0x6A4C – 0x6A6C – 8 Reserved

0x6A12 0x6A32 0x6A52 0x6A72
ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 1 Capture Control Register 1
ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 1 Capture Control Register 2
ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 Capture Interrupt Enable Register

ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 1 Capture Interrupt Flag Register
ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 Capture Interrupt Clear Register
ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 1 Capture Interrupt Force Register

Reserved 0x6A1A – 0x6A3A – 0x6A5A – 0x6A7A – 6 Reserved

0x6A1F 0x6A3F 0x6A5F 0x6A7F

SIZE

(x16)

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QWDTMR

QWDPRD

16

QWDOG

UTIME

QUPRD

QUTMR

32

UTOUT

WDTOUT

Quadrature

Capture

Unit

(QCAP)

QCPRDLAT

QCTMRLAT

16

QFLG

QEPSTS

QEPCTL

Registers

Used by

Multiple Units

QCLK

QDIR

QI

QS

PHE

PCSOUT

Quadrature

Decoder

(QDU)

QDECCTL

16

Position Counter/

Control Unit

(PCCU)

QPOSLAT

QPOSSLAT

16

QPOSILAT

EQEPxAIN

EQEPxBIN

EQEPxIIN

EQEPxIOUT

EQEPxIOE

EQEPxSIN

EQEPxSOUT

EQEPxSOE

GPIO
MUX

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxS

EQEPxI

QPOSCMP

QEINT

QFRC

32

QCLR

QPOSCTL

1632

QPOSCNT

QPOSMAX

QPOSINIT

PIE

EQEPxINT

Enhanced QEP (eQEP) Peripheral

System Control

Registers

QCTMR

QCPRD

1616

QCAPCTL

EQEPxENCLK

SYSCLKOUT

To CPU

Data Bus

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

4.5 Enhanced QEP Modules (eQEP1/2)

The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the

TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) Module Reference Guide

(literature number SPRU790) for more details.

www.ti.com

Figure 4-6. eQEP Functional Block Diagram

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TMS320C2801 TMS320F28016 TMS320F28015

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-4. eQEP Control and Status Registers

NAME SIZE(x16)/ REGISTER DESCRIPTION

QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position Counter
QPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position Count
QPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position Count
QPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compare
QPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position Latch
QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position Latch
QPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position Latch
QUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit Timer
QUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period Register
QWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog Timer
QWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period Register
QDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control Register
QEPCTL 0x6B15 0x6B55 1/0 eQEP Control Register
QCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control Register
QPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control Register
QEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable Register
QFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag Register
QCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear Register
QFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force Register
QEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status Register
QCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture Timer
QCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period Register
QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer Latch
QCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period Latch
Reserved 0x6B21– 0x6B61 – 31/0 Reserved

eQEP1 eQEP2

ADDRESS ADDRESS

0x6B3F 0x6B7F

eQEP1

#SHADOW

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0,ValueDigital =

V0inputwhen £

4095,ValueDigital =

V3inputwhen ³

V3inputV0when <<

3

ADCLOVoltageAnalogInput

4096ValueDigital

-

´=

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

4.6 Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 4-7. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)

• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select anyone of 16 input channels

• Sequencer can be operated as two independent 8-channel sequencers or as one large 16-channel
sequencer (that is, two cascaded 8-channel sequencers)

• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:

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A. All fractional values are truncated.

• Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.

• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.

• SOCA and SOCB triggers can operate independently in dual-sequencer mode.

• Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25­MHz ADC clock. The ADC module has a 16-channel sequencer, configurable as two independent 8­channel sequencers. The two independent 8-channel sequencers can be cascaded to form a 16-channel
sequencer. Although there are multiple input channels and two sequencers, there is only one converter in
the ADC module. Figure 4-7 shows the block diagram of the ADC module.

The two 8-channel sequencer modules have the capability to autosequence a series of conversions, each
module has the choice of selecting any one of the respective eight channels available through an analog
MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each
sequencer, once the conversion is complete, the selected channel value is stored in its respective
RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing
the user to perform oversampling algorithms. This gives increased resolution over traditional single­sampled conversion results.

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Result Registers

EPWMSOCB

S/W

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

12-Bit

ADC

Module

Analog

MUX

EPWMSOCA

S/W

GPIO/XINT2_

ADCSOC

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

Control Block

High-Speed

Prescaler

HSPCLK

ADCENCLK

DSP

SYSCLKOUT

S/H

S/H

HALT

Sequencer 2Sequencer 1

SOCSOC

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 4-7. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (V
V

DD2A18

, V

DDA2

, V

DDAIO

) from the digital supply. Figure 4-8 and Figure 4-9 show the ADC pin connections

DD1A18

for the 280x devices.

NOTE

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:

– ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the

clock to the register will still function. This is necessary to make sure all registers and
modes go into their default reset state. The analog module, however, will be in a low­power inactive state. As soon as reset goes high, then the clock to the registers will
be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a
certain time delay (ms range) before the ADC is stable and can be used.

– HALT: This mode only affects the analog module. It does not affect the registers. In

this mode, the ADC module goes into low-power mode. This mode also will stop the
clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will
be turned off indirectly.

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,

ADCINA[7:0]
ADCINB[7:0]

ADCLO

ADCREFIN

ADCRESEXT

ADCREFP

V

DD1A18

V

DD2A18

V

SS1AGND

V

SS2AGND

V

DDAIO

V

SSAIO

V

DDA2

V

SSA2

ADCREFM

Analog input 0-3 V with respect to ADCLO

Connect to analog ground

ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)

ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V)

ADCREFP and ADCREFM should not
be loaded by external circuitry

ADC Analog Ground Pin

ADC External Current Bias Resistor

ADC Reference Positive Output

ADC Reference Medium Output

ADC Power

ADC Analog and Reference I/O Power

ADC 16-Channel Analog Inputs

Float or ground if internal reference is used

ADC Analog Ground Pin
ADC Analog Ground Pin

22 k

2.2 Fμ

(A)

2.2 Fμ

(A)

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 4-8 shows the ADC pin-biasing for internal reference and Figure 4-9 shows the ADC pin-biasing for

external reference.

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A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

Figure 4-8. ADC Pin Connections With Internal Reference

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ADCINA[7:0]
ADCINB[7:0]

ADCLO

ADCREFIN

ADC External Current Bias Resistor

ADCRESEXT

ADCREFP

V

DD1A18

V

DD2A18

V

SS1AGND

V

SS2AGND

V

DDAIO

V

SSAIO

V

DDA2

V

SSA2

ADC Reference Positive Output

ADCREFM

ADC Reference Medium Output

ADC Analog Power

ADC Analog and Reference I/O Power

Analog input 0-3 V with respect to ADCLO

Connect to Analog Ground

ADCREFP and ADCREFM should not
be loaded by external circuitry

ADC 16-Channel Analog Inputs

Connect to 1.500, 1.024, or 2.048-V precision source

(D)

ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)

ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin

ADC Analog Ground Pin
ADC Analog Ground Pin

ADC Analog Power Pin (3.3 V)

22 k

2.2 Fμ

(A)

2.2 Fμ

(A)

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on

the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.

The temperature rating of any recommended component must match the rating of the end
product.

4.6.1 ADC Connections if the ADC Is Not Used

It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:

• V

DD1A18/VDD2A18

• V

• V

• ADCLO – Connect to V

• ADCREFIN – Connect to V

• ADCREFP/ADCREFM – Connect a 100-nF cap to V

• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.

• ADCINAn, ADCINBn - Connect to V
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power

savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog

ground (V

, V

DDA2
SS1AGND/VSS2AGND

SS1AGND/VSS2AGND

Figure 4-9. ADC Pin Connections With External Reference

– Connect to V

DDAIO

– Connect to V

DDIO

, V

, V

SSA2

SSAIO

SS

SS

)

NOTE

DD

– Connect to V

SS

SS

SS

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

4.6.2 ADC Registers

The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5.

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Table 4-5. ADC Registers

0x711B

0x711F

(1)

ADDRESS

NAME ADDRESS

ADCTRL1 0x7100 1 ADC Control Register 1
ADCTRL2 0x7101 1 ADC Control Register 2

ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x7107 1 ADC Auto-Sequence Status Register
ADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0
ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1
ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2
ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3
ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4
ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5
ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6
ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7
ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8
ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9

ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10
ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11
ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12
ADCRESULT13 0x7115 0x0B0D 1 ADC Conversion Result Buffer Register 13
ADCRESULT14 0x7116 0x0B0E 1 ADC Conversion Result Buffer Register 14
ADCRESULT15 0x7117 0x0B0F 1 ADC Conversion Result Buffer Register 15

ADCTRL3 0x7118 1 ADC Control Register 3

ADCST 0x7119 1 ADC Status Register

Reserved 2 Reserved

ADCREFSEL 0x711C 1 ADC Reference Select Register

ADCOFFTRIM 0x711D 1 ADC Offset Trim Register

Reserved 2 Reserved

(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left

justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

0x711A –

0x711E –

(2)

SIZE (x16) DESCRIPTION

(1)

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)

• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

SPRS230N –OCTOBER 2003–REVISED MAY 2012

NOTE

For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.

Copyright © 2003–2012, Texas Instruments Incorporated Peripherals 67

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Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 x 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and

Message Objects Control

Message Controller

32 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

32

Controls

Address Data

eCAN1INTeCAN0INT

32

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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PART NUMBER VREF OTHER T

SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C

SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C

SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C

SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C

SN65HVD232 3.3 V None None None – –40°C to 85°C

SN65HVD232Q 3.3 V None None None – –40°C to 125°C

SN65HVD233 3.3 V Standby Adjustable None Diagnostic –40°C to 125°C

SN65HVD234 3.3 V Standby & Sleep Adjustable None – –40°C to 125°C
SN65HVD235 3.3 V Standby Adjustable None Autobaud –40°C to 125°C

Figure 4-10. eCAN Block Diagram and Interface Circuit

SUPPLY LOW-POWER SLOPE

VOLTAGE MODE CONTROL

Table 4-6. 3.3-V eCAN Transceivers

A

Loopback

Loopback

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Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

Master Control - CANMC

Bit-Timing Configuration - CANBTC

Error and Status - CANES

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Global Interrupt Flag 1 - CANGIF1

Time-Out Control - CANTOC

Time-Out Status - CANTOS

Reserved

eCAN-A Control and Status Registers

Message Identifier - MSGID

61E8h-61E9h

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h

603Fh

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

6040h

607Fh

6080h

60BFh
60C0h

60FFh

eCAN-A Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Mailbox 06100h-6107h

Mailbox 1

6108h-610Fh

Mailbox 2

6110h-6117h

Mailbox 3

6118h-611Fh

eCAN-A Memory RAM (512 Bytes)

Mailbox 4

6120h-6127h

Mailbox 28

61E0h-61E7h

Mailbox 2961E8h-61EFh

Mailbox 3061F0h-61F7h

Mailbox 31

61F8h-61FFh

61EAh-61EBh

61ECh-61EDh

61EEh-61EFh

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If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled for this.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

Figure 4-11. eCAN-A Memory Map

NOTE

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

Master Control - CANMC

Bit-Timing Configuration - CANBTC

Error and Status - CANES

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Global Interrupt Flag 1 - CANGIF1

Time-Out Control - CANTOC

Time-Out Status - CANTOS

Reserved

eCAN-B Control and Status Registers

Message Identifier - MSGID

63E8h-63E9h

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6200h

623Fh

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

6240h

627Fh

6280h

62BFh

62C0h

62FFh

eCAN-B Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Mailbox 06300h-6307h

Mailbox 1

6308h-630Fh

Mailbox 2

6310h-6317h

Mailbox 3

6318h-631Fh

eCAN-B Memory RAM (512 Bytes)

Mailbox 4

6320h-6327h

Mailbox 28

63E0h-63E7h

Mailbox 2963E8h-63EFh

Mailbox 3063F0h-63F7h

Mailbox 31

63F8h-63FFh

63EAh-63EBh

63ECh-63EDh

63EEh-63EFh

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 4-12. eCAN-B Memory Map

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The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-7. CAN Register Map

REGISTER NAME DESCRIPTION

CANME 0x6000 0x6200 1 Mailbox enable
CANMD 0x6002 0x6202 1 Mailbox direction

CANTRS 0x6004 0x6204 1 Transmit request set

CANTRR 0x6006 0x6206 1 Transmit request reset

CANTA 0x6008 0x6208 1 Transmission acknowledge
CANAA 0x600A 0x620A 1 Abort acknowledge

CANRMP 0x600C 0x620C 1 Receive message pending

CANRML 0x600E 0x620E 1 Receive message lost

CANRFP 0x6010 0x6210 1 Remote frame pending

CANGAM 0x6012 0x6212 1 Global acceptance mask

CANMC 0x6014 0x6214 1 Master control

CANBTC 0x6016 0x6216 1 Bit-timing configuration

CANES 0x6018 0x6218 1 Error and status

CANTEC 0x601A 0x621A 1 Transmit error counter

CANREC 0x601C 0x621C 1 Receive error counter

CANGIF0 0x601E 0x621E 1 Global interrupt flag 0

CANGIM 0x6020 0x6220 1 Global interrupt mask

CANGIF1 0x6022 0x6222 1 Global interrupt flag 1

CANMIM 0x6024 0x6224 1 Mailbox interrupt mask

CANMIL 0x6026 0x6226 1 Mailbox interrupt level

CANOPC 0x6028 0x6228 1 Overwrite protection control
CANTIOC 0x602A 0x622A 1 TX I/O control
CANRIOC 0x602C 0x622C 1 RX I/O control

CANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode)
CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

eCAN-A eCAN-B SIZE

ADDRESS ADDRESS (x32)

(1)

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devices)MHz-60(forb/s

10

3.75

16

MHz60

ratebitMax

6

´==

devices)MHz-100(forb/s

10

6.25

16

MHz100

ratebitMax

6

´==

8*1)(BRR

LSPCLK

rateBaud

+

=

0BRRwhen ¹

16

LSPCLK

rateBaud =

0BRRwhen =

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)

The 280x devices include two serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard non­return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full­duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,
and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud­select register.

Features of each SCI module include:

• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

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• Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

•

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.

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Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-8. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x7050 1 SCI-A Communications Control Register

SCICTL1A 0x7051 1 SCI-A Control Register 1

SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x7054 1 SCI-A Control Register 2

SCIRXSTA 0x7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register

SCIFFTXA

SCIFFRXA

SCIFFCTA

SCIPRIA 0x705F 1 SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2)

(2)

(2)

0x705A 1 SCI-A FIFO Transmit Register
0x705B 1 SCI-A FIFO Receive Register
0x705C 1 SCI-A FIFO Control Register

Table 4-9. SCI-B Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRB 0x7750 1 SCI-B Communications Control Register

SCICTL1B 0x7751 1 SCI-B Control Register 1

SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits

SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits

SCICTL2B 0x7754 1 SCI-B Control Register 2

SCIRXSTB 0x7755 1 SCI-B Receive Status Register

SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register

SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register

SCIFFTXB

SCIFFRXB

SCIFFCTB

SCIPRIB 0x775F 1 SCI-B Priority Control Register

(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2)

(2)

(2)

0x775A 1 SCI-B FIFO Transmit Register
0x775B 1 SCI-B FIFO Receive Register
0x775C 1 SCI-B FIFO Control Register

(1)

(1) (2)

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LSPCLK

Frame Format and Mode

Even/Odd

Enable

Parity

8

SCIRXD

SCIRXST.1

TXENA

RXWAKE

SCITXD

SCICCR.6 SCICCR.5

RXSHF Register

SCITXD

TXSHF

Register

WUT

SCICTL1.3

TXWAKE

1

Baud Rate

MSbyte

Register

Baud Rate

LSbyte

Register

SCIHBAUD. 15 - 8

SCILBAUD. 7 - 0

TX

FIFO

Interrupts

RXENA

SCICTL1.0

RX

FIFO

Interrupts

SCICTL1.1

SCIRXD

RX ERR INT ENA

SCICTL1.6

RX Error

PEFE OE

RX Error

SCIRXST.7 SCIRXST.4 - 2

8

SCITXBUF.7-0

TX FIFO Registers

Transmitter-Data

Buffer Register

8

SCIFFENA

TX FIFO _15

- - - - -

TX FIFO _1

TX FIFO _0

SCIFFTX.14

SCIRXBUF.7-0

RX FIFO Registers

Receive-Data

Buffer Register

SCIRXBUF.7-0

8

SCIFFRX.15

RXFFOVF

RX FIFO _0

- - - - -

RX FIFO _1

RX FIFO _15

SCI TX Interrupt Select Logic

TX EMPTY

SCICTL2.6

TXINT

TXRDY

SCICTL2.0

TX INT ENA

SCICTL2.7

To CPU

AutoBaud Detect Logic

TX Interrupt Logic

RX Interrupt Logic

SCI RX Interrupt Select Logic

RXRDY

SCIRXST.6

BRKDT

SCIRXST.5

RX/BK INT ENA

SCICTL2.1

RXINT

To CPU

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 4-13 shows the SCI module block diagram.

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Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram

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1)(SPIBRR

LSPCLK

rateBaud

+

=

127to3SPIBRRwhen =

4

LSPCLK

rateBaud =

21,0,SPIBRRwhen =

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)

The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules
(SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that
allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the
device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include external I/O or
peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave
Baud rate: 125 different programmable rates.

SPRS230N –OCTOBER 2003–REVISED MAY 2012

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

• 16-level transmit/receive FIFO

• Delayed transmit control

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The SPI port operation is configured and controlled by the registers listed in Table 4-10 through Table 4-

13.

Table 4-10. SPI-A Registers

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NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7040 1 SPI-A Configuration Control Register

SPICTL 0x7041 1 SPI-A Operation Control Register
SPISTS 0x7042 1 SPI-A Status Register

SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register

SPIFFRX 0x704B 1 SPI-A FIFO Receive Register

SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Table 4-11. SPI-B Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7740 1 SPI-B Configuration Control Register

SPICTL 0x7741 1 SPI-B Operation Control Register
SPISTS 0x7742 1 SPI-B Status Register

SPIBRR 0x7744 1 SPI-B Baud Rate Register

SPIRXEMU 0x7746 1 SPI-B Receive Emulation Buffer Register

SPIRXBUF 0x7747 1 SPI-B Serial Input Buffer Register
SPITXBUF 0x7748 1 SPI-B Serial Output Buffer Register

SPIDAT 0x7749 1 SPI-B Serial Data Register

SPIFFTX 0x774A 1 SPI-B FIFO Transmit Register

SPIFFRX 0x774B 1 SPI-B FIFO Receive Register

SPIFFCT 0x774C 1 SPI-B FIFO Control Register

SPIPRI 0x774F 1 SPI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 4-12. SPI-C Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7760 1 SPI-C Configuration Control Register

SPICTL 0x7761 1 SPI-C Operation Control Register
SPISTS 0x7762 1 SPI-C Status Register

SPIBRR 0x7764 1 SPI-C Baud Rate Register

SPIRXEMU 0x7766 1 SPI-C Receive Emulation Buffer Register

SPIRXBUF 0x7767 1 SPI-C Serial Input Buffer Register
SPITXBUF 0x7768 1 SPI-C Serial Output Buffer Register

SPIDAT 0x7769 1 SPI-C Serial Data Register

SPIFFTX 0x776A 1 SPI-C FIFO Transmit Register

SPIFFRX 0x776B 1 SPI-C FIFO Receive Register

SPIFFCT 0x776C 1 SPI-C FIFO Control Register

SPIPRI 0x776F 1 SPI-C Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Table 4-13. SPI-D Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7780 1 SPI-D Configuration Control Register

SPICTL 0x7781 1 SPI-D Operation Control Register
SPISTS 0x7782 1 SPI-D Status Register

SPIBRR 0x7784 1 SPI-D Baud Rate Register

SPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer Register

SPIRXBUF 0x7787 1 SPI-D Serial Input Buffer Register
SPITXBUF 0x7788 1 SPI-D Serial Output Buffer Register

SPIDAT 0x7789 1 SPI-D Serial Data Register

SPIFFTX 0x778A 1 SPI-D FIFO Transmit Register

SPIFFRX 0x778B 1 SPI-D FIFO Receive Register

SPIFFCT 0x778C 1 SPI-D FIFO Control Register

SPIPRI 0x778F 1 SPI-D Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

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S

S

LSPCLK

456 123 0

0123

SPI Bit Rate

State Control

SPICCR.3 - 0

SPIBRR.6 - 0

Clock

Polarity

SPICCR.6

Clock

Phase

SPICTL.3

Talk

SPICTL.1

M

S

M

M

S

Master/Slave

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

S

M

M

S

SW3

To CPU

M

SW1

SPIDAT.15 - 0

16

16

SPITXINT

TX

FIFO

Interrupt

RX

FIFO

Interrupt

SPISTE

(A)

RX FIFO Registers

SPIRXBUF

SPIFFTX.14

SPIFFENA

RX FIFO _15

- - - - -

RX FIFO _1

RX FIFO _0

TX FIFO Registers

SPITXBUF

- - - - -

TX FIFO _15

TX FIFO _0

TX FIFO _1

16

SPITXBUF Buffer Register

SPIRXBUF Buffer Register

SPICTL.0

SPI

INT ENA

SPI

INT FLAG

SPISTS.6

Receiver

Overrun Flag

Overrun
INT ENA

SPISTS.7

SPICTL.4

SPIINT/SPIRXINT

RX Interrupt

Logic

TX Interrupt

Logic

SPIFFOVF

FLAG

SPIFFRX.15

SPIDAT Data Register

16

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Figure 4-14 is a block diagram of the SPI in slave mode.

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A. SPISTE is driven low by the master for a slave device.

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Figure 4-14. SPI Module Block Diagram (Slave Mode)

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4.10 Inter-Integrated Circuit (I2C)

The 280x device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module
interfaces within the 280x device.

The I2C module has the following features:

• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)

• One 16-word receive FIFO and one 16-word transmit FIFO

• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:

– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave

• An additional interrupt that can be used by the CPU when in FIFO mode

• Module enable/disable capability

• Free data format mode

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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SYSRS

SYSCLKOUT

Control

I2CINT1A

I2CINT2A

C28x CPU

GPIO

MUX

Peripheral Bus

I2C-A

System Control Block

I2CAENCLK

PIE

Block

SDAA

SCLA

Data[16]

Data[16]

Addr[16]

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

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A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-15. I2C Peripheral Module Interfaces

The registers in Table 4-14 configure and control the I2C port operation.

Table 4-14. I2C-A Registers

NAME ADDRESS DESCRIPTION

I2COAR 0x7900 I2C own address register

I2CIER 0x7901 I2C interrupt enable register

I2CSTR 0x7902 I2C status register

I2CCLKL 0x7903 I2C clock low-time divider register

I2CCLKH 0x7904 I2C clock high-time divider register

I2CCNT 0x7905 I2C data count register
I2CDRR 0x7906 I2C data receive register
I2CSAR 0x7907 I2C slave address register

I2CDXR 0x7908 I2C data transmit register
I2CMDR 0x7909 I2C mode register
I2CISRC 0x790A I2C interrupt source register

I2CPSC 0x790C I2C prescaler register
I2CFFTX 0x7920 I2C FIFO transmit register

I2CFFRX 0x7921 I2C FIFO receive register

I2CRSR - I2C receive shift register (not accessible to the CPU)

I2CXSR - I2C transmit shift register (not accessible to the CPU)

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GPxDAT (read)

Input

Qualification

GPxMUX1/2

High-Impedance

Output Control

GPIOx pin

XRS

0 = Input, 1 = Output

Low-Power

Modes Block

01

10

11

01

10

11

01

10

11

GPxPUD

Internal

Pullup

= Default at Reset

External Interrupt

MUX

Peripheral 3 Input

Peripheral 3 Output Enable

Peripheral 2 Output Enable

Peripheral 1 Output Enable

Peripheral 3 Output

Peripheral 2 Output

Peripheral 1 Output

Peripheral 2 Input

Peripheral 1 Input

N/C

GPxDIR (latch)

GPxDAT (latch)

Asynchronous

path

Asynchronous path

LPMCR0

GPIOLMPSEL

GPxCTRL

GPxQSEL1/2

GPIOXNMISEL

GPIOXINT2SEL

GPIOXINT1SEL

GPxSET

GPxCLEAR

GPxTOGGLE

00

00

00

PIE

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4.11 GPIO MUX

On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts
Reference Guide (literature number SPRU712) for details.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

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Figure 4-16. GPIO MUX Block Diagram

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.

Table 4-15. GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)

GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)
Reserved 2 Reserved

GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 35)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 35)
GPBQSEL2 0x6F94 2 Reserved

GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 35)
GPBMUX2 0x6F98 2 Reserved

GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 35)

GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 35)
Reserved 2 Reserved

Reserved 32 Reserved

GPADAT 0x6FC0 2 GPIO Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO Data Set Register (GPIO0 to 31)

GPACLEAR 0x6FC4 2 GPIO Data Clear Register (GPIO0 to 31)

GPATOGGLE 0x6FC6 2 GPIO Data Toggle Register (GPIO0 to 31)

GPBDAT 0x6FC8 2 GPIO Data Register (GPIO32 to 35)
GPBSET 0x6FCA 2 GPIO Data Set Register (GPIO32 to 35)

GPBCLEAR 0x6FCC 2 GPIO Data Clear Register (GPIO32 to 35)

GPBTOGGLE 0x6FCE 2 GPIO Data Toggle Register (GPIO32 to 35)

Reserved 16 Reserved

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)

Reserved 5 Reserved

GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

Reserved 22 Reserved

0x6F8E –

0x6F8F

0x6F9E –

0x6F9F

0x6FA0 –

0x6FBF

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

0x6FD0 –

0x6FDF

0x6FE3 –

0x6FE7

0x6FEA –

0x6FFF

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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Table 4-16. F2808 GPIO MUX Table

DEFAULT AT RESET

GPAMUX1/2

REGISTER FUNCTION SELECTION 1

11–10 GPIO5 EPWM3B (O) SPICLKD (I/O) ECAP1 (I/O)
13–12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15–14 GPIO7 EPWM4B (O) SPISTED (I/O) ECAP2 (I/O)
17–16 GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O)
19–18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
21–20 GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O)
23–22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP4 (I/O)
25–24 GPIO12 TZ1 (I) CANTXB (O) SPISIMOB (I/O)
27–26 GPIO13 TZ2 (I) CANRXB (I) SPISOMIB (I/O)
29–28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O)
31–30 GPIO15 TZ4 (I) SCIRXDB (I) SPISTEB (I/O)

11–10 GPIO21 EQEP1B (I) SPISOMIC (I/O) CANRXB (I)
13–12 GPIO22 EQEP1S (I/O) SPICLKC (I/O) SCITXDB (O)
15–14 GPIO23 EQEP1I (I/O) SPISTEC (I/O) SCIRXDB (I)
17–16 GPIO24 ECAP1 (I/O) EQEP2A (I) SPISIMOB (I/O)
19–18 GPIO25 ECAP2 (I/O) EQEP2B (I) SPISOMIB (I/O)
21–20 GPIO26 ECAP3 (I/O) EQEP2I (I/O) SPICLKB (I/O)
23–22 GPIO27 ECAP4 (I/O) EQEP2S (I/O) SPISTEB (I/O)
25–24 GPIO28 SCIRXDA (I) Reserved
27–26 GPIO29 SCITXDA (O) Reserved
29–28 GPIO30 CANRXA (I) Reserved
31–30 GPIO31 CANTXA (O) Reserved

(1) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
(2) This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin

descriptions for more detail.

(3) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(4) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(1)

PRIMARY I/O PERIPHERAL PERIPHERAL PERIPHERAL

(2)

SELECTION 2 SELECTION 3

BITS (GPxMUX1/2 (GPxMUX1/2 BITS = 0,1) (GPxMUX1/2 BITS = 1,0) (GPxMUX1/2 BITS = 1,1)

BITS = 0,0)

GPAMUX1

1–0 GPIO0 EPWM1A (O) Reserved
3–2 GPIO1 EPWM1B (O) SPISIMOD (I/O) Reserved
5–4 GPIO2 EPWM2A (O) Reserved
7–6 GPIO3 EPWM2B (O) SPISOMID (I/O) Reserved
9–8 GPIO4 EPWM3A (O) Reserved

GPAMUX2

1–0 GPIO16 SPISIMOA (I/O) CANTXB (O) TZ5 (I)
3–2 GPIO17 SPISOMIA (I/O) CANRXB (I) TZ6 (I)
5–4 GPIO18 SPICLKA (I/O) SCITXDB (O) Reserved
7–6 GPIO19 SPISTEA (I/O) SCIRXDB (I) Reserved
9–8 GPIO20 EQEP1A (I) SPISIMOC (I/O) CANTXB (O)

GPBMUX1

1–0 GPIO32 SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O)
3–2 GPIO33 SCLA (I/OC) EPWMSYNCO (O) ADCSOCBO (O)
5–4 GPIO34 Reserved

(4)

Reserved

SPRS230N –OCTOBER 2003–REVISED MAY 2012

(3)

(3)

(3)

(4)
(4)
(4)
(4)

(4)

Reserved

Reserved

Reserved

TZ5 (I)
TZ6 (I)
Reserved
Reserved

Reserved

(3)
(3)
(3)
(3)
(3)

(4)
(4)

(4)
(4)

(4)

Copyright © 2003–2012, Texas Instruments Incorporated Peripherals 83

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TMS320C2801 TMS320F28016 TMS320F28015

GPyCTRL Reg

SYNC

SYSCLKOUT

Qualification

Input Signal
Qualified by

3 or 6 Samples

GPIOx

Time Between Samples

GPxQSEL

Number of Samples

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:

• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

• Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.

www.ti.com

Figure 4-17. Qualification Using Sampling Window

• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 6-12 (for 6-sample mode).

• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a
peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not
selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

84 Peripherals Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

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www.ti.com

5 Device Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.

The following products support development of 280x-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• 2808 eZdsp™

• Evaluation modules

• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB

• Universal 5-V dc power supply

• Documentation and cables

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F2808). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical

specifications

TMP Final silicon die that conforms to the device's electrical specifications but has not

completed quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.

Copyright © 2003–2012, Texas Instruments Incorporated Device Support 85

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TMS320C2801 TMS320F28016 TMS320F28015

TMS

320

F

28015

PZ

PREFIX

TMX = Experimental Device
TMP = Prototype Device
TMS = Qualified Device

DEVICE FAMILY

320 = TMS320 DSP Family

TM

TECHNOLOGY

PACKAGE TYPE
PZ = 100-Pin Low-Profile Quad Flatpack (LQFP)
GGM = 100-Ball Ball Grid Array (BGA)
ZGM = 100-Ball Lead-Free BGA

F = Flash EEPROM

(1.8-V Core/3.3-V I/O)

C = ROM

(1.8-V Core/3.3-V I/O)

DEVICE
2809
2808
2806
2802
2801
28015
28016

A

-60

Indicates 60-MHz device.
Absence of “-60” indicates
100-MHz device.

TEMPERTURE RANGE
A = −40 °

−40°C to 125°C

Q = −40°C to 125°C (Q100 qualification)

°C to 85 C

S =

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZ) and temperature range (for example, S). Figure 5-1 provides a legend for
reading the complete device name for any family member.

www.ti.com

86 Device Support Copyright © 2003–2012, Texas Instruments Incorporated

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

Figure 5-1. Example of TMS320x280x/2801x Device Nomenclature

TMS320C2801 TMS320F28016 TMS320F28015

Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

5.2 Documentation Support

Extensive documentation supports all of the TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.

Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.

See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more
information on types of peripherals.

Table 5-1. TMS320x280x, 2801x Peripheral Selection Guide

PERIPHERAL GUIDE TYPE

TMS320x280x, 2801x, 2804x DSP System Control and Interrupts SPRU712 – X
TMS320x280x, 2801x, 2804x Boot ROM SPRU722 –
TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) SPRU716 1 X
TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator SPRU791 0 X

(ePWM) Module
TMS320x280x, 2801x, 2804x High-Resolution Pulse Width Modulator SPRU924 0 X
TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) Module SPRU807 0 X
TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse SPRU790 0 X

(eQEP) Module
TMS320x280x/2801x Enhanced Controller Area Network (eCAN) SPRUEU0 0 X
TMS320x280x, 2801x, 2804x Serial Communication Interface (SCI) SPRUFK7 0 X
TMS320x280x, 2801x, 2804x Serial Peripheral Interface SPRUG72 0 X
TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Module SPRU721 0 X

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.

LITERATURE

NUMBER

SPRS230N –OCTOBER 2003–REVISED MAY 2012

F2809, F2808,

(1)

F2806, F2802,
F2801, C2802,

C2801, F28016,

F28015

The following documents are available on the TI website (www.ti.com):

Data Manual and Errata

SPRS230 TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801,

TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015 Digital Signal
Processors Data Manual contains the pinout, signal descriptions, as well as electrical and

timing specifications for the F280x, C280x, and F2801x devices.

SPRZ171 TMS320F280x, TMS320C280x, and TMS320F2801x DSC Silicon Errata describes known

advisories on silicon and provides workarounds.

CPU User's Guides

SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing

unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.

SPRU712 TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide

describes the various interrupts and system control features of the 280x digital signal
processors (DSPs).

Copyright © 2003–2012, Texas Instruments Incorporated Device Support 87

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Peripheral Guides

SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference

guides of the 28x digital signal processors (DSPs).

SPRU716 TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) Reference Guide

describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined
ADC.

SPRU791 TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module

Reference Guide describes the main areas of the enhanced pulse width modulator that

include digital motor control, switch mode power supply control, UPS (uninterruptible power
supplies), and other forms of power conversion

SPRU790 TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) Module

Reference Guide describes the eQEP module, which is used for interfacing with a linear or

rotary incremental encoder to get position, direction, and speed information from a rotating
machine in high performance motion and position control systems. It includes the module
description and registers

SPRU807 TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) Module Reference Guide

describes the enhanced capture module. It includes the module description and registers.

www.ti.com

SPRU924 TMS320x280x, 2801x, 2804x High-Resolution Pulse Width Modulator Reference Guide

describes the operation of the high-resolution extension to the pulse width modulator
(HRPWM).

SPRUEU0 TMS320x280x/2801x Enhanced Controller Area Network (eCAN) Reference Guide

describes the enhanced controller area network (eCAN) on the x280x and x2801x devices.

SPRUFK7 TMS320x280x, 2801x, 2804x Serial Communication Interface (SCI) Reference Guide

describes the features and operation of the serial communication interface (SCI) module that
is available on the TMS320x280x, 2801x, 2804x devices.

SPRUG72 TMS320x280x, 2801x, 2804x Serial Peripheral Interface Reference Guide describes how

the serial peripheral interface works.

SPRU721 TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Module Reference Guide describes

the features and operation of the inter-integrated circuit (I2C) module.

SPRU722 TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and

features of the bootloader (factory-programmed boot-loading software). It also describes
other contents of the device on-chip boot ROM and identifies where all of the information is
located within that memory.

Tools Guides

SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly

language tools (assembler and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C28x device.

SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the

TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code
and produces TMS320 DSP assembly language source code for the TMS320C28x device.

SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.

SPRU625 TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference

Guide describes development using DSP/BIOS.

88 Device Support Copyright © 2003–2012, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

www.ti.com

Application Reports and Software

SPRAAQ7 TMS320x281x to TMS320x2833x or 2823x Migration Overview describes how to migrate

SPRAAQ8 TMS320x280x to TMS320x2833x or 2823x Migration Overview describes how to migrate

SPRAAN9 C28x FPU Primer provides an overview of the floating-point unit (FPU) in the

SPRAAM0 Getting Started With TMS320C28x Digital Signal Controllers is organized by

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Key Links Include:

1. C2000 Get Started - www.ti.com/c2000getstarted

2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw

3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib

4. DSP Power Management Reference Designs - www.ti.com/dsppower

from the 281x device design to 2833x or 2823x designs.

from a 280x device design to 2833x or 2823x designs.

TMS320F28335, TMS320F28334, and TMS320F28332 Digital Signal Controller (DSC)
devices.

development flow and functional areas to make your design effort as seamless as possible.
Tips on getting started with C28x™ DSP software and hardware development are provided
to aid in your initial design and debug efforts. Each section includes pointers to valuable
information including technical documentation, software, and tools for use in each phase of
design.

SPRA958 Running an Application from Internal Flash Memory on the TMS320F28xxx DSP covers

the requirements needed to properly configure application software for execution from on­chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are
presented. Example code projects are included.

SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware

abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is
compared to traditional #define macros and topics of code efficiency and special case
registers are also addressed.

SPRAA88 Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal

Controller presents a method for utilizing the on-chip pulse width modulated (PWM) signal

generators on the TMS320F280x family of digital signal controllers as a digital-to-analog
converter (DAC).

SPRAA91 TMS320F280x Digital Signal Controller USB Connectivity Using the TUSB3410 USB-to-

UART Bridge Chip presents hardware connections as well as software preparation and

operation of the development system using a simple communication echo program.

SPRAAH1 Using the Enhanced Quadrature Encoder Pulse (eQEP) Module in TMS320x280x,

28xxx as a Dedicated Capture provides a guide for the use of the eQEP module as a

dedicated capture unit and is applicable to the TMS320x280x, 28xxx family of processors.

SPRAAI1 Using the ePWM Module for 0% – 100% Duty Cycle Control provides a guide for the use

of the ePWM module to provide 0% to 100% duty cycle control and is applicable to the
TMS320x280x family of processors.

SPRAAD5 Power Line Communication for Lighting Applications Using Binary Phase Shift Keying

(BPSK) with a Single DSP Controller presents a complete implementation of a power line

modem following CEA-709 protocol using a single DSP.

Copyright © 2003–2012, Texas Instruments Incorporated Device Support 89

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

SPRAAD8 TMS320x280x and TMS320F2801x ADC Calibration describes a method for improving the

absolute accuracy of the 12-bit ADC found on the TMS320x280x and TMS320F2801x
devices. Inherent gain and offset errors affect the absolute accuracy of the ADC. The
methods described in this report can improve the absolute accuracy of the ADC to levels
better than 0.5%. This application report has an option to download an example program that
executes from RAM on the F2808 EzDSP.

SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for

online stack overflow detection on the TMS320C28x DSP. C-source code is provided that
contains functions for implementing the overflow detection on both DSP/BIOS and non­DSP/BIOS applications.

SPRA806 An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP

provides instructions and suggestions to configure the C compiler to assist with C-callable
assembly routines.

SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the

Texas Instruments TMS320x281x and the TMS320x280x/2801x/2804x DSPs to assist in
application migration.

Software
SPRC191 C280x, C2801x C/C++ Header Files and Peripheral Examples

www.ti.com

BSDL Models

SPRM244 F2809 GGM/ZGM BSDL Model
SPRM245 F2809 PZ BSDL Model
SPRM198 F2808 100-Pin GGM/ZGM BSDL Model
SPRM197 F2808 100-Pin PZ BSDL Model
SPRM196 F2806 100-Pin PZ BSDL Model
SPRM200 F2806 100-Pin GGM/ZGM BSDL Model
SPRM414 F2802 GGM BSDL Model
SPRM413 F2802 PZ BSDL Model
SPRM415 F2802 ZGM BSDL Model
SPRM194 F2801 100-Pin GGM/ZGM BSDL Model
SPRM195 F2801 100-Pin PZ BSDL Model
SPRM261 C2802 100-Pin GGM/ZGM BSDL Model
SPRM260 C2802 100-Pin PZ BSDL Model
SPRM259 C2801 100-Pin GGM/ZGM BSDL Model
SPRM258 C2801 100-Pin PZ BSDL Model
SPRM416 F28016 GGM BSDL Model
SPRM357 F28016 PZ BSDL Model
SPRM417 F28016 ZGM BSDL Model
SPRM412 F28015 GGM BSDL Model
SPRM356 F28015 PZ BSDL Model
SPRM355 F28015 ZGM BSDL Model

90 Device Support Copyright © 2003–2012, Texas Instruments Incorporated

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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

TMS320C2801 TMS320F28016 TMS320F28015

www.ti.com

IBIS Models

SPRM445 F2809 GGM IBIS Model
SPRM295 F2809 PZ IBIS Model
SPRM444 F2809 ZGM IBIS Model
SPRM291 F2808 GGM IBIS Model
SPRM292 F2808 PZ IBIS Model
SPRM293 F2808 ZGM IBIS Model
SPRM288 F2806 GGM IBIS Model
SPRM289 F2806 PZ IBIS Model
SPRM290 F2806 ZGM IBIS Model
SPRM285 F2802 GGM IBIS Model
SPRM286 F2802 PZ IBIS Model
SPRM287 F2802 ZGM IBIS Model

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

SPRM282 F2801 GGM IBIS Model
SPRM283 F2801 PZ IBIS Model
SPRM284 F2801 ZGM IBIS Model
SPRM310 C2802 GGM IBIS Model
SPRM449 C2802 PZ IBIS Model
SPRM311 C2802 ZGM IBIS Model
SPRM308 C2801 GGM IBIS Model
SPRM448 C2801 PZ IBIS Model
SPRM309 C2801 ZGM IBIS Model
SPRM405 F28016 GGM IBIS Model
SPRM300 F28016 PZ IBIS Model
SPRM404 F28016 ZGM IBIS Model
SPRM403 F28015 GGM IBIS Model
SPRM299 F28015 PZ IBIS Model
SPRM402 F28015 ZGM IBIS Model

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.

Updated information on the TMS320 DSP controllers can be found on the worldwide web at:

http://www.ti.com.

To send comments regarding this data manual (literature number SPRS230), use the
[e-mail] email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

Copyright © 2003–2012, Texas Instruments Incorporated Device Support 91

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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

5.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.

www.ti.com

92 Device Support Copyright © 2003–2012, Texas Instruments Incorporated

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6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F280x DSPs.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

6.1 Absolute Maximum Ratings

(1) (2)

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.

Supply voltage range, V
Supply voltage range, V
Supply voltage range, V
Supply voltage range, V
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, IIK(VIN< 0 or VIN> V
Output clamp current, IOK(VO< 0 or VO> V
Operating ambient temperature ranges TA: A version (GGM, ZGM, PZ)

Junction temperature range, T
Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the

voltage to a diode drop above V
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for

TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).

DDIO
DDA2
DD
DD1A18
SSA2

IN

O

, V

, V

, V

DD3VFL

DDAIO

, V

DD2A18

SSAIO

(4)

J

(4)

stg

, V

SS1AGND

DDA2

with respect to V
with respect to V
with respect to V
with respect to V

, V

SS2AGND

(3)

)

DDIO

) ±20 mA

DDIO

with respect to V

TA: S version (GGM, ZGM, PZ)
TA: Q version (PZ)

SS
SSA
SS
SSA
SS

(4)

(4)

(4)

–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–65°C to 150°C

or below V

SSA2

.

–0.3 V to 4.6 V
–0.3 V to 4.6 V
–0.3 V to 2.5 V
–0.3 V to 2.5 V
–0.3 V to 0.3 V
–0.3 V to 4.6 V
–0.3 V to 4.6 V

±20 mA

–40°C to 85°C

Copyright © 2003–2012, Texas Instruments Incorporated Electrical Specifications 93

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Device supply voltage, I/O, V
Device supply voltage CPU, V
Supply ground, VSS, V
ADC supply voltage (3.3 V), V
ADC supply voltage (1.8 V), V
Flash supply voltage, V

SSIO

DD3VFL

DDIO

DD

DDA2
DD1A18

, V

DDAIO

, V

DD2A18

Device clock frequency (system clock), 100-MHz devices 2 100 MHz
f

SYSCLKOUT

High-level input voltage, V

IH

60-MHz devices 2 60 MHz
All inputs except X1 2 V
X1 0.7 * VDD– 0.05 V

Low-level input voltage, V

IL

All inputs except X1 VSS– 0.3 0.8 V
X1 0.3 * VDD+ 0.05

High-level output source current,
VOH= 2.4 V, I

OH

Low-level output sink current,
VOL= VOLMAX, I

OL

All I/Os except Group 2 –4 mA

(1)

Group 2
All I/Os except Group 2 4 mA

(1)

Group 2
A version –40 85 °C

Ambient temperature, T

A

S version –40 125
Q version –40 125

(Q100 Qualification)

(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1

3.14 3.3 3.47 V

1.71 1.8 1.89 V
0 V

3.14 3.3 3.47 V

1.71 1.8 1.89 V

3.14 3.3 3.47 V

DDIO

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+ 0.3 V

DD

–8

8

6.3 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOHHigh-level output voltage V

VOLLow-level output voltage IOL= IOLMAX 0.4 V

Pin with pullup

I

IL

Input current
(low level)

enabled
Pin with pulldown

enabled
Pin with pullup

enabled

Input current Pin with pulldown

I

IH

(high level) enabled

Pin with pulldown
enabled

Output current, pullup or

I

OZ

pulldown disabled

CIInput capacitance 2 pF

IOH= IOHMAX 2.4
IOH= 50 μA V

V

= 3.3 V, VIN= 0 V All I/Os (including XRS) –80 –140 –190

DDIO

V

= 3.3 V, VIN= 0 V ±2

DDIO

V

= 3.3 V, VIN= V

DDIO

V

= 3.3 V, VIN= V

DDIO

V

= 3.3 V, VIN= V

DDIO

VO= V

DDIO

or 0 V ±2 μA

DDIO

(F280x) 28 50 80 μA

DDIO

(C280x) 80 140 190

DDIO

DDIO

– 0.2

±2

μA

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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6.4 Current Consumption

Table 6-1. TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz

SYSCLKOUT

SPRS230N –OCTOBER 2003–REVISED MAY 2012

I

MODE TEST CONDITIONS

The following peripheral
clocks are enabled:

• ePWM1/2/3/4/5/6

• eCAP1/2/3/4

• eQEP1/2

• eCAN-A

• SCI-A/B

• SPI-A

• ADC

Operational
(Flash)

IDLE 75 mA 90 mA 500 μA 2 mA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

STANDBY 6 mA 12 mA 100 μA 500 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

HALT Peripheral clocks are off. 70 μA 60 μA 120 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

(1) I
(2) The I

During flash programming, extra current is drawn from the VDDand V

• I2C
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the
SCI-A, SCI-B, and
eCAN-A ports. The
hardware multiplier is
exercised.
Code is running out of
flash with 3 wait-states.
XCLKOUT is turned off.

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C
Flash is powered down.

Peripheral clocks are off.
Flash is powered down.

Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

current indicated in this table is the flash read-current and does not include additional current for erase/write operations.

DD3VFL

DD

(5)

TYP

195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

MAX

(6)

TYP

involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.

(3) I
(4) I

(5) TYP numbers are applicable over room temperature and nominal voltage.

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

DDA2

and V

and V

DD2A18

DDAIO

pins. In order to realize the I

pins.

(5)

I

DDIO

(1)

MAX

(6)

TYP MAX

rails, as indicated in Table 6-45. If the user application

DD3VFL

(2)

I

DD3VFL

DDA18

(6)

TYP

currents shown for IDLE, STANDBY, and HALT,

I

(5)

DDA18

(3)

MAX

(6)

TYP

(5)

I

DDA33

(4)

MAX

(6) MAX numbers are at 125°C and MAX voltage.

(6)

NOTE

The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, the
current drawn by the device will be more than the numbers specified in the current
consumption tables.

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 6-2. TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT

www.ti.com

I

MODE TEST CONDITIONS

The following peripheral
clocks are enabled:

• ePWM1/2/3/4/5/6

• eCAP1/2/3/4

• eQEP1/2

• eCAN-A

• SCI-A/B

• SPI-A

Operational
(Flash)

IDLE 75 mA 90 mA 500 μA 2 mA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

STANDBY 6 mA 12 mA 100 μA 500 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

HALT Peripheral clocks are off. 70 μA 60 μA 120 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

(1) I
(2) The I

• ADC

• I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI­A, SCI-B, and eCAN-A
ports. The hardware
multiplier is exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C
Flash is powered down.

Peripheral clocks are off.
Flash is powered down.

Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

During flash programming, extra current is drawn from the VDDand V

current indicated in this table is the flash read-current and does not include additional current for erase/write operations.

DD3VFL

DD

(5)

TYP

195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

MAX

(6)

TYP

involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.

(3) I
(4) I

(5) TYP numbers are applicable over room temperature and nominal voltage.

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

DDA2

and V

and V

DD2A18

DDAIO

pins. In order to realize the I

pins.

(1)

I

DDIO

(5)

MAX

(6)

TYP

rails, as indicated in Table 6-45. If the user application

DD3VFL

DDA18

I

DD3VFL

(5)

(2)

MAX

(6)

TYP

I

(5)

DDA18

(3)

MAX

I

TYP

DDA33

(5)

(6)

currents shown for IDLE, STANDBY, and HALT,

(4)

MAX

(6) MAX numbers are at 125°C and MAX voltage.

(6)

NOTE

The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, the
current drawn by the device will be more than the numbers specified in the current
consumption tables.

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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Table 6-3. TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz

SYSCLKOUT

SPRS230N –OCTOBER 2003–REVISED MAY 2012

I

MODE TEST CONDITIONS

The following peripheral
clocks are enabled:

• ePWM1/2/3

• eCAP1/2

• eQEP1

• eCAN-A

• SCI-A

• SPI-A

Operational
(Flash)

IDLE 75 mA 90 mA 500 μA 2 mA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

STANDBY 6 mA 12 mA 100 μA 500 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

HALT Peripheral clocks are off. 70 μA 60 μA 120 μA 2 μA 10 μA 5 μA 50 μA 15 μA 30 μA

(1) I
(2) The I

During flash programming, extra current is drawn from the VDDand V

• ADC

• I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off.

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C
Flash is powered down.

Peripheral clocks are off.
Flash is powered down.

Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

current indicated in this table is the flash read-current and does not include additional current for erase/write operations.

DD3VFL

DD

(5)

TYP

180 mA 210 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

MAX

(6)

TYP

involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.

(3) I
(4) I

(5) TYP numbers are applicable over room temperature and nominal voltage.

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

DDA2

and V

and V

DD2A18

DDAIO

pins. In order to realize the I

pins.

(1)

I

DDIO

(5)

MAX

DD3VFL

(6)

TYP

rails, as indicated in Table 6-45. If the user application

DDA18

I

DD3VFL

(5)

(2)

MAX

(6)

TYP

I

(5)

DDA18

(3)

MAX

I

TYP

DDA33

(5)

(6)

currents shown for IDLE, STANDBY, and HALT,

(4)

MAX

(6) MAX numbers are at 125°C and MAX voltage.

(6)

NOTE

The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, the
current drawn by the device will be more than the numbers specified in the current
consumption tables.

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 6-4. TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-

MHz SYSCLKOUT

www.ti.com

I

MODE TEST CONDITIONS

The following peripheral clocks
are enabled:

• ePWM1/2/3

• eCAP1/2

• eQEP1

• eCAN-A

• SCI-A

• SPI-A

Operational
(ROM)

IDLE 75 mA 90 mA 500 μA 2 mA 5 μA 50 μA 15 μA 30 μA

STANDBY Peripheral clocks are off. 6 mA 12 mA 100 μA 500 μA 5 μA 50 μA 15 μA 30 μA
HALT 70 μA 80 μA 120 μA 5 μA 50 μA 15 μA 30 μA

(1) I

DDIO

(2) I

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

(3) I

DDA33

(4) TYP numbers are applicable over room temperature and nominal voltage.

• ADC

• I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left unconnected.
Data is continuously transmitted
out of the SCI-A, SCI-B, and
eCAN-A ports. The hardware
multiplier is exercised.
Code is running out of ROM with
3 wait-states.
XCLKOUT is turned off.

XCLKOUT is turned off.
The following peripheral clocks
are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C

Peripheral clocks are off.
Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

includes current into V
includes current into V

DD1A18

DDA2

and V

and V

DD2A18

DDAIO

DD

(4)

TYP

150 mA 165 mA 5 mA 10 mA 30 mA 38 mA 1.5 mA 2 mA

MAX

(5)

TYP

pins. In order to realize the I

pins.

(1)

I

DDIO

(4)

(5)

MAX

currents shown for IDLE, STANDBY, and HALT,

DDA18

TYP

(4)

I

DDA18

(2)

MAX

(3)

I

TYP

(4)

DDA33

MAX

(5)

(5) MAX numbers are at 125°C and MAX voltage.

(5)

NOTE

The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, the
current drawn by the device will be more than the numbers specified in the current
consumption tables.

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6.4.1 Reducing Current Consumption

280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been
removed, the following new peripherals have been added on the 280x:

• 3 SPI modules

• 1 CAN module

• 1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6),

eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs
incorporate a unique method to reduce the device current consumption. Since each peripheral unit has an
individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the
clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-5
indicates the typical reduction in current consumption achieved by turning off the clocks.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

Table 6-5. Typical Current Consumption by Various

Peripherals (at 100 MHz)

PERIPHERAL IDDCURRENT

MODULE REDUCTION (mA)

ADC 8

I2C 5

eQEP 5

ePWM 5

eCAP 2

SCI 4

SPI 5

eCAN 11

(1) All peripheral clocks are disabled upon reset. Writing to/reading from

peripheral registers is possible only after the peripheral clocks are
turned on.

(2) For peripherals with multiple instances, the current quoted is per

module. For example, the 5 mA number quoted for ePWM is for one
ePWM module.

(3) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(I

) as well.

DDA18

(1)

(2)

(3)

NOTE

I

current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

DDIO

NOTE

The baseline IDDcurrent (current when the core is executing a dummy loop with no
peripherals enabled) is 110 mA, typical. To arrive at the IDDcurrent for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to the
baseline IDDcurrent.

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0.0

100.0

200.0

300.0

400.0

500.0

600.0

10 20 30 40 50 60 70 80 90 100

SYSCLKOUT (MHz)

Device Power (mW)

TOTAL POWER

0.0

50.0

100.0

150.0

200.0

250.0

10 20 30 40 50 60 70 80 90 100

SYSCLKOUT (MHz)

Current (mA)

IDD IDDA18 IDDIO IDD3VFL 3.3-V current

1.8-V current

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N –OCTOBER 2003–REVISED MAY 2012

6.4.2 Current Consumption Graphs

Figure 6-1. Typical Operational Current Versus Frequency (F2808)

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100 Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated

Figure 6-2. Typical Operational Power Versus Frequency (F2808)

NOTE

Typical operational current for 60-MHz devices can be estimated from Figure 6-1. For I
current alone, subtract the current contribution of non-existent peripherals after scaling the
peripheral currents for 60 MHz. For example, to compute the current of F2801-60 device, the
contribution by the following peripherals must be subtracted from IDD: ePWM4/5/6, eCAP3/4,
eQEP2, SCI-B.

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TMS320C2801 TMS320F28016 TMS320F28015

DD