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TMS320DM644x
User Manual
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User Manual
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Texas Instruments TMS320DM644x User Manual

TMS320DM644x DMSoC
General-Purpose Input/Output (GPIO)
User's Guide
Literature Number: SPRUE25
December 2005
2 SPRUE25 – December 2005
Contents
Preface ............................................................................................................................... 6
1.1 Purpose of the Peripheral.......................................................................................... 8
1.2 Features .............................................................................................................. 8
1.3 Functional Block Diagram ......................................................................................... 9
1.4 Industry Standard(s) Compliance Statement .................................................................... 9
2.1 Clock Control ........................................................................................................ 9
2.2 Signal Descriptions ................................................................................................. 9
2.3 GPIO Register Structure ......................................................................................... 10
2.4 Using a GPIO Signal as an Output ............................................................................. 11
2.5 Using a GPIO Signal as an Input ............................................................................... 12
2.6 Reset Considerations ............................................................................................. 13
2.7 Interrupt Support .................................................................................................. 13
2.8 EDMA Event Support ............................................................................................. 15
2.9 Power Management ............................................................................................... 15
2.10 Emulation Considerations ........................................................................................ 15
3 Registers .................................................................................................................. 16
3.1 Peripheral Identification Register (PID) ......................................................................... 17
3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................... 18
3.3 GPIO Direction Registers (DIR n) ................................................................................ 19
3.4 GPIO Output Data Register (OUT_DATA n) ................................................................... 20
3.5 GPIO Set Data Register (SET_DATA n) ........................................................................ 21
3.6 GPIO Clear Data Register (CLR_DATA n) ..................................................................... 23
3.7 GPIO Input Data Register (IN_DATA n) ........................................................................ 25
3.8 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIG n) ............................................... 26
3.9 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIG n) ............................................ 28
3.10 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIG n) .............................................. 30
3.11 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIG n) .......................................... 32
3.12 GPIO Interrupt Status Register (INTSTAT n)................................................................... 34
SPRUE25 – December 2005 Table of Contents 3
List of Figures
1 GPIO Peripheral Block Diagram ........................................................................................... 9
2 Peripheral Identification Register (PID) .................................................................................. 17
3 GPIO Interrupt Per-Bank Enable Register (BINTEN) .................................................................. 18
4 GPIO Banks 0 and 1 Direction Register (DIR01) ...................................................................... 19
5 GPIO Banks 2 and 3 Direction Register (DIR23) ...................................................................... 19
6 GPIO Bank 4 Direction Register (DIR4) ................................................................................. 19
7 GPIO Banks 0 and 1 Output Data Register (OUT_DATA01)......................................................... 20
8 GPIO Banks 2 and 3 Output Data Register (OUT_DATA23)......................................................... 20
9 GPIO Bank 4 Output Data Register (OUT_DATA4) ................................................................... 20
10 GPIO Banks 0 and 1 Set Data Register (SET_DATA01) ............................................................. 21
11 GPIO Banks 2 and 3 Set Data Register (SET_DATA23) ............................................................. 21
12 GPIO Bank 4 Set Data Register (SET_DATA4) ....................................................................... 21
13 GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .......................................................... 23
14 GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .......................................................... 23
15 GPIO Bank 4 Clear Data Register (CLR_DATA4) ..................................................................... 23
16 GPIO Banks 0 and 1 Input Data Register (IN_DATA01) .............................................................. 25
17 GPIO Banks 2 and 3 Input Data Register (IN_DATA23) .............................................................. 25
18 GPIO Bank 4 Input Data Register (IN_DATA4) ........................................................................ 25
19 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (SET_RIS_TRIG01) .................................... 26
20 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (SET_RIS_TRIG23) .................................... 26
21 GPIO Bank 4 Set Rising Edge Interrupt Register (SET_RIS_TRIG4) .............................................. 27
22 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG01) ................................. 28
23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG23) ................................. 28
24 GPIO Bank 4 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG4) ............................................ 29
25 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (SET_FAL_TRIG01) ................................... 30
26 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (SET_FAL_TRIG23) ................................... 30
27 GPIO Bank 4 Set Falling Edge Interrupt Register (SET_FAL_TRIG4) .............................................. 31
28 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG01) ................................. 32
29 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG23) ................................. 32
30 GPIO Bank 4 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG4) ........................................... 33
31 GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ........................................................ 34
32 GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ........................................................ 34
33 GPIO Bank 4 Interrupt Status Register (INTSTAT4) .................................................................. 35
List of Figures4 SPRUE25 – December 2005
List of Tables
1 GPIO Register Bits and Banks Associated With GPIO Pins ......................................................... 10
2 GPIO Interrupts to the ARM CPU and DSP CPU ...................................................................... 13
3 GPIO Synchronization Events to the EDMA ............................................................................ 15
4 General-Purpose Input/Output (GPIO) Registers ...................................................................... 16
5 Peripheral Identification Register (PID) Field Descriptions ........................................................... 17
6 GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ........................................... 18
7 GPIO Direction Register (DIR n) Field Descriptions .................................................................... 19
8 GPIO Output Data Register (OUT_DATA n) Field Descriptions ...................................................... 20
9 GPIO Set Data Register (SET_DATA n) Field Descriptions .......................................................... 22
10 GPIO Clear Data Register (CLR_DATA n) Field Descriptions ........................................................ 24
11 GPIO Input Data Register (IN_DATA n) Field Descriptions ........................................................... 25
12 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIG n) Field Descriptions ................................. 27
13 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIG n) Field Descriptions ............................... 29
14 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIG n) Field Descriptions ................................. 31
15 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIG n) Field Descriptions .............................. 33
16 GPIO Interrupt Status Register (INTSTAT n) Field Descriptions ..................................................... 35
SPRUE25 – December 2005 List of Tables 5
About This Manual
Notational Conventions

Preface

SPRUE25 – December 2005
Read This First
Describes the general-purpose input/output (GPIO) peripheral in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the DM644x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUE14 — TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsytem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the video processing subsystem, and a majority of the peripherals and external memories.
SPRUE15 — TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).
SPRUE19 — TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM644x Digital Media System-on-Chip (DMSoC).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.
Preface6 SPRUE25 – December 2005
www.ti.com
Related Documentation From Texas Instruments
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating
from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.
Trademarks
SPRUE25 – December 2005 Read This First 7

1 Introduction

The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the state of the input by reading the state of an internal register.

1.1 Purpose of the Peripheral

Most system on a chip (SoC) devices require some general-purpose input/output (GPIO) functionality in order to interact with other components in the system using low-speed interface pins. The control and use of the GPIO capability on this device is grouped together in the GPIO peripheral and is described in the following sections.
User's Guide
SPRUE25 – December 2005
General-Purpose Input/Output (GPIO)

1.2 Features

The GPIO peripheral consists of the following features.
• Output set/clear functionality through separate data set and clear registers allows multiple software processes to control GPIO signals without critical section protection.
• Set/clear functionality through writing to a single output data register is also supported.
• Separate input/output registers
– Output register can be read to reflect output drive status. – Input register can be read to reflect pin status.
• Some GPIO signals can be used as interrupt sources with configurable edge detection.
8 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005
www.ti.com

1.3 Functional Block Diagram

DIR
register logic
Direction
register
SET_DATA
CLR_DATA
register
OUTDATA
register
GPIO signal
Synchronizing flip−flops
INDATA
register
SET_RIS_TRIG
register
CLR_RIS_TRIG
register
SET_FAL_TRIG
register
CLR_FAL_TRIG
register
register
INSTAT
Edge
detection
logic
EDMA event
Interrupt to ARM or DSP CPU
Figure 1 shows a block diagram of the GPIO peripheral.
Peripheral Architecture
Figure 1. GPIO Peripheral Block Diagram

1.4 Industry Standard(s) Compliance Statement

The GPIO peripheral connects to external devices. While it is possible that the software implements some standard connectivity protocol over GPIO, the GPIO peripheral itself is not compliant with any such standards.

2 Peripheral Architecture

The following sections describe the GPIO peripheral.

2.1 Clock Control

The input clock to the GPIO peripheral is the SYSCLK5 chip-level clock. SYSCLK5 represents PLL1 divided by 6. The maximum operation speed for the GPIO peripheral is 10 MHz.

2.2 Signal Descriptions

The DM644x device supports up to 71 GPIO signals. GPIO[53:0] are 1.8V I/O signals. GPIOV33_[16:0] are 3.3V I/O signals. For information on the package pinout of each GPIO signal, refer to the device data manual.
SPRUE25 – December 2005 General-Purpose Input/Output (GPIO) 9
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Peripheral Architecture

2.3 GPIO Register Structure

The GPIO signals are grouped into banks of 16 signals per bank. The GPIO configuration registers are organized as one 32-bit register per pair of banks. When there are
an odd number of banks, the upper 16-bit of registers for the last pair are reserved and have no effect. For the interrupt configuration, the registers associated with GPIO signals that do not support interrupt capability are also reserved and have no effect. Table 1 shows the banks and register control bit information associated with each GPIO pin on the device. The table can be used to locate the register bits that control each GPIO signal. For detailed information on the GPIO registers, see section Section 3 .
GPIO Signal Bank Number Register Pair Number Register Field Number Bit Number
Table 1. GPIO Register Bits and Banks Associated With GPIO Pins
GPIO0 0 register_name01 field_name0 Bit 0 GPIO1 0 register_name01 field_name1 Bit 1 GPIO2 0 register_name01 field_name2 Bit 2 GPIO3 0 register_name01 field_name3 Bit 3 GPIO4 0 register_name01 field_name4 Bit 4 GPIO5 0 register_name01 field_name5 Bit 5 GPIO6 0 register_name01 field_name6 Bit 6 GPIO7 0 register_name01 field_name7 Bit 7 GPIO8 0 register_name01 field_name8 Bit 8
GPIO9 0 register_name01 field_name9 Bit 9 GPIO10 0 register_name01 field_name10 Bit 10 GPIO11 0 register_name01 field_name11 Bit 11 GPIO12 0 register_name01 field_name12 Bit 12 GPIO13 0 register_name01 field_name13 Bit 13 GPIO14 0 register_name01 field_name14 Bit 14 GPIO15 0 register_name01 field_name15 Bit 15 GPIO16 1 register_name01 field_name16 Bit 16 GPIO17 1 register_name01 field_name17 Bit 17 GPIO18 1 register_name01 field_name18 Bit 18 GPIO19 1 register_name01 field_name19 Bit 19 GPIO20 1 register_name01 field_name20 Bit 20 GPIO21 1 register_name01 field_name21 Bit 21 GPIO22 1 register_name01 field_name22 Bit 22 GPIO23 1 register_name01 field_name23 Bit 23 GPIO24 1 register_name01 field_name24 Bit 24 GPIO25 1 register_name01 field_name25 Bit 25 GPIO26 1 register_name01 field_name26 Bit 26 GPIO27 1 register_name01 field_name27 Bit 27 GPIO28 1 register_name01 field_name28 Bit 28 GPIO29 1 register_name01 field_name29 Bit 29 GPIO30 1 register_name01 field_name30 Bit 30 GPIO31 1 register_name01 field_name31 Bit 31 GPIO32 2 register_name23 field_name32 Bit 0 GPIO33 2 register_name23 field_name33 Bit 1 GPIO34 2 register_name23 field_name34 Bit 2 GPIO35 2 register_name23 field_name35 Bit 3 GPIO36 2 register_name23 field_name36 Bit 4 GPIO37 2 register_name23 field_name37 Bit 5
General-Purpose Input/Output (GPIO)10 SPRUE25 – December 2005
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Peripheral Architecture
Table 1. GPIO Register Bits and Banks Associated With GPIO Pins (continued)
GPIO Signal Bank Number Register Pair Number Register Field Number Bit Number
GPIO38 2 register_name23 field_name38 Bit 6 GPIO39 2 register_name23 field_name39 Bit 7 GPIO40 2 register_name23 field_name40 Bit 8 GPIO41 2 register_name23 field_name41 Bit 9 GPIO42 2 register_name23 field_name42 Bit 10 GPIO43 2 register_name23 field_name43 Bit 11 GPIO44 2 register_name23 field_name44 Bit 12 GPIO45 2 register_name23 field_name45 Bit 13 GPIO46 2 register_name23 field_name46 Bit 14 GPIO47 2 register_name23 field_name47 Bit 15 GPIO48 3 register_name23 field_name48 Bit 16 GPIO49 3 register_name23 field_name49 Bit 17 GPIO50 3 register_name23 field_name50 Bit 18 GPIO51 3 register_name23 field_name51 Bit 19 GPIO52 3 register_name23 field_name52 Bit 20 GPIO53 3 register_name23 field_name53 Bit 21
GPIOV33_0 3 register_name23 field_name54 Bit 22 GPIOV33_1 3 register_name23 field_name55 Bit 23 GPIOV33_2 3 register_name23 field_name56 Bit 24 GPIOV33_3 3 register_name23 field_name57 Bit 25 GPIOV33_4 3 register_name23 field_name58 Bit 26 GPIOV33_5 3 register_name23 field_name59 Bit 27 GPIOV33_6 3 register_name23 field_name60 Bit 28 GPIOV33_7 3 register_name23 field_name61 Bit 29 GPIOV33_8 3 register_name23 field_name62 Bit 30
GPIOV33_9 3 register_name23 field_name63 Bit 31 GPIOV33_10 4 register_name4 field_name64 Bit 0 GPIOV33_11 4 register_name4 field_name65 Bit 1 GPIOV33_12 4 register_name4 field_name66 Bit 2 GPIOV33_13 4 register_name4 field_name67 Bit 3 GPIOV33_14 4 register_name4 field_name68 Bit 4 GPIOV33_15 4 register_name4 field_name69 Bit 5 GPIOV33_16 4 register_name4 field_name70 Bit 6

2.4 Using a GPIO Signal as an Output

GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO direction register (DIR). This section describes using the GPIO signal as an output signal.
2.4.1 Configuring a GPIO Output Signal
To configure a given GPIO signal as an output, clear the bit in DIR that is associated with the desired GPIO signal. For detailed information on DIR, see Section 3 .
SPRUE25 – December 2005 General-Purpose Input/Output (GPIO) 11
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