Texas instruments TMS320DM6443 User Manual

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SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

TMS320DM6443

Digital Media System-on-Chip

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1 Digital Media System-on-Chip (DMSoC)

1.1 Features

• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture – 594-MHz C64x+™ Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct – 297-MHz ARM926EJ-S™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 4752 C64x+ MIPS – Fully Software-Compatible With C64x /

ARM9™

• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core

– Eight Highly Independent Functional Units

• Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

• Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • ARM9 Memory Architecture Results) per Clock Cycle

– Load-Store Architecture With Non-Aligned

Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional – Additional C64x+™ Enhancements

• Protected Mode Operation

• Exceptions Support for Error Detection and Program Redirection

• Hardware Support for Modulo Loop Operation

• C64x+ Instruction Set Features – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions – Additional Instructions to Support Complex

Multiplies

Mapped)

– 80K-Byte L1D Data RAM/Cache (2-Way

Set-Associative)

– 64K-Byte L2 Unified Mapped RAM/Cache

(Flexible RAM/Cache Allocation)

• ARM926EJ-S Core – Support for 32-Bit and 16-Bit (Thumb®

Mode) Instruction Sets

– DSP Instruction Extensions and Single Cycle

MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ Logic for Real-Time

Debug

– 16K-Byte Instruction Cache – 8K-Byte Data Cache – 16K-Byte RAM – 8K-Byte ROM

• Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug

• Endianness: Little Endian for ARM and DSP

• Video Processing Subsystem – Resize Engine Provides:

• Resize Images From 1/4x to 4x

• Separate Horizontal and Vertical Control

– Back End Provides:

• Hardware On-Screen Display (OSD)

• 4 - 54 MHz DACs for a Combination of – Composite NTSC/PAL Video – Luma/Chroma Separate Video

(S-video)

– Component (YPbPr or RGB) Video

(Progressive)

• Digital Output – 8-/16-Bit YUV or up to 24-Bit RGB – HD Resolution – Up to 2 Video Windows

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

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• External Memory Interfaces (EMIFs) • 10/100 Mb/s Ethernet MAC (EMAC) – 32-Bit DDR2 SDRAM Memory Controller With – IEEE 802.3 Compliant

256M-Byte Address Space (1.8-V I/O)

– Asynchronous16-Bit-Wide EMIF (EMIFA)

With 128M-Byte Address Reach

• Flash Memory Interfaces – NOR (8-/16-Bit-Wide Data) – NAND (8-/16-Bit-Wide Data)

• Flash Card Interfaces

– Media Independent Interface (MII)

• VLYNQ™ Interface (FPGA Interface)

• Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data

• USB Port With Integrated 2.0 PHY – USB 2.0 High-/Full-Speed (480 Mbps) Client – USB 2.0 High-/Full-/Low-Speed Host

– Multimedia Card (MMC)/Secure Digital (SD) (Mini-Host, Supporting One External

with Secure Data I/O (SDIO) Device)

– Compact Flash Controller With True IDE • Three Pulse Width Modulator (PWM) Outputs

Mode

• On-Chip ARM ROM Bootloader (RBL) to Boot

– SmartMedia From NAND Flash or UART

• Enhanced Direct-Memory-Access (EDMA3) • ATA/ATAPI I/F (ATA/ATAPI-6 Specification) Controller (64 Independent Channels)

• Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)

• One 64-Bit Watch Dog Timer

• Three UARTs (One with RTS and CTS Flow Control)

• One Serial Peripheral Interface (SPI) with Two Chip-Selects

• Master/Slave Inter-Integrated Circuit (I2C Bus™)

• Audio Serial Port (ASP) – I2S – AC97 Audio Codec Interface – Standard Voice Codec Interface (AIC12)

• Individual Power-Saving Modes for ARM/DSP

• Flexible PLL Clock Generators

• IEEE-1149.1 (JTAG) BoundaryScan-Compatible

• Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)

• 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch

• 0.09-mm/6-Level Cu Metal Process (CMOS)

• 3.3-V and 1.8-V I/O, 1.2-V Internal

• Applications: – Digital Media – Networked Media Encode/Decode – Video Imaging

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1.2 Description

The TMS320DM6443 (also referenced as DM6443) leverages TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program Memory Management Units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

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The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

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The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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JTAG Interface

System Control

PLLs/Clock

Generator

Input

Clock(s)

Power/Sleep

Controller

Multiplexing

ARM Subsystem

ARM926EJ-S CPU

16 KB

I-Cache

16 KB RAM

8 KB

D-Cache

8 KB ROM

DSP Subsystem

C64x+t DSP CPU

32 KB

L1 Pgm

64 KB L2 RAM

80 KB

L1 Data

Video Processing Subsystem (VPSS)

Front End

Resizer

10b DAC

On-Screen

Display

(OSD)

Video

Encoder

(VENC)

10b DAC

10b DAC 10b DAC

Back End 8b BT.656,

Y/C, 24b RGB

NTSC/ PAL, S-Video, RGB, YPbPr

Switched Central Resource (SCR)

Peripherals

EDMA3

Audio Serial

Port

I2C SPI

UART

Serial Interfaces

DDR2

Mem Ctlr

(16b/32b)

Async EMIF/

NAND/

SmartMedia

ATA/

Compact

Flash

MMC/

SD/

SDIO

Program/Data Storage

Watchdog

Timer

PWM

System

GeneralPurpose

Timer

USB 2.0

PHY

VLYNQ

EMAC

With

MDIO

Connectivity

HPI

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Figure 1-1. TMS320DM6443 Functional Block Diagram

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1 Digital Media System-on-Chip (DMSoC) ............ 1 6 Peripheral and Electrical Specifications .......... 89

1.1 Features .............................................. 1

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 5

Revision History .............................................. 7

2 Device Overview ....................................... 11

2.1 Device Characteristics .............................. 11

2.2 Device Compatibility ................................ 12

2.3 ARM Subsystem .................................... 12

2.4 DSP Subsystem .................................... 17

2.5 Memory Map Summary ............................. 21

2.6 Pin Assignments .................................... 25

2.7 Terminal Functions ................................. 29

2.8 Device Support ..................................... 56

3 Device Configurations ................................ 61

3.1 System Module Registers .......................... 61

3.2 Power Considerations .............................. 62

3.3 Bootmode ........................................... 63

3.4 Configurations at Reset ............................ 66

3.5 Configurations After Reset ......................... 70

3.6 Emulation Control ................................... 82

4 System Interconnect .................................. 84

4.1 System Interconnect Block Diagram ............... 85

5 Device Operating Conditions ....................... 86

5.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(Unless Otherwise Noted) ................................. 86

5.2 Recommended Operating Conditions .............. 87

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 88

6.1 Parameter Information .............................. 89

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 90

6.3 Power Supplies ..................................... 90

6.4 Reset ............................................... 99

6.5 External Clock Input From MXI/CLKIN Pin ........ 102

6.6 Clock PLLs ........................................ 105

6.7 Interrupts .......................................... 111

6.8 General-Purpose Input/Output (GPIO) ............ 118

6.9 Enhanced Direct Memory Access (EDMA3)

Controller .......................................... 121

6.10 External Memory Interface (EMIF) ................ 133

6.11 ATA/CF ............................................ 142

6.12 MMC/SD/SDIO .................................... 155

6.13 Video Processing Sub-System (VPSS) Overview

..................................................... 158

6.14 Host-Port Interface (HPI) .......................... 171

6.15 USB 2.0 ........................................... 174

6.16 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 183

6.17 Serial Peripheral Interface (SPI) .................. 186

6.18 Inter-Integrated Circuit (I2C) ...................... 190

6.19 Audio Serial Port (ASP) ........................... 193

6.20 Ethernet Media Access Controller (EMAC) ....... 197

6.21 Management Data Input/Output (MDIO) .......... 203

6.22 Timer .............................................. 205

6.23 Pulse Width Modulator (PWM) .................... 207

6.24 VLYNQ ............................................ 209

6.25 IEEE 1149.1 JTAG ................................ 213

7 Mechanical Packaging and Orderable

Information ............................................ 215

7.1 Thermal Data for ZWT ............................ 215

7.2 Packaging Information ............................ 215

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This data manual revision history highlights the technical changes made to the SPRS282F device-specific data manual to make it an SPRS282G revision.

Scope: Added information/data on silicon revision 2.3. Applicable updates to the DM64x device family, specifically relating to the TMS320DM6443 device, have been incorporated.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

TMS320DM6443 Revision History

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Global

Section 1.3 Figure 1-1, TMS320DM6443 Functional Block Diagram:

Functional Block Diagram

Section 2.1 Table 2-1, Characteristics of the Processor:

Device Characteristics

• Added information/data on silicon revision 2.3

• Updated/changed all applicable EDMA instances to "EDMA3" [Cleared Documentation Feedback Issue]

• Updated the document to reflect the following: – "ARM can boot from internal ROM SPI".

• Removed PCLK

• Video Processing Subsystem (VPSS): – Removed CCD Controller Video Interface, Histogram/3A, and Preview from Front End block

• Updated/changed "C64x+ Megamodule Revision" for silicon revision 2.3

• Updated/changed "JTAG BSDL_ID" for silicon revision 2.3

• Added "ball finish SnAgCu" to the BGA Package HARDWARE FEATURES row [Cleared Documentation Feedback Issue]

Section 2.4

DSP Subsystem

Section 2.8.2 Figure 2-6, Device Nomenclature:

Device and Development-Support Tool Nomenclature

Section 2.8.3.1

Related Documentation From Texas Instruments

Section 3.3.1.1

BOOTCFG Register Description

Section 3.5.1 Table 3-12, DM6443 Default Bus Master Priorities:

Switched Central Resource (SCR) Bus Priorities

Section 3.5.2 "A summary of the pin multiplexing is ..." paragraph:

Multiplexed Pin Configurations

• Added DSP Subsystem features list

• Added "B = Silicon 2.3" under SILICON REVISION

• Updated/changed list of reference documents

• Updated/changed the location of the BOOTCFG register from "0x01C4 000A" to "0x01C4 0014" [Cleared Documentation Feedback Issue]

• Added, for clarity, ", DMA_PRI bit field" to the VPSSP DEFAULT PRIORITY LEVEL description [Cleared Documentation Feedback Issue]

• Added "[For more detailed information ..." statement to the VPSSP, EDMATC0P, EDMATC1P, and C64X+_DMAP rows

• Added "(MSTPRI1 Register)" to the HPIP DEFAULT PRIORITY LEVEL description

Figure 3-6, MSTPRI1 Register:

• Updated/changed bits 22:20 from Reserved to HPIP

• Added "these are multiplexed with GPIOs" to "The VPBE function of the VPSS requires ..." sentence

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TMS320DM6443 Revision History (continued)

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Section 3.5.2 Table 3-13, DM6443 Multiplexed Peripheral Pins and Multiplexing Controls:

Multiplexed Pin Configurations

Section 3.5.4 Figure 3-7, PINMUX0 Register:

PINMUX0 Register Description

Section 6.3.1.3 Figure 6-6, PLL1 and PLL2 Clock Domain Block Diagram:

DM6443 Power and Clock Domains

• "VPFE CCD, VPBE RGB888, GPIO" row: – MULTIPLEXED PERIPHERALS column: Removed "VPFE CCD" from "VPFE CCD, VPBE

RGB888, GPIO" – TERTIARY FUNCTION column: Removed "VPFE: CCD_FIELD" – TERTIARY REGISTER/PIN CONTROL column: Removed "PinMux0:CFLDEN"

• "UART2, VPFE" row: – MULTIPLEXED PERIPHERALS column: Removed "VPFE" from "UART2, VPFE" – PRIMARY (DEFAULT) FUNCTION column: Updated/changed "VPFE:

CI[7:6]/CCD_DATA[15:14]" to "N/A"

• "UART2, VPFE" row: – MULTIPLEXED PERIPHERALS column: Removed "VPFE" from "UART2, VPFE" – PRIMARY (DEFAULT) FUNCTION column: Updated/changed "VPFE:

CI[5:4]/CCD_DATA[13:12]" to "N/A"

• Bits 28–26: Updated/changed "R/W-0" to "R/W-000"

• Bits 4–0: Updated/changed "R/W-LLLL" to "R/W-LLLLL"

• Updated/changed footnote—removed bit 29 from footnote

Table 3-14, PINMUX0 Register Description:

• Updated/changed the description of HPIEN [Cleared Documentation Feedback Issue]

• Added "HPI" block

• Updated/changed "EDMA" to "EDMA3"

• Removed PCLK

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Section 6.3.1.4 Table 6-6, PSC Register Memory Map [Cleared Documentation Feedback Issue]:

Power and Sleep Controller (PSC) Module

Section 6.4.1 Figure 6-9, Reset Timing:

Reset Electrical Data/Timing

Section 6.6.3 Table 6-19, Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1:

Clock PLL Electrical Data/Timing (Input and Output Clocks)

Section 6.9

Enhanced Direct Memory Access (EDMA3) Controller

Section 6.10.1.2 Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous

EMIFA Electrical Memory Cycles for EMIFA Module: Data/Timing

Section 6.12.1 Table 6-43, MMC/SD/SDIO Register Descriptions:

MMC/SD/SDIO Peripheral Description(s)

Section 6.13

Video Processing Sub-System (VPSS) Overview

• Updated/changed address range "0x01C4 1004 through 0x01C4 1014 to "Reserved"

• Updated/changed address range "0x01C4 107C through 0x01C4 111F to "Reserved"

• Updated/changed address range "0x01C4 1308 through 0x01C4 17FF to "Reserved"

• Updated/changed the pins specified in the Z Group [Cleared Documentation Feedback Issue]

• Parameter 1 (tC): Added "ns" in UNIT column

• Added "The EDMA3 controller supports two addressing modes ..." paragraph

• Parameter 24 [t

• Updated/changed 0x01E1 0064 from "SDIO" to "SDIOCTL (SDIO Control Register)"

• Updated/changed 0x01E1 0068 from "SDIO" to "SDIOST0 (SDIO Status Register 0)"

• Updated/changed 0x01E1 006C from "SDIO" to "SDIOIEN (SDIO Interrupt Enable Register)"

• Updated/changed 0x01E1 0070 from "Reserved" to "SDIOIST (SDIO Interrupt Status Register)"

• Updated/changed "The DM6443 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface ..." paragraph

• Updated/changed Note

w(EMWEL)

]: Added "ns" in UNIT column

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TMS320DM6443 Revision History (continued)

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Section 6.13.1.2 VPFE Electrical Data/Timing

Section 6.13.2.3 Table 6-52, Timing Requirements for VPBE CLK Inputs:

VPBE Electrical Data/Timing

• Removed "VPFE Electrical Data/Timing" section

• Removed Parameter 1 [t

• Removed Parameter 2 [t

• Removed Parameter 3 [t

• Removed Parameter 4 [t

], Cycle time, PCLK

c(PCLK)

], Pulse duration, PCLK high

w(PCLKH)

], Pulse duration, PCLK low

w(PCLKL)

], Transition time, PCLK

t(PCLK)

Figure 6-46, VPBECLK Timing:

• Updated/changed figure title from "VPBE PCLK and VPBECLK Timing" to "VPBECLK Timing"

• Removed PCLK waveform

Table 6-53, Timing Requirements for VPBE Control Input With Respect to VPBECLK:

• Updated/changed table title from "Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK" to "Timing Requirements for VPBE Control Input With Respect to VPBECLK"

• Removed Parameter 9 [t

• Removed Parameter 10 [t

su(VCTLV-PCLK)

h(PCLK-VCTLV)

• Renumbered Parameter 27 as Parameter 9 [t VPBECLK rising edge

• Renumbered Parameter 28 as Parameter 10 [t VPBECLK rising edge

• Removed Parameter 33 [t

• Removed Parameter 34 [t

su(FIELD-PCLK) h(PCLK-FIELD)

• Renumbered Parameter 35 as Parameter 33 [t VPBECLK edge

• Renumbered Parameter 36 as Parameter 34 [t VPBECLK edge

], Setup time, VCTL valid before PCLK edge

], Hold time, VCTL valid after PCLK edge

su(VCTLV-VPBECLK)

h(VPBECLK-VCTLV)

], Setup time, LCD_FIELD valid before PCLK edge

], Hold time, LCD_FIELD valid after PCLK edge

su(FIELD-VPBECLK)

h(VPBECLK-FIELD)

• Removed "PCLK may be configured ..." footnote

• Updated/changed "P = 1/(VCLKIN clock frequency) in ns ..." footnote

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

], Setup time, VCTL valid before

], Hold time, VCTL valid after

], Setup time, LCD_FIELD valid before

], Hold time, LCD_FIELD valid after

Figure 6-47, VPBE Input Timing With Respect to VPBECLK:

• Updated/changed figure title from "VPBE Input Timing With Respect to PCLK and VPBECLK" to "VPBE Input Timing With Respect to VPBECLK"

• Removed VPBECLK waveform

• Renamed PCLK (Positive Edge Clocking) waveform as VPBECLK waveform

• Removed PCLK (Negative Edge Clocking) waveform

• Removed Parameters 27, 28, 35, and 36

Table 6-54, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VPBECLK:

• Updated/changed table title from "Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and VPBECLK" to "Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VPBECLK"

• Removed Parameter 11 [t

• Removed Parameter 12 [t

• Removed Parameter 13 [t

• Removed Parameter 14 [t

d(PCLK-VCTLV) d(PCLK-VCTLIV) d(PCLK-VDATAV) d(PCLK-VDATAIV)

], Delay time, PCLK edge to VCTL valid

], Delay time, PCLK edge to VCTL invalid

], Delay time, PCLK edge to VDATA valid

], Delay time, PCLK edge to VDATA invalid

• Removed "PCLK may be configured ..." footnote

Figure 6-48, VPBE Output Timing With Respect to VPBECLK:

• Updated/changed figure title from "VPBE Output Timing With Respect to PCLK and VPBECLK" to "VPBE Output Timing With Respect to VPBECLK"

• Removed PCLK (Positive Edge Clocking) waveform

• Removed PCLK (Negative Edge Clocking) waveform

• Removed Parameters 11, 12, 13, and 14

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TMS320DM6443 Revision History (continued)

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Table 6-55, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VCLK:

• Updated/changed PARAMETER NO. 22 to "Delay time, VCLKIN low to VCLK low". [Cleared Documentation Feedback Issue]

• Updated/changed "VCLKIN = PCLK or VPBECLK" footnote to "VCLKIN = VPBECLK"

Figure 6-49, VPBE Control and Data Output Timing With Respect to VCLK:

• Updated/changed "VCLKIN = PCLK or VPBECLK" footnote to "VCLKIN = VPBECLK"

Section 6.13.2.4

DAC Electrical Data/Timing

Section 6.25

IEEE 1149.1 JTAG

Section 6.25.1

JTAG Peripheral Register Description(s) – JTAG ID Register

• Updated/changed "The DM6443's analog video DAC outputs ..." paragraph. [Cleared Documentation Feedback Issue]

• Updated/changed the "TRST only needs to be released when it is necessary to use ..." paragraph. [Cleared Documentation Feedback Issue]

• Added "Note:" to the end of Section 6.25

• Updated/changed "The JTAG ID register is a read-only register ..." paragraph

Figure 6-74, JTAG ID Register Description - DM6443 Register Value - 0xXB70 002F:

• Updated/changed footnote

Table 6-106, JTAG ID Register Selection Bit Descriptions:

• Updated/changed DESCRIPTION of Bits 31:28 (VARIANT)

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2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320DM6443 SoC. The table shows significant features of the

device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES DM6443

DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous EMIF (EMIFA)

Flash Cards MMC/SD with secure data input/output (SDIO)

EDMA3

Timers separate 32-bit timers)

Peripherals Not all peripherals pins are

available at the same time. (For more details, see

Section 3, Device

Configurations.)

On-Chip Memory

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 C64x+ Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 (Silicon Revision 1.3 and earlier)

Revision (address location: 0x0181 2000) 0x0003 (Silicon Revision 2.1 and later) JTAG BSDL_ID

CPU Frequency (Maximum) MHz DM6443 -594

Cycle Time (Minimum) ns DM6443 -594

UART 3 (one with RTS and CTS flow control) SPI 1 (supports 2 slave devices) I2C 1 (Master/Slave) Audio Serial Port [ASP] 1 10/100 Ethernet MAC with Management Data

Input/Output VLYNQ 1 HPI 1 (16-bit multiplexed address/data) General-Purpose Input/Output Port Up to 71 PWM 3 outputs ATA/CF 1 (ATA/ATAPI-6)

Configurable Video Port

USB 2.0 Size (Bytes) 160KB RAM, 8KB ROM

Organization

JTAGID Register 0x0B70 002F (Silicon Revision 1.3 and earlier) (address location: 0x01C4 0028) 0x1B70 002F (Silicon Revision 2.1 and later)

Asynchronous (8/16-bit bus width) RAM, Flash

(NOR,NAND)

Compact Flash SmartMedia/xD

64 independent channels

8 QDMA channels

2 64-Bit General Purpose (each configurable as 2

1 64-Bit Watch Dog

Resizer

1 Output (VPBE)

High Speed Device

High Speed Host

DSP

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 80KB L1 Data (L1D)/Cache (up to 32KB)

• 64KB Unified Mapped RAM/Cache (L2) ARM

• 16KB I-cache

• 8KB D-cache

• 16KB RAM

• 8KB ROM

DSP 594 MHz ARM 297 MHz

DSP 1.68 ns

ARM 3.37 ns

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Table 2-1. Characteristics of the Processor (continued)

HARDWARE FEATURES DM6443

Voltage

PLL Options x1 (Bypass), x22 (-594)

BGA Package 357-Pin BGA (ZWT) Process Technology µm 0.09 µm

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

Core (V) 1.2 V (-594) I/O (V) 1.8 V, 3.3 V CLKIN frequency multiplier

(27 MHz reference) 16 x 16 mm

ball finish SnAgCu

Product Preview (PP), Advance Information (AI), PD or Production Data (PD)

2.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the

C64x DSP family.

2.3 ARM Subsystem

The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem, the VPSS Subsystem, and a majority of the peripherals and external memories.

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The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 8KB Data cache

• Write Buffer

• 16KB Internal RAM (32-bit-wide access)

• 8KB Internal ROM (ARM bootloader for non-EMIFA boot options)

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

• PLL Controller

• Power and Sleep Controller (PSC)

• System Module

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2.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data Caches

• Write buffer

• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

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For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com.

2.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

2.3.3 MMU

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux®, Windows® CE, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

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2.3.4 Caches and Write Buffer

The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables.

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

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2.3.5 Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA3 or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction region at 0x0000 and data region at 0x8000 map to the same physical 16KB TCM RAM. Placing the instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks.

The ARM926EJ-S has built in DMA support for direct accesses to the ARM internal memory from a nonARM device. Furthermore, because of the time critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

2.3.6 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

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2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6443 also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The DM6443 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

2.3.8 ARM Memory Mapping

The ARM memory map is shown in Section 2.5, Memory Map Summary, of this document. The ARM has access to memories shown in the following sections.

2.3.8.1 ARM Internal Memories

The ARM has access to the following ARM internal memories:

• 16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions.

• 8KB ARM Internal ROM

2.3.8.2 External Memories

The ARM has access to the following external memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash / NAND Flash

• ATA/CF

• Flash card devices: – MMC/SD with SDIO – xD – SmartMedia

2.3.8.3 DSP Memories

The ARM has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.3.8.4 ARM-DSP Integration

DM6443 ARM and DSP integration features are as follows:

• DSP visibility from ARM’s memory map, see Section 2.5, Memory Map Summary, for details

• Boot Modes for DSP - see Device Configurations section, Section 3.3.3, DSP Boot, for details

• ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2, ARM Boot, for details

• ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for details

• ARM & DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts, for details

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2.3.9 Peripherals

The ARM9 has access to all of the peripherals on the DM6443 device.

2.3.10 PLL Controller (PLLC)

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for configuring DM6443’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following configuration and control:

• PLL Bypass Mode

• Set PLL multiplier parameters

• Set PLL divider parameters

• PLL power down

• Oscillator power down

The PLLs are briefly described in this document in Section 6.6, Clock PLLs. For more detailed information on the PLLs and PLL Controller register descriptions, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

2.3.11 Power and Sleep Controller (PSC)

The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more detailed information and complete register descriptions for the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

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2.3.12 ARM Interrupt Controller (AINTC)

The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ (interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14)

2.3.13 System Module

The ARM Subsystem includes the System module. The System module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the System module, see Section 3, Device Configurations, and see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

2.3.14 Power Management

DM6443 has several means of managing power consumption. There is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For more details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral and Electrical Specifications, and see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

DM6443 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. Several typical power management scenarios are described in the following sections.

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2.4 DSP Subsystem

The DSP Subsystem includes the following features:

• C64x+ DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 80KB L1 Data (L1D)/Cache (up to 32KB)

• 64KB Unified Mapped RAM/Cache (L2)

• Little endian

2.4.1 C64x+ DSP CPU Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

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The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

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Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.

• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x Technical Overview (literature number SPRU395)

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src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

even dst

odd dst

dst1

dst

src2

long src

DA1

ST1b

LD1b LD1a

ST1a

Data path A

Odd

file A

(A1, A3,

A5...A31)

Odd

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB 32 LSB

dst2

(A)

32 MSB

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B) (A)

(C)

Even

file A

(A0, A2,

A4...A30)

Even

file B

(B0, B2,

B4...B30)

(D)

A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

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Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths

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2.4.2 DSP Memory Mapping

The DSP memory map is shown in Section 2.5, Memory Map Summary. Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections.

2.4.2.1 ARM Internal Memories

The DSP has access to the 16KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).

2.4.2.2 External Memories

The DSP has access to the following External memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash

2.4.2.3 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.4.2.4 C64x+ CPU

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The C64x+ core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 80 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.

Table 2-2. C64x+ Cache Registers

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA3 access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register

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Table 2-2. C64x+ Cache Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P Global Invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate

0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF

0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF

0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF

0x0184 8108 - 0x0184 813C MAR66 - MAR79

0x0184 8140- 0x0184 81FC MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF

0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF

Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 0x4FFF FFFF

2.4.3 Peripherals

The DSP has controllability for the following peripherals:

• EDMA3

• ASP

• 2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers

2.4.4 DSP Interrupt Controller

The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s available interrupts. The DSP Interrupt Controller is briefly described in this document in Section 6.7,

Interrupts. For more detailed on the DSP Interrupt Controller, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

2.5 Memory Map Summary

Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of

the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

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Table 2-3. Memory Map Summary

START END SIZE EDMA3/

ADDRESS ADDRESS (Bytes) PERIPHERAL

0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) 0x0000 4000 0x0000 5FFF 8K ARM ROM (Instruction) 0x0000 6000 0x0000 7FFF 8K Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) Reserved ARM RAM1 ARM RAM1 0x0000 C000 0x0000 DFFF 8K ARM ROM (Data) ARM ROM ARM ROM 0x0000 E000 0x0000 FFFF 8K 0x0001 0000 0x000F FFFF 960K 0x0010 0000 0x001F FFFF 1M 0x0020 0000 0x007F FFFF 6M 0x0080 0000 0x0080 FFFF 64K L2 RAM/Cache 0x0081 0000 0x00E0 7FFF 6112K Reserved 0x00E0 8000 0x00E0 FFFF 32K L1P Cache 0x00E1 0000 0x00F0 3FFF 976K Reserved 0x00F0 4000 0x00F0 FFFF 48K L1D RAM 0x00F1 0000 0x00F1 7FFF 32K L1D Cache 0x00F1 8000 0x017F FFFF 9120K Reserved 0x0180 0000 0x01BB FFFF 3840K 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus Peripherals CFG BusPeripherals CFG Bus Peripherals 0x0200 0000 0x09FF FFFF 128M EMIFA (Code andData) EMIFA (Data) EMIFA (Data) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved VLYNQ (Remote) 0x1000 0000 0x1000 7FFF 32K Reserved 0x1000 8000 0x1000 9FFF 8K ARM RAM0 ARM RAM0 0x1000 A000 0x1000 BFFF 8K ARM RAM1 ARM RAM1 0x1000 C000 0x1000 DFFF 8K ARM ROM ARM ROM 0x1000 E000 0x1000 FFFF 8K 0x1001 0000 0x110F FFFF 17344K 0x1110 0000 0x111F FFFF 1M 0x1120 0000 0x117F FFFF 6M 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache 0x1181 0000 0x11E0 7FFF 6112K Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache 0x11F1 8000 0x1FFF FFFF 241M- Reserved Reserved Reserved

0x2000 0000 0x2000 7FFF 32K DDR2 Control Registers DDR2 Control Registers DDR2 Control Registers DDR2 Control Registers 0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved

0x4200 0000

0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved Reserved

(2)

0x4FFF FFFF 224M Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow Reserved

Reserved

32K

(1) HPI's access to the configuration bus peripherals is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and

HPI configuration registers.

(2) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000

through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be used by C64x+ for both code execution and data accesses.

ARM C64x+ HPI VPSS

Reserved Reserved

(1)

Reserved

Reserved Reserved

Reserved

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Table 2-4. Configuration Memory Map Summary

START END SIZE ARM/EDMA3 C64x+

ADDRESS ADDRESS (Bytes)

0x0180 0000 0x0180 FFFF 64K C64x+ Interrupt Controller 0x0181 0000 0x0181 0FFF 4K C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K C64x+ Security ID 0x0181 2000 0x0181 2FFF 4K C64x+ Revision ID 0x0182 0000 0x0182 FFFF 64K Reserved C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved

0x0188 0000 0x01BB FFFF 3328K Reserved 0x01BC 0000 0x01BC 00FF 256 Reserved 0x01BC 0100 0x01BC 01FF 256 ARM ETB Memory Pin Manager and Trace 0x01BC 0200 0x01BC 0FFF 3.5K 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA3 CC EDMA3 CC 0x01C1 0000 0x01C1 03FF 1K EDMA3 TC0 EDMA3 TC0 0x01C1 0400 0x01C1 07FF 1K EDMA3 TC1 EDMA3 TC1 0x01C1 8800 0x01C1 9FFF 6K 0x01C1 A000 0x01C1 FFFF 24K 0x01C2 0000 0x01C2 03FF 1K UART0 0x01C2 0400 0x01C2 07FF 1K UART1 Reserved 0x01C2 0800 0x01C2 0BFF 1K UART2 0x01C2 0C00 0x01C2 0FFF 1K Reserved 0x01C2 1000 0x01C2 13FF 1K I2C 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (Watchdog) 0x01C2 2000 0x01C2 23FF 1K PWM0 0x01C2 2400 0x01C2 27FF 1K PWM1 Reserved 0x01C2 2800 0x01C2 2BFF 1K PWM2 0x01C2 2C00 0x01C3 FFFF 117K Reserved 0x01C4 0000 0x01C4 07FF 2K System Module System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and Sleep Controller 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP Reg 0x01C4 2034 0x01C4 23FF 1K - 52 0x01C4 2400 0x01C4 7FFF 23K 0x01C4 8000 0x01C4 83FF 1K ARM Interrupt Controller 0x01C4 8400 0x01C5 FFFF 95K 0x01C6 0000 0x01C6 3FFF 16K Reserved 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Registers / RAM 0x01C6 6000 0x01C6 67FF 2K ATA/CF 0x01C6 6800 0x01C6 6FFF 2K SPI 0x01C6 7000 0x01C6 77FF 2K GPIO

Reserved

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Table 2-4. Configuration Memory Map Summary (continued)

START END SIZE ARM/EDMA3 C64x+

ADDRESS ADDRESS (Bytes)

0x01C6 7800 0x01C6 7FFF 2K HPI HPI 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Registers 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Registers 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Registers Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM 0x01C8 4000 0x01C8 47FF 2K MDIO Control Registers 0x01C8 4800 0x01C8 4FFF 2K 0x01C8 5000 0x01CB FFFF 236K 0x01CC 0000 0x01CD FFFF 128K 0x01CE 0000 0x01CF FFFF 128K 0x01D0 0000 0x01DF FFFF 1M

0x01E0 0000 0x01E0 0FFF 4K EMIFA Control

0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Registers

0x01E0 2000 0x01E0 3FFF 8K ASP ASP

0x01E0 4000 0x01E0 FFFF 48K Reserved

0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO

0x01E2 0000 0x01E3 FFFF 128K

0x01E4 0000 0x01FF FFFF 1792K

0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code (CS2) EMIFA Data (CS2)

0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code (CS3) EMIFA Data (CS3)

0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code (CS4) EMIFA Data (CS4)

0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code (CS5) EMIFA Data (CS5)

0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote)

Reserved

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DDR_D[1]

DDR2

EM_A[4]/

GPIO27

CLK_OUT0/

GPIO48

MXI/CLKIN

EM_A[5]/

GPIO26

MXV

PLLV

DD18

RSV24

EM_A[6]/

GPIO25

EM_A[8]/

GPIO23

EM_A[7]/

GPIO24

EM_A[13]/

GPIO18

EM_A[10]/

GPIO21

EM_A[15]/

GPIO16/

VLYNQ_TXD3

EM_A[11]/

GPIO20

EM_A[17]/

GPIO14/

VLYNQ_TXD2

EM_A[19]/

GPIO12/

VLYNQ_TXD1

EM_A[20]/

GPIO11/

VLYNQ_RXD0

EM_CS4

GPIO9/ VLYNQ_ SCRUN

DDR_

DQM[0]

DDR_D[0]

EM_A[21]/

GPIO10/

VLYNQ_TXD0

EM_A[14]/

GPIO17/

VLYNQ_RXD3

EM_A[9]/

GPIO22

MXV

RESET

RSV3

DDR2

DDR_A[11]DDR_A[12]DDR_CLK0

DDR_CLK0DDR_D[14]

DDR2

DDR_D[5]

DDR_D[6]

DDR_D[9]

DD18

EM_A[16]/

GPIO15/

VLYNQ_RXD2

DDR2

DDR_BS[2]

DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8]

DDR2

DDR_

DQM[1]

DDR_CAS

DDR_WE DDR_VDDDLL

DDDSP

DDR_DQS[1] DDR_RAS DDR_A[10]

DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1]

DDR_D[4] DDR_D[12]

EM_A[3]/

GPIO28

DD18

RSV7

MXO V

DD18

EM_A[18]/

GPIO13/

VLYNQ_RXD1

EM_A[12]/

GPIO19

DDR_CS

DDDSP

DDR_DQS[0] DDR_D[10] DDR_BS[0]

EM_CS5

GPIO8/

VLYNQ_

CLOCK

RSV6

DDR_D[7]

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2.6 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document.

2.6.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A,

B, C, and D).

Figure 2-2. Pin Map [Quadrant A]

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DDR_A[9]

DDR2

DDR_

VSSDLL

DDR_ZPDDR_ZN

DD18

RSV11 RSV9

DDA_1P8V

UART_TXD2 UART_RXD2

DAC_IOUT_B

RSV4DDR_D[29]DDR_D[27]DDR_D[21]DDR_D[18]

DAC_IOUT_A

RSV19

DAC_RBIAS

DDR_A[3]

DDR_A[4]

DDR_A[0]

DDR_DQM[2]

DDR_D[26]

RSV16

DDR_D[17] DDR_D[22] DDR_D[24] DDR_D[30]

RSV23

SSA_1P8V

UART_CTS2

RSV14

UART_RTS2

DDR_VREF DDR_DQM[3] DDR_D[23] DAC_IOUT_D

RSV22 RSV20

DDR_D[20] DDR_DQS[3] DDR_D[31]

RSV17 RSV10

DDR_A[7] DDR_A[2] DDR_D[19] DDR_D[28]

DDR_A[6] DDR_D[16]

DAC_IOUT_C

DDDSP

RSV13

RSV18

DAC_V

REF

DD18

RSV15

RSV12

DDR2

DDA_1P1V

DDR2

SSA_1P1V

RSV21

DDR_A[1] DDR_DQS[2] DDR_D[25]

DDR_A[5]

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Figure 2-3. Pin Map [Quadrant B]

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DDDSP

YOUT4/R4/

AEAW4

GPIOV33_1/

TXCLK

GPIOV33_2/

COL

GPIOV33_9/

RXD2

GPIOV33_8/

RXD1

GPIOV33_6/

TXD3

GPIOV33_4/

TXD1

GPIOV33_12/

RXDV

GPIO2/G0

GPIOV33_7/

RXD0

GPIOV33_10/

RXD3

DD33

GPIO1

GPIO0/

LCD_OE

GPIO4/R0

GPIOV33_0/

TXEN

GPIO6/B1

VSYNC VPBECLK

M24XI

YOUT3/R3/

AEAW3

VCLK

YOUT7/R7

CLK_OUT1/

TIM_IN/ GPIO49

PWM1/R2/

GPIO46

M24V

DDDSP

GPIO38/R1

DD18

USB_R1

COUT5/G2

COUT0/B3/

BTSEL0

YOUT6/R6

YOUT2/G7/

AEAW2

COUT7/G4

YOUT1/G6/

AEAW1

DD18

USB_

SSREF

USB_

SSA1P2LD0

USB_DP

COUT2/B5/

EM_WIDTH

RSV2

USB_V

SS1P8

USB_DM

COUT3/B6/

DSP_BT

COUT6/G3

M24XO

GPIOV33_5/

TXD2

PWM2/

B2/GPIO47

HSYNC

COUT1/B4/

BTSEL1

M24V

GPIO3/B0/

LCD_FIELD

PWM0/

GPIO45

YOUT0/G5/

AEAW0

GPIO5/G1 YOUT5/R5

USB_

DDA1P2LD0

COUT4/B7

DD18

USB_V

DD1P8

GPIOV33_3/

TXD0

DDDSP

USB_

SSA3P3

DD18

USB_ID

USB_

DDA3P3

DDDSP

USB_VBUS

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Figure 2-4. Pin Map [Quadrant C]

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EM_BA[1]/

DA1/

GPIO52

TMS

SPI_EN0/

GPIO37

RSV1

EM_CS3

SPI_CLK/

GPIO39

SPI_EN1/

HDDIR/ GPIO42

EM_CS2

HCS

GPIO7

EM_D12/

DD12/

HD12

EM_D1/

DD1/

HD1

EM_D5/

DD5/

HD5

RSV5

EM_D15/

DD15/

HD15

EM_D3/

DD3/

HD3

EM_D9/

DD9/

HD9

EM_D13/

DD13/

HD13

EM_D6/

DD6/ HD6

EM_D8/

DD8/

HD8

EM_WE

/(WE)/

(IOWR

)/DIOW/

HDS2

EM_D11/

DD11/

HD11

GPIO51/

ATA_CS1

EM_R/W

INTRQ/

HR/W

EM_D4/

DD4/

HD4

SCL/

GPIO43

TDOSDA/GPIO44

TDI

SD_DATA3

GPIOV33_14/

CRS

SD_DATA2

GPIOV33_13/

RXER

SD_DATA1

GPIOV33_15/

MDIO

RTCK

DMACK/

UART_TXD1

EM_BA[0]/

DA0/ HINT

UART_RXD0/

GPIO35

EM_D2/

DD2/

HD2

EM_D10/

DD10/ HD10

SD_CMD

GPIO50/

ATA_CS0

DD18

DDDSP

DR/

GPIO34

SD_DATA0

FSR/

GPIO32

TRST

DD18

CLKR/

GPIO30

GPIOV33_11/

RXCLK

DD18

DDDSP

CLKX/

GPIO29

GPIOV33_16/

MDCLK

EM_A[2]/

(CLE)/

HCNTL0

EM_A[1]/

(ALE)/ HHWIL

EM_A[0]/

DA2/

HCNTL1/

GPIO53

DDDSP

DD33

SPI_DO/

GPIO41

TCK

FSX/

GPIO31

DX/

GPIO33

DD18

EM_D7/

DD7/

HD7

UART_TXD0/

GPIO36

EMU1

EMU0

EM_D0/

DD0/

HD0

DD18

EM_WAIT/

(RDY/BSY

IORDY

HRDY

DD18

SD_CLK

EM_OE/(RE)/ (IORD

)/DIOR/

HDS1

EM_D14/

DD14/ HD14

DDDSP

DMARQ/

UART_RXD1

SPI_DI/ GPIO40

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Figure 2-5. Pin Map [Quadrant D]

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2.7 Terminal Functions

The terminal functions tables (Table 2-5 through Table 2-29) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, and multiplexed/shared pins, see Section 3, Device Configurations, of this data manual.

Table 2-5. BOOT Terminal Functions

SIGNAL

NAME NO.

COUT0/

B3/ A16 I/O/Z

BTSEL0

COUT1/

B4/ B16 I/O/Z

BTSEL1

COUT2/ bus width (EM_WIDTH). For an 8-bit-wide EMIFA data

B5/ A17 I/O/Z bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus,

EM_WIDTH EM_WIDTH = 1.

COUT3/ source DSP_BT. The DSP is booted by the ARM when

B6/ B17 I/O/Z DSP_BT=0. The DSP boots from EMIFA when

DSP_BT DSP_BT=1.

YOUT0/

G5/ D15 I/O/Z

AEAW0

YOUT1/ VPBE. At reset, the input states of AEAW[4:0] are

G6/ D16 I/O/Z sampled to set the EMIFA address bus width. See

AEAW1 Section 3.4.2, Peripheral Selection at Device Reset, for

YOUT2/ After reset, these are video encoder outputs YOUT[0:4]

G7/ D17 I/O/Z or RGB666/888 Red and Green data bit outputs G5, G6,

AEAW2 G7, R3, and R4. YOUT3/

R3/ D18 I/O/Z

AEAW3 YOUT4/

R4/ E15 I/O/Z

AEAW4

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) (3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2) (3)

DESCRIPTION

BOOT

These pins are multiplexed between ARM boot mode and the VPBE. At reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to determine the ARM boot

IPD configuration. See below for the boot modes set by these

DD18

inputs. See Section 3.3, Bootmode, for more details. After reset, these are video encoder outputs COUT0 and COUT1, or RGB666/888 Blue output data bits 3 and 4 B3/B4.

BTSEL1 BTSEL0 ARM Boot Mode

ARM ROM Boot (NAND, SPI) [default]

IPD

DD18

0 0 0 1 ARM EMIFA Boot (NOR)

1 0 ARM ROM Boot (HPI) 1 1 ARM ROM Boot (UART0)

This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is sampled to set the EMIFA data

IPD

DD18

After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5 B5.

This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is sampled to set the DSP boot

IPD

DD18

After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output B6.

IPD

DD18

These pins are multiplexed between EMIFA and the

IPD

DD18

details.

IPD

DD18

IPD

DD18

IPD

DD18

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Table 2-6. Oscillator/PLL Terminal Functions

SIGNAL

NAME NO.

MXI/CLKIN L1 I DV

MXO M1 O DV

MXV

L5 S

L2 GND

M24XI F18 I DV

M24XO F19 O DV

M24V

PLLV

DD18

F16 S

F17 GND

M2 S

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal (3) For more information, see Section 5.2, Recommended Operating Conditions.

TYPE

(1)

OTHER

(2)

DESCRIPTION

OSCILLATOR, PLL

Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz). If a crystal

DD18

(3)

input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input.

Crystal output for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXO should be left as a No Connect.

1.8-V power supply for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVDDshould still be connected to the 1.8-V power supply.

(3)

Ground for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVSSshould still be connected to ground.

Crystal input for M24 oscillator (24 MHz for USB). If a crystal input is not used, but

DD18

instead a physical clock-in source is supplied, this is the external oscillator clock input. When the USB peripheral is not used, M24XI should be left as a No Connect.

Crystal output for M24 oscillator. If a crystal input is not used, but instead a physical

DD18

clock-in source is supplied, M24XO should be left as a No Connect. When the USB peripheral is not used, M24XO should be left as a No Connect.

1.8-V power supply for M24 oscillator. If a crystal input is not used, but instead a

(3)

physical clock-in source is supplied, M24VDDshould still be connected to the 1.8-V power supply. When the USB peripheral is not used, M24VDDshould be connected to the 1.8-V power supply.

(3)

Ground for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24VSSshould still be connected to ground. When the USB peripheral is not used, M24VSSshould be connected to ground.

(3)

1.8-V power supply for PLLs (system).

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Table 2-7. Clock Generator Terminal Functions

SIGNAL

NAME NO.

CLK_OUT0/

GPIO48

K1 I/O/Z DV

CLK_OUT1/ This pin is multiplexed between the USB clock generator, timer, and GPIO.

TIM_IN/ E19 I/O/Z DV

GPIO49 12 MHz or 24 MHz clock outputs.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

CLOCK GENERATOR

This pin is multiplexed between the PLL1 clock generator and GPIO.

DD18

For the PLL1 clock generator, it is clock output CLK_OUT0. This is configurable for

13.5 MHz or 27 MHz clock outputs.

For the USB clock generator, it is clock output CLK_OUT1. This is configurable for

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Table 2-8. RESET and JTAG Terminal Functions

SIGNAL

NAME NO.

RESET L4 I This is the active low global reset input.

TMS E6 I JTAG test-port mode select input

TDO B5 O/Z JTAG test-port data output

TDI A5 I JTAG test-port data input

TCK A6 I JTAG test-port clock input

RTCK B6 O/Z JTAG test-port return clock output

TRST D7 I JTAG compatibility statement portion of this data manual (Section 6.25, IEEE

EMU1 C6 I/O/Z Emulation pin 1

EMU0 D6 I/O/Z Emulation pin 0

TYPE

(1)

OTHER

IPU

IPD

IPU

(2) (3)

DD18

–

DD18

–

DD18

DESCRIPTION

RESET

JTAG

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

1149.1 JTAG).

Table 2-9. EMIFA Terminal Functions

SIGNAL

NAME NO.

COUT2/ sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit-wide EMIFA

B5/ A17 I/O/Z data bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus, EM_WIDTH = 1.

EM_WIDTH After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5

COUT3/ sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when

B6/ B17 I/O/Z DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.

DSP_BT After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output

YOUT0/

G5/ D15 I/O/Z

AEAW0

YOUT1/

G6/ D16 I/O/Z

AEAW1

YOUT2/ of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2,

G7/ D17 I/O/Z Peripheral Selection at Device Reset, for details.

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and

YOUT3/

R3/ D18 I/O/Z

AEAW3

YOUT4/

R4/ E15 I/O/Z

AEAW4

TYPE

(1)

OTHER

IPD

(2) (3)

EMIFA BOOT CONFIGURATION

This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is

DD18

B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is

DD18

B6.

DD18

These pins are multiplexed between EMIFA and the VPBE. At reset, the input states

Green data bit outputs G5, G6, G7, R3, and R4.

DD18

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Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_CS2/ For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

HCS memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot

C2 I/O/Z DV

EM_CS3 B1 I/O/Z DV

EM_CS4/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO9/ T2 I/O/Z DV

VLYNQ_SCRUN (i.e., NOR flash) or NAND flash.

EM_CS5/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO8/ T1 I/O/Z DV

VLYNQ_CLOCK (i.e., NOR flash) or NAND flash.

EM_R/W/

INTRQ/ G3 I/O/Z DV

HR/W

EM_WAIT/

(RDY/BSY)/ IPU This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

IORDY/ DV

F1 I/O/Z

HRDY

EM_OE/

(RE)/

(IORD)/ H4 I/O/Z DV

DIOR/ HDS1

EM_WE

(WE)

(IOWR)/ G2 I/O/Z DV

DIOW/

HDS2

EM_BA[0]/

DA0/ J3 I/O/Z

HINT

EM_BA[1]/

DA1/ H2 I/O/Z DV

GPIO52

EM_A[21]/

GPIO10/ T3 I/O/Z DV

VLYNQ_TXD0

EM_A[20]/

GPIO11/ R3 I/O/Z DV

VLYNQ_RXD0

EM_A[19]/

GPIO12/ R4 I/O/Z DV

VLYNQ_TXD1

EM_A[18]/

GPIO13/ P5 I/O/Z DV

VLYNQ_RXD1

EM_A[17]/

GPIO14/ R2 I/O/Z DV

VLYNQ_TXD2

EM_A[16]/

GPIO15/ R5 I/O/Z DV

VLYNQ_RXD2

TYPE

(1)

(2) (3)

OTHER

DESCRIPTION

EMIFA FUNCTIONAL PINS: ASYNC / NOR

This pin is multiplexed between EMIFA and HPI.

DD18

and ROM boot modes.

DD18

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e., NOR flash) or NAND flash.

For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories

For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories

This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, it is read/write output EM_R/W.

For EMIFA, it is wait state extension input EM_WAIT.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is output enable output EM_OE.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.

This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, this is the Bank Address 0 output (EM_BA[0]).

IPD When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of

DD18

the byte address. When connected to a 16-bit asynchronous memory, this pin has the same function as EMIF address pin 22 (EM_A[22]).

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is the Bank Address 1 output EM_BA[1].

DD18

When connected to a 16 bit asynchronous memory this pin is the lowest order bit of the 16-bit word address. When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address.

DD18

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 21 output EM_A[21].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 20 output EM_A[20].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 19 output EM_A[19].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 18 output EM_A[18].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 17 output EM_A[17].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 16 output EM_A[16].

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Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_A[15]/

GPIO16/ P3 I/O/Z DV

VLYNQ_TXD3

EM_A[14]/

GPIO17/ P4 I/O/Z DV

VLYNQ_RXD3

EM_A[13]/ This pin is multiplexed between EMIFA and GPIO.

GPIO18 For EMIFA, it is address bit 13 output EM_A[13].

EM_A[12]/ This pin is multiplexed between EMIFA and GPIO.

GPIO19 For EMIFA, it is address bit 12 output EM_A[12].

EM_A[11]/ This pin is multiplexed between EMIFA and GPIO.

GPIO20 For EMIFA, it is address bit 11 output EM_A[11].

EM_A[10]/ This pin is multiplexed between EMIFA and GPIO.

GPIO21 For EMIFA, it is address bit 10 output EM_A[10].

EM_A[9]/ This pin is multiplexed between EMIFA and GPIO.

GPIO22 For EMIFA, it is address bit 9 output EM_A[9].

EM_A[8]/ This pin is multiplexed between EMIFA and GPIO.

GPIO23 For EMIFA, it is address bit 8 output EM_A[8].

EM_A[7]/ This pin is multiplexed between EMIFA and GPIO.

GPIO24 For EMIFA, it is address bit 7 output EM_A[7].

EM_A[6]/ This pin is multiplexed between EMIFA and GPIO.

GPIO25 For EMIFA, it is address bit 6 output EM_A[6].

EM_A[5]/ This pin is multiplexed between EMIFA and GPIO.

GPIO26 For EMIFA, it is address bit 5 output EM_A[5].

EM_A[4]/ This pin is multiplexed between EMIFA and GPIO.

GPIO27 For EMIFA, it is address bit 4 output EM_A[4].

EM_A[3]/ This pin is multiplexed between EMIFA and GPIO.

GPIO28 For EMIFA, it is address bit 3 output EM_A[3].

N4 I/O/Z DV

R1 I/O/Z DV

P2 I/O/Z DV

P1 I/O/Z DV

M4 I/O/Z DV

N3 I/O/Z DV

N2 I/O/Z DV

N1 I/O/Z DV

K3 I/O/Z DV

K4 I/O/Z DV

K2 I/O/Z DV

EM_A[2]/

(CLE)/ J1 I/O/Z DV

HCNTL0 EM_A[1]/

(ALE)/ J2 I/O/Z DV

HHWIL

EM_A[0]/ For EMIFA, this is Address output EM_A[0], which is the least significant bit on a

DA2/ 32-bit word address.

HCNTL1/ When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the

J4 I/O/Z DV

GPIO53 address.

TYPE

(1)

OTHER

(2) (3)

DD18

DESCRIPTION

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 15 output EM_A[15].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 14 output EM_A[14].

This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is the EM_A[2] address line.

This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI.

This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.

For an 8-bit asynchronous memory, this pin is the 3rd bit of the address.

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Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D0/

DD0/ E5 I/O/Z DV HD0

EM_D1/

DD1/ D3 I/O/Z DV HD1

EM_D2/

DD2/ F5 I/O/Z DV HD2

EM_D3/

DD3/ E3 I/O/Z DV HD3

EM_D4/

DD4/ E4 I/O/Z DV HD4

EM_D5/

DD5/ D2 I/O/Z DV HD5

EM_D6/

DD6/ F4 I/O/Z DV HD6

EM_D7/

DD7/ C1 I/O/Z DV HD7

EM_D8/

DD8/ F3 I/O/Z DV HD8

EM_D9/

DD9/ E2 I/O/Z DV HD9

EM_D10/

DD10/ G5 I/O/Z DV

HD10

EM_D11/

DD11/ G4 I/O/Z DV

HD11

EM_D12/

DD12/ D1 I/O/Z DV

HD12

EM_D13/

DD13/ F2 I/O/Z DV

HD13

EM_D14/

DD14/ H5 I/O/Z DV

HD14

EM_D15/

DD15/ E1 I/O/Z DV

HD15

TYPE

(1)

OTHER

(2) (3)

DD18

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DESCRIPTION

These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0].

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Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_A[1]/

(ALE)/ J2 I/O/Z DV

HHWIL

EM_A[2]/

(CLE)/ J1 I/O/Z DV

HCNTL0

EM_WAIT/

(RDY/BSY)/ IPU This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

IORDY/ DV

F1 I/O/Z

HRDY

EM_OE/

( RE )/

( IORD )/ H4 I/O/Z DV

DIOR/ HDS1

EM_WE

(WE)

(IOWR)/ G2 I/O/Z DV

DIOW/

HDS2

EM_CS2/ For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

HCS memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot

C2 I/O/Z DV

EM_CS3 B1 I/O/Z DV

EM_CS4/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO9/ T2 I/O/Z DV

VLYNQ_SCRUN NAND flash.

EM_CS5/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO8/ T1 I/O/Z DV

VLYNQ_CLOCK NAND flash.

TYPE

(1)

OTHER

(2) (3)

EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD

DD18

This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is read enable output (RE).

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is write enable output (WE).

This pin is multiplexed between EMIFA and HPI.

DD18

and ROM boot modes.

DD18

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e. NOR flash) or NAND flash.

Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

DESCRIPTION

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Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D0/

DD0/ E5 I/O/Z DV HD0

EM_D1/

DD1/ D3 I/O/Z DV HD1

EM_D2/

DD2/ F5 I/O/Z DV HD2

EM_D3/

DD3/ E3 I/O/Z DV HD3

EM_D4/

DD4/ E4 I/O/Z DV HD4

EM_D5/

DD5/ D2 I/O/Z DV HD5

EM_D6/

DD6/ F4 I/O/Z DV HD6

EM_D7/

DD7/ C1 I/O/Z DV HD7

EM_D8/

DD8/ F3 I/O/Z DV HD8

EM_D9/

DD9/ E2 I/O/Z DV HD9

EM_D10/

DD10/ G5 I/O/Z DV

HD10

EM_D11/

DD11/ G4 I/O/Z DV

HD11

EM_D12/

DD12/ D1 I/O/Z DV

HD12

EM_D13/

DD13/ F2 I/O/Z DV

HD13

EM_D14/

DD14/ H5 I/O/Z DV

HD14

EM_D15/

DD15/ E1 I/O/Z DV

HD15

TYPE

(1)

OTHER

(2) (3)

DD18

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DESCRIPTION

These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0].

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Table 2-10. DDR2 Memory Controller Terminal Functions

SIGNAL

NAME NO.

DDR_CLK0 W7 I/O/Z DV DDR_CLK0 W8 I/O/Z DV

DDR_CKE V8 I/O/Z DV

DDR_CS T9 I/O/Z DV

DDR_WE T8 I/O/Z DV DDR_DQM[3] T16 I/O/Z DV DDR_DQM[2] T14 I/O/Z DV DDR_DQM[1] T6 I/O/Z DV DDR_DQM[0] T4 I/O/Z DV

DDR_RAS U7 I/O/Z DV

DDR_CAS T7 I/O/Z DV DDR_DQS[0] U4 I/O/Z DV DDR_DQS[1] U6 I/O/Z DV DDR_DQS[2] U14 I/O/Z DV

DDR_DQS[3] U16 I/O/Z DV

DDR_BS[0] U8 DDR_BS[1] V9 I/O/Z DV DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10

DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 I/O/Z DV DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] U13 DDR_A[0] W13

TYPE

(1)

OTHER

(2) (3)

DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2

DDR2

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

DESCRIPTION

DDR2 Memory Controller

DDR2 Clock DDR2 Differential clock DDR2 Clock Enable DDR2 Active low chip select DDR2 Active low Write enable

DDR2 Data mask outputs DQM3: For upper byte data bus DDR_D[31:24] DQM2: For DDR_D[23:16] DQM1: For DDR_D[15:8] DQM0: For lower byte DDR_D[7:0]

DDR2 Row Access Signal output DDR2 Column Access Signal output Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to

the DDR2 memory when writing and inputs when reading. They are used to synchronize the data transfers. DQS3 : For upper byte DDR_D[31:24] DQS2: For DDR_D[23:16] DQS1: For DDR_D[15:8] DQS0: For bottom byte DDR_D[7:0]

Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories.

DDR2 address bus

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Table 2-10. DDR2 Memory Controller Terminal Functions (continued)

SIGNAL

NAME NO.

DDR_D[31] U19 DDR_D[30] V19 DDR_D[29] W18 DDR_D[28] V18 DDR_D[27] W17 DDR_D[26] U18 DDR_D[25] U17 DDR_D[24] V17 DDR_D[23] T17 DDR_D[22] V16 DDR_D[21] W16 DDR_D[20] U15 DDR_D[19] V15 DDR_D[18] W15 DDR_D[17] V14 DDR_D[16] W14 DDR_D[15] V7 DDR_D[14] W6 DDR_D[13] V6 DDR_D[12] W5 DDR_D[11] V5 DDR_D[10] U5

DDR_D[9] W4 DDR_D[8] V4 DDR_D[7] W3 DDR_D[6] V3 DDR_D[5] U3 DDR_D[4] W2 DDR_D[3] V2 DDR_D[2] V1 DDR_D[1] U2 DDR_D[0] U1

DDR_VREF T15 I DDR_VSSDLL T11 GND DDR_VDDDLL T10 S

DDR_ZN T12 O/Z

DDR_ZP T13 O/Z

(4) For more information, see Section 5.2, Recommended Operating Conditions.

(1)

TYPE

OTHER

I/O/Z DV

(2) (3)

DDR2

(4) (4) (4)

(4)

DDR2 data bus can be configured as 32 bits wide or 16 bits wide.

Reference voltage input for the SSTL_18 IO buffers. Ground for the DDR2 Digital Locked Loop. Power (1.8 Volts) for the DDR2 Digital Locked Loop. Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor

to DV

DDR2

Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor to VSS.

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DESCRIPTION

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Table 2-11. I2C Terminal Functions

SIGNAL

NAME NO.

SCL/ This pin is multiplexed between I2C and GPIO.

GPIO43 For I2C, it is clock output SCL.

SDA/ This pin is multiplexed between I2C and GPIO.

GPIO44 For I2C, it is bi-directional data signal SDA.

C4 I/O/Z DV

B4 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

I2C

DD18

Table 2-12. Audio Serial Port (ASP) Terminal Functions

SIGNAL

NAME NO.

CLKX/ This pin is multiplexed between ASP and GPIO.

GPIO29 For ASP, it is Transmit clock IO CLKX.

CLKR/ This pin is multiplexed between ASP and GPIO.

GPIO30 For ASP, it is Receive clock IO CLKR.

FSX/ This pin is multiplexed between ASP and GPIO.

GPIO31 For ASP, it is Transmit frame synchronization IO FSX.

FSR/ This pin is multiplexed between ASP and GPIO.

GPIO32 For ASP, it is Receive frame synchronization IO FSR.

DX/ This pin is multiplexed between ASP and GPIO.

GPIO33 For ASP, it is Data Transmit output DX.

DR/ This pin is multiplexed between ASP and GPIO.

GPIO34 For ASP, it is Data Receive input DR.

B8 I/O/Z DV

A8 I/O/Z DV

C8 I/O/Z DV

C7 I/O/Z DV

B7 I/O/Z DV

A7 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

Audio Serial Port (ASP)

DD18

Table 2-13. SPI Terminal Functions

SIGNAL

NAME NO.

SPI_EN0/ This pin is multiplexed between SPI and GPIO.

GPIO37 When used by SPI, it is SPI slave device 0 enable output SPI_EN0.

A4 I/O/Z DV

SPI_EN1/

HDDIR/ B2 I/O/Z DV

GPIO42

SPI_CLK/ This pin is multiplexed between SPI and GPIO.

GPIO39 For SPI, it is clock output SPI_CLK.

SPI_DI/ This pin is multiplexed between SPI and GPIO.

GPIO40 For SPI, it is data input SPI_DI.

SPI_DO/ This pin is multiplexed between SPI and GPIO.

GPIO41 For SPI it is data output SPI_DO.

A3 I/O/Z DV

B3 I/O/Z DV

A2 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

Serial Peripheral Interface (SPI)

DD18

This pin is multiplexed between SPI, ATA, and GPIO. When used by SPI, it is SPI slave device 1 enable output SPI_EN1.

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Table 2-14. EMAC and MDIO Terminal Functions

SIGNAL

NAME NO.

GPIOV33_0/ This pin is multiplexed between GPIO and Ethernet MAC.

TXEN In Ethernet MAC mode, it is Transmit Enable output TXEN.

GPIOV33_1/ This pin is multiplexed between GPIO and Ethernet MAC.

TXCLK In Ethernet MAC mode, it is Transmit Clock input TXCLK.

GPIOV33_2/ This pin is multiplexed between GPIO and Ethernet MAC.

COL In Ethernet MAC mode, it is Collision Detect input COL.

GPIOV33_6/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD3 In Ethernet MAC mode, it is Transmit Data 3 output TXD3.

GPIOV33_5/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD2 In Ethernet MAC mode, it is Transmit Data 2 output TXD2.

GPIOV33_4/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD1 In Ethernet MAC mode, it is Transmit Data 1 output TXD1.

GPIOV33_3/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD0 In Ethernet MAC mode, it is Transmit Data 0 output TXD0.

GPIOV33_11/ This pin is multiplexed between GPIO and Ethernet MAC.

RXCLK In Ethernet MAC mode, it is Receive Clock input RXCLK.

GPIOV33_12/ This pin is multiplexed between GPIO and Ethernet MAC.

RXDV In Ethernet MAC mode, it is Receive Data Valid input RXDV.

GPIOV33_13/ This pin is multiplexed between GPIO and Ethernet MAC.

RXER In Ethernet MAC mode, it is Receive Error input RXER.

GPIOV33_14/ This pin is multiplexed between GPIO and Ethernet MAC.

CRS In Ethernet MAC mode, it is Carrier Sense input CRS.

GPIOV33_10/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD3 In Ethernet MAC mode, it is Receive Data 3 input RXD3.

GPIOV33_9/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD2 In Ethernet MAC mode, it is Receive Data 2 input RXD2.

GPIOV33_8/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD1 In Ethernet MAC mode, it is Receive data 1 input RXD1.

GPIOV33_7/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD0 In Ethernet MAC mode, it is Receive Data 0 input RXD0.

GPIOV33_16/ This pin is multiplexed between GPIO and Ethernet MAC.

MDCLK In Ethernet MAC mode, it is Management Data Clock output MDCLK.

GPIOV33_15/ This pin is multiplexed between GPIO and Ethernet MAC.

MDIO In Ethernet MAC mode, it is Management Data IO MDIO.

B13 I/O/Z DV

A13 I/O/Z DV

A12 I/O/Z DV

C12 I/O/Z DV

A11 I/O/Z DV

D12 I/O/Z DV

B12 I/O/Z DV

A10 I/O/Z DV

D11 I/O/Z DV

D10 I/O/Z DV

C10 I/O/Z DV

E11 I/O/Z DV

B11 I/O/Z DV

C11 I/O/Z DV

E12 I/O/Z DV

B10 I/O/Z DV

E10 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

EMAC

DD33

MDIO

DD33

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Table 2-15. GPIOV33 Terminal Functions

SIGNAL

NAME NO.

GPIOV33_16/ This pin is multiplexed between GPIO and Ethernet MAC.

MDCLK In GPIO mode, it is 3.3V GPIO GPIOV33_16.

GPIOV33_15/ This pin is multiplexed between GPIO and Ethernet MAC.

MDIO In GPIO mode, it is 3.3V GPIO GPIOV33_15.

GPIOV33_14/ This pin is multiplexed between GPIO and Ethernet MAC.

CRS In GPIO mode, it is 3.3V GPIO GPIOV33_14.

GPIOV33_13/ This pin is multiplexed between GPIO and Ethernet MAC.

RXER In GPIO mode, it is 3.3V GPIO GPIOV33_13.

GPIOV33_12/ This pin is multiplexed between GPIO and Ethernet MAC.

RXDV In GPIO mode, it is 3.3V GPIO GPIOV33_12.

GPIOV33_11/ This pin is multiplexed between GPIO and Ethernet MAC.

RXCLK In GPIO mode, it is 3.3V GPIO GPIOV33_11.

GPIOV33_10/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD3 In GPIO mode, it is 3.3V GPIO GPIOV33_10.

GPIOV33_9/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD2 In GPIO mode, it is 3.3V GPIO GPIOV33_9.

GPIOV33_8/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD1 In GPIO mode, it is 3.3V GPIO GPIOV33_8.

GPIOV33_7/ This pin is multiplexed between GPIO and Ethernet MAC.

RXD0 In GPIO mode, it is 3.3V GPIO GPIOV33_7.

GPIOV33_6/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD3 In GPIO mode, it is 3.3V GPIO GPIOV33_6.

GPIOV33_5/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD2 In GPIO mode, it is 3.3V GPIO GPIOV33_5.

GPIOV33_4/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD1 In GPIO mode, it is 3.3V GPIO GPIOV33_4.

GPIOV33_3/ This pin is multiplexed between GPIO and Ethernet MAC.

TXD0 In GPIO mode, it is 3.3V GPIO GPIOV33_3.

GPIOV33_2/ This pin is multiplexed between GPIO and Ethernet MAC.

COL In GPIO mode, it is 3.3V GPIO GPIOV33_2.

GPIOV33_1/ This pin is multiplexed between GPIO and Ethernet MAC.

TXCLK In GPIO mode, it is 3.3V GPIO GPIOV33_1.

GPIOV33_0/ This pin is multiplexed between GPIO and Ethernet MAC.

TXEN In GPIO mode, this pin is 3.3V GPIO pin GPIOV33_0.

B10 I/O/Z DV

E10 I/O/Z DV

C10 I/O/Z DV

D10 I/O/Z DV

D11 I/O/Z DV

A10 I/O/Z DV

E11 I/O/Z DV

B11 I/O/Z DV

C11 I/O/Z DV

E12 I/O/Z DV

C12 I/O/Z DV

A11 I/O/Z DV

D12 I/O/Z DV

B12 I/O/Z DV

A12 I/O/Z DV

A13 I/O/Z DV

B13 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

GPIOV33

DD33

Table 2-16. Standalone GPIOV18 Terminal Functions

SIGNAL

NAME NO.

GPIO7 C3 I/O/Z DV GPIO1 E13 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

Standalone GPIOV18

DD18 DD18

This pin is standalone and functions as GPIO7. This pin is standalone and functions as GPIO1.

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Table 2-17. USB Terminal Functions

SIGNAL

NAME NO.

M24XI F18 I DV

M24XO F19 O DV

M24V

F16 S

F17 GND

USB_VBUS J17 A I/O

USB_ID J16 A I/O

USB_DP G19 A I/O USB bi-directional Data Differential signal pair [positive/negative].

USB_DM H19 A I/O

USB_R1 H18 A I/O

USB_V

SSREF

DDA3P3

SSA3P3

DD1P8

SS1P8

G16 GND

J19 S

J18 GND

H17 S

H16 GND

TYPE

(1)

OTHER

(2) (3)

USB 2.0

Crystal input for M24 oscillator (24 MHz for USB).

DD18

If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input.

When the USB peripheral is not used, M24XI should be left as a No Connect. Crystal output for M24 oscillator.

DD18

If a crystal input is not used, but instead a physical clock-in source is supplied, M24XO should be left as a No Connect.

When the USB peripheral is not used, M24XO should be left as a No Connect.

1.8-V power supply for M24 oscillator.

(3)

If a crystal input is not used, but instead a physical clock-in source is supplied, M24VDDshould still be connected to the 1.8-V power supply.

When the USB peripheral is not used, M24VDDshould be connected to the 1.8-V power supply.

Ground for M24 oscillator.

(3)

If a crystal input is not used, but instead a physical clock-in source is supplied, M24VSSshould still be connected to ground.

When the USB peripheral is not used, M24VSSshould be connected to ground. 5-V input that signifies that VBUS is connected.

(3)

When the USB peripheral is not used, the USB_VBUS signal should be either pulled down or pulled up via a 10-kΩ resistor.

USB operating mode identification pin. For Host mode operation, pull down this pin to ground (VSS) via an external 1.5-kΩ resistor. For Device mode operation, pull up this pin to DV

rail via an external 1.5-kΩ resistor.

DD33

When the USB peripheral is not used, the USB_ID signal should be either pulled down or pulled up via a 10-kΩ resistor.

When the USB peripheral is not used, the USB_DP signal should be pulled high and the USB_DM signal should be pulled down via a 10-kΩ resistor.

Reference current output. This must be connected via a 10-kΩ ±1% resistor to

(3)

USB_V

SSREF

When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_V

Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to

(3)

USB_R1. When the USB peripheral is not used, the USB_V

to VSS. Analog 3.3 V power supply for USB phy.

(3)

When the USB peripheral is not used, the USB_V connected to DV

DD33

Analog ground for USB phy. When the USB peripheral is not used, the USB_V

signal should be connected to VSS.

SSA3P3

1.8-V I/O power supply for USB phy.

(3)

When the USB peripheral is not used, the USB_V to DV

DD18

I/O Ground for USB phy.

(3)

When the USB peripheral is not used, the USB_V to VSS.

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SSREF

DESCRIPTION

signal should be connected

SSREF

signal should be

DDA3P3

signal should be connected

DD1P8

signal should be connected

SS1P8

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Table 2-17. USB Terminal Functions (continued)

SIGNAL

NAME NO.

USB_V

DDA1P2LDO

USB_V

SSA1P2LDO

G18 S

G17 GND

TYPE

(1)

OTHER

(3)

(2) (3)

DESCRIPTION

Core Power supply LDO output for USB phy. This must be connected via a 1-mF capacitor to VSS.

When the USB peripheral is not used, the USB_V connected via a 1-mF capacitor to VSS.

Core Ground for USB phy. This is the ground for the LDO and must be connected to VSS.

When the USB peripheral is not used, the USB_V connected to VSS.

Table 2-18. VLYNQ Terminal Functions

SIGNAL

NAME NO.

EM_CS5/

GPIO8/ T1 I/O/Z DV

VLYNQ_CLOCK

EM_CS4/

GPIO9/ T2 I/O/Z DV

VLYNQ_SCRUN

EM_A[15]/

GPIO16/ P3 I/O/Z DV

VLYNQ_TXD3

EM_A[17]/

GPIO14/ R2 I/O/Z DV

VLYNQ_TXD2

EM_A[19]/

GPIO12/ R4 I/O/Z DV

VLYNQ_TXD1

EM_A[21]/

GPIO10/ T3 I/O/Z DV

VLYNQ_TXD0

EM_A[14]/

GPIO17/ P4 I/O/Z DV

VLYNQ_RXD3

EM_A[16]/

GPIO15/ R5 I/O/Z DV

VLYNQ_RXD2

EM_A[18]/

GPIO13/ P5 I/O/Z DV

VLYNQ_RXD1

EM_A[20]/

GPIO11/ R3 I/O/Z DV

VLYNQ_RXD0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

VLYNQ

DD18

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is the clock (VLYNQ_CLOCK).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is the Serial Clock run request (VLYNQ_SCRUN).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.

DDA1P2LDO

SSA1P2LDO

signal should still be

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Table 2-19. VPBE Terminal Functions

SIGNAL

NAME NO.

HSYNC C17 I/O/Z VPBE Horizontal Sync signal that can be either an input or an output.

VSYNC C18 I/O/Z VPBE Vertical Sync signal that can be either an input or an output.

VCLK D19 I/O/Z DV

VPBECLK C19 I/O/Z VPBE Clock Input

COUT0/ This pins is multiplexed between ARM boot mode and the VPBE.

B3/ A16 I/O/Z After reset, this pin is either video encoder outputs COUT0, or

BTSEL0 RGB666/888 Blue output data bits 3, B3. COUT1/ This pins is multiplexed between ARM boot mode and the VPBE.

B4/ B16 I/O/Z After reset, this pin is either video encoder outputs COUT1, or

BTSEL1 RGB666/888 Blue output data bits 4, B4. COUT2/ This pin is multiplexed between EMIFA and the VPBE.

B5/ A17 I/O/Z After reset, it is video encoder output COUT2 or RGB666/888 Blue

EM_WIDTH output data bit 5 B5.

COUT3/ This pin is multiplexed between DSP boot and the VPBE.

B6/ B17 I/O/Z After reset, it is video encoder output COUT3 or RGB666/888 Blue data

DSP_BT bit 6 output B6.

COUT4/

COUT5/ Video encoder output COUT5 or RGB666/888 Green data bit 2 output

G2 G2.

COUT6/ Video encoder output COUT6 or RGB666/888 Green data bit 3 output

G3 G3.

COUT7/ Video encoder output COUT7 or RGB666/888 Green data bit 4 output

G4 G4.

A18 O DV

B18 O DV

B19 O DV

C16 O DV

YOUT0/

G5/ D15 I/O/Z

AEAW0

YOUT1/

G6/ D16 I/O/Z

AEAW1

YOUT2/ These pins are multiplexed between EMIFA and the VPBE.

G7/ D17 I/O/Z After reset, these are video encoder outputs YOUT[0:4] or RGB666/888

AEAW2 Red and Green data bit outputs G5, G6, G7, R3, and R4.

YOUT3/

R3/ D18 I/O/Z

AEAW3

YOUT4/

R4/ E15 I/O/Z

AEAW4

YOUT5/

YOUT6/

YOUT7/

GPIO0/ This pin is multiplexed between GPIO and the VPBE.

LCD_OE In VPBE mode, it is the LCD output enable LCD_OE.

GPIO2/ This pin is multiplexed between GPIO and the VPBE.

G0 In VPBE mode, it is RGB888 Green data bit 0 output G0.

E16 O DV

E17 O DV

E18 O DV

C13 I/O/Z DV

D13 I/O/Z DV

TYPE

(1)

OTHER

(2) (3)

DESCRIPTION

VIDEO OUT (VPBE)

IPD

DD18

IPD

DD18 DD18

VPBE Clock Output

IPD

DD18

IPD

DD18

IPD

DD18

IPD

DD18

IPD

DD18

Video encoder output COUT4 or RGB666/888 Blue data bit 7 output B7.

IPD

DD18

IPD

DD18

IPD

DD18

IPD

DD18

IPD

DD18

Video encoder output YOUT5 or RGB666/888 Red data bit 5 output R5.

Video encoder output YOUT6 or RGB666/888 Red data bit 6 output R6.

Video encoder output YOUT7 or RGB666/888 Red data bit 7 output R7.

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Table 2-19. VPBE Terminal Functions (continued)

SIGNAL

NAME NO.

GPIO3/ This pin is multiplexed between GPIO, and the VPBE.

B0/ C14 I/O/Z DV

LCD_FIELD interlaced bidirectional LCD_FIELD.

GPIO4/ This pin is multiplexed between GPIO and the VPBE.

R0 In VPBE mode, it is RGB888 Red data bit 0 output R0.

GPIO5/ This pin is multiplexed between GPIO and the VPBE.

G1 In VPBE mode, it is RGB888 Green data bit 1 output G1.

GPIO6/ This pin is multiplexed between GPIO and the VPBE.

B1 In VPBE mode, it is RGB888 Blue data bit 1 output B1.

GPIO38/ This pin is multiplexed between VPBE and GPIO.

R1 In VPBE mode, it is RGB888 Red output data bit 1.

B14 I/O/Z DV

E14 I/O/Z DV

A14 I/O/Z DV

D14 I/O/Z DV

PWM1/

R2/ B15 I/O/Z DV

GPIO46

PWM2/

B2/ A15 I/O/Z DV

GPIO47

TYPE

(1)

OTHER

DD18

(2) (3)

DESCRIPTION

In VPBE mode, it is RGB888 Blue data bit 0 output B0 or LCD

This pin is multiplexed between PWM1, VPBE, and GPIO. In VPBE mode, it is RGB888 Red output bit 2 (R2).

This pin is multiplexed between PWM2, VPBE, and GPIO. In VPBE mode, it is RGB888 Blue output bit 2 (B2).

Table 2-20. DAC [Part of VPBE] Terminal Functions

SIGNAL

NAME NO.

DAC_VREF R17 A I

DAC_IOUT_A P19 A O

DAC_IOUT_B P18 A O

DAC_IOUT_C R19 A O

DAC_IOUT_D T19 A O

DDA_1P8V

SSA_1P8V

DDA_1P1V

SSA_1P1V

R18 S

P17 GND

P16 S

T18 GND

DAC_RBIAS R16 A I

TYPE

(1)

OTHER

(3)

(2) (3)

DESCRIPTION

DAC[A:D]

Reference voltage input (0.5 V). When the DAC is not used, the DAC_VREF signal should be connected to VSS.

Output of DAC A. When the DAC is not used, the DAC_IOUT_A signal should be left as a No Connect.

Output of DAC B. When the DAC is not used, the DAC_IOUT_B signal should be left as a No Connect.

Output of DAC C. When the DAC is not used, the DAC_IOUT_C signal should be left as a No Connect.

Output of DAC D. When the DAC is not used, the DAC_IOUT_D signal should be left as a No Connect.

1.8-V analog I/O power. When the DAC is not used, the V connected to VSS.

Analog I/O ground. When the DAC is not used, the V connected to VSS.

1.20-V analog core supply voltage (-594 device). When the DAC is not used, the V

DDA_1P1V

signal should be connected to VSS.

Analog core ground. When the DAC is not used, the V connected to VSS.

External resistor connection for current bias configuration. This pin must be connected via a 4-kΩ resistor to V DAC_RBIAS signal should be connected to VSS.

. When the DAC is not used, the

SSA_1P8V

DDA_1P8V

SSA_1P8V

SSA_1P1V

signal should be

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Table 2-21. UART0, UART1, UART2 Terminal Functions

SIGNAL

NAME NO.

UART_RXD2 N19 I/O/Z Receive data input UART_RXD2

UART_TXD2 N18 I/O/Z Transmit data output UART_TXD2

UART_CTS2 N17 I/O/Z Clear to send input UART_CTS2

UART_RTS2 N16 I/O/Z Ready to send output UART_RTS2

DMACK/ This pin is multiplexed between ATA/CF and UART1.

UART_TXD1 For UART1, it is transmit data output UART_TXD1.

DMARQ/ IPD This pin is multiplexed between ATA/CF and UART1.

UART_RXD1 DV

UART_RXD0/ This pin is multiplexed between UART0 and GPIO.

GPIO35 For UART0, it is Receive Data input UART_RXD0.

UART_TXD0/ This pin is multiplexed between UART0 and GPIO.

GPIO36 For UART0, it is Transmit Data output UART_TXD0.

H3 I/O/Z DV

G1 I/O/Z

D5 I/O/Z DV

C5 I/O/Z DV

TYPE

(1)

OTHER

IPD

DD18

(2) (3)

UART2

UART1

For UART1, it is receive data input UART_RXD1.

UART0

DESCRIPTION

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Table 2-22. PWM0, PWM1, PWM2 Terminal Functions

SIGNAL

NAME NO.

PWM2/

B2/ A15 I/O/Z DV

GPIO47

PWM1/

R2/ B15 I/O/Z DV

GPIO46

PWM0/ This pin is multiplexed between PWM0 and GPIO.

GPIO45 For PWM0, it is output PWM0.

C15 I/O/Z DV

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

PWM2

DD18

This pin is multiplexed between PWM2, VPBE, and GPIO. For PWM2, it is output PWM2.

PWM1

DD18

This pin is multiplexed between PWM1, VPBE, and GPIO. For PWM1, it is output PWM1.

PWM0

DD18

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Table 2-23. ATA/CF Terminal Functions

SIGNAL

NAME NO.

SPI_EN1/

HDDIR/ B2 I/O/Z DV

GPIO42

GPIO50/ This pin is multiplexed between GPIO and ATA/CF.

ATA_CS0 In ATA mode, it is ATA/CF chip select output ATA_CS0.

GPIO51/ This pin is multiplexed between GPIO and ATA/CF.

ATA_CS1 In ATA mode, it is ATA/CF chip select output ATA_CS1.

J5 O DV

H1 O DV

EM_R/W/

INTRQ/ G3 I DV

H/W

EM_WAIT/

(RDY/BSY)/ IPU This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

IORDY/ DV

F1 I

HRDY

EM_OE/

( RE )/ This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

( IORD )/ H4 O DV

DIOR/ For ATA, it is read strobe output DIOR. HDS1

EM_WE

(WE) This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

(IOWR)/ G2 O DV

DIOW/ For ATA, it is write strobe output DIOW.

HDS2

DMACK/ This pin is multiplexed between ATA/CF and UART1.

UART_TXD1 For ATA/CF, it is DMA acknowledge output DMACK.

DMARQ/ IPD This pin is multiplexed between ATA/CF and UART1.

UART_RXD1 DV

H3 O DV

G1 O

TYPE

(1)

OTHER

DD18

(2) (3)

DESCRIPTION

ATA/CF

This pin is multiplexed between SPI, ATA, and GPIO. For ATA, it is buffer direction control output HDDIR.

This pin is multiplexed between EMIFA, ATA/CF, and HPI. For ATA/CF, it is interrupt request input INTRQ.

For ATA/CF, it is IO Ready input IORDY.

For CF, it is read strobe output (IORD).

For CF, it is write strobe output (IOWR).

For ATA/CF, it is DMA request DMARQ input.

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Table 2-23. ATA/CF Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D15/

DD15/ E1

HD15

EM_D14/

DD14/ H5

HD14

EM_D13/

DD13/ F2

HD13

EM_D12/

DD12/ D1

HD12

EM_D11/

DD11/ G4

HD11

EM_D10/

DD10/ G5

HD10

EM_D9/

DD9/ E2 HD9

EM_D8/

DD8/ F3 HD8

EM_D7/

DD7/ C1 HD7

EM_D6/

DD6/ F4 HD6

EM_D5/

DD5/ D2 HD5

EM_D4/

DD4/ E4 HD4

EM_D3/

DD3/ E3 HD3

EM_D2/

DD2/ F5 HD2

EM_D1/

DD1/ D3 HD1

EM_D0/

DD0/ E5 HD0

EM_A[0]/

DA2/ This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.

HCNTL1/ For ATA/CF, it is Device address bit 2 output DA2.

J4 I/O/Z DV

GPIO53

EM_BA[1]/

DA1/ H2 I/O/Z DV

GPIO52

EM_BA[0]/

DA0/ J3 I/O/Z DV

HINT

(1)

TYPE

OTHER

I/O/Z DV

DD18

(2) (3)

DESCRIPTION

These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For ATA/CF, these are DD[15:0].

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For ATA/CF, it is Device address bit 1 output DA1.

This pin is multiplexed between EMIFA, ATA/CF, HPI. For ATA/CF, it is Device address bit 0 output DA0.

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Table 2-24. MMC/SD/SDIO Terminal Functions

SIGNAL

NAME NO.

SD_CLK A9 O DV

SD_CMD B9 I/O/Z DV SD_DATA3 C9 I/O/Z SD_DATA2 D9 I/O/Z SD_DATA1 E9 I/O/Z SD_DATA0 D8 I/O/Z

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

MMC/SD/SDIO

Data clock output SD_CLK Bi-directional command IO SD_CMD

These pins are the nibble-wide bi-directional data bus SD_DATA[3:0].

DD33 DD33

DD33

Table 2-25. HPI Terminal Functions

SIGNAL

NAME NO.

EM_CS3 B1 I/O/Z DV

EM_BA[0]/

DA0/ J3 I/O/Z DV

HINT

EM_A[0]/ This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.

DA2/ For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine

HCNTL1/ if address, data, or control information is being transmitted between an external

J4 I/O/Z DV

GPIO53 host and DM644X.

EM_A[2]/

(CLE)/ J1 I/O/Z DV

HCNTL0 EM_A[1]/

(ALE)/ J2 I/O/Z DV

HHWIL

EM_R/W/ This pin is multiplexed between EMIFA, ATA/CF, and HPI.

INTRQ/ G3 I/O/Z DV

HR/W and low for writes.

EM_CS2/ This pin is multiplexed between EMIFA and HPI.

HCS In HPI mode, this pin is HPI Active Low Chip Select input HCS.

C2 I/O/Z DV

EM_WE

(WE)

(IOWR)/ G2 I/O/Z DV

DIOW/

HDS2

EM_OE/

(RE)/

(IORD)/ H4 I/O/Z DV

DIOR/ HDS1

EM_WAIT/

(RDY/BSY)/ IPU This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

IORDY/ DV

F1 I/O/Z

HRDY

TYPE

(1)

OTHER

(2) (3)

DESCRIPTION

Host-Port Interface (HPI)

DD18

For EMIFA, this pin is Chip Select 3 output. In HPI mode this pin must be pulled high via an external 10-kΩ resistor.

This pin is multiplexed between EMIFA, ATA/CF, and HPI. In HPI mode, it is the host interrupt output HINT.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.

DD18

In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0 determine if address, data, or control information is being transmitted between an external host and DM644X.

DD18

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. In HPI mode, it is Half-word identification input HHWIL.

For HPI, it is the Host Read Write input HR/W. This signal is active high for reads

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For HPI, it is data strobe 2 input HDS2.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For HPI, it is data strobe 1 input HDS1.

For HPI, it is ready output HRDY.

(1) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) (2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (3) Specifies the operating I/O supply voltage for each signal

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Table 2-25. HPI Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D15/

DD15/ E1

HD15

EM_D14/

DD14/ H5

HD14

EM_D13/

DD13/ F2

HD13

EM_D12/

DD12/ D1

HD12

EM_D11/

DD11/ G4

HD11

EM_D10/

DD10/ G5

HD10

EM_D9/

DD9/ E2 HD9

EM_D8/

DD8/ F3 HD8

EM_D7/

DD7/ C1 HD7

EM_D6/

DD6/ F4 HD6

EM_D5/

DD5/ D2 HD5

EM_D4/

DD4/ E4 HD4

EM_D3/

DD3/ E3 HD3

EM_D2/

DD2/ F5 HD2

EM_D1/

DD1/ D3 HD1

EM_D0/

DD0/ E5 HD0

(1)

TYPE

I/O/Z DV

OTHER

(2) (3)

DD18

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DESCRIPTION

These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In HPI mode, these are HD[15:0] and are multiplexed internally with the HPI address lines.

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Table 2-26. Timer 0, Timer 1, and Timer 2 Terminal Functions

SIGNAL

NAME NO.

No external pins. The Timer 2 and Timer 1 peripheral pins are not pinned out as external pins.

CLK_OUT1/

TIM_IN/ E19 I/O/Z DV

GPIO49

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

(2)

DESCRIPTION

Timer 2 and Timer 1

Timer 0

DD18

This pin is multiplexed between the USB clock generator, timer, and GPIO. For Timer0, it is the timer event capture input TIM_IN.

Table 2-27. Reserved Terminal Functions

SIGNAL

NAME NO.

RSV1 A1 Reserved. (Leave unconnected, do not connect to power or ground) RSV2 A19 Reserved. (Leave unconnected, do not connect to power or ground) RSV3 W1 Reserved. (Leave unconnected, do not connect to power or ground) RSV4 W19 Reserved. (Leave unconnected, do not connect to power or ground)

RSV5 D4 I Reserved. This pin must be tied directly to VSSfor normal device operation. RSV6 L3 A O Reserved. (Leave unconnected, do not connect to power or ground)

RSV7 R8 A Reserved. (Leave unconnected, do not connect to power or ground)

RSV9 M19 I V RSV10 L19 I/O/Z Reserved. (Leave unconnected, do not connect to power or ground) RSV11 M18 I/O/Z Reserved. (Leave unconnected, do not connect to power or ground) RSV12 N15 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV13 M17 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV14 M16 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV15 M15 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV16 L18 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV17 L17 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV18 L16 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV19 L15 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV20 K19 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV21 K18 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV22 K17 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV23 K16 I IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV24 M3 S Reserved. (Leave unconnected, do not connect to power or ground)

TYPE

(1)

OTHER

IPD V

(2) (3)

DESCRIPTION

RESERVED

Reserved. This pin must be tied directly to VSSfor normal device operation.

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Table 2-28. Supply Terminal Functions

SIGNAL

NAME NO.

DD33

DD18

DDR2

F10 F11 F12 F13

G15

F14

J15 H14 K14 M14

L13

F8 E7

J7 L7 F6

T5 P6

P8 N9 R9

P10 N11 R11 P12 N13 R13 P14 R15

TYPE

(1)

OTHER DESCRIPTION

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SUPPLY VOLTAGE PINS

3.3 V I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual)

1.8 V I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual)

1.8 V DDR2 I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual)

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NAME NO.

DDDSP

SIGNAL

TYPE

F15 K12 M12

L11 M10

L10 K10

L9 L8

J13 H12 H11

J11 K11

J10 S H10

J9 K9 K8

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Table 2-28. Supply Terminal Functions (continued)

(1)

OTHER DESCRIPTION

1.20 V core supply voltage (-594 device) (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual)

1.20 V DSPSS supply voltage (-594 device) (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual)

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Table 2-29. Ground Terminal Functions

SIGNAL

NAME NO.

K5 M5 G6

L6 N6 R6

F7 H7

K7 M7

P7 R7

E8 G8

J8 N8

F9 H9

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

M9 GND Ground pins

G10 N10 R10 G11 M11 P11 G12

J12

N12

L12 R12 G13 H13 K13 M13 P13 G14

J14

TYPE

(1)

OTHER DESCRIPTION

GROUND PINS

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NAME NO.

SIGNAL

L14 N14 R14 H15 K15 P15

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Table 2-29. Ground Terminal Functions (continued)

(1)

TYPE

GND Ground pins

OTHER DESCRIPTION

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2.8 Device Support

2.8.1 Development Support

TI offers an extensive line of development tools for the TMS320DM644x SoC platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of TMS320DM644x SoC-based applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target

software needed to support any SoC application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator For a complete listing of development-support tools for the TMS320DM644x SoC platform, visit the

Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

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2.8.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320DM6443ZWT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical

specifications.

TMP Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

TMS Fully-qualified production device. Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

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DM644x DMSoC:

DM6443 DM6446

PREFIX DEVICE SPEED RANGE

TMS 320 DM6443 ZWT ( )

TMX = Experimental device TMS = Qualified device

DEVICE FAMILY

320 = TMS320t DSP family

PACKAGE TYPE

(A)

ZWT = 361-pin plastic BGA, with Pb-free soldered balls

DEVICE

(B)

TEMPERATURE RANGE (DEFAULT: 0°C TO 85°C)

( )

Blank = 0°C to 85°C, commercial temperature

Blank = 594-MHz DSP, 297-MHz ARM9 [Default]

A. BGA = Ball Grid Array B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com).

( )

SILICON REVISION

Blank = Silicon 1.3 A = Silicon 2.1 B = Silicon 2.3

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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default [594-MHz DSP, 297-MHz ARM9]).

Figure 2-6 provides a legend for reading the complete device name for any TMS320DM644x SoC platform

member.

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Figure 2-6. Device Nomenclature

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2.8.3 Documentation Support

2.8.3.1 Related Documentation From Texas Instruments

The following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at http://www.ti.com. Tip: Enter the literature number in the search box provided at http://www.ti.com.

The current documentation that describes the DM644x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: http://www.ti.com/c6000.

SPRU395 TMS320C64x Technical Overview. Provides an introduction to the TMS320C64x digital

signal processors (DSPs) of the TMS320C6000 DSP family.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital

signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM

subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the video processing subsystem, and a majority of the peripherals and external memories.

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SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal

processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRUE19 TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview

and briefly describes the peripherals available on the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRUE20 TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference

Guide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices.

SPRUE21 TMS320DM644x DMSoC ATA Controller User's Guide. Describes the ATA controller in

the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ATA controller provides a glueless interface to storage media to be used by video and audio applications for video and audio data storage.

SPRUE22 TMS320DM644x DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2

memory controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices.

SPRUE23 TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's

Guide. Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC.

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SPRUE24 TMS320DM644x DMSoC Ethernet Media Access Controller (EMAC)/Management Data

SPRUE25 TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes

SPRUE26 TMS320DM644x DMSoC 64-Bit Timer User's Guide. Describes the operation of the

SPRUE29 TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide. Describes the operation

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Input/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller (EMAC) and physical layer (PHY) device management data input/output (MDIO) module in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packet data from the DMSoC to the PHY. The MDIO module controls PHY configuration and status monitoring.

the general-purpose input/output (GPIO) peripheral in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.

software-programmable 64-bit timer in the TMS320DM644x Digital Media System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access (EDMA) synchronization events. The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop.

of the audio serial port (ASP) audio interface in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface.

SPRUE35 TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide. Describes

the universal serial bus (USB) controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices and also supports host negotiation.

SPRUE37 TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide. Describes

the video processing back end (VPBE) in the TMS320DM644x Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screen display, and digital LCD controller.

SPRUE97 TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide. Describes the features

and operation of the host port interface (HPI) in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRA839 Using IBIS Models for Timing Analysis. Describes how to properly use IBIS models to

attain accurate timing analysis for a given system.

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas

Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRAAA6 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating

from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.

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SPRAAC5 Implementing DDR2 PCB Layout on the TMS320DM644x DSP. Contains implementation

instructions for the DDR2 interface contained on the TMS320DM644x digital signal processor (DSP) device.

SPRAAD6 TMS320DM6446/3 Power Consumption Summary. This document discusses the power

consumption of the Texas Instruments TMS320DM6446 and TMS320DM6443 digital media System-on-Chip (DMSoC).

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3 Device Configurations

3.1 System Module Registers

The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configurations are discussed in the following sections.

Table 3-1. System Module Register Memory Map

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x01C4 0000 PINMUX0 Pin multiplexing control 0. For details, see Section 3.5.4, PINMUX0 Register

0x01C4 0004 PINMUX1 Pin multiplexing control 1. For details, see Section 3.5.5, PINMUX1 Register

0x01C4 0008 DSPBOOTADDR Boot address of DSP. For details, see Section 3.3.1.2, DSPBOOTADDR

0x01C4 000C SUSPSRC Emulator Suspend Source. For details, see Section 3.6, Emulation Control. 0x01C4 0010 INTGEN ARM/DSP Interrupt Status and Control. For details, see Section 6.7.3,

0x01C4 0014 BOOTCFG Device boot configuration. For details, see Section 3.3.1.1, BOOTCFG

0x01C4 0018 - 0x01C4 0027 – Reserved.

0x01C4 0028 JTAGID JTAGID/Device ID number. For details, see Section 6.25.1, JTAG Peripheral

0x01C4 002C – Reserved. 0x01C4 0030 HPI_CTL HPI control. For details, see Section 3.5.6.10, HPI and EMIFA/ATA Pin

0x01C4 0034 USBPHY_CTL USB PHY control. For details, see Section 6.15.1, USBPHY_CTL Register

0x01C4 0038 CHP_SHRTSW Chip shorting switch control. For details, see Section 3.2.1, Power

0x01C4 003C MSTPRI0 Bus master priority control 0. For details, see Section 3.5.1, Switched Central

0x01C4 0040 MSTPRI1 Bus master priority control 1. For details, see Section 3.5.1, Switched Central

0x01C4 0044 VPSS_CLKCTL VPSS clock control. 0x01C4 0048 VDD3P3V_PWDN VDD 3.3V I/O powerdown control. For details, see Section 3.2.2, Power

0x01C4 004C DRRVTPER Enables access to the DDR2 VTP Register.

0x01C4 0050 - 0x01C4 006F – Reserved.

Description.

ARM/DSP Communications Interrupts.

Multiplexing.

Description.

Configurations at Reset.

Resource (SCR) Bus Priorities.

Configurations after Reset.

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3.2 Power Considerations

Global device power domains are controlled by the Power and Sleep Controller, except as shown in the following sections.

3.2.1 Power Configurations at Reset

As described in Section 6.3.1.3, DM6443 Power and Clock Domains, the DM6443 has two power domains: Always On and DSP. There is a shorting switch between the two power domains that must be opened when the DSP domain is powered off and closed when the DSP domain is powered on.

The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain. Setting the DSPPWRON bit to '1’ closes (enables) the switch and enables the DSP power domain. The default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected (DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of '1'. For ARM boot operation (DSP_BT=0), DSPPWRON will be set to the disable value of '0' and must be set by the ARM before the DSP domain power is turned on.

Note: Once the DSP power domain is enabled (powered up), it cannot be disabled (powered down). Dynamic power down of the DSP is not supported on this device.

Figure 3-1. CHP_SHRTSW Register

31 1 0

RESERVED DSPPWRON

R-0000 0000 0000 0000 0000 0000 0000 000 R/W-L

LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising

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Table 3-2. CHP_SHRTSW Register Description

NAME DESCRIPTION

DSPPWRON DSP power domain enable.

0 = Shorting switch open 1 = Shorting switch closed

3.2.2 Power Configurations after Reset

The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO and GPIOV33. The 3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and described in Table 3-3. By default, these pins are all disabled at reset.

Figure 3-2. VDD3P3V_PWDN Register

31 2 1 0

RESERVED IOPWDN1 IOPWDN0

R-0000 0000 0000 0000 0000 0000 0000 00 R/W-1 R/W-1

LEGEND: R = Read, W = Write, n = value at reset

Table 3-3. VDD3P3V_PWDN Register Description

NAME DESCRIPTION

IOPWDN0 GIOV33 I/O Powerdown controls GIOV33[16:0] pins.

IOPWDN1 MMC/SD/SDIO I/O Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins.

0 = I/O buffers powered up 1 = I/O buffers powered down

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3.3 Bootmode

The device is booted through multiple means: pin states captured at reset, primary bootloaders within internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and register configurations required for booting the device, are described in the following sections.

3.3.1 Bootmode Registers

The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status of various pins required for proper boot are stored within these registers.

3.3.1.1 BOOTCFG Register Description

The BOOTCFG register (located at address 0x01C4 0014) contains the status values of the BTSEL1, BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pins captured at the rising edge of RESET. The register format is shown in Figure 3-3 and bit field descriptions are shown in Table 3-4. The captured bits are software readable after reset.

Figure 3-3. BOOTCFG Register

31 9 8 7 6 5 4 3 2 1 0

RESERVED DSP_BT BTSEL EM_WIDTH DAEAW

R-0000 0000 0000 0000 0000 000 R-L R-LL R-L R-LLLLL

LEGEND: R = Read; W = Write; L = pin state latched at reset rising; -n = value after reset

Table 3-4. BOOTCFG Register Description

NAME DESCRIPTION

BTSEL ARM Boot mode selection pin states (BTSEL1, BTSEL0) captured at the rising edge of RESET.

‘00’ indicates ARM boots from ROM (NAND Flash/SPI Flash). ‘01’ indicates that ARM boots from EMIFA (NOR Flash). ‘10’ indicates that ARM boots from ROM (HPI). ‘11’ indicates that ARM boots from ROM (UART0).

DSP_BT DSP Boot mode selection pin state captured at the rising edge of RESET.

‘0’ sets ARM boot of C64x+. ‘1’ sets C64x+ self boot.

EM_WIDTH EMIFA data bus width selection pin state captured at the rising edge of RESET.

‘0’ sets EMIFA to 8 bit data bus width ‘1’ sets EMIFA to 16 bit data bus width.

DAEAW EMIFA address bus width selection pin states (AEAW[4:0]) captured at the rising edge of RESET. This configures

EMIFA address pins multiplexed with GPIO. See the GPIO and EMIFA Multiplexing tables (Table 3-9,Table 3-10, and Table 3-11 ).

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3.3.1.2 DSPBOOTADDR Register Description

The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in Figure 3-4 and bit field descriptions are shown in Table 3-5. DSPBOOTADDR is readable and writable by software after reset.

Figure 3-4. DSPBOOTADDR Register

31 10 9 0

BOOTADDR[21:0] RESERVED

R- 0100 0010 0010 0000 0000 00 R-00 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-5. DSPBOOTADDR Register Description

NAME DESCRIPTION

BOOTADDR[21:0] Upper 22 bits of the C64x+ DSP boot address.

3.3.2 ARM Boot

The DM6443 ARM can boot from EMIFA, internal ROM (NAND, SPI), UART0, or HPI, as determined by the setting of the BTSEL[1:0] pins. The BTSEL[1:0] pins are read by the ARM ROM Boot Loader (RBL) to further define the ROM boot mode. The ARM boot modes are summarized in Table 3-6.

Table 3-6. ARM Boot Modes

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BTSEL1 BTSEL0 BOOT MODE ARM RESET BRIEF DESCRIPTION

0 0 ARM NAND, SPI RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through NAND with up

0 1 ARM EMIFA External Boot 0x0200 0000 EMIFA EM_CS2 external memory space. 1 0 ARM HPI RBL 0x0000 4000 Up to 14 K-btyes secondary boot loader through an external

1 1 ARM UART RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through UART0.

VECTOR

to 2 K-bytes page sizes.

host.

When the BTSEL[1:0] pins are set to the ARM EMIFA External Boot ("01"), the ARM immediately begins executing code from the EMIFA EM_CS2 memory space (0x0200 0000). When the BTSEL[1:0] pins indicate a condition other than the ARM EMIFA External Boot (!01), the RBL begins execution.

ARM NAND/SPI Boot mode has the following features:

• Loads a secondary User Boot Loader (UBL) from NAND/SPI flash to ARM Internal RAM (AIM) and transfers control to the user software.

• Support for NAND with page sizes up to 2048 bytes.

• Support for error correction when loading UBL

• Support for up to 14KB UBL

• Optional, user selectable, support for use of DMA, I-cache, and PLL enable while loading UBL

ARM UART Boot mode has the following features:

• Loads a secondary UBL via UART0 to AIM and transfers control to the user software.

• Support for up to 14KB UBL

ARM HPI Boot Mode has the following features:

• No support for a full firmware boot. Instead, waits for external host to load a secondary UBL via HPI to AIM and transfers control to the user software.

• Support for up to 14KB UBL.

For further details on the ROM Bootloader, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

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3.3.3 DSP Boot

For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be the master of C64x+ and control booting (Host Boot mode). If DSP_BT is high, the C64x+ will boot itself coming out of device reset (Self-Boot mode). Table 3-7 shows a summary of the DSP boot modes.

Table 3-7. DSP Boot Modes

DSP_BT DSP ARM DSPBOOTADDR BRIEF DESCRIPTION

3.3.3.1 Host-Boot Mode

BOOT MODE BOOT MODE REGISTER VALUE

0 Host Boot Internal Boot Programmable ARM sets an internal DSP memory location in DSPBOOTADDR

register where valid DSP code resides and loads code to this internal DSP memory through DMA prior to releasing DSP reset.

0 Host Boot External Boot Programmable ARM sets an external DSP memory location in DSPBOOTADDR

releasing DSP reset. 1 Self Boot Any, except HPI 0x4220 0000 Default EMIFA Base Address 1 Host Boot HPI Programmable ARM sets a DSP memory location in the DSPBOOTADDR

entry point set to the memory location specified in the

DSPBOOTADDR register. Once the HPI completes loading the

code, the ARM should release the DSP from reset.

In host boot mode, the ARM is the master and controls the reset and boot of the C64x+. The C64x+ DSP remains powered-off after device reset. The ARM is responsible for enabling power to the C64x+ and releasing it from reset (PSC MMR bits: MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Prior to releasing the C64x+ reset, the ARM must program the address from which the C64x+ will begin execution in the DSPBOOTADDR register.

3.3.3.2 Self-Boot Mode

In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000) contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache enabled.

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3.4 Configurations at Reset

The following sections give information on configuration settings for the device at reset.

3.4.1 Device Configuration at Device Reset

Table 3-8 shows a summary of device inputs required for booting the ARM and DSP, and configuring

EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET input.

Table 3-8. Device Configurations (Input Pins Sampled at Reset)

DEVICE SIGNALS

SAMPLED DESCRIPTION AT RESET

BTSEL[1:0] COUT[1:0] ARM Boot mode selection pins.

DSP_BT COUT3 DSP Boot mode selection pin.

EM_WIDTH COUT2 EMIFA data bus width selection pin.

AEAW[4:0] YOUT[4:0] EMIFA address bus width selection pins for EMIFA address pins multiplexed with GPIO.

DEVICE SIGNAL NAME

AFTER RESET

‘00’ indicates ARM boots from ROM (NAND/SPI Flash). ‘01’ indicates that ARM boots from EMIFA (NOR Flash). ‘10’ indicates that the ARM boots from the HPI (ROM) ‘11’ indicates that ARM boots from ROM (UART0).

‘0’ sets ARM boot of C64x+. ‘1’ sets C64x+ self boot.

‘0’ sets EMIFA to 8-bit data bus width ‘1’ sets EMIFA to 16-bit data bus width.

See the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11) for details.

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3.4.2 Peripheral Selection at Device Reset

As briefly mentioned in Table 3-8, the state of the AEAW[4:0] pins captured at reset configures the number of EMIFA address pins required for device boot. These values are stored in the AEAW field of the PINMUX0 register. At reset, this provides proper addressing for external boot. Unused address pins are available for use as GPIO. The register settings are software programmable after reset. Table 3-9,

Table 3-10, and Table 3-11 show the AEAW[4:0] bit settings and the corresponding multiplexing for

EMIFA address and GPIO pins. The number of EMIFA address bits enabled is configurable from 0 to 23. EM_BA[1] and EM_A[21:0] pins

that are not assigned to another peripheral and not enabled as address signals become GPIO pins. The enabled address pins are always contiguous from EM_BA[1] upwards and address bits cannot be skipped. The exception to this are the EM_A[2:1] pins. EM_A[2:1] are usable as the ALE and CLE signals for the NAND Flash mode of EMIFA and are always enabled as EMIFA pins. If an address width of 0 is selected, this still allows a NAND Flash to be accessed. Also, selecting an address width of 2, 3, or 4 (AEAW[4:0] = 00010, 00011, or 00100) always results in 4 address outputs. For these and other address bit enable settings, see the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11).

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Table 3-9. GPIO and EMIFA Multiplexing (Part 1)

Pin Mux Register AEAW[4:0] Bit Settings 00000 00001 00010 00011 00100 00101 00110 00111

(default)

GPIO[52] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] GPIO[53] GPIO[53] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[28] GPIO[28] GPIO[28] GPIO[28] GPIO[28] EM_A[3] EM_A[3] EM_A[3] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] EM_A[4] EM_A[4] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] EM_A[5] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10]

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Table 3-10. GPIO and EMIFA Multiplexing (Part 2)

Pin Mux Register AEAW[4:0] Bit Settings 01000 01001 01010 01011 01100 01101 01110 01111

EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] GPIO[24] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] GPIO[23] GPIO[23] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] GPIO[22] GPIO[22] GPIO[22] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] GPIO[21] GPIO[21] GPIO[21] GPIO[21] EM_A[10] EM_A[10] EM_A[10] EM_A[10] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] EM_A[11] EM_A[11] EM_A[11] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] EM_A[12] EM_A[12] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] EM_A[13] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10]

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Table 3-11. GPIO and EMIFA Multiplexing (Part 3)

Pin Mux Register AEAW[4:0] Bit Settings 10000 10001 10010 10011 10100 10101 10110 Others

EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] GPIO[16] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] GPIO[15] GPIO[15] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] GPIO[14] GPIO[14] GPIO[14] EM_A[17] EM_A[17] EM_A[17] EM_A[17] EM_A[17] GPIO[13] GPIO[13] GPIO[13] GPIO[13] EM_A[18] EM_A[18] EM_A[18] EM_A[18] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] EM_A[19] EM_A[19] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] EM_A[20] EM_A[20] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] EM_A[21]

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3.5 Configurations After Reset

The following sections give the details on configuring the device after reset.

3.5.1 Switched Central Resource (SCR) Bus Priorities

Prioritization within the switched central resource (SCR) is programmable for each master. The register bit fields and default priority levels for DM6443 bus masters are shown in Table 3-12. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and

Figure 3-6. The C64x+, VPSS, and EDMA3 masters contain registers that control their own priority values.

Table 3-12. DM6443 Default Bus Master Priorities

BUS

PRIORITY BIT FIELD MASTER DEFAULT PRIORITY LEVEL

VPSSP VPSS 0 (VPSS PCR Register, DMA_PRI bit field)

[For more detailed information on the DMA_PRI bit field, see the

TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (literature number SPRUE37).]

EDMATC0P EDMATC0 0 (EDMA3CC QUEPRI Register)

[For more detailed information on the QUEPRI register, see the

TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).]

EDMATC1P EDMATC1 0 (EDMA3CC QUEPRI Register)

[For more detailed information on the QUEPRI register, see the

TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).]

ARM_DMAP ARM (DMA) 1 (MSTPRI0 Register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 Register) C64X+_DMAP C64X+ 7 (C64x+ MDMAARBE.PRI Register bit field)

(DMA) [For more detailed information on the PRI bit field, see the

TMS320DM644x DMSoC ARM Subsystem Reference Guide

(literature number SPRUE14).]

C64X+_CFGP C64X+ 1 (MSTPRI0 Register)

(CFG) EMACP EMAC 4 (MSTPRI1 Register) USBP USB 4 (MSTPRI1 Register) ATAP ATA/CF 4 (MSTPRI1 Register) VLYNQP VLYNQ 4 (MSTPRI1 Register) HPIP HPI 4 (MSTPRI1 Register)

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Figure 3-5. MSTPRI0 Register

31 19 18 16

RESERVED RESERVED

R-0000 0000 0000 0 R/W-101

15 11 10 8 7 6 4 3 2 0

RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP

R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001

LEGEND: R = Read; W = Write; -n = value after reset

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Figure 3-6. MSTPRI1 Register

31 23 22 20 19 18 16

RESERVED HPIP RSV VLYNQP

R-0000 0000 0 R/W-100 R-0 R/W-100

15 14 13 12 11 10 8 7 6 4 3 2 0

RSV ATAP RSV USBP RSV RESERVED RSV EMACP

R-0 R/W-100 R-0 R/W-100 R-0 R/W-100 R-0 R/W-100

LEGEND: R = Read; W = Write; -n = value after reset

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3.5.2 Multiplexed Pin Configurations

There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins are configured by external pullup/pulldown resistors only at reset, and others are configured by software. As described in detail in Section 3.4.1 (Device Configuration at Device Reset) and Section 3.4.2 (Peripheral Selection at Device Reset), hardware configurable multiplexed pins are programmed by external pullup/pulldown resistors at reset to set the initial functionality of pins for use by a single peripheral. After reset, software configurable multiplexed pins are programmable through Memory Mapped Registers (MMR) to allow the switching of pin functionalities during run-time. See Section 3.5.3, Peripheral Selection After Device Reset, for more details on the register settings.

A summary of the pin multiplexing is shown in Table 3-13. The EMAC peripheral shares pins with the 3.3V GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional pins to implement the RGB888 mode, these are multiplexed with GPIOs.

Table 3-13. DM6443 Multiplexed Peripheral Pins and Multiplexing Controls

MULTIPLEXED SECONDARY

PERIPHERALS FUNCTION FUNCTION

EMIFA (NAND), HPI EMIFA (NAND): HPI: PinMux0:HPIEN,

EMIFA, HPI, ATA EMIFA: ATA (CF): HPI: PinMux0:ATAEN PinMux0:HPIEN, (CF) EM_D[0:15], DD[0:15], DA0 HD[0:15], HINT Pins:BTSEL[1:0] = 10

EMIFA (NAND), EMIFA (NAND): ATA (CF): HPI: PinMux0:ATAEN PinMux0:HPIEN, HPI, ATA (CF) R/W, EM_WAIT INTRQ, IORDY, HR/W, HRDY, HDS1, Pins:BTSEL[1:0] = 10

VPBE LCD, GPIO GPIO:GPIO[0] VPBE: LCD_OE PinMux0:LOEEN VPBE RGB888, GPIO:GPIO[2] VPBE: PinMux0:RGB888

GPIO RGB888 G0 VPBE GPIO:GPIO[3] VPBE: VPBE: PinMux0:RGB888 PinMux0:LFLDEN

LCD/RGB888, GPIO RGB888 B0 LCD_FIELD VPBE RGB888, GPIO:GPIO[4] VPBE: PinMux0:RGB888

GPIO RGB888 R0 VPBE RGB888, GPIO: VPBE: PinMux0:RGB888

GPIO GPIO[5:6, 38] RGB888 G1, B1,

EMIFA, VLYNQ, GPIO:GPIO[8] EMIFA: VLYNQ: PinMux0:AECS5 PinMux0:VLYNQEN GPIO EM_CS5 VLYNQ_CLOCK

EMIFA, VLYNQ, GPIO:GPIO[9] EMIFA: VLYNQ: PinMux0:AECS4 PinMux0:VLSCREN GPIO EM_CS4 VLYNQ_SCRUN

EMIFA, VLYNQ, GPIO: EMIFA: VLYNQ: PinMux0:AEAW, PinMux0:VLYNQEN, GPIO GPIO[10:17] EM_A[21:14] VLYNQ_TXD[0:3], Pins:DAEAW[4:0] PinMux0:VLYNQWD[1:0]

EMIFA, GPIO GPIO: EMIFA: PinMux0:AEAW,

PRIMARY SECONDARY TERTIARY

(DEFAULT) REGISTER/PIN

FUNCTION CONTROL CONTROL

EM_A[1] (ALE), HHWIL, HCNTL0, Pins:BTSEL[1:0] = 10 EM_A[2] (CLE), HCS EM_CS2, EM_CS3

EM_BA[0]

(RDY/BSY), DIOR(IORD) , HDS2 EM_OE (RE), DIOW (IOWR) EM_WE (WE)

GPIO[18:28] EM_A[13:3] Pins:DAEAW[4:0]

(1)

TERTIARY

VLYNQ_RXD[0:3]

(2)

(3)

(1) When the Secondary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO) and Tertiary functions are

disabled.

(2) When the Tertiary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO), Secondary, and other Tertiary

functions are disabled.

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Table 3-13. DM6443 Multiplexed Peripheral Pins and Multiplexing Controls (continued)

MULTIPLEXED SECONDARY

PERIPHERALS FUNCTION FUNCTION

PRIMARY SECONDARY TERTIARY

(DEFAULT) REGISTER/PIN

FUNCTION CONTROL CONTROL

ASP, GPIO GPIO: ASP: PinMux1:ASP

GPIO[29:34] (all pins)

UART0, GPIO GPIO: UART0: PinMux1:UART0

GPIO[35:36] RXD, TXD

SPI, GPIO GPIO: SPI: PinMux1:SPI

GPIO[37, 39:41] SPI_EN0,

SPI_CLK,

SPI_DI, SPI_DO SPI, ATA, GPIO GPIO:GPIO[42] SPI: SPI_EN1 ATA: HDDIR PinMux1:SPI PinMux0:HDIREN I2C, GPIO GPIO: I2C: SCL, SDA PinMux1:I2C

GPIO[43:44] PWM0, GPIO GPIO:GPIO[45] PWM0 PinMux1:PWM0 PWM1, VPBE GPIO:GPIO[46] VPBE: PWM1: PinMux0:RGB666/ PinMux1:PWM1

(RGB666/RGB888), RGB666/RGB888 PWM1 PinMux0:RGB888 GPIO R2

PWM2, VPBE GPIO:GPIO[47] VPBE: PWM2: PinMux0:RGB666/ PinMux1:PWM2 (RGB666/RGB888), RGB666/RGB888 PWM2 PinMux0:RGB888 GPIO B2

ClockOut0, GPIO GPIO:GPIO[48] CLK_OUT0 PinMux1:CLK0 ClockOut1, TIMER0, GPIO:GPIO[49] CLK_OUT1 TIMER0: PinMux1:CLK1 PinMux1:TIM_IN

GPIO TIM_IN ATA, GPIO GPIO: ATA: PinMux0:ATAEN

GPIO[50:51] ATA_CS0,

ATA_CS1

EMIFA, GPIO, ATA GPIO:GPIO[52] EMIFA: ATA (CF): PinMux0:AEAW[4:0], PinMux0:ATAEN (CF) EM_BA[1] DA1 Pins:DAEAW[4:0]

EMIFA, HPI, ATA GPIO:GPIO[53] EMIFA: ATA (CF): DA2/ PinMux0:AEAW[4:0], PinMux0:ATAEN, (CF), GPIO EM_A[0] HPI: HCNTL1 Pins:DAEAW[4:0] PinMux0:HPIEN,

EMAC, GPIO3V GPIO: EMAC: PinMux0:EMACEN

GPIO3V[0:13] (all pins, except

CRS)

(5)

EMAC, MDIO, GPIO: EMAC: PinMux0:EMACEN GPIO3V GPIO3V[14:16] CRS,

MDIO:

MDIO, MDCLK

UART1, ATA (CF) N/A ATA (CF): UART1: TXD, RXD PinMux0:ATAEN PinMux1:UART1

DMACK, DMARQ

UART2 N/A UART2: PinMux1:UART2

UART_RXD2, UART_TXD2

UART2 N/A UART2: PinMux1:UART2,

UART_CTS2, PinMux1:U2FLO UART_RTS2

(4) See Section 2.7, Terminal Functions, for pin details. (5) See Section 2.7, Terminal Functions, for pin details.

(1)

(4)

TERTIARY

(2)

(3)

Pins:BTSEL[1:0] = 10

(3)

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3.5.3 Peripheral Selection After Device Reset

After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing of shared device pins between peripherals, as given in Section 2.7, Terminal Functions. Section 3.5.4 (PINMUX0 Register Description), Section 3.5.5 (PINMUX1 Register Description), and Section 3.5.6 (Pin Multiplexing Register Field Details) identify the register settings necessary to configure specific multiplexed functions and show the primary (default) function after reset.

3.5.4 PINMUX0 Register Description

The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins among EMAC, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on the PINMUX0 pin muxing fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function.

Figure 3-7. PINMUX0 Register

31 30 29 28 26 25 24 23 22 21 18 17 16

EMACEN Rsvd HPIEN Reserved LFLDEN LOEEN RGB888 RGB666 Reserved ATAEN HDIREN

R/W-0 R/W-0 R/W-D R/W-000 R/W-0 R/W-0 R/W-0 R/W-0 R-0000 R/W-0 R/W-0

15 14 13 12 11 10 9 5 4 0

VLYNQEN VLSCREN VLYNQWD AECS5 AECS4 Reserved AEAW

R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R-00000 R/W-LLLLL

LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset

(1) For proper DM6443 device operation, always write a value of '0' to RSV bits 30, 27, and 26.

(1)

Table 3-14. PINMUX0 Register Description

Name Description

EMACEN Enable EMAC and MDIO function on default GPIO3V[0:16] pins. HPIEN Enable HPI module pins. Default value is derived from BTSEL[1:0] configuration inputs. HPIEN is 1 when the

LFLDEN Enable LCD_FIELD function on default GPIO[3] pin LOEEN Enable LCD_OE function on default GPIO[0] pin RGB888 Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins RGB666 Enable VPBE RGB666 function on default GPIO[46:47] pins ATAEN Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins HDIREN Enable HDDIR function on default GPIO[42] pin VLYNQEN Enable VLYNQ function on default GPIO[9,10:17] pins VLSCREN Enable VLYNQ SCRUN function on default GPIO[9] pin VLYNQWD VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3] functions on default GPIO[10:17]

AECS5 Enable EMIFA EM_CS5 function on GPIO[8] AECS4 Enable EMIFA EM_CS4 function on GPIO[9] AEAW EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This

BTSEL[1:0] = 10 and HPIEN is 0 (the default state) when BTSEL[1:0] is 00, 01, or 11.

pins.

enables EMIF address function on default GPIO[10:28] pins.

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3.5.5 PINMUX1 Register Description

The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in

Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing

fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function.

Figure 3-8. PINMUX1 Register

31 19 18 17 16

RESERVED TIMIN CLK1 CLK0

R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0

15 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ASP RSV SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0

R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) For proper DM6443 device operation, always write a value of '0' to RSV bit 9. (2) Following device power up or reset to enable the UART2 and UART2 flow control, a value of '1' must be written to the UART2 and

U2FLO bits (bits 2 and 3, respectively).

Table 3-15. PINMUX1 Register Description

Name Description

TIMIN Enable TIM_IN function on default GPIO[49] pin CLK1 Enable CLK_OUT1 function on default GPIO[49] pin CLK0 Enable CLK_OUT0 function on default GPIO[48] pin ASP Enable ASP function on default GPIO[29:34] pins SPI Enable SPI function on default GPIO[37,39:42] pins I2C Enable I2C function on default GPIO[43:44] pins PWM2 Enable PWM2 function on default GPIO[47] pin PWM1 Enable PWM1 function on default GPIO[46] pin PWM0 Enable PWM0 function on default GPIO[45] pin U2FLO Enable UART2 flow control function on default disabled UART2 Enable UART2 function on default disabled UART1 Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins UART0 Enable UART0 function on default GPIO[35:36] pins

(1) (2)

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3.5.6 Pin Multiplexing Register Field Details

The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are described in the following sections.

3.5.6.1 EMAC and GPIO3V Pin Multiplexing

The EMAC pin functions are selected as shown in Table 3-16. The functionality for each of the individual pins affected by the PINMUX0 field settings is given in Table 3-17.

Table 3-16. EMAC and GPIO3V Pin Multiplexing Control

EMACEN PIN FUNCTIONALITY SELECTED

0 GPIO3V 1 EMAC

Table 3-17. EMAC and GPIO3V Multiplexed Pins

GPIO EMAC

GPIO3V[0] TXEN GPIO3V[1] TXCLK GPIO3V[2] COL GPIO3V[3] TXD[0] GPIO3V[4] TXD[1] GPIO3V[5] TXD[2] GPIO3V[6] TXD[3] GPIO3V[7] RXD[0] GPIO3V[8] RXD[1]

GPIO3V[9] RXD[2] GPIO3V[10] RXD[3] GPIO3V[11] RXCLK GPIO3V[12] RXDV GPIO3V[13] RXER GPIO3V[14] CRS GPIO3V[15] MDIO GPIO3V[16] MDCLK

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3.5.6.2 VPBE (LCD) and GPIO Pin Multiplexing

The LCD controller in the VPSS requires multiplex control bit settings for certain modes of operation. Bits within the PinMux0 register, which select between the LCD control signal function and GPIO, are summarized in Table 3-18.

Table 3-18. VPBE (LCD) and GPIO Pin Multiplexing

PINMUX0

LFLDEN LOEEN LCD_FIELD/B0/GPIO[3] LCD_OE/GPIO[0]

- 0 - GPIO[0]

- 1 - LCD_OE 0 - B0/GPIO[3] 1 - LCD_FIELD -

(1) Depends on RGB888 bit setting, see Table 3-19.

(1)

MULTIPLEXED PINS

3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing

Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19 and Table 3-20. Enabling PWM2, PWM1, and LCD functionality overrides the the RGB modes. RGB666 interface pin functionality requires setting the RGB666 PINMUX0 Register bit field to ‘1’ and PINMUX1 Register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0 Register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, and LFLDEN must be set to ‘0’.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Table 3-19. VPBE (RGB666, RGB888, and LCD), and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

RGB888 RGB666 PWM2 PWM1 LFLDEN B2/ R2/ B0/

0 0 0 0 0 GPIO[47] GPIO[46] GPIO[3]

- - - - 1 - - LCD_FIELD

- - - 1 - - PWM1 -

- - 1 - - PWM2 - 0 1 0 0 0 B2 R2 GPIO[3] 1 - 0 0 0 B2 R2 B0

PWM2/ PWM1/ LCD_FIELD/ GPIO[47] GPIO[46] GPIO[3]

Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

RGB888 PWM2 PWM1 LFLDEN

0 0 0 0 GPIO[38] GPIO[6] GPIO[5] GPIO[2] 1 0 0 0 R1 B1 G1 G0

R1/ B1/ G1/ G0/ GPIO[38] GPIO[6] GPIO[5] GPIO[2]

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3.5.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1 if the buffer is not being used (i.e. for Compact Flash). This multiplexing is shown in Table 3-22. When ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA buffers drive away from DM644X and don’t cause bus contention with the EMIFA. Note that switching between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA requests have completed before clearing the ATAEN bit.

Table 3-21. ATA, EMIFA, and GPIO Pin Multiplexing Control

PINMUX0

BIT FIELD

ATAEN GPIO[52]/ GPIO[53]/ DD[15:0]

0 1 ATA_CS0 ATA_CS1 INTRQ ATA0 IORDY DIOR DIOW ATA1 ATA2 DD[15:0]

(1) This table assumes that the HPIEN bit in the PINMUX0 register is "0". (2) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

GPIO[50]/ GPIO[51]/ EM_R/W EM_BA[0]/ EM_WAIT DIOR/ DIOW/ ATA_CS0 ATA_CS1 INTRQ ATA0 IORDY EM_OE EM_WE

GPIO[50] GPIO[51] EM_R/W EM_BA[0] EM_WAIT EM_OE EM_WE EM_BA[1]/ EM_A[0]/ EM_D[15:0]

(1)

EM_BA[1]/ EM_A[0]/ EM_D[15:0]/ ATA1 ATA2

GPIO[52]

(2)

GPIO[53]

(2)

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Table 3-22. ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

ATAEN UART1 HDIREN SPI HDDIR/

0 0 0 0 DMACK DMARQ GPIO[42] 0 0 0 1 DMACK DMARQ SPI_EN1 0 0 1 - DMACK DMARQ Driven Low 0 1 0 0 UART_TXD1 UART_RXD1 GPIO[42] 0 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1 0 1 1 - UART_TXD1 UART_RXD1 Driven Low 1 0 0 0 DMACK DMARQ GPIO[42]x 1 0 0 1 DMACK DMARQ SPI_EN1x 1 0 1 - DMACK DMARQ HDDIR 1 1 0 0 UART_TXD1 UART_RXD1 GPIO[42]x 1 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1x 1 1 1 - UART_TXD1 UART_RXD1 HDDIR

UART_TXD1/ UART_RXD1/

DMACK DMARQ

SPI_EN1/ GPIO[42]

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3.5.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing

Table 3-23 and Table 3-24 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled

(VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] / EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address based on the AEAW value.

Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing

PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS

VLYNQEN VLSCREN AECS5 AECS4 GPIO[8]/ GPIO[9]/

0 - 0 0 GPIO[8] GPIO[9] 0 - 0 1 GPIO[8] EM_CS4 0 - 1 0 EM_CS5 GPIO[9] 0 - 1 1 EM_CS5 EM_CS4 1 0 - 0 VLYNQ_CLOCK GPIO[9] 1 0 - 1 VLYNQ_CLOCK EM_CS4 1 1 - - VLYNQ_CLOCK VLYNQ_SCRUN

EM_CS5/ EM_CS4/

VLYNQ_CLOCK VLYNQ_SCRUN

Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing

PINMUX0

BIT FIELDS

VLYNQEN VLYNQWD GPIO[10]/ GPIO[11]/ GPIO[12]/ GPIO[13]/ GPIO[14]/ GPIO[15]/ GPIO[16]/ GPIO[17]/

0 -

1 00

1 01

1 10 1 11 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 VL_TXD3 VLRXD3

EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

VL_TXD0 VL_RXD0 VL_TXD1 VL_RXD1 VL_TXD2 VL_RXD2 VL_TXD3 VL_RXD3

EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

(1)

GPIO[10]

VL_TXD0 VLRXD0 EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 EM_A[15]/ EM_A[14]/

GPIO[11]

(1)

GPIO[12]

(1)

GPIO[13]

(1)

GPIO[13]

(1)

GPIO[14]

(1)

GPIO[15]

(1)

GPIO[16]

(1)

GPIO[17]

(1)

GPIO[17]

(1)

GPIO[17]

(1)

GPIO[17]

(1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

3.5.6.6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing

The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-25.

Table 3-25. Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing

PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

TIMIN CLK1 TIM_IN/

0 0 GPIO[49] 0 1 CLK_OUT1 1 - TIM_IN

CLK_OUT1/

GPIO[49]

(1)

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3.5.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing

When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as seen in Table 3-26, Table 3-27, and Table 3-28. The SPI_EN1 pin can also function as the HDDIR buffer control when ATAEN is selected and the HDIREN bit is set.

Table 3-26. ASP and GPIO Pin Multiplexing

PINMUX1 REGISTER BIT FIELD MULTIPLEXED PINS

ASP

0 GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] 1 CLKX CLKR FSX FSR DX DR

CLKX/ CLKR/ FSX/ FSR/ DX/ DR/

GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34]

Table 3-27. SPI and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

SPI ATAEN HDIREN HDDIR/ GPIO[41] GPIO[40] GPIO[39] GPIO[37]

0 0 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 0 1 Driven Low GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 1 HDDIR GPIO[41] GPIO[40] GPIO[39] GPIO[37] 1 0 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 0 1 Driven Low SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 1 HDDIR SPI_DO SPI_DI SPI_CLK SPI_EN0

SP_EN1/ SPI_DO/ SPI_DI/ SPI_CLK/ SPI_EN0/

GPIO[42]

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Table 3-28. I2C and GPIO Pin Multiplexing

PINMUX1 REGISTER

BIT FIELD

I2C

0 GPIO[43] GPIO[44] 1 I2C_CLK I2C_DATA

MULTIPLEXED PINS

I2C_CLK/ I2C_DATA/ GPIO[43] GPIO[44]

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3.5.6.8 PWM, RGB888, and GPIO Pin Multiplexing

Table 3-29 shows the PWM0/1/2 pin multiplexing. Each PWM output is independently controlled by its

own enable bit. The PWM function has priority over RGB888 muxing [see Section 3.5.6.3, VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing ].

Table 3-29. PWM0/1/2, RGB888, and GPIO Pin Multiplexing

PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

PWM2 PWM1 PWM0 RGB888 B2/ R2/ GPIO[45]

0 0 0 0 GPIO[47] GPIO[46] GPIO[45] 0 0 0 1 B2 R2 GPIO[45]

- - 1 - - - PWM0

- 1 - - - PWM1 -

1 - - - PWM2 - -

3.5.6.9 UART, ATA, and GPIO Pin Multiplexing

Each UART has independent pin multiplexing control bits in the PINMUX1 register. Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with

the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However, ATA PIO mode is still supported with UART1 enabled. This is shown in Table 3-30. If the ATA module is not enabled, the pins are always configured for use by UART1.

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PWM2/ PWM1/ PWM0/

GPIO[47] GPIO[46]

Table 3-30. UART1 and ATA Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER

ATAEN UART1

0 - UART_TXD1 UART_RXD1 1 0 DMACK DMARQ 1 1 UART_TXD1 UART_RXD1

BIT FIELDS

UART_TXD1/ UART_RXD1/

DMACK DMARQ

MULTIPLEXED PINS

As Table 3-31 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO.

Table 3-31. UART0 and GPIO Pin Multiplexing

PINMUX1 REGISTER BIT

FIELD

UART0

0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0

UART_TXD0/ UART_RXD0/

GPIO[36] GPIO[35]

MULTIPLEXED PINS

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3.5.6.10 HPI and EMIFA/ATA Pin Multiplexing

When the HPIEN bit is set, the HPI module is given control of most of the EMIFA/ATA control pins as well as the EMIFA/ATA data bus. Table 3-32 shows which pins the HPI controls. HPIEN is set to 1 when the state of the BTSEL[1:0] pins = 10 is latched at the rising edge of reset. Also, this bit can be manipulated after reset by software. When the ATAEN bit is set and HPIEN is 0, the ATA mode of operation for pins shared with the HPI is available. EMIFA mode functionality for the shared HPI pins is set when both HPIEN and ATAEN are '0'.

Table 3-32. HPI and EMIFA/ATA Pin Multiplexing

PINMUX0

BIT FIELDS

HPI ATA HCS/ HHWIL/ HCNTLA/

EN EN EM_CS2 EM_A[1] EM_A[2]

0 0 EM_CS2 EM_A[1] 0 1 EM_CS2 EM_A[1] 1 - HCS HHWIL HR/W HRDY HDS1 HDS2 HCNTLA HCNTLB HINT HD[15:0]

(1) This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14.

HR/W/ HRDY/ HDS1/ HDS2/ HCNTLB/ HINT/ HD[15:0]/

INTRQ/ EM_WAIT/ DIOR/ DIOW/ ATA2/ ATA0/ DD[15:0]/

EM_R/W IORDY EM_OE EM_WE EM_A[0] EM_BA[0] EM_D[15:0]

(1)

EM_R/W EM_WAIT EM_OE EM_WE EM_A[2]

(1)

INTRQ IORDY DIOR DIOW EM_A[2]

(1) (1)

EM_A[0] EM_A[0]

(1)

EM_BA[0] EM_D[15:0]

(1)

ATA0 DD[15:0]

3.6 Emulation Control

The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. This allows peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register indicates the emulation suspend source for those peripherals which support emulation suspend. The SUSPSRC register format is shown in Figure 3-9. Brief details on the peripherals which correspond to the register bits is given in Table 3-33. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator.

Figure 3-9. Emulation Suspend Source Register (SUSPSRC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd Rsvd Rsvd

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0

15 13 12 11 10 9 8 6 5 4 0

Reserved Reserved Reserved Reserved

LEGEND: R = Read, W = Write, n = value at reset

(1) For proper DM6443 device operation, always write a value of '0' to RSV bits 30 and 31.

TIMR2 TIMR1 TIMR0 GPIO PWM2 PWM1 PWM0 SPI UART2 UART1 UART0 I2C ASP

SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC

HPI USB EMAC

SRC SRC SRC

R-000 R/W-0 R-00 R/W-0 R-000 R/W-0 R-0 0000

(1)

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Table 3-33. SUSPSRC Register Description

Name Description

TIMR2SRC Timer2 (WD Timer) emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

TIMR1SRC Timer1 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

TIMR0SRC Timer0 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

GPIOSRC GPIO emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

PWM2SRC PWM2 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

PWM1SRC PWM1 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

PWM0SRC PWM0 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

SPISRC SPI emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

UART2SRC UART2 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

UART1SRC UART1 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

UART0SRC UART0 emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

I2CSRC I2C emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

ASPSRC ASP emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

HPISRC HPI emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

USBSRC USB emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

EMACSRC Ethernet MAC emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

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4 System Interconnect

On the DM6443 device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture (shown in Figure 4-1). The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals and slave peripherals. Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. Through SCR, the ARM subsystem can send data to the DDR2 Memory Controller without affecting a data transfer between the EMAC and L2 memory. Bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 8 performs a frequency conversion between a bus operating at DSP/6 clock rate and a bus operating at DSP/3 clock rate. Furthermore, Bridge 3 performs a bus-width conversion between a 64-bit bus and a 32-bit bus.

The C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the various system peripherals can be classified into two categories: master peripherals and slave peripherals. Master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, CF/ATA, VLYNQ, EMAC, USB, and VPSS. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by an X in Table 4-1.

Table 4-1. System Connection Matrix

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MASTER

C64x+ X X X

ARM X X X

VPSS X

CF/ATA X X X X

VLYNQ X X X X

EMAC X X X X

USB X X X X EDMA3TC0 X X X X EDMA3TC1 X X X X

HPI X X X

(1) The C64x+ megamodule has access to only the following peripherals connected to SCR3: EDMA3, ASP, and Timers. All other

peripherals/modules that support a connection to SCR3 have access to all peripherals/modules connected to SCR3.

(2) HPI's access to SCR3 is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and HPI configuration registers.

C64x+ ARM DDR2 MEMORY CONTROLLER SCR3

SLAVE

(1)

(2)

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SCR5

Bridge2

CF/ATA

VLYNQ

EMAC

USB2.0

SCR2

Bridge1

Bridge7

ARM

C64x+

CFG MDMA

L2Cache

Bridge6

Bridge5

SCR3

VPSS

EDMA3TC1

Bridge3

ARM

TCM

C64x+ L2/L1

SDMA

DDR2Ctrl

(Mem/Reg)

SCR6

CF/ATA Reg

USBReg

EMACReg

EMACCtrlModReg

EMACCtrlModRAM

MDIO

VPSSReg

SPI0/1

GPIO

AINTC

SystemReg

PSC

PLLC0

PLLC1

Bridge9

Bridge8

SCR7

ASP

VLYNQ

MMC/SD

EMIFA/NAND

SCR8

UART0

UART1

UART2

I2C

PWM0

PWM1

PWM2

Timer0

Timer1

Timer2

SCR4

EDMA3CC

EDMA3TC0

EDMA3TC1

32 64

64 64

Read

Write Read

Write

128

DSP/2ClockRate

DSP/3ClockRate

DSP/6ClockRate

EDMA3TC0

MXI/CLKINRate

HPI

TMS320DM6443

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4.1 System Interconnect Block Diagram

Figure 4-1 displays the DM6443 system interconnect block diagram. The following is a list that helps

interpret this diagram:

• The direction of the arrows indicates either bus master or bus slave.

• The arrow originates at a bus master and terminates at a bus slave.

• The direction of the arrows does not indicate the direction of data flow. Data flow is typically bi-directional for each of the documented bus paths.

• The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3, or DSP/6 clock rate.

• Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple instances shown for a variety of reasons, some of which are described below:

– The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register

access, data access, and/or memory access. Examples of these peripherals are C64x+ megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI.

– The peripheral/module has a master port as well as slave memories. Examples of these are the

C64x+ megamodule and the ARM subsystem.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Figure 4-1. System Interconnect Block Diagram

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5 Device Operating Conditions

5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Supply voltage ranges

Input voltage ranges

Output voltage ranges

Operating case temperature ranges, T Storage temperature range, T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This pin is an internal LDO output and connected via 1 µF capacitor to USB_V (3) All voltage values are with respect to V

stg

(1)

Core (CVDD, V I/O, 3.3V (DV I/O, 1.8V (DV

USB_V

DD1P8

, USB_V

DDA1P1V

, USB_V

DD33

, DV

DD18

, MXVDD, M24VDD)

DDR2

DDA3P3

, DDR_V

DDA1P2LDO

(3)

)

DDDLL

(3)

(2)

, CV

, PLLV

DDDSP

DD18

)

, V

DDA1P8V

(3)

, -0.5 V to 2.5 V

VII/O, 3.3V -0.5 V to 4.2 V VII/O, 1.8V -0.5 V to 2.5 V VOI/O, 3.3V -0.5 V to 4.2 V VOI/O, 1.8V -0.5 V to 2.5 V (default) 0°C to 85°C

(default) -55°C to 150°C

SS.

SSA1P2LDO

-0.5 V to 1.5 V

-0.5 V to 4.2 V

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SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

5.2 Recommended Operating Conditions

Supply voltage, Core (CVDD, V CV

) (-594 devices)

DDDSP

Supply voltage, I/O, 3.3V (DV

Supply voltage, I/O, 1.8V (DV PLLV

DD18

, V

DDA1P8V

, USB_V

Supply ground (VSS, V

USB_V MXV

SSREF

(3)

, M24V

, USB_V

SS1P8

(3)

DDR_VREF DDR2 reference voltage

(2)

SSA1P8V

, USB_V

)

(4)

, USB_V

DDA1P1V

, USB_DV

DD33

, DV

DD18

DDR2

, MXVDD, M24VDD)

DD1P8

, V

SSA1P1V

SSA3P3

, DDR_V

DDA1P2LDO

DDA3P3

, DDR_V

, USB_V

DDR_ZP DDR2 impedance control, connected via 200 Ω resistor to V DDR_ZN DV

DDR2 impedance control, connected via 200 Ω resistor to DV

DDR2

(1)

) 3.15 3.3 3.45 V

DDDLL

SSDLL

, 0 0 0 V

SSA1P2LDO

DAC_VREF DAC reference voltage input 0.475 0.5 0.525 V DAC_RBIAS DAC biasing, connected via 4 kΩ resistor to V

SSA_1P8V

USB_VBUS USB external charge pump input 4.75 5 5.25 V

SYSCLK1

High-level input voltage, I/O, 3.3V 2 V High-level input voltage, non-DDR I/O, 1.8V 0.65DV Low-level input voltage, I/O, 3.3V 0.8 V Low-level input voltage, non-DDR I/O, 1.8V 0.35DV Operating case temperature Default 0 85 °C DSP Operating Frequency (SYSCLK1) 20 600 MHz

(1) This pin is an internal LDO output and connected via 1 mF capacitor to USB_V (2) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2, 1.26 V with ±3% tolerances) by implementing simple board changes such as reference resistor values or input pin

configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC

devices. (3) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. (4) DDR_VREF is expected to equal 0.5DV

of the transmitting device and to track variations in the DV

DDR2

MIN NOM MAX UNIT

1.14 1.2 1.26 V

1.71 1.8 1.89 V

0.49DV

SSA1P2LDO

DDR2

0.5DV

DDR2

SSA_1P8V

DDR2

0.51DV

DDR2

V V

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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Case Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS

Low/full speed: USB_DN and USB_DP

High speed:

USB_DN and USB_DP High-level output voltage (3.3V I/O) DV High-level output voltage (1.8V I/O) DV

= MIN, IOH= MAX 2.4 V

DD33

= MIN, IOH= MAX DVDD- 0.45 V

DD18

Low/full speed: USB_DN and USB_DP

High speed:

USB_DN and USB_DP Low-level output voltage (3.3V I/O) DV Low-level output voltage (1.8V I/O) DV

= MIN, IOL= MAX 0.4 V

DD33

= MIN, IOL= MAX 0.45 V

DD18

VI= VSSto DVDDwithout opposing internal resistor

I I

C C

(2)

Input current 50 100 250 mA

High-level output current All peripherals -4 mA

Low-level output current All peripherals 4 mA

(4)

I/O Off-state output current

Core (CVDD, V

CDD

) supply current

DDDSP

3.3V I/O (DV current

(6)

DDD

1.8V I/O (DV PLLV

DDD

I o

, V

DD18

M24VDD) supply current Input capacitance 4 pF Output capacitance 4 pF

DDA1P1V

DD33

DD18

DDA1P8V

, USB_V

, DV

DDR2

, USB_V

DDA1P2LDO

(6)

) supply

DDA3P3

, DDR_V

DDDLL

, MXVDD, DVDD= 1.8 V, DSP clock = 594 MHz 102 mA

DD1P8

(6)

VI= VSSto DVDDwith opposing internal pullup resistor

VI= VSSto DVDDwith opposing internal pulldown resistor

(3)

VO= DVDDor VSS; internal pull disabled ±20 mA VO= DVDDor VSS; internal pull enabled ±100 mA

(5)

CVDD= 1.2 V, DSP clock = 594 MHz 767 mA

DVDD= 3.3 V, DSP clock = 594 MHz 6 mA

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in Section 5.2, Recommended Operating

Conditions. (2) IIapplies to input-only pins and bi-directional pins. For input-only pins, IIindicates the input leakage current. For bi-directional pins, I

indicates the input leakage current and off-state (Hi-Z) output leakage current. (3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. (4) IOZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current. (5) This pin is an internal LDO output and connected via 1 mF capacitor to USB_V (6) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other

housekeeping activities); DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes, 32 bits, 50% bit switching; 2 MHz ASP at

100% utilization; Timer0 at 100% utilization. At room temperature (25°C) for typical process devices. The actual current draw varies

across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information

relevant to board power supply design, see the TMS320DM6446/3 Power Consumption Summary application report (literature number

SPRAAD6).

(1)

SSA1P2LDO

MIN TYP MAX UNIT

2.8 USB_V

360 440 mV

0.0 0.3 V

-10 10 mV

-250 -100 -50 mA

DDAP3

±10 mA

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Transmission Line

4.0 pF 1.85 pF

Z0 = 50 Ω (see note)

Tester Pin Electronics

Data Manual Timing Reference Point

Output Under Test

NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data manual timings.

42 Ω 3.5 nH

Device Pin (see note)

Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

ref

= VIL MAX (or VOL MAX)

ref

= VIH MIN (or VOH MIN)

TMS320DM6443

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6 Peripheral and Electrical Specifications

6.1 Parameter Information

6.1.1 Parameter Information Device-Specific Information

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Figure 6-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1.1 Signal Transition Levels

All input and output timing parameters are referenced to V V

= 1.5 V. For 1.8 V I/O, V

ref

Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VILMAX and VIHMIN for input clocks, VOLMAX and VOHMIN for output clocks.

Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels

= 0.9 V.

ref

for both "0" and "1" logic levels. For 3.3 V I/O,

ref

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6.1.1.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the TMS320DM644x DSP Application Report (literature number SPRAAC5).

6.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between VIHand VIL(or between VILand VIH) in a monotonic manner.

6.3 Power Supplies

For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower.

www.ti.com

6.3.1 Power-Supply Sequencing

The DM6443 includes two core supplies — CVDDand CV DV

The core supply power-up sequence is dependent on the DSP boot mode selected at reset. If the DSP boot mode is configured as Self-Boot mode, then both core supplies must be powered up at the same time.

If the DSP boot mode is configured as Host-Boot, where the ARM boots the DSP, the two core supplies may be ramped simultaneously or powered up separately. When powered up separately, the CV supply must not be ramped prior to the CVDDsupply. The CV shorting switch is closed (enabled). Prior to powering up the CV not driven to ground. Table 6-1 and Figure 6-4 describe the power-on sequence timing requirements for DSP Host-Boot mode.

To minimize the voltage difference between these two core supplies, a single regulator source must be used to power the CVDDand CV

For more information, see Section 3.2.1, Power Configurations at Reset.

DDR2

, and DV

. To ensure proper device operation, a specific power-up sequence must be followed.

DD33

DDDSP

supplies.

, as well as three I/O supplies — DV

DDDSP

supply must be powered up before the

DDDSP

supply, it should be left floating and

DDDSP

DD18

DDDSP

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DDDSP

DDXX

(A)

Note A:DV denotesallI/Osupplies.

DDXX

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SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4)

NO. UNIT

1 t

d(CVDD-CVDDDSP)

(1) In Host-Boot mode, the CV

and DSP power domains.

Delay time, CVDDsupply ready to CV

supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON

DDDSP

supply ramp start 0

DDDSP

-594

MIN MAX

(1)

Figure 6-4. DSP Host-Boot Mode Core Supply Timings

Once the CVDDsupply has been powered up, the I/O supplies may be powered up. Table 6-2 and

Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DV

used to denote all I/O supplies. Note: the DV power-up, not the CV

DDDSP

supply.

supply power-up is specified relative to the CVDDsupply

DDXX

Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5)

NO. UNIT

1 t

d(CVDD-DVDD)

Delay time, CVDDsupply ready to DV

supply ramp start 0 100 ms

DDXX

-594

MIN MAX

There is not a specific power-up sequence that must be followed with respect to the order of the power-up of the DV

DD18

specification is met, the DV preference. All other supplies may also be powered up in any order of preference once the t specification has been met.

, DV

DDR2

, and DV

DD18

Figure 6-5. I/O Supply Timings

supplies. Once the CVDDsupply is powered up and the t

DD33

, DV

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, and DV

DDR2

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supplies may be powered up in any order of

DD33

d(CVDD-DVDDXX)

TMS320DM6443

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

6.3.1.1 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the DM6443 device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

6.3.1.2 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to DM6443. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6443 power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior".

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered.

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6.3.1.3 DM6443 Power and Clock Domains

DM6443 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the VDDpins of the DM6443. The majority of the DM6443's modules lie within the "Always On" power domain. A separate domain called the "DSP" domain houses the C64x+. The "DSP" domain is not always on. The "DSP" power domain is powered by the CV

pins of the DM6443. Table 6-3 provides a listing of the DM6443 power and clock

DDDSP

domains. Two primary reference clocks are required for the DM6443 device. These can either be crystal input or

driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3. The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For further description of the DM6443 clock domains, see Table 6-4 (DM6443 Clock Domains) and Figure 6-6 (PLL1 and PLL2 Clock Domain Block Diagram).

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Table 6-3. DM6443 Power and Clock Domains

POWER DOMAIN CLOCK DOMAIN PERIPHERAL/MODULE

Always On CLKIN UART0 Always On CLKIN UART1 Always On CLKIN UART2 Always On CLKIN I2C Always On CLKIN Timer0 Always On CLKIN Timer1 Always On CLKIN Timer2 Always On CLKIN PWM0 Always On CLKIN PWM1 Always On CLKIN PWM2 Always On CLKDIV2 ARM Subsystem Always On CLKDIV3 DDR2 Always On CLKDIV3 VPSS Always On CLKDIV3 EDMA3 Always On CLKDIV3 SCR Always On CLKDIV6 GPSC Always On CLKDIV6 LPSCs Always On CLKDIV6 Ice Pick Always On CLKDIV6 EMIFA Always On CLKDIV6 USB Always On CLKDIV6 HPI Always On CLKDIV6 VLYNQ Always On CLKDIV6 EMAC Always On CLKDIV6 ATA/CF Always On CLKDIV6 MMC/SD/SDIO Always On CLKDIV6 SPI Always On CLKDIV6 ASP Always On CLKDIV6 GPIO

DSP CLKDIV1 C64x+ CPU

Table 6-4. DM6443 Clock Domains

SUBSYSTEM

PLL1 – 27 MHz 594 MHz DSP 1:1 27 MHz 594 MHz ARM 1:2 13.5 MHz 297 MHz EDMA3/VPSS 1:3 9 MHz 198 MHz Peripherals 1:6 4.5 MHz 99 MHz

(1) These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 22.

FIXED RATIO vs.

PLL1

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PLL BYPASS PLL ENABLED

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CLOCK MODES (FREQUENCY)

(1)

DSP Subsystem

ARM Subsystem

SYSCLK1

SYSCLK2

SYSCLK5

SCR

EDMA3

VPFE

(Resizer Only)

VPBE

DACs

DDR2 PHY DDR2 VTP

DDR2 Mem Ctlr

PLLDIV1 (/10)

PLLDIV2 (/2)

BPDIV

PLL Controller 2

PLL Controller 1

PLLDIV3 (/3)

PLLDIV5 (/6)

PLLDIV2 (/2)

PLLDIV1 (/1)

SYSCLK3

Bypass Clock

UARTs (x3)

I2C

Timers (x3)

PWMs (x3)

ATA/CF

EMIF/NAND

EMAC

VLYNQ

MMC/SD

SPI

GPIO

ASP

ARM INTC

USB 2.0

USB PHY

60 MHz

24 MHz

27 MHz

VPBECLK

PLLDIV4 (/4)

HPI

TMS320DM6443

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

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Figure 6-6. PLL1 and PLL2 Clock Domain Block Diagram

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PLLDIV1 (/1)

PLLDIV2 (/2)

PLLDIV4 (/4)

PLLDIV3 (/3)

PLLDIV5 (/6)

SYSCLK1

SYSCLK2

SYSCLK4

SYSCLK3

SYSCLK5

Post−DIV

PLLM

PLL

BPDIV

CLKMODE

CLKIN

OSCIN

PLLEN

AUXCLK SYSCLKBP

PLLDIV1

PLLDIV2

Post−Div

(/1)

PLLM

PLL

BPDIV

CLKMODE

CLKIN

OSCIN

PLLEN

PLL2_SYSCLK1 (VPSS−VPBE)

PLL2_SYSCLK2 (DDR2 PHY)

PLL2_SYSCLKBP (DDR2 VTP)

TMS320DM6443

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For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-7 and Figure 6-8, respectively.

SPRS282G–DECEMBER 2005–REVISED AUGUST 2010

Figure 6-7. PLL1 Structure Block Diagram

Figure 6-8. PLL2 Structure Block Diagram

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6.3.1.4 Power and Sleep Controller (PSC) Module

The Power and Sleep Controller (PSC) controls DM6443 device power by turning off unused power domains or gating off clocks to individual peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, power domain control, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The GPSC controls all of DM6443’s LPSCs. The ARM subsystem does not have an LPSC module. ARM sleep mode is accomplished through the wait for interrupt instruction. The LPSCs for DM6443 are shown in Table 6-5. The PSC register memory map is given in Table 6-6. For more details on the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

Table 6-5. DM6443 LPSC Assignments

LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE

NUMBER NUMBER NUMBER

0 VPSS DMA 14 EMIFA 28 TIMER1 1 VPSS MMR 15 MMC/SD/SDIO 29 Reserved 2 EDMA3CC 16 Reserved 30 Reserved 3 EDMA3TC0 17 ASP 31 Reserved 4 EDMA3TC1 18 I2C 32 Reserved 5 EMAC 19 UART0 33 Reserved 6 EMAC Memory Controller 20 UART1 34 Reserved 7 MDIO 21 UART2 35 Reserved 8 Reserved 22 SPI 36 Reserved

9 USB 23 PWM0 37 Reserved 10 ATA/CF 24 PWM1 38 Reserved 11 VLYNQ 25 PWM2 39 C64x+ CPU 12 HPI 26 GPIO 40 Reserved 13 DDR2 Memory Controller 27 TIMER0

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Table 6-6. PSC Register Memory Map

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1000 PID Peripheral Revision and Class Information Register

0x01C4 1004 - 0x01C4 1014 - Reserved

0x01C4 1018 INTEVAL Interrupt Evaluation Register

0x01C4 101C - 0x01C4 103F - Reserved

0x01C4 1040 MERRPR0 Module Error Pending 0 (mod 0 - 31) Register 0x01C4 1044 MERRPR1 Module Error Pending 1 (mod 32- 63) Register

0x01C4 1048 - 0x01C4 104F - Reserved

0x01C4 1050 MERRCR0 Module Error Clear 0 (mod 0 - 31) Register 0x01C4 1054 MERRCR1 Module Error Clear 1 (mod 32 - 63) Register

0x01C4 1058 - 0x01C4 105F - Reserved

0x01C4 1060 PERRPR Power Error Pending Register

0x01C4 1064 - 0x01C4 1067 - Reserved

0x01C4 1068 PERRCR Power Error Clear Register

0x01C4 106C - 0x01C4 106F - Reserved

0x01C4 1070 EPCPR External Power Error Pending Register

0x01C4 1074 - 0x01C4 1077 - Reserved

0x01C4 1078 EPCCR External Power Control Clear Register

0x01C4 107C - 0x01C4 111F - Reserved

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Table 6-6. PSC Register Memory Map (continued)

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1120 PTCMD Power Domain Transition Command Register

0x01C4 1124 - 0x01C4 1127 - Reserved

0x01C4 1128 PTSTAT Power Domain Transition Status Register

0x01C4 112C - 0x01C4 11FF - Reserved

0x01C4 1200 PDSTAT0 Power Domain Status 0 Register (Always On) 0x01C4 1204 PDSTAT1 Power Domain Status 1 Register (DSP)

0x01C4 1208 - 0x01C4 12FF - Reserved

0x01C4 1300 PDCTL0 Power Domain Control 0 Register (Always On) 0x01C4 1304 PDCTL1 Power Domain Control 1 Register (DSP)

0x01C4 1308 - 0x01C4 17FF - Reserved

0x01C4 1800 MDSTAT0 Module Status 0 Register (VPSS DMA) 0x01C4 1804 MDSTAT1 Module Status 1 Register (VPSS MMR) 0x01C4 1808 MDSTAT2 Module Status 2 Register (EDMA3CC)

0x01C4 180C MDSTAT3 Module Status 3 Register (EDMA3TC0)

0x01C4 1810 MDSTAT4 Module Status 4 Register (EDMA3TC1) 0x01C4 1814 MDSTAT5 Module Status 5 Register (EMAC) 0x01C4 1818 MDSTAT6 Module Status 6 Register (EMAC Memory Controller)

0x01C4 181C MDSTAT7 Module Status 7 Register (MDIO)

0x01C4 1820 Reserved 0x01C4 1824 MDSTAT9 Module Status 9 Register (USB) 0x01C4 1828 MDSTAT10 Module Status 10 Register (ATA/CF)

0x01C4 182C MDSTAT11 Module Status 11 Register (VLYNQ)

0x01C4 1830 MDSTAT12 Module Status 12 Register (HPI) 0x01C4 1834 MDSTAT13 Module Status 13 Register (DDR2) 0x01C4 1838 MDSTAT14 Module Status 14 Register (EMIFA)

0x01C4 183C MDSTAT15 Module Status 15 Register (MMC/SD/SDIO)

0x01C4 1840 Reserved 0x01C4 1844 MDSTAT17 Module Status 17 Register (ASP) 0x01C4 1848 MDSTAT18 Module Status 18 Register (I2C)

0x01C4 184C MDSTAT19 Module Status 19 Register (UART0)

0x01C4 1850 MDSTAT20 Module Status 20 Register (UART1) 0x01C4 1854 MDSTAT21 Module Status 21 Register (UART2) 0x01C4 1858 MDSTAT22 Module Status 22 Register (SPI)

0x01C4 185C MDSTAT23 Module Status 23 Register (PWM0)

0x01C4 1860 MDSTAT24 Module Status 24 Register (PWM1) 0x01C4 1864 MDSTAT25 Module Status 25 Register (PWM2) 0x01C4 1868 MDSTAT26 Module Status 26 Register (GPIO)

0x01C4 186C MDSTAT27 Module Status 27 Register (TIMER0)

0x01C4 1870 MDSTAT28 Module Status 28 Register (TIMER1)

0x01C4 1874 - 0x01C4 189B - Reserved

0x01C4 189C MDSTAT39 Module Status 39 Register (C64x+ CPU)

0x01C4 18A0 MDSTAT40 Module Status 40 Register (Reserved)

0x01C4 18A4 - 0x01C4 19FF - Reserved

0x01C4 1A00 MDCTL0 Module Control 0 Register (VPSS DMA) 0x01C4 1A04 MDCTL1 Module Control 1 Register (VPSS MMR) 0x01C4 1A08 MDCTL2 Module Control 2 Register (EDMA3CC)

0x01C4 1A0C MDCTL3 Module Control 3 Register (EDMA3TC0)

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Table 6-6. PSC Register Memory Map (continued)

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1A10 MDCTL4 Module Control 4 Register (EDMA3TC1) 0x01C4 1A14 MDCTL5 Module Control 5 Register (EMAC) 0x01C4 1A18 MDCTL6 Module Control 6 Register (EMAC Memory Controller)

0x01C4 1A1C MDCTL7 Module Control 7 Register (MDIO)

0x01C4 1A20 Reserved 0x01C4 1A24 MDCTL9 Module Control 9 Register (USB) 0x01C4 1A28 MDCTL10 Module Control 10 Register (ATA/CF)

0x01C4 1A2C MDCTL11 Module Control 11 Register (VLYNQ)

0x01C4 1A30 MDCTL12 Module Control 12 Register (HPI) 0x01C4 1A34 MDCTL13 Module Control 13 Register (DDR2) 0x01C4 1A38 MDCTL14 Module Control 14 Register (EMIFA)

0x01C4 1A3C MDCTL15 Module Control 15 Register (MMC/SD/SDIO)

0x01C4 1A40 Reserved 0x01C4 1A44 MDCTL17 Module Control 17 Register (ASP) 0x01C4 1A48 MDCTL18 Module Control 18 Register (I2C)

0x01C4 1A4C MDCTL19 Module Control 19 Register (UART0)

0x01C4 1A50 MDCTL20 Module Control 20 Register (UART1) 0x01C4 1A54 MDCTL21 Module Control 21 Register (UART2) 0x01C4 1A58 MDCTL22 Module Control 22 Register (SPI)

0x01C4 1A5C MDCTL23 Module Control 23 Register (PWM0)

0x01C4 1A60 MDCTL24 Module Control 24 Register (PWM1) 0x01C4 1A64 MDCTL25 Module Control 25 Register (PWM2) 0x01C4 1A68 MDCTL26 Module Control 26 Register (GPIO)

0x01C4 1A6C MDCTL27 Module Control 27 Register (TIMER0)

0x01C4 1A70 MDCTL28 Module Control 28 Register (TIMER1)

0x01C4 1A74 - 0x01C4 1A9B - Reserved

0x01C4 1A9C MDCTL39 Module Control 39 Register (C64x+ CPU) 0x01C4 1AA0 MDCTL40 Module Control 40 Register (Reserved)

0x01C4 1AA4 - 0x01C4 1FFF - Reserved

0x01C4 1000 MPFAR Memory Protection Fault Address Register 0x01C4 1004 MPFSR Memory Protection Fault Status Register 0x01C4 1008 MPFCR Memory Protection Fault Command Register

0x01C4 100C MPAA Memory Protection Page Attribute Register

0x01C4 1010 - 0x01C4 1FFF - Reserved

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6.4 Reset

DM6443 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset, C64x+ local reset, and module reset are summarized in Table 6-7.

Table 6-7. DM6443 Resets

Type Initiator Description

Power-on-reset (POR) RESET pin active low while TRST is low. Global chip reset (Cold reset). Activates the POR signal

Warm reset RESET pin active low while TRST is high. Resets everything except for test and emulation logic.

Maximum reset Emulator, WD Timer Same as Warm reset, except for initiators. C64x+ Local reset Software (register bit) MMR controls the C64x+ reset input. This is used for

Power-on-reset (POR) is the global chip reset and it affects test, emulation, and other circuitry. It is invoked by driving the RESET pin active low while TRST is held low. A POR is required to place DM6443 into a known good initial state. POR can be asserted prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be asserted (held low) during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and if an external 27 MHz oscillator is used on the MXI/CLKIN pin, the external clock should also be running at the correct frequency.

on chip, which is used to reset test and emulation logic.

ARM emulator stays alive during warm reset, but the C64x+ emulator does not.

control of C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive when in local reset.

Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a C64x+ emulator session will not.

Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the maximum reset initiators can be masked by the ARM emulator.

System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test, emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets.

The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be accessible.

For details on reset control/status registers, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14)

For information on peripheral selection at the rising edge of RESET, see Section 3, Device Configurations, of this data manual.

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6.4.1 Reset Electrical Data/Timing

Table 6-8. Timing Requirements for Reset (see Figure 6-9)

NO. UNIT

1 t 2 t 3 t

w(RST) su(BOOT) h(BOOT)

Width of the RESET pulse 444 ns Setup time, boot configuration bits valid before RESET high 444 ns Hold time, boot configuration bits valid after RESET high 444 ns

Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 6-9)

NO. UNIT

26 t

d(PLL_LOCK)

4 t

d(RSTL-DDRZZ)

5 t

d(RSTL-DDRLL)

6 t

d(RSTL-DDRHH)

16 t

d(RSTL-DDRZHZ)

17 t

d(RSTL-DDRLHL)

7 t

d(RSTL-ZZ)

8 t

d(RSTL-LOWL)

9 t

d(RSTL-HIGHH)

18 t

d(RSTL-HIGHLOWH)

19 t

d(RSTL-LOWHIGHL)

24 t

d(RSTL-ZIZ)

10 t

d(RSTH-DDRZV)

11 t

d(RSTH-DDRLV)

12 t

d(RSTH-DDRHV)

20 t

d(RSTH-DDRZHV)

21 t

d(RSTH-DDRLHV)

13 t

d(RSTH-ZV)

14 t

d(RSTH-LOWV)

15 t

d(RSTH-HIGHV)

22 t

d(RSTH-HIGHLOWV)

23 t

d(RSTH-LOWHIGHV)

25 t

d(RSTH-ZIIV)

(1) P = MXI/CLKIN cycle time, in ns. (2) Following RESET high, this signal group maintains the state the pins(s) achieved while RESET was driven low until the peripheral is

enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low and remains in the high-impedance state following RESET high until the DDR2 controller is enabled via the PSC.

Delay time, PLL1 lock time 2000P ns Delay time, RESET low to DDR2 Z Group high impedance 0 2P + 20 ns Delay time, RESET low to DDR2 Low Group low 0 20 ns Delay time, RESET low to DDR2 High Group high 0 20 ns Delay time, RESET low to DDR2 Z/High Group high impedance 0 5P + 20 ns Delay time, RESET low to DDR2 Low/High Group low 0 20 ns Delay time, RESET low to Z Group high impedance 0 20 ns Delay time, RESET low to Low Group low 0 20 ns Delay time, RESET low to High Group high 0 20 ns Delay time, RESET low to High/Low Group high 0 20 ns Delay time, RESET low to Low/High Group low 0 20 ns Delay time, RESET low to Z/Invalid Group high impedance 0 20 ns Delay time, RESET high to DDR2 Z Group valid Delay time, RESET high to DDR2 Low Group valid Delay time, RESET high to DDR2 High Group valid Delay time, RESET high to DDR2 Z/High Group valid high 4000P ns Delay time, RESET high to DDR2 Low/High Group valid high 4000P ns Delay time, RESET high to Z Group valid Delay time, RESET high to Low Group valid Delay time, RESET high to High Group valid Delay time, RESET high to High/Low Group valid low 5100P ns Delay time, RESET high to Low/High Group valid high 5100P ns Delay time, RESET high to Z/Invalid Group invalid 4000P ns

-594

MIN MAX

(1)

-594

MIN MAX

(2) (2) (2)

ns ns ns

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Texas instruments TMS320DM6443 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

1.2 Description

1.3 Functional Block Diagram

Revision History

2 Device Overview

2.1 Device Characteristics

2.2 Device Compatibility

2.3 ARM Subsystem

2.3.1 ARM926EJ-S RISC CPU

2.3.2 CP15

2.3.3 MMU

2.3.4 Caches and Write Buffer

2.3.5 Tightly Coupled Memory (TCM)

2.3.6 Advanced High-Performance Bus (AHB)

2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

2.3.8 ARM Memory Mapping

2.3.8.1 ARM Internal Memories

2.3.8.2 External Memories

2.3.8.3 DSP Memories

2.3.8.4 ARM-DSP Integration

2.3.9 Peripherals

2.3.10 PLL Controller (PLLC)

2.3.11 Power and Sleep Controller (PSC)

2.3.12 ARM Interrupt Controller (AINTC)

2.3.13 System Module

2.3.14 Power Management

2.4 DSP Subsystem

2.4.1 C64x+ DSP CPU Description

2.4.2 DSP Memory Mapping

2.4.2.1 ARM Internal Memories

2.4.2.2 External Memories

2.4.2.3 DSP Internal Memories

2.4.2.4 C64x+ CPU

2.4.3 Peripherals

2.4.4 DSP Interrupt Controller

2.5 Memory Map Summary

2.6 Pin Assignments

2.6.1 Pin Map (Bottom View)

2.7 Terminal Functions

2.8 Device Support

2.8.1 Development Support

2.8.2 Device and Development-Support Tool Nomenclature

2.8.3 Documentation Support

2.8.3.1 Related Documentation From Texas Instruments

3 Device Configurations

3.1 System Module Registers

3.2 Power Considerations

3.2.1 Power Configurations at Reset

3.2.2 Power Configurations after Reset

3.3 Bootmode

3.3.1 Bootmode Registers

3.3.1.1 BOOTCFG Register Description

3.3.1.2 DSPBOOTADDR Register Description

3.3.2 ARM Boot

3.3.3 DSP Boot

3.3.3.1 Host-Boot Mode

3.3.3.2 Self-Boot Mode

3.4 Configurations at Reset

3.4.1 Device Configuration at Device Reset

3.4.2 Peripheral Selection at Device Reset

3.5 Configurations After Reset

3.5.1 Switched Central Resource (SCR) Bus Priorities

3.5.2 Multiplexed Pin Configurations

3.5.3 Peripheral Selection After Device Reset

3.5.4 PINMUX0 Register Description

3.5.5 PINMUX1 Register Description

3.5.6 Pin Multiplexing Register Field Details

3.5.6.1 EMAC and GPIO3V Pin Multiplexing

3.5.6.2 VPBE (LCD) and GPIO Pin Multiplexing

3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing

3.5.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

3.5.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing

3.5.6.6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing

3.5.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing

3.5.6.8 PWM, RGB888, and GPIO Pin Multiplexing