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TMS320DM643x
User Manual
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Texas Instruments TMS320DM643x User Manual

TMS320DM643x DMP
DSP Subsystem
Reference Guide
Literature Number: SPRU978E
March 2008
2 SPRU978E – March 2008
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Contents
1 Introduction ............................................................................................................. 11
1.1 Introduction ......................................................................................................... 12
1.2 Block Diagram ..................................................................................................... 12
1.3 DSP Subsystem in TMS320DM643x DMP .................................................................... 13
1.3.1 Components of the DSP Subsystem .................................................................. 13
2 TMS320C64x+ Megamodule ....................................................................................... 15
2.1 Introduction ......................................................................................................... 16
2.2 TMS320C64x+ CPU .............................................................................................. 16
2.3 Memory Controllers ............................................................................................... 18
2.3.1 L1P Controller ............................................................................................ 18
2.3.2 L1D Controller ............................................................................................ 20
2.3.3 L2 Controller .............................................................................................. 20
2.3.4 External Memory Controller (EMC) .................................................................... 21
2.3.5 Internal DMA (IDMA) ..................................................................................... 21
2.4 Internal Peripherals ............................................................................................... 22
2.4.1 Interrupt Controller (INTC) .............................................................................. 22
2.4.2 Power-Down Controller (PDC) .......................................................................... 22
2.4.3 Bandwidth Manager ...................................................................................... 23
3 System Memory ....................................................................................................... 25
3.1 Memory Map ....................................................................................................... 26
3.1.1 DSP Internal Memory (L1P, L1D, L2) ................................................................. 26
3.1.2 External Memory ......................................................................................... 26
3.1.3 Internal Peripherals ...................................................................................... 26
3.1.4 Device Peripherals ....................................................................................... 26
3.2 Memory Interfaces Overview .................................................................................... 27
3.2.1 DDR2 External Memory Interface ...................................................................... 27
3.2.2 External Memory Interface .............................................................................. 27
4 Device Clocking ....................................................................................................... 29
4.1 Overview ............................................................................................................ 30
4.2 Clock Domains ..................................................................................................... 30
4.2.1 Core Domains ............................................................................................ 30
4.2.2 Core Frequency Flexibility .............................................................................. 32
4.2.3 DDR2/EMIF Clock ........................................................................................ 33
4.2.4 I/O Domains ............................................................................................... 34
4.2.5 Video Processing Back End ............................................................................ 35
5 PLL Controller .......................................................................................................... 37
5.1 PLL Module ........................................................................................................ 38
5.2 PLL1 Control ....................................................................................................... 38
5.2.1 Device Clock Generation ................................................................................ 39
5.2.2 Steps for Changing PLL1/Core Domain Frequency ................................................. 39
5.3 PLL2 Control ....................................................................................................... 43
5.3.1 Device Clock Generation ................................................................................ 43
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5.3.2 Steps for Changing PLL2 Frequency .................................................................. 44
5.4 PLL Controller Registers ......................................................................................... 48
5.4.1 Peripheral ID Register (PID) ............................................................................ 49
5.4.2 Reset Type Status Register (RSTYPE) ............................................................... 49
5.4.3 PLL Control Register (PLLCTL) ........................................................................ 50
5.4.4 PLL Multiplier Control Register (PLLM) ............................................................... 51
5.4.5 PLL Controller Divider 1 Register (PLLDIV1) ......................................................... 51
5.4.6 PLL Controller Divider 2 Register (PLLDIV2) ......................................................... 52
5.4.7 PLL Controller Divider 3 Register (PLLDIV3) ......................................................... 52
5.4.8 Oscillator Divider 1 Register (OSCDIV1) .............................................................. 53
5.4.9 Bypass Divider Register (BPDIV) ...................................................................... 54
5.4.10 PLL Controller Command Register (PLLCMD) ...................................................... 55
5.4.11 PLL Controller Status Register (PLLSTAT) .......................................................... 55
5.4.12 PLL Controller Clock Align Control Register (ALNCTL) ............................................ 56
5.4.13 PLLDIV Ratio Change Status Register (DCHANGE) ............................................... 57
5.4.14 Clock Enable Control Register (CKEN) .............................................................. 58
5.4.15 Clock Status Register (CKSTAT) ..................................................................... 59
5.4.16 SYSCLK Status Register (SYSTAT) .................................................................. 60
6 Power and Sleep Controller ....................................................................................... 61
6.1 Introduction ......................................................................................................... 62
6.2 Power Domain and Module Topology .......................................................................... 63
6.3 Power Domain and Module States .............................................................................. 64
6.3.1 Power Domain States .................................................................................... 64
6.3.2 Module States ............................................................................................ 64
6.3.3 Local Reset ............................................................................................... 65
6.4 Executing State Transitions ...................................................................................... 65
6.4.1 Power Domain State Transitions ....................................................................... 65
6.4.2 Module State Transitions ................................................................................ 65
6.5 IcePick Emulation Support in the PSC ......................................................................... 66
6.6 PSC Interrupts ..................................................................................................... 66
6.6.1 Interrupt Events ........................................................................................... 66
6.6.2 Interrupt Registers ........................................................................................ 67
6.6.3 Interrupt Handling ........................................................................................ 68
6.7 PSC Registers ..................................................................................................... 68
6.7.1 Peripheral Revision and Class Information Register (PID) ......................................... 69
6.7.2 Interrupt Evaluation Register (INTEVAL) .............................................................. 69
6.7.3 Module Error Pending Register 1 (MERRPR1) ...................................................... 70
6.7.4 Module Error Clear Register 1 (MERRCR1) .......................................................... 70
6.7.5 Power Domain Transition Command Register (PTCMD) ........................................... 71
6.7.6 Power Domain Transition Status Register (PTSTAT) ............................................... 71
6.7.7 Power Domain Status 0 Register (PDSTAT0) ........................................................ 72
6.7.8 Power Domain Control 0 Register (PDCTL0) ........................................................ 73
6.7.9 Module Status n Register (MDSTATn) ................................................................ 74
6.7.10 Module Control n Register (MDCTLn) ................................................................ 75
7 Power Management .................................................................................................. 77
7.1 Overview ............................................................................................................ 78
7.2 PSC and PLLC Overview ........................................................................................ 78
7.3 Clock Management ............................................................................................... 79
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7.3.1 Module Clock ON/OFF .................................................................................. 79
7.3.2 Module Clock Frequency Scaling ...................................................................... 79
7.3.3 PLL Bypass and Power Down .......................................................................... 79
7.4 DSP Sleep Mode Management ................................................................................. 80
7.4.1 DSP Sleep Modes ........................................................................................ 80
7.4.2 DSP Module Clock ON/OFF ............................................................................ 80
7.5 3.3 V I/O Power Down ............................................................................................ 81
7.6 Video DAC Power Down ......................................................................................... 81
8 Interrupt Controller ................................................................................................... 83
9 System Module ........................................................................................................ 85
9.1 Overview ............................................................................................................ 86
9.2 Device Identification ............................................................................................... 86
9.3 Device Configuration .............................................................................................. 86
9.3.1 Pin Multiplexing Control ................................................................................. 86
9.3.2 Device Boot Configuration Status ...................................................................... 86
9.4 3.3 V I/O Power-Down Control .................................................................................. 87
9.5 Peripheral Status and Control ................................................................................... 87
9.5.1 Timer Control ............................................................................................. 87
9.5.2 VPSS Clock and DAC Control .......................................................................... 87
9.5.3 DDR2 VTP Control ....................................................................................... 87
9.5.4 HPI Control ................................................................................................ 87
9.6 Bandwidth Management .......................................................................................... 88
9.6.1 Bus Master DMA Priority Control ....................................................................... 88
9.6.2 EDMA Transfer Controller Configuration .............................................................. 89
9.7 Boot Control ........................................................................................................ 89
10 Reset ...................................................................................................................... 91
10.1 Overview ............................................................................................................ 92
10.2 Reset Pins .......................................................................................................... 92
10.3 Device Configurations at Reset ................................................................................. 92
10.4 DSP Reset ......................................................................................................... 93
10.4.1 DSP Local Reset ........................................................................................ 93
10.4.2 DSP Module Reset ...................................................................................... 93
11 Boot Modes ............................................................................................................. 95
A Revision History ....................................................................................................... 97
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List of Figures
1-1 TMS320DM643x DMP Block Diagram .................................................................................. 12
2-1 TMS320C64x+ Megamodule Block Diagram ........................................................................... 17
2-2 C64x+ Cache Memory Architecture ...................................................................................... 19
4-1 Overall Clocking Diagram ................................................................................................. 31
4-2 VPBE/DAC Clocking ....................................................................................................... 35
5-1 PLL1 Structure in the TMS320DM643x DMP .......................................................................... 39
5-2 PLL2 Structure in the TMS320DM643x DMP .......................................................................... 43
5-3 Peripheral ID Register (PID) .............................................................................................. 49
5-4 Reset Type Status Register (RSTYPE) ................................................................................. 49
5-5 PLL Control Register (PLLCTL) .......................................................................................... 50
5-6 PLL Multiplier Control Register (PLLM) ................................................................................. 51
5-7 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 51
5-8 PLL Controller Divider 2 Register (PLLDIV2) .......................................................................... 52
5-9 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 52
5-10 Oscillator Divider 1 Register (OSCDIV1) ................................................................................ 53
5-11 Bypass Divider Register (BPDIV) ........................................................................................ 54
5-12 PLL Controller Command Register (PLLCMD) ......................................................................... 55
5-13 PLL Controller Status Register (PLLSTAT) ............................................................................. 55
5-14 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 56
5-15 PLLDIV Ratio Change Status Register (DCHANGE) .................................................................. 57
5-16 Clock Enable Control Register (CKEN) ................................................................................. 58
5-17 Clock Status Register (CKSTAT) ........................................................................................ 59
5-18 SYSCLK Status Register (SYSTAT) ..................................................................................... 60
6-1 Power and Sleep Controller (PSC) Integration ......................................................................... 62
6-2 Peripheral Revision and Class Information Register (PID) ........................................................... 69
6-3 Interrupt Evaluation Register (INTEVAL) ................................................................................ 69
6-4 Module Error Pending Register 1 (MERRPR1) ........................................................................ 70
6-5 Module Error Clear Register 1 (MERRCR1) ............................................................................ 70
6-6 Power Domain Transition Command Register (PTCMD) ............................................................. 71
6-7 Power Domain Transition Status Register (PTSTAT) ................................................................. 71
6-8 Power Domain Status 0 Register (PDSTAT0) .......................................................................... 72
6-9 Power Domain Control 0 Register (PDCTL0) .......................................................................... 73
6-10 Module Status n Register (MDSTAT n) .................................................................................. 74
6-11 Module Control n Register (MDCTL n) ................................................................................... 75
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List of Tables
4-1 System Clock Modes and Fixed Ratios for Core Clock Domains.................................................... 30
4-2 Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) .................................................... 32
4-3 Example PLL2 Frequencies (Core Voltage = 1.2V) ................................................................... 33
4-4 Example PLL2 Frequencies (Core Voltage = 1.05V) .................................................................. 33
4-5 Peripheral I/O Domain Clock ............................................................................................. 34
4-6 Possible Clocking Modes.................................................................................................. 36
5-1 System PLLC1 Output Clocks ............................................................................................ 39
5-2 DDR PLLC2 Output Clocks ............................................................................................... 43
5-3 PLL and Reset Controller List ............................................................................................ 48
5-4 PLL and Reset Controller Registers ..................................................................................... 48
5-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 49
5-6 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 49
5-7 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 50
5-8 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 51
5-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 51
5-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 52
5-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 52
5-12 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions ......................................................... 53
5-13 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 54
5-14 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 55
5-15 PLL Controller Status Register (PLLSTAT) Field Descriptions ....................................................... 55
5-16 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................ 56
5-17 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 57
5-18 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 58
5-19 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 59
5-20 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 60
6-1 DM643x DMP Default Module Configuration ........................................................................... 63
6-2 Module States .............................................................................................................. 64
6-3 IcePick Emulation Commands ............................................................................................ 66
6-4 PSC Interrupt Events ...................................................................................................... 66
6-5 Power and Sleep Controller (PSC) Registers .......................................................................... 68
6-6 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 69
6-7 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 69
6-8 Module Error Pending Register 1 (MERRPR1) Field Descriptions .................................................. 70
6-9 Module Error Clear Register 1 (MERRCR1) Field Descriptions ..................................................... 70
6-10 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 71
6-11 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 71
6-12 Power Domain Status 0 Register (PDSTAT0) Field Descriptions ................................................... 72
6-13 Power Domain Control 0 Register (PDCTL0) Field Descriptions .................................................... 73
6-14 Module Status n Register (MDSTAT n) Field Descriptions ............................................................ 74
6-15 Module Control n Register (MDCTL n) Field Descriptions ............................................................. 75
7-1 Power Management Features ............................................................................................ 78
9-1 TMS320DM643x DMP Master IDs ....................................................................................... 88
9-2 TMS320DM643x DMP Default Master Priorities ....................................................................... 89
10-1 Reset Types ................................................................................................................. 92
A-1 Document Revision History ............................................................................................... 97
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List of Tables8 SPRU978E – March 2008
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About This Manual
This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRU983 — TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).

Preface

SPRU978E – March 2008
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SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
SPRU862 — TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.
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TMS320C6000, C6000 are trademarks of Texas Instruments.
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SPRU978E – March 2008

Introduction

Topic .................................................................................................. Page
1.1 Introduction .............................................................................. 12
1.2 Block Diagram .......................................................................... 12
1.3 DSP Subsystem in TMS320DM643x DMP ..................................... 13
Chapter 1
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JTAG Interface
System Control
PLLs/Clock Generator
Input
Clock(s)
Power/Sleep Controller
Pin Multiplexing
DSP Subsystem
C64x+t DSP CPU
32 KB
L1 Pgm
128 KB L2 RAM
80 KB
L1 Data
BT.656, Y/C, Raw (Bayer)
Video Processing Subsystem (VPSS)
CCD
Controller
Video
Interface
Front End
Resizer
Histogram/
3A
Preview
10b DAC
On-Screen
Display
(OSD)
Video
Encoder
(VENC)
10b DAC
10b DAC 10b DAC
Back End 8b BT.656,
Y/C, 24b RGB
NTSC/ PAL, S-Video, RGB, YPbPr
Switched Central Resource (SCR)
Peripherals
EDMA
I2C HECC UART
Serial Interfaces
DDR2
Mem Ctlr
(32b)
Async EMIF/
NAND/
(8b)
Program/Data Storage
Watchdog
Timer
PWM
System
General­Purpose
Timer
PCI
(33 MHz)
VLYNQ
EMAC
With
MDIO
Connectivity
HPI
McASP McBSP
OSC
Boot ROM
16b
GPIO
Introduction

1.1 Introduction

1.2 Block Diagram

The TMS320DM643x Digital Media Processor (DMP) contains a powerful DSP to efficiently handle image, video, and audio processing tasks. The DM643x DMP consists of the following primary components and sub-systems:
• DSP Subsystem (DSPSS), including the C64x+ Megamodule and associated memory.
• Video Processing Subsystem (VPSS), including the Video Processing Front End (VPFE) Subsystem,
Image Input and Image Processing Subsystem, and the Video Processing Back End (VPBE) Display Subsystem
• A set of I/O peripherals
• A powerful DMA subsystem and DDR2 memory controller interface
The DSP subsystem includes TI’s standard TMS320C64x+ Megamodule and several blocks of internal memory (L1P, L1D, and L2).
For more information, see the TMS320C64x+ DSP Megamodule Peripherals Reference Guide (SPRU871 ), the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732 ), and the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ).
An example block diagram for the TMS320DM643x DMP is shown in Figure 1-1 .
Figure 1-1. TMS320DM643x DMP Block Diagram
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1.3 DSP Subsystem in TMS320DM643x DMP

In the DM643x DMP, the DSP subsystem is responsible for performing digital signal processing for digital media applications. In addition, the DSP subsystem acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control.

1.3.1 Components of the DSP Subsystem

The DSP subsystem in the DM643x DMP consists of the following components:
• C64x+ Megamodule
• DSP Internal Memories
– Level-1 program memory (L1P) – Level-1 data memory (L1D) – Level-2 unified memory (L2)
The DSP also manages/controls all peripherals on the device. Refer to device-specific data manual for the full list of peripherals.
Figure 1-1 shows the functional block diagram of the DM643x DMP and how the DSP subsystem is
connected to the rest of the device. The DM643x DMP architecture uses the System Infrastructure (Switched Central Resource) to transfer data within the system.
Chapter 2 discusses the C64x+ Megamodule in more details, including its detailed block diagram.
DSP Subsystem in TMS320DM643x DMP
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SPRU978E – March 2008

TMS320C64x+ Megamodule

Topic .................................................................................................. Page
2.1 Introduction .............................................................................. 16
2.2 TMS320C64x+ CPU .................................................................... 16
2.3 Memory Controllers ................................................................... 18
2.4 Internal Peripherals ................................................................... 22
Chapter 2
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Introduction

2.1 Introduction

The C64x+ Megamodule (Figure 2-1 ) consists of the following components:
• TMS320C64x+ CPU
• Internal memory controllers:
– Level-1 program memory controller (L1P controller) – Level-1 data memory controller (L1D controller) – Level-2 unified memory controller (L2 controller) – External memory controller (EMC) – Internal direct memory access (IDMA) controller
• Internal peripherals – Interrupt controller (INTC)
– Power-down controller (PDC)

2.2 TMS320C64x+ CPU

The C64x+ Megamodule includes the C64x+ CPU. The C64x+ CPU is a member of the TMS320C6000™ generation of devices. The C6000™ devices execute up to eight 32-bit instructions per cycle. The CPU consists of 64 general-purpose 32-bit registers and eight functional units. The eight functional units contain two multipliers and six ALUs. For more information on the CPU, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732 ).
Features of the C6000 devices include:
• Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units – Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
– Allows designers to develop highly effective RISC-like code for rapid development time
• Instruction packing – Gives code-size equivalence for eight instructions that execute serially or in parallel
– Reduces code size, program fetches, and power consumption
• Conditional execution of most instructions – Reduces costly branching
– Increases parallelism for higher sustained performance
• Efficient code execution on independent functional units – Industry's most efficient C compiler on DSP benchmark suite
– Industry's first assembly optimizer for rapid development and improved parallelization
• 8/16/32-bit data support, providing efficient memory support for a variety of applications
• 40-bit arithmetic options add extra precision for vocoders and other computationally intensive
applications
• Saturation and normalization provide support for key arithmetic operations
• Field manipulation and instruction extract, set, clear, and bit counting support a common operation
found in control and data manipulation applications
The C64x+ devices include the following additional features:
• Each multiplier can perform two 16 × 16-bit or four 8 × 8-bit multiplies every clock cycle
• Quad 8-bit and dual 16-bit instruction set extensions with data flow support
• Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses
• Special communication-specific instructions to address common operations in error-correcting codes
• Bit count and rotate hardware extends support for bit-level algorithms
• Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code
size
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Cache control
Memory protect
Bandwidth mgmt
L1P
RAM/ cache
256
Bandwidth mgmt
Memory protect
Cache control
256
L2
256
RAM/
Cache
ROM
256
Instruction fetch
file A file B
C64x+ CPU
256
Cache control
Memory protect
Bandwidth mgmt
L1D
128 128
8 x 32
IDMA
256
256
128
256
Power down
Interrupt
controller
CFG
MDMA SDMA
EMC
256
32
Chip
registers
64 64
RAM/
cache
Register Register
System
infrastructure
• Protected mode operation: a two-level system of privileged program execution to support higher capability operating systems and system features, such as memory protection
• Exceptions support for error detection and program redirection to provide robust code execution
• Hardware support for modulo loop operation to reduce code size
• Industry's first assembly optimizer for rapid development and improved parallelization
Figure 2-1. TMS320C64x+ Megamodule Block Diagram
TMS320C64x+ CPU
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Memory Controllers

2.3 Memory Controllers

The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1D are configurable as part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory locations.
The following controllers manage RAM/cache configuration and cache data paths:
• L1P controller
• L1D controller
• L2 controller
• External memory controller (EMC)
The internal direct memory access (IDMA) controller manages DMA among the L1P, L1D, and L2 memories.
This section briefly describes the cache and DMA controllers. For detailed information about each of these controllers, see the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ).
Note: The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D,
and L2 memories are not part of the megamodule, even though they reside in the DSP subsystem. Thus, the physical memories are described separately because the C64x+ Megamodule supports a variety of memory configurations. Refer to Section 3.1 for more information on the L1P, L1D, and L2 memory configuration specific to the DM643x DMP.

2.3.1 L1P Controller

The L1P controller is the hardware interface between level 1 program memory (L1P memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1P controller responds to instruction fetch requests from the C64x+ CPU and manages transfer operations between L1P memory and the L2 controller and between L1P memory and the EMC.
Refer to the device-specific data manual for the amount of L1P memory on the device. The L1P controller has a register interface that allows you to configure part or all of the L1P RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1P is divided into two regions—denoted L1P region 0 and L1P region 1. This is the L1P architecture on the DM643x DMP:
• L1P region 0: Not populated with memory.
• L1P region 1: Populated with memory that can be configured as mapped memory or cache. The L1P
region 1 memory has 0 wait state. This region is shown as “L1P RAM/Cache” in the device-specific data manual.
The DM643x DMP does not support the L1P memory protection feature of the standard C64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L1P controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L1P controller and for a description of its control registers.
18 TMS320C64x+ Megamodule SPRU978E – March 2008
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C64x+ CPU
Fetch Path Data Path
Write
Buffer
L1D
Cache
L1D
SRAM
L1 Data
L1P
Cache
L1P
SRAM
L1 Program
L2 Cache
L2 SRAM
L2 Unified Data/Program Memory
External Memory
64 bit
256 bit
128 bit
256 bit
256 bit
2 x 64 bit
Legend:
addressable memory
cache memory
data paths managed by cache controller
256 bit
Figure 2-2. C64x+ Cache Memory Architecture
Memory Controllers
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Memory Controllers

2.3.2 L1D Controller

The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D controller responds to data requests from the C64x+ CPU and manages transfer operations between L1D memory and the L2 controller and between L1D memory and the EMC.
Refer to the device-specific data manual for the amount of L1D memory on the device. The L1D controller has a register interface that allows you to configure part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1D is divided into two regions—denoted L1D region 0 and L1D region 1. This is the L1D architecture on the DM643x DMP:
• L1D region 0: On some DM643x devices, this region is populated with mapped memory. If it is populated with memory, this region is shown as “L1D RAM” in the device-specific data manual.
• L1D region 1: Populated with memory that can be configured as mapped memory or cache. This region is shown as “L1D RAM/Cache” in the device-specific data manual.
The DM643x DMP does not support the L1D memory protection features of the standard C64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L1D controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L1D controller and for a description of its control registers.

2.3.3 L2 Controller

The L2 controller is the hardware interface between level 2 memory (L2 memory) and the other components in the C64x+ Megamodule (for example, L1P controller, L1D controller, and EMC). The L2 controller manages transfer operations between L2 memory and the other memory controllers (L1P controller, L1D controller, and EMC).
Refer to device-specific data manual for the amount of L2 memory on the device. The L2 controller has a register interface that allows you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 32 KB, 64 KB, or 128 KB of the RAM.
The L2 memory implements two separate memory ports. This is the L2 architecture on the DM643x DMP:
• Port 0 – Shown as “L2 RAM/Cache” in the device-specific data manual.
– Banking scheme: 2 × 128-bit banks – Latency: 1 cycle (0 wait state)
• Port 1 – Shown as “Boot ROM” in the device-specific data manual.
– Banking scheme: 1 × 256-bit bank – Latency: 1 cycle (0 wait state)
The DM643x DMP does not support the L2 memory protection feature of the standard C64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L2 controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L2 controller and for a description of its control registers.
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2.3.4 External Memory Controller (EMC)

The external memory controller (EMC) is the hardware interface between the external memory map (external memory and external registers) and the other controllers in the C64x+ Megamodule (for example, L1P controller, L1D controller, and L2 controller). The EMC manages transfer operations between external memory and registers and the other memory controllers (L1P controller, L1D controller, and EMC).
EMC does not support the memory protection feature of the standard C64x+ Megamodule. Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871 ) for more information on the EMC and for a description of its control registers.

2.3.5 Internal DMA (IDMA)

The internal DMA (IDMA) controller facilitates DMA transfers between any two internal memory-mapped locations. Internal memory-mapped locations include L1P, L1D, L2, and internal peripheral configuration registers.
Note: The IDMA cannot facilitate DMA to or from external memory-mapped locations. The EDMA
facilitates external DMA transfers. Refer to Section 3.1 and to the TMS320DM643x DMP Enhanced Direct Memory Access (EDMA) Controller User's Guide (SPRU987 ) for information on EDMA.
The IDMA controller enables the rapid paging of data sections to any local memory-mapped RAM. A key advantage of the IDMA is that it allows paging between slower L2 and faster L1D data memory. These transfers take place without CPU intervention and without cache stalls.
Another key advantage is that you can use the IDMA controller to program internal peripheral configuration registers without CPU intervention.
Refer to the internal DMA (IDMA) controller section in the TMS320C64x+ DSP Megamodule Reference
Guide (SPRU871 ) for more information on the IDMA controller and for a description of its control registers.
Memory Controllers
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Internal Peripherals

2.4 Internal Peripherals

This C64x+ Megamodule includes the following internal peripherals:
• Interrupt controller (INTC)
• Power-down controller (PDC)
This section briefly describes the INTC and PDC. For more information on these peripherals, see the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ).

2.4.1 Interrupt Controller (INTC)

The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC maps the 0 to 127 DSP device events to 12 CPU interrupts. Refer to device-specific data manual for a list of all the DSP device events. The interrupt controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) fully describes the INTC and how it maps the DSP device events to the 12 CPU interrupts.

2.4.2 Power-Down Controller (PDC)

The C64x+ Megamodule includes a power-down controller (PDC). The PDC can power-down all of the following components of the C64x+ Megamodule:
• C64x+ CPU
• L1P controller
• L1D controller
• L2 controller
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
The DM643x DMP does not support power-down of the internal memories of the DSP subsystem. The C64x+ Megamodule is capable of providing both dynamic and static power-down; however, only static
power-down is supported on the DM643x DMP. The TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) describes the power-down control in more detail.
• Static power-down: The PDC initiates power down of the entire C64x+ Megamodule and all internal memories immediately upon command from software.
On the DM643x DMP, static power-down affects all components of the C64x+ Megamodule. The DM643x DMP does not support power-down of the internal memories. Software can initiate static power-down via a register bit in the PDC register. For more information on the PDC, see the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ).
Note: The DM643x DMP does not support dynamic power-down.
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2.4.3 Bandwidth Manager

The bandwidth manager provides a programmable interface for optimizing bandwidth among the requesters for resources, which include the following:
• EDMA-initiated DMA transfers (and resulting coherency operations)
• IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
• CPU direct-initiated transfers
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of C64x+ Megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor (EDMA, IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The programmable priority level has a single meaning throughout the system. There are a total of nine priority levels, where priority zero is the highest priority and priority eight is the lowest priority. When requests for a single resource contend, access is granted to the highest-priority requestor. When the contention occurs for multiple successive cycles, a contention counter assures that the lower-priority requestor gets access to the resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1 represents a transfer whose priority has been increased due to expiration of the contention counter or a transfer that is fixed as the highest-priority transfer to a given resource.
Internal Peripherals
– Block based coherency operations – Global coherency operations
– Data access (load/store) – Program access
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SPRU978E – March 2008

System Memory

Topic .................................................................................................. Page
3.1 Memory Map ............................................................................. 26
3.2 Memory Interfaces Overview ...................................................... 27
Chapter 3
SPRU978E – March 2008 System Memory 25
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Memory Map

3.1 Memory Map

Refer to your device-specific data manual for memory-map information.

3.1.1 DSP Internal Memory (L1P, L1D, L2)

This section describes the configuration of the DSP internal memory in the DM643x DMP that consists of L1P, L1D, and L2. In the DM643x DMP:
• L1P memory: The L1P controller allows you to configure part or all of the L1P RAM as normal program RAM or as direct mapped cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
• L1D memory: The L1D controller allows you to configure part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
• L2 memory: The L2 controller allows you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 32 KB, 64 KB, or 128 KB of the RAM.
Refer to device-specific data manual for the exact amount of RAM/cache. Refer to TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for information on how to configure the cache.

3.1.2 External Memory

The DSP has access to the following external memories:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR/NAND Flash
The external memory controller (EMC) facilitates DSP access to these memories in the C64x+ Megamodule. The following external memories are accessible to the DSP:
• DDR2 port
• Asynchronous EMIF (for example, NOR and NAND Flash in 4 EM_CS regions)
For the memory-map locations of these external memories, refer to the memory-map section of the device-specific data manual.

3.1.3 Internal Peripherals

3.1.4 Device Peripherals

The following internal peripherals are accessible to the DSP:
• Power-down controller (PDC)
• Interrupt controller (INTC)
For more information on the internal peripherals, see the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ).
The DSP has access to all peripherals on the device. Refer to device-specific data manual for the full list of peripherals.
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3.2 Memory Interfaces Overview

This section describes the different memory interfaces of DM643x DMP. The DM643x DMP supports several memory and external device interfaces, including the following:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR/NAND Flash

3.2.1 DDR2 External Memory Interface

The DDR2 external memory interface (EMIF) port is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and can support either 16-bit or 32-bit interfaces.
DDR2 SDRAM plays a key role in a DM643x DMP-based system. Such a system is expected to require a significant amount of high-speed external memory for the following:
• Buffering input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the video processing front end (VPFE)
• Video processing back end (VPBE) display buffers
• Intermediate buffering for large raw Bayer data image files while performing still camera processing
functions
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable firmware for DSP

3.2.2 External Memory Interface

The DM643x DMP external memory interface (EMIF) provides an 8-bit data bus, an address bus width of up to 24-bits, and 4 dedicated chip selects, along with memory control signals. These signals are statically multiplexed between the asynchronous EMIF (EMIFA) module that provides asynchronous EMIF and NAND interfaces.
The EMIFA signals are multiplexed with other peripheral signals on the device. Refer to device-specific data manual for details on pin multiplexing.
Memory Interfaces Overview
3.2.2.1 Asynchronous EMIF Interface
The asynchronous EMIF (EMIFA) interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided. Each is individually configurable to provide either asynchronous EMIF or NAND support.
• The asynchronous EMIF mode supports asynchronous devices (RAM, ROM, and NOR Flash)
• 64MB asynchronous address range over 4 chip selects (16MB each)
• Supports 8-bit data bus width
• Programmable asynchronous cycle timings
• Supports extended waits
• Supports Select Strobe mode
• Supports TI DSP HPI interface
• Supports booting DM643x DMP from CS2 (SRAM/NOR Flash)
3.2.2.2 NAND Interface
The asynchronous EMIF (EMIFA) interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each is individually configurable to provide either EMIFA or NAND support.
• The NAND mode supports NAND Flash on up to 4 asynchronous chip selects
• Supports 8-bit data bus width
• Programmable cycle timings
• Performs ECC calculation
• Bootloader code in Boot ROM supports booting of the DM643x DMP from NAND-Flash located at CS2
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Device Clocking

Topic .................................................................................................. Page
4.1 Overview .................................................................................. 30
4.2 Clock Domains ......................................................................... 30
Chapter 4
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Overview

4.1 Overview

The DM643x DMP requires one primary reference clock. The primary reference clock can be either crystal input or driven by external oscillators. A 27 MHZ crystal at the MXI/CLKIN pin is recommended for the system PLLs, which generate the clocks for the DSP, peripherals, DMA, and imaging peripherals. The recommended 27 MHZ input enables you to use the video DACs to drive NTSC/PAL television signals at the proper frequencies.
For detailed specifications on clock frequency and voltage requirements, see the device-specific data manual.
There are two clocking modes:
• PLL Bypass Mode - power saving (device defaults to this mode)
• PLL Mode - PLL multiplies input clock up to the desired operating frequency
The clock of the major chip subsystems must be programmed to operate at fixed ratios of the primary system/DSP clock frequency within each mode, as shown in Table 4-1 . The DM643x DMP clocking architecture is shown in Figure 4-1 .
Table 4-1. System Clock Modes and Fixed Ratios for Core Clock Domains
Subsystem Core Clock Domain Fixed Ratio vs. DSP frequency
DSP CLKDIV1 1:1 EDMA CLKDIV3 1:3
VPSS Peripherals (CLKDIV3 domain) CLKDIV3 1:3 Peripherals (CLKDIV6 domain) CLKDIV6 1:6

4.2 Clock Domains

4.2.1 Core Domains

The core domains refer to the clock domains for all of the internal processing elements of the DM643x DMP, such as the DSP/EDMA/peripherals, etc. All internal communications between DSP and modules operate at core domain clock frequencies. All of the core clock domains are synchronous to each other, come from a single PLL (PLL1), have aligned clock edges, and have fixed divide by ratio requirements, as shown in Table 4-1 and Figure 4-1 . It is user's responsibility to ensure the fixed divide ratios between these core clock domains are achieved.
The DSP is in the CLKDIV1 domain and receives the PLL1 frequency directly (PLLDIV1 of PLL controller 1 (PLLC1) set to divide by 1), or receives the divided-down PLL1 frequency (PLLDIV1 of PLLC1 set to divide by 2, 3, etc.). The DSP has internal clock dividers that it uses to create the DSP ÷ 3 clock frequency to communicate with other components on-chip.
Modules in the CLKDIV3 domain (for example, EDMA, VPSS, CLKDIV3 domain peripherals) must run at 1/3 the DSP frequency.
Modules in the CLKDIV6 domain (for example, CLKDIV6 domain peripherals) must run at 1/6 the DSP frequency.
Modules in the CLKIN domain (for example, UART, Timer, I2C, PWM, HECC) run at the MXI/CLKIN frequency, asynchronous to the DSP. There is no fixed ratio requirement between these peripherals frequencies and the DSP frequency.
Refer to device-specific data manual for the core clock domain for each peripheral.
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