Texas Instruments TMS320DM643 User Manual
TMS320DM643x DMP
DDR2 Memory Controller
User's Guide
Literature Number: SPRU986B
November 2007
2 SPRU986B – November 2007
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Contents
Preface ............................................................................................................................... 6
1 Introduction ................................................................................................................ 7
1.1 Purpose of the Peripheral ....................................................................................... 7
1.2 Features ........................................................................................................... 7
1.3 Functional Block Diagram ....................................................................................... 8
1.4 Supported Use Case Statement ............................................................................... 8
1.5 Industry Standard(s) Compliance Statement ................................................................. 8
2 Peripheral Architecture ................................................................................................ 9
2.1 Clock Control ..................................................................................................... 9
2.2 Memory Map .................................................................................................... 10
2.3 Signal Descriptions ............................................................................................. 11
2.4 Protocol Description(s) ......................................................................................... 12
2.5 Memory Width and Byte Alignment .......................................................................... 20
2.6 Endianness Considerations ................................................................................... 21
2.7 Address Mapping ............................................................................................... 22
2.8 DDR2 Memory Controller Interface .......................................................................... 26
2.9 Refresh Scheduling ............................................................................................ 29
2.10 Self-Refresh Mode.............................................................................................. 29
2.11 Reset Considerations .......................................................................................... 30
2.12 VTP IO Buffer Calibration ..................................................................................... 31
2.13 Auto-Initialization Sequence ................................................................................... 31
2.14 Interrupt Support ................................................................................................ 34
2.15 DMA Event Support ............................................................................................ 34
2.16 Power Management ............................................................................................ 34
2.17 Emulation Considerations ..................................................................................... 35
3 Supported Use Cases ................................................................................................ 36
3.1 Connecting the DDR2 Memory Controller to DDR2 Memory ............................................. 36
3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification ............................. 36
4 DDR2 Memory Controller Registers ............................................................................. 40
4.1 SDRAM Status Register (SDRSTAT) ........................................................................ 41
4.2 SDRAM Bank Configuration Register (SDBCR) ............................................................ 42
4.3 SDRAM Refresh Control Register (SDRCR)................................................................ 44
4.4 SDRAM Timing Register (SDTIMR) .......................................................................... 45
4.5 SDRAM Timing Register 2 (SDTIMR2) ...................................................................... 46
4.6 Peripheral Bus Burst Priority Register (PBBPR) ........................................................... 47
4.7 Interrupt Raw Register (IRR) .................................................................................. 48
4.8 Interrupt Masked Register (IMR) ............................................................................. 49
4.9 Interrupt Mask Set Register (IMSR) .......................................................................... 50
4.10 Interrupt Mask Clear Register (IMCR) ....................................................................... 51
4.11 DDR PHY Control Register (DDRPHYCR) .................................................................. 52
4.12 VTP IO Control Register (VTPIOCR) ........................................................................ 53
4.13 DDR VTP Register (DDRVTPR) .............................................................................. 54
4.14 DDR VTP Enable Register (DDRVTPER) ................................................................... 54
Appendix A Revision History ............................................................................................. 55
SPRU986B – November 2007 Table of Contents 3
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List of Figures
1 Data Paths to DDR2 Memory Controller .................................................................................. 8
2 DDR2 Memory Controller Clock Block Diagram ......................................................................... 9
3 DDR2 Memory Controller Signals ........................................................................................ 11
4 Refresh Command ......................................................................................................... 13
5 DCAB Command ........................................................................................................... 14
6 DEAC Command ........................................................................................................... 15
7 ACTV Command ........................................................................................................... 16
8 DDR2 READ Command ................................................................................................... 17
9 DDR2 WRT Command .................................................................................................... 18
10 DDR2 MRS and EMRS Command ...................................................................................... 19
11 Byte Alignment .............................................................................................................. 20
12 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 24
13 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 25
14 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 26
15 DDR2 Memory Controller Reset Block Diagram ....................................................................... 30
16 DDR2 Memory Controller Power Sleep Controller Diagram .......................................................... 34
17 Connecting DDR2 Memory Controller for 32-Bit Connection ......................................................... 37
18 Connecting DDR2 Memory Controller for 16-Bit Connection ......................................................... 37
19 SDRAM Status Register (SDRSTAT).................................................................................... 41
20 SDRAM Bank Configuration Register (SDBCR) ....................................................................... 42
21 SDRAM Refresh Control Register (SDRCR) ........................................................................... 44
22 SDRAM Timing Register (SDTIMR) ..................................................................................... 45
23 SDRAM Timing Register 2 (SDTIMR2).................................................................................. 46
24 Peripheral Bus Burst Priority Register (PBBPR) ....................................................................... 47
25 Interrupt Raw Register (IRR) ............................................................................................. 48
26 Interrupt Masked Register (IMR) ......................................................................................... 49
27 Interrupt Mask Set Register (IMSR) ..................................................................................... 50
28 Interrupt Mask Clear Register (IMCR) ................................................................................... 51
29 DDR PHY Control Register (DDRPHYCR) ............................................................................. 52
30 VTP IO Control Register (VTPIOCR) .................................................................................... 53
31 DDR VTP Register (DDRVTPR) ......................................................................................... 54
32 DDR VTP Enable Register (DDRVTPER) .............................................................................. 54
4 List of Figures SPRU986B – November 2007
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List of Tables
1 PLLC2 Configuration ....................................................................................................... 10
2 DDR2 Memory Controller Signal Descriptions ......................................................................... 11
3 DDR2 SDRAM Commands ............................................................................................... 12
4 Truth Table for DDR2 SDRAM Commands ............................................................................ 12
5 Addressable Memory Ranges ............................................................................................ 20
6 16-Bit External Memory ................................................................................................... 21
7 32-Bit External Memory ................................................................................................... 21
8 Bank Configuration Register Fields for Address Mapping ............................................................ 22
9 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 23
10 Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM ................................................ 23
11 DDR2 Memory Controller FIFO Description ............................................................................ 26
12 Refresh Urgency Levels ................................................................................................... 29
13 Reset Sources .............................................................................................................. 30
14 DDR2 SDRAM Configuration by MRS Command ..................................................................... 32
15 DDR2 SDRAM Configuration by EMRS(1) Command ................................................................ 32
16 SDRAM Bank Configuration Register (SDBCR) Configuration ...................................................... 38
17 DDR2 Memory Refresh Specification ................................................................................... 38
18 SDRAM Refresh Control Register (SDRCR) Configuration .......................................................... 38
19 SDRAM Timing Register (SDTIMR) Configuration .................................................................... 39
20 SDRAM Timing Register 2 (SDTIMR2) Configuration ................................................................. 39
21 DDR PHY Control Register (DDRPHYCR) Configuration ............................................................ 40
22 DDR2 Memory Controller Registers Relative to Base Address 2000 0000h ....................................... 41
23 DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h ...................................... 41
24 DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h ...................................... 41
25 SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................. 41
26 SDRAM Bank Configuration Register (SDBCR) Field Descriptions ................................................. 42
27 SDRAM Refresh Control Register (SDRCR) Field Descriptions ..................................................... 44
28 SDRAM Timing Register (SDTIMR) Field Descriptions ............................................................... 45
29 SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ........................................................... 46
30 Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ................................................. 47
31 Interrupt Raw Register (IRR) Field Descriptions ....................................................................... 48
32 Interrupt Masked Register (IMR) Field Descriptions ................................................................... 49
33 Interrupt Mask Set Register (IMSR) Field Descriptions ............................................................... 50
34 Interrupt Mask Clear Register (IMCR) Field Descriptions ............................................................. 51
35 DDR PHY Control Register (DDRPHYCR) Field Descriptions ....................................................... 52
36 VTP IO Control Register (VTPIOCR) Field Descriptions .............................................................. 53
37 DDR VTP Register (DDRVTPR) Field Descriptions ................................................................... 54
38 DDR VTP Enable Register (DDRVTPER) Field Descriptions ........................................................ 54
A-1 Document Revision History ............................................................................................... 55
SPRU986B – November 2007 List of Tables 5
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About This Manual
This document describes the DDR2 memory controller in the TMS320DM643x Digital Media Processor
(DMP).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these
documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box
provided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRU978 — TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP).
Preface
SPRU986B – November 2007
Read This First
SPRU983 — TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
6 Preface SPRU986B – November 2007
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1 Introduction
This document describes the DDR2 memory controller in the TMS320DM643x Digital Media Processor
(DMP).
1.1 Purpose of the Peripheral
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories
are not supported. The DDR2 memory controller is the major memory location for program and data
storage.
1.2 Features
The DDR2 memory controller supports the following features:
• JESD79D-2A standard compliant DDR2 SDRAM
• 256 Mbyte memory space
• Data bus width of 32 or 16 bits (see the device-specific data manual for the mode(s) that are
supported)
• CAS latencies: 2, 3, 4, and 5
• Internal banks: 1, 2, 4, and 8
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM autoinitialization
• Self-refresh mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little-endian operating mode
User's Guide
SPRU986B – November 2007
DDR2 Memory Controller
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SCR
DDR2
memory
controller
BUS BUS
External
DDR2 SDRAM
DSP
Master
peripherals
EDMA
VPSS
Introduction
1.3 Functional Block Diagram
The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays the
general data paths to on-chip peripherals and external DDR2 SDRAM.
Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controller
through the switched central resource (SCR).
1.4 Supported Use Case Statement
The DDR2 memory controller supports JESD79D-2A DDR2-400 SDRAM memories utilizing either 32-bit
or 16-bit of the DDR2 memory controller data bus. See Section 3 for more details.
Figure 1. Data Paths to DDR2 Memory Controller
1.5 Industry Standard(s) Compliance Statement
The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the
exception of the following feature list:
• On Die Termination (ODT). The DDR2 memory controller does not include any on-die terminating
resistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled
by tying the ODT input pin of the DDR2 SDRAM to ground.
• Differential DQS. The DDR2 memory controller supports single ended DQS signals.
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2 Peripheral Architecture
DDR2
memory
controller
/2
PLLC2
/3
PLLC1
X2_CLKVCLK
DDR_CLK
DDR_CLK
PLL2_SYSCLK1
SYSCLK2
This section describes the architecture of the DDR2 memory controller as well as how it is structured and
how it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelessly
interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and
prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh
rate, CAS latency, and many SDRAM timing parameters. The following sections include details on how to
interface and properly configure the DDR2 memory controller to perform read and write operations to
externally-connected DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacing
the DDR2 memory controller to a common DDR2 SDRAM device.
2.1 Clock Control
The DDR2 memory controller receives two input clocks from internal clock sources, SYSCLK2 and
PLL2_SYSCLK1 (Figure 2 ). SYSCLK2 is a divided-down version of the DSP clock. PLL2_SYSCLK1
should be configured to clock at the frequency of the desired data rate, or stated similarly, it should
operate at twice the frequency of the desired DDR2 memory clock. DDR_CLK and DDR_CLK are the two
output clocks of the DDR2 memory controller providing the interface clock to the DDR2 SDRAM memory.
These two clocks operate at a frequency of PLL2_SYSCLK1/2.
2.1.1 Clock Source
SYSCLK2 and PLL2_SYSCLK1 are sourced from two independent PLLs (Figure 2 ). SYSCLK2 is sourced
from PLL controller 1 (PLLC1) and PLL2_SYSCLK1 is sourced from PLL controller 2 (PLLC2).
SYSCLK2 is clocked at a fixed divider ratio of PLL1. This divider is fixed at 3, meaning SYSCLK2 is
clocked at a frequency of PLL1/3. Once inside the DDR2 memory controller, this signal is called VCLK.
PLLC2 has a programmable divider that is used to divide-down the output clock of PLL2. This divider
should be configured such that PLLC2 supplies the PLL2_SYSCLK1 at the desired frequency. For
example, if a 150-MHZ DDR2 interface clock (DDR_CLK) is desired, then PLLC2 must be configured to
generate a 300-MHZ clock on PLL2_SYSCLK1. Once inside the DDR2 memory controller,
PLL2_SYSCLK1 is called X2_CLK.
Peripheral Architecture
Figure 2. DDR2 Memory Controller Clock Block Diagram
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Peripheral Architecture
2.1.2 Clock Configuration
The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider
ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1
shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in
Table 1 is derived by assuming a 27-MHZ reference clock. See the device-specific data manual for the
clock frequencies that are supported. See the TMS320DM643x DMP DSP Subsystem Reference Guide
(SPRU978 ) for information on the PLL controller.
Note: PLLC2 should be configured and a stable clock present on PLL2_SYSCLK1 before releasing
the DDR2 memory controller from reset.
Table 1. PLLC2 Configuration
PLL Multiplier PLL Frequency (MHZ) Divider Ratio X2_CLK Frequency (MHZ) DDR2 Clock Frequency (MHZ)
28 756 3 252 126
19 513 2 256.6 128.3
29 783 3 261 130.5
20 540 2 270 135
31 837 3 279 139.5
21 567 2 283.5 141.8
32 864 3 288 144
22 594 2 297 148.5
23 621 2 310 155.3
24 648 2 324 162
25 675 2 337.5 168.8
2.1.3 DDR2 Memory Controller Internal Clock Domains
There are two clock domains within the DDR2 memory controller. The two clock domains are driven by
VCLK and a divided-down by 2 version of X2_CLK called MCLK. The command FIFO, write FIFO, and
read FIFO described in Section 2.8 are all on the VCLK domain. From this, you can see that VCLK drives
the interface to the peripheral bus.
The MCLK domain consists of the DDR2 memory controller state machine and memory-mapped registers.
This clock domain is clocked at the rate of the external DDR2 memory, X2_CLK/2.
To conserve power within the DDR2 memory controller, VCLK, MCLK, and X2_CLK may be stopped. See
Section 2.16 for proper clock stop procedures.
2.2 Memory Map
See the device-specific data manual for information describing the device memory-map.
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DDR_D[31:0]
DDR2
memory
controller
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_DQS[3:0]
DDR_A[12:0]
DDR_ZN
DDR_ZP
200 Ω
200 Ω
Peripheral Architecture
2.3 Signal Descriptions
The DDR2 memory controller signals are shown in Figure 3 and described in Table 2 . The following
features are included:
• The maximum data bus is 32-bits wide.
• The address bus is 13-bits wide with an additional 3 bank address pins.
• Two differential output clocks driven by internal clock sources.
• Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
• One chip select signal and one clock enable signal.
Figure 3. DDR2 Memory Controller Signals
Table 2. DDR2 Memory Controller Signal Descriptions
Pin Type Description
DDR_CLK, O/Z Clock: Differential clock outputs.
DDR_CLK
DDR_CKE O/Z Clock enable: Active high.
DDR_CS O/Z Chip select: Active low.
DDR_WE O/Z Write enable strobe: Active low, command output.
DDR_RAS O/Z Row address strobe: Active low, command output.
DDR_CAS O/Z Column address strobe: Active low, command output.
DDR_DQM[3:0] O/Z Data mask: Output mask signal for write data.
DDR_DQS[3:0] I/O/Z Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0] O/Z Bank address: Output, defining which bank a given command is applied.
DDR_A[12:0] O/Z Address: Address bus.
DDR_D[31:0] I/O/Z Data: Bi-directional data bus. Input for read data, output for write data.
DDR_ZN, O Output impedance control: Required to set the DDR2 output impedance. Connected by way of
DDR_ZP a 200-ohm resistor to power and ground (see Figure 3 ). The resistor should be chosen to be
SPRU986B – November 2007 DDR2 Memory Controller 11
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4 times the desired impedance of the output buffer. By changing the size of the resistor, the
DDR2 outputs can be tuned to match the board load, if necessary.
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Peripheral Architecture
2.4 Protocol Description(s)
The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3 . Table 4 shows the
signal truth table for the DDR2 SDRAM commands.
Table 3. DDR2 SDRAM Commands
Command Function
ACTV Activates the selected bank and row.
DCAB Precharge all command. Deactivates (precharges) all banks.
DEAC Precharge single command. Deactivates (precharges) a single bank.
DESEL Device Deselect.
EMRS Extended Mode Register set. Allows altering the contents of the mode register.
MRS Mode register set. Allows altering the contents of the mode register.
NOP No operation.
Power Down Power down mode.
READ Inputs the starting column address and begins the read operation.
READ with Inputs the starting column address and begins the read operation. The read operation is followed by a
autoprecharge precharge.
REFR Autorefresh cycle.
SLFREFR Self-refresh mode.
WRT Inputs the starting column address and begins the write operation.
WRT with Inputs the starting column address and begins the write operation. The write operation is followed by a
autoprecharge precharge.
Table 4. Truth Table for DDR2 SDRAM Commands
DDR2
SDRAM: CKE CS RAS CAS WE BA[2:0] A[12:11, 9:0] A10
DDR2
memory
controller: DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_BA[2:0] DDR_A[12:11, 9:0] DDR_A[10]
Previous
Cycles Current Cycle
ACTV H H L L H H Bank Row Address
DCAB H H L L H L X X L
DEAC H H L L H L Bank X L
MRS H H L L L L BA OP Code
EMRS H H L L L L BA OP Code
READ H H L H L H BA Column Address L
READ with H H L H L H BA Column Address H
precharge
WRT H H L H L L BA Column Address L
WRT with H H L H L L BA Column Address L
precharge
REFR H H L L L H X X X
SLFREFR H L L L L H X X X
entry
SLFREFR L H H X X X X X X
exit
NOP H X L H H H X X X
DESEL H X H X X X X X X
Power Down H L H X X X X X X
entry
Power Down L H H X X X X X X
exit
L H H H X X X
L H H H X X X
L H H H X X X
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2.4.1 Refresh Mode
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]
DDR_BA[2:0]
DDR_DQM[3:0]
RFR
DDR_CLK
The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory (Figure 4 ). REFR
is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks
selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a
rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Page information
is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This
type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the
DDR2 memory controller. See Section 2.9 for more details on REFR command scheduling.
Peripheral Architecture
Figure 4. Refresh Command
SPRU986B – November 2007 DDR2 Memory Controller 13
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DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DCAB
DDR_A[10]
DDR_CAS
DDR_CLK
Peripheral Architecture
2.4.2 Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to
ensure the deactivation of all banks. Figure 5 shows the timing diagram for a DCAB command.
Figure 5. DCAB Command
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DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DEAC
DDR_A[10]
DDR_CAS
DDR_CLK
Peripheral Architecture
The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows
the timings diagram for a DEAC command.
Figure 6. DEAC Command
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DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
DDR_DQM[3:0]
ACTV
DDR_A[12:0]
DDR_CAS
BANK
ROW
DDR_CLK
Peripheral Architecture
2.4.3 Activation (ACTV)
The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to
a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or
writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects
the row. When the DDR2 memory controller issues an ACTV command, a delay of t
a read or write command is issued. Figure 7 shows an example of an ACTV command. Reads or writes to
the currently active row and bank of memory can achieve much higher throughput than reads or writes to
random areas because every time a new row is accessed, the ACTV command must be issued and a
delay of t
is incurred before
RCD
incurred.
RCD
Figure 7. ACTV Command
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2.4.4 READ Command
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[12:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BA[2:0]
CAS Latency
D0 D1 D2 D3 D4 D5 D6 D7
DDR_CLK
Peripheral Architecture
Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ
command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives
low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank
address is driven on DDR_BA[2:0].
The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or
5. The CAS latency is three cycles in Figure 8 . Read latency is equal to CAS latency plus additive latency.
The DDR2 memory controller always configures the memory to have an additive latency of 0, so read
latency equals CAS latency. Since the default burst size is 8, the DDR2 memory controller returns 8
pieces of data for every read command. If additional accesses are not pending to the DDR2 memory
controller, the read burst completes and the unneeded data is disregarded. If additional accesses are
pending, depending on the scheduling result, the DDR2 memory controller can terminate the read burst
and start a new read burst. Furthermore, the DDR2 memory controller does not issue a DAB/DEAC
command until page information becomes invalid.
Figure 8. DDR2 READ Command
SPRU986B – November 2007 DDR2 Memory Controller 17
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