Texas instruments TMS320DM368 User Manual

TMS320DM368

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SPRS668B–APRIL 2010–REVISED NOVEMBER 2010

TMS320DM368

Digital Media System-on-Chip (DMSoC)

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1 TMS320DM368 Digital Media System-on-Chip (DMSoC)

1.1 Features

• Highlights – High-Performance Digital Media

System-on-Chip (DMSoC) – Support for 32-Bit and 16-Bit – 432-MHz ARM926EJ-S Clock Rate – Two Video Image Co-processors

(HDVICP, MJCP) Engines – Supports a Range of Encode, Decode, and

Video Quality Operations – Embedded ICE-RT Logic for Real-Time – Video Processing Subsystem

• HW Face Detect Engine

• Resize Engine from 1/16x to 8x

• 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz – 32K-Byte RAM

• 4:2:2 (8-/16-bit) Interface – 16K-Byte ROM

• 8-/16-bit YCC and Up to 24-Bit RGB888 – Little Endian Digital Output

• 3 DACs for HD Analog Video Output (HDVICP, MJCP) Engines

• Hardware On-Screen Display (OSD) – Support a Range of Encode and Decode

– Capable of 1080p 30fps H.264 video

processing – H.264, MPEG4, MPEG2, MJPEG, JPEG,

– Peripherals include EMAC, USB 2.0 OTG,

DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Video Processing Subsystem MMC/SD/SDIO, Key Scan

– 8 Different Boot Modes and Configurable

Power-Saving Modes

– Pin-to-pin and software compatible with

DM365

– Extended temperature (-40ºC – 85ºC)

available – 3.3-V and 1.8-V I/O, 1.35-V Core – 338-Pin Ball Grid Array at 65nm Process

Technology

• High-Performance Digital Media System-on-Chip (DMSoC)

– 432-MHz ARM926EJ-S Clock Rate – 4:2:2 (8-/16-Bit) Interface – Capable of 1080p 30fps H.264 video

processing – Pin compatible with DM365 processors – Fully Software-Compatible With ARM9™ – Extended temperature available for 432-Mhz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

device

• ARM926EJ-S™ Core

(Thumb® Mode) Instruction Sets

– DSP Instruction Extensions and Single Cycle

MAC

– ARM® Jazelle® Technology

Debug

• ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache

• Two Video Image Co-processors

Operations

WMV9/VC1

– Front End Provides:

• HW Face Detect Engine

• Hardware IPIPE for Real-Time Image Processing

– Resize Engine

– Resize Images From 1/16x to 8x – Separate Horizontal/Vertical

Control

– Two Simultaneous Output Paths

• IPIPE Interface (IPIPEIF)

• Image Sensor Interface (ISIF) and CMOS Imager Interface

• 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz

• Glueless Interface to Common Video Decoders

• BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface

• Histogram Module

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• Lens distortion correction module (LDC) configurable as two 32-bit timers)

– Back End Provides: • One 64-Bit Watch Dog Timer

• Hardware On-Screen Display (OSD) • Two UARTs (One fast UART with RTS and CTS

• Composite NTSC/PAL video encoder

Flow Control)

output • Five Serial Port Interfaces (SPI) each with two

• 8-/16-bit YCC and Up to 24-Bit RGB888

Chip-Selects

Digital Output • One Master/Slave Inter-Integrated Circuit

• 3 DACs for HD Analog Video Output

• LCD Controller

• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface

• Analog-to-Digital Convertor (ADC)

• Power Management and Real Time Clock

(I2C) Bus™

• One Multi-Channel Buffered Serial Port (McBSP)

– I2S – AC97 Audio Codec Interface – S/PDIF via Software

Subsystem (PRTCSS) – Standard Voice Codec Interface (AIC12) – Real Time Clock – SPI Protocol (Master Mode Only)

• 16-Bit Host-Port Interface (HPI) – Direct Interface to T1/E1 Framers

• 10/100 Mb/s Ethernet Media Access Controller – Time Division Multiplexed Mode (TDM) (EMAC) - Digital Media

– IEEE 802.3 Compliant – Supports Media Independent Interface (MII) – Management Data I/O (MDIO) Module

– 128 Channel Mode

• Four Pulse Width Modulator (PWM) Outputs

• Four RTO (Real Time Out) Outputs

• Up to 104 General-Purpose I/O (GPIO) Pins

• Key Scan (Multiplexed with Other Device Functions)

• Voice Codec • Boot Modes

• External Memory Interfaces (EMIFs) – On-Chip ARM ROM Bootloader (RBL) to Boot – DDR2 and mDDR SDRAM 16-bit wide EMIF

With 256 MByte Address Space (1.8-V I/O)

– Asynchronous16-/8-bit Wide EMIF (AEMIF)

• Flash Memory Interfaces – NAND (8-/16-bit Wide Data) – 16 MB NOR Flash, SRAM – OneNAND(16-bit Wide Data)

• Flash Card Interfaces – Two Multimedia Card (MMC) / Secure Digital

(SD/SDIO)

– SmartMedia/xD

• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)

• USB Port with Integrated 2.0 High-Speed PHY that Supports

– USB 2.0 High-Speed Device – USB 2.0 High-Speed Host (mini-host,

supporting one external device)

– USB On The Go (HS-USB OTG)

• Four 64-Bit General-Purpose Timers (each

From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI

– AEMIF (NOR and OneNAND)

• Configurable Power-Saving Modes

• Crystal or External Clock Input (typically

19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)

• Flexible PLL Clock Generators

• Debug Interface Support – IEEE-1149.1 (JTAG™)

Boundary-Scan-Compatible

– ETB (Embedded Trace Buffer) with 4K-Bytes

Trace Buffer memory

– Device Revision ID Readable by ARM

• 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch

• 65nm Process Technology

• 3.3-V and 1.8-V I/O, 1.35-V Internal

• Community Resources – TI E2E Community – TI Embedded Processors Wiki

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1.2 Description

Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI).

The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368.

Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

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Lens Dist

Face Det

IPIPE

Resizer

ISIF

Video FE

3Ch

DAC

Video

Encoder

OSD

Video BE

Buffer

SDTV/HDTV

Analog Video

Digital

RGB/YUV

Camera

AFE

VPSS

DDR2

Controller

EDMA

NAND/SM

Memory

I/F

HPI

16-Bit DDR2/ mDDR

NAND/

OneNAND/

NOR Flash,

SmartMedia/

Host CPU

16 Bit

8/16 Bit

16 Bit

USB2.0 HS w/OTG

MMC/SD (x2)

SPI (x5)

UART (x2)

I2C

Timer (x4-64b)

WDT (x1-64b)

GIO

PWM (x4)

RTO McBSP EMAC

ADC

Key Scan

Voice Codec

System

I/O

Interface

I-Cache

16 KB

D-Cache

8 KB

RAM

32 KB

ROM

16 KB

ARM926EJ-S

ARM INTC

PRTCSS

CLOCK Ctrl

PLL

JTAG

I/F

HDVICP MJCP

DMA/Data and Configuration Bus

19.2 MHz, 24 MHz

27 MHz or 36 MHz

32.768 kHz

PMIC/

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320DM368 device.

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Figure 1-1. Functional Block Diagram

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1 TMS320DM368 Digital Media System-on-Chip 6 Peripheral Information and Electrical

(DMSoC) ................................................... 1 Specifications .......................................... 76

1.1 Features .............................................. 1

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 4

Revision History (Revision B) ............................. 6

2 Device Overview ........................................ 7

2.1 Device Characteristics ............................... 7

2.2 Device Compatibility ................................. 8

2.3 ARM Subsystem Overview .......................... 8

2.4 System Control Module ............................. 12

2.5 Power Management ................................ 13

2.6 Memory Map Summary ............................. 14

2.7 Pin Assignments .................................... 16

2.8 Terminal Functions ................................. 21

2.9 Device Support ..................................... 46

3 Device Configurations ................................ 50

3.1 System Module Registers .......................... 50

3.2 Boot Modes ......................................... 51

3.3 Device Clocking .................................... 54

3.4 Power and Sleep Controller (PSC) ................. 61

3.5 Pin Multiplexing ..................................... 63

3.6 Device Reset ....................................... 64

3.7 Default Device Configurations ...................... 64

3.8 Debugging Considerations ......................... 69

4 System Interconnect .................................. 70

5 Device Operating Conditions ....................... 71

5.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(Unless Otherwise Noted) ................................. 71

5.2 Recommended Operating Conditions .............. 72

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless

Otherwise Noted) ................................... 74

6.1 Parameter Information Device-Specific Information

...................................................... 76

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 77

6.3 Power Supplies ..................................... 77

6.4 Power-Supply Sequencing ......................... 78

6.5 Reset ............................................... 80

6.6 Oscillators and Clocks .............................. 81

6.7 Power Management and Real Time Clock

Subsystem (PRTCSS) .............................. 85

6.8 General-Purpose Input/Output (GPIO) ............. 87

6.9 EDMA Controller .................................... 89

6.10 External Memory Interface (EMIF) ................. 99

6.11 MMC/SD ........................................... 120

6.12 Video Processing Subsystem (VPSS) Overview

..................................................... 123

6.13 USB 2.0 ........................................... 147

6.14 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 155

6.15 Serial Port Interface (SPI) ......................... 157

6.16 Inter-Integrated Circuit (I2C) ...................... 167

6.17 Multi-Channel Buffered Serial Port (McBSP) ..... 170

6.18 Timer .............................................. 179

6.19 Pulse Width Modulator (PWM) .................... 181

6.20 Real Time Out (RTO) ............................. 183

6.21 Ethernet Media Access Controller (EMAC) ....... 185

6.22 Management Data Input/Output (MDIO) .......... 191

6.23 Host-Port Interface (HPI) Peripheral .............. 193

6.24 Key Scan .......................................... 197

6.25 Analog-to-Digital Converter (ADC) ................ 199

6.26 Voice Codec ....................................... 199

6.27 IEEE 1149.1 JTAG ................................ 201

7 Mechanical Data ...................................... 204

7.1 Thermal Data for ZCE ............................. 204

7.2 Packaging Information ............................ 204

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NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

highlights the technical changes made to the SPRS668A device-specific data sheet to make it an SPRS668B revision.

See Additions/Changes/Deletions

Table 6-23 Updated table note.

Table 6-96 Corrected hold time for t Section 6.7 Added last 3 bullets. Section 6.8 Changed second bullet.

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Revision History

Revision B Updates

h(MDCLKH-MDIO)

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2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,

including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES DEVICE

DDR2 / mDDR Memory Controller DDR2 / mDDR (16-bit bus width) Asynchronous EMIF (AEMIF)

Flash Card Interfaces

EDMA

Timers configurable as two separate 32-bit timers)

UART Two (one with RTS and CTS flow control)

Peripherals Not all peripherals pins are

available at the same time (For more detail, see the Device Configuration section).

On-Chip CPU Memory Organization 16-KB I-cache, 8-KB D-cache, 32-KB RAM,

JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) CPU Frequency (Maximum) MHz ARM: 432-MHz

Voltage

PLL Options BGA Package 13 x 13 mm 338-Pin BGA (ZCE)

Process Technology 65 nm

SPI Five (each supports two slave devices) I2C One (Master/Slave) 10/100 Ethernet MAC with Management Data I/O One Multi-Channel Buffered Serial Port [McBSP] One McBSP Power Management and Real Time Clock Subsystem

(PRTCSS) Key Scan 4 x 4 Matrix, 5 x 3 Matrix Voice Codec One Analog-to-Digital Converter (ADC) 6-channel, 10-bit Interface General-Purpose Input/Output Port Up to 104 Pulse width modulator (PWM) Four outputs

Configurable Video Ports

USB 2.0 High Speed Host

Wireless Interfaces Through SDIO RTO Four Channels

Core (V) 1.35 V I/O (V) 3.3 V, 1.8 V Reference frequency options 19.2 MHz, 24 MHz, 27 MHz, 36 MHz

Configurable PLL controller PLL bypass, programmable PLL

Asynchronous (8/16-bit bus width) RAM,

Flash (NOR, NAND, OneNAND)

Two MMC/SD

One SmartMedia/xD

64 independent DMA channels

Eight QDMA channels

Four 64-Bit General Purpose (each

One 64-Bit Watch Dog

RTC (32.768kHz), GPIO

One Input (VPFE)

One Output (VPBE)

High Speed Device

On The Go (HS-USB-OTG)

ARM

16-KB ROM

See Section 6.27.1, JTAG Register

Description(s)

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Table 2-1. Characteristics of the Processor (continued)

HARDWARE FEATURES DEVICE

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

Product Preview (PP), Advance Information (AI), PD or Production Data (PD)

2.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

2.3 ARM Subsystem Overview

The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall device system, including the components of the ARM Subsystem, the peripherals, and the external memories.

The ARM is responsible for handling system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, interface and control of the subsystem, etc. The ARM is master and performs these functions because it has a large program memory space and fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose control tasks.

2.3.1 Components of the ARM Subsystem

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The ARM Subsystem consists of the following components:

• ARM926EJ-S RISC processor, including: – coprocessor 15 (CP15) – MMU – 16KB Instruction cache – 8KB Data cache – Write Buffer – Java accelerator

• ARM Internal Memories – 32KB Internal RAM (32-bit wide access) – 16KB Internal ROM (ARM bootloader for non-AEMIF boot modes)

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• System Control Peripherals – ARM Interrupt Controller – PLL Controller – Power and Sleep Controller – System Control Module

The ARM also manages/controls all the device peripherals.

Figure 2-1 shows the functional block diagram of the ARM Subsystem.

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ARM926EJ-S

16KI$

8KD$ MMU

CP15

Arbiter Arbiter

I-AHB D-AHB

Master

DMA Bus

I-TCM

D-TCM

16K

RAM0

RAM1

16K

ROM

16K

Arbiter

Slave

MasterIF

CFGBus

ARM

Interrupt

Controller

(AINTC)

Control

System

PLLC2

PLLC1

(PSC)

Controller

Sleep

Power

Peripherals

...

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2.3.2 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data Caches

• Write buffer

• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com

Figure 2-1. ARM Subsystem Block Diagram

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2.3.3 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

2.3.4 MMU

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux, WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

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2.3.5 Caches and Write Buffer

The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables.

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.6 Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt

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Vector table. ARM internal ROM boot modes include NAND, MMC/SD, UART, USB, SPI, EMAC, and HPI. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks.

2.3.7 Advanced High-performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the configuration bus and the external memories bus.

2.3.8 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

2.3.9 ARM Memory Mapping

The ARM memory map is shown in Table 2-3 and Table 2-4. This section describes the memories and interfaces within the ARM's memory map.

2.3.9.1 ARM Internal Memories

The ARM has access to the following ARM internal memories:

• 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions.

• 16KB ARM Internal ROM

2.3.9.2 External Memories

The ARM has access to the following External memories:

• DDR2 / mDDR Synchronous DRAM

• Asynchronous EMIF / OneNAND / NOR

• NAND Flash

• Flash card devices: – MMC/SD

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– xD – SmartMedia

2.3.10 Peripherals

The ARM has access to all of the peripherals on the device.

2.3.11 ARM Interrupt Controller (AINTC)

The device ARM Interrupt Controller (AINTC) has the following features:

• Supports up to 64 interrupt channels (16 external channels)

• Interrupt mask for each channel

• Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt.

• Hardware prioritization of simultaneous interrupts

• Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)

• Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time

The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a software dispatcher to determine the asserted interrupt.

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2.4 System Control Module

The system control module is a system-level module containing status and top-level control logic required by the device. The system control module consists of a miscellaneous set of status and control registers, accessible by the ARM and supporting all of the following system features and operations:

• Device identification

• Device configuration – Pin multiplexing control – Device boot configuration status

• ARM interrupt and EDMA event multiplexing control

• Special peripheral status and control – Timer64 – USB PHY control – VPSS clock and video DAC control and status – DDR VTP control – Clockout circuitry – GIO de-bounce control

• Power management – Deep sleep

• Bandwidth Management – Bus master DMA priority control For more information on the System Control Module refer to Section 3, Device Configurations and the

TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).

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2.5 Power Management

The device is designed for minimal power consumption. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed. Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required time-line or to run at a clock setting until the work is complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be performed. Leakage power is due to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be avoided by removing power completely from a device or subsystem. The device includes several power management modes which are briefly described in

Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5) for more information on power management.

Table 2-2. Power Management Conditions

POWER MGMT. OTHER DDR

APPLICATION PRTCSS PERIPH. CLOCK/ DESCRIPTION

SCENARIO CLOCKS MODE

PRTCSS Active Off Off Off Off Off Off Off Off

Deep Sleep Mode

Standby Active On On Off On Off Off "Self- device. Clocks are

Low-power Bypass timers. Since ARM will (PLL Bypass Mode) Mode not have access to

System Running (PLL Mode)

(1)

Active On Off Off Off Off Off "Self- for PRTCSS and core

Active On On On On / Off On / Off On / Off "Self-

Active On On PLL Mode On On / Off On / Off On / Off Clock / This condition

CORE OSC. PLL ARM926 UART, PWM,

POWER POWER CNTRLR. CLOCK I2C TIMER

Bypass Mode (not Active)

Bypass Mode

(1) For more details, see TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5)

GIO, SPI,

CLOCKS CLOCKS

This condition consumes the lowest possible power, except for the PRTCSS.

This mode consumes Suspend / possible power, except Refresh" power, where only the

Suspend / in order to wake up the Refresh" suspended except for

Suspend / Refresh"

Nominal system PLLs, are on. Operation conserves the least

the second lowest

deep sleep circuit is on

in this mode.

This condition keeps

the minimum possible

modules powered-on

GIO (interrupts),

UART, and I2C (in

slave mode).

Most clocks are

suspended, except for

ARM, GIO, UART,

SPI, I2C, PWM, and

DDR, its internal

Cache will be either

frozen or not

accessed.

The device, including

amount of power.

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2.6 Memory Map Summary

Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of

the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. The bus masters are the ARM, EDMA, EMAC, USB, HPI, MJCP, HDVICP and VPSS. The Master Peripherals are EMAC, USB, and HPI. Please refer to Section 4 for more details.

Table 2-3. Memory Map

Start Address End Address Size (Bytes) ARM EDMA Master Periph VPSS

0x0000 0000 0x0000 3FFF 16K ARM RAM0

0x0000 4000 0x0000 7FFF 16K ARM RAM1

0x0000 8000 0x0000 BFFF 16K ARM ROM

0x0000 C000 0x0000 FFFF 16K Reserved 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0001 8000 0x0001 BFFF 16K ARM ROM ARM ROM ARM ROM 0x0001 C000 0x000F FFFF 912K Reserved

0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K

0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus CFG Bus

0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data)

0x0A00 0000 0x11EF FFFF 127M - 16K Reserved Reserved

0x11F0 0000 0x11F1 FFFF 128K MJCP DMA Port MJCP DMA Port

0x11F2 0000 0x11FF FFFF 896K Reserved Reserved

0x1200 0000 0x1207 FFFF 512K HDVICP DMA Port1 HDVICP DMA Port1 HDVICP

0x1208 0000 0x120F FFFF 512K Reserved HDVICP DMA Port2 Reserved

0x1210 0000 0x1217 FFFF 512K HDVICP DMA Port3

0x1218 0000 0x1FFF FFFF 222.5M Reserved

0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control

0x2000 8000 0x41FF FFFF 544M-32K

0x4200 0000 0x49FF FFFF 128M Reserved Reserved

0x4A00 0000 0x7FFF FFFF 864M

0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF

0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved

Mem Map Mem Map Mem Map Mem Map

(Instruction)

Peripherals Peripherals Peripherals

Regs Regs

Reserved Reserved

DMA Port1

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Table 2-4. ARM Configuration Bus Access to Peripherals

Address

Region Start End Size

EDMA CC 0x01C0 0000 0x01C0 FFFF 64K EDMA TC0 0x01C1 0000 0x01C1 03FF 1K EDMA TC1 0x01C1 0400 0x01C1 07FF 1K EDMA TC2 0x01C1 0800 0x01C1 0BFF 1K EDMA TC3 0x01C1 0C00 0x01C1 0FFF 1K

Reserved 0x01C1 1000 0x01C1 FFFF 60 K

UART0 0x01C2 0000 0x01C2 03FF 1K

Reserved 0x01C2 0400 0x01 20 7FFF 1K

Timer 3 0x01C2 0800 0x01C2 0BFF 1K

Real-time out 0x01C2 0C00 0x01C2 0FFF 1K

I2C 0x01C2 1000 0x01C2 13FF 1K Timer 0 0x01C2 1400 0x01C2 17FF 1K Timer 1 0x01C2 1800 0x01C2 1BFF 1K Timer 2 0x01C2 1C00 0x01C2 1FFF 1K

PWM0 0x01C2 2000 0x01C2 23FF 1K PWM1 0x01C2 2400 0x01C2 27FF 1K PWM2 0x01C2 2800 0x01C2 2BFF 1K PWM3 0x01C2 2C00 0x01C2 2FFF 1K

SPI4 0x01C2 3000 0x01C2 37FF 2K

Timer 4 0x01C2 3800 0x01C2 3BFF 1K

ADCIF 0x01C2 3C00 0x01C2 3FFF 1K

Reserved 0x01C2 4000 0x01C3 4FFF 112K

System Module 0x01C4 0000 0x01C4 07FF 2K PLL Controller 1 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 2 0x01C4 0C00 0x01C4 0FFF 1K

Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K

Reserved 0x01C4 2000 0x01C4 7FFF 24K

ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K

Reserved 0x01 C4 8400 0x01C63FFF 111K

USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K

SPI0 0x01C6 6000 0x01C6 67FF 2K SPI1 0x01C6 6800 0x01C6 6FFF 2K

GPIO 0x01C6 7000 0x01C6 77FF 2K

SPI2 0x01C6 7800 0x01C6 FFFF 2K SPI3 0x01C6 8000 0x01C6 87FF 2K

Reserved 0x01C6 8800 0x01C6 87FF 2K

PRTCSS Interface Registers 0x01C6 9000 0x01C6 93FF 1K

KEYSCAN 0x01C6 9400 0x01C6 97FF 1K

HPI 0x01C6 9800 0x01C6 9FFF 2K

Reserved 0x01C6 A000 0x01C6 FFFF 24K

VPSS Subsystem

ISP System Configuration Registers 0x01C7 0000 0x01C7 00FF 256

VPBE Clock Control Register 0x01C7 0200 0x01C7 02FF 256

Resizer Registers 0x01C7 0400 0x01C7 07FF 1K

IPIPE Registers 0x01C7 0800 0x01C7 0FFF 2K

ISIF Registers 0x01C7 1000 0x01C7 11FF 512

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Table 2-4. ARM Configuration Bus Access to Peripherals (continued)

Address

IPIPEIF Registers 0x01C7 1200 0x01C7 12FF 768

Reserved 0x01C7 1400 0x01C7 17FF 768 FDIF Registers 0x01C7 1800 0x01C7 1BFF 1K OSD Registers 0x01C7 1C00 0x01C7 1CFF 256

Reserved 0x01C7 1D00 0x01C7 1DFF 256

VENC Registers 0x01C7 1E00 0x01C7 1FFF 512

Reserved 0x01C7 2000 0x01CF FFFF 568K

Multimedia / SD 1 0x01D0 0000 0x01D0 1FFF 8K

McBSP 0x01D0 2000 0x01D0 3FFF 8K

Reserved 0x01D0 4000 0x01D0 5FFF 8K

UART1 0x01D0 6000 0x01D0 63FF 1K

Reserved 0x01D0 6400 0x01D0 7FFF 3K

EMAC Control Registers 0x01D0 7000 0x01D0 9FFF 0x01D0 7FFF4K

EMAC Control Module RAM 0x01D0 8000 8K

EMAC Control Module Registers 0x01D0 A000 0x01D0 AFFF 4K

EMAC MDIO Control Registers 0x01D0 B000 0x01D0 B7FF 2K

Voice Codec 0x01D0 C000 0x01D0 C3FF 1K

Reserved 0x01D0 C400 0x01D0 FFFF 17K

ASYNC EMIF Control 0x01D1 0000 0x01D1 0FFF 4K

Multimedia / SD 0 0x01D1 1000 0x01D1 FFFF 60K

Reserved 0x01D2 0000 0x01D3 FFFF 128K

Reserved 0x01D4 0000 0x01DF FFFF 768K

Reserved 0x01E0 0000 0x01FF FFFF 2M

ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M

Reserved 0x0600 0000 0x09FF FFFF 64M

Reserved 0x0A00 0000 0x0FFF FFFF 96M

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2.7 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

2.7.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the pin assignments in four quadrants (A, B, C, and D). Note that

micro-vias are not required.

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DD12_

PRTCSS

PWCTRO3

DDS18

PWCTRIO4PECTRIO0

DDS33

EMU1RESET

RTCXO

DDA18_ADC

EMU0N.B.RTCXI

SSA_ADC

DDS33

TDITCKGIO21GIO20

DDA18_VC

ADC_CH0GIO44

GPIO46

DD18_SLDO

GIO17GIO19GIO16

SSA33_VC

ADC_CH3

GIO1

GIO49GIO13

GIO14

LINEO

MICIN

N.B.

GIO47

GIO3

GIO2

N.B.GIO12

SPP

MICIP

ADC_CH1

GPIO45

GIO0

GIO5GIO6GIO11

SPN

VCOM

ADC_CH2ADC_CH5

GIO48

GIO4GIO7

RSV0

PWCTRIO1

SS_32K

TMS

RTCK

GIO18

GIO15

GIO9

GIO10

GIO8

PWCTRIO2

SSA18_VC

ADC_CH4

DDRAM

DDS33

TDO N.B.

TRST

TMS320DM368

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(1) N.B stands for No-Ball.

Figure 2-2. ZCE Pin Map [Quadrant A]

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DDR_

DQ6

DDR_

DQ8

765

GIO36

GIO32

GIO38GIO34GIO23

DDR_

DQSN0

GIO24

DDR_

DQ12

DDR_

DQM1

GIO41

DDR_

DQ5

DDR_ DQ11

DDR_

DQ14

DDR_

DQ15

GIO33

GIO28

DDR_DQ9N.B.

DDR_

DQSN1

GIO40

GIO35

GIO31N.B.GIO29GIO26

DDR_

DQGATE1

DDR_

DQGATE0

GIO43

GIO37GIO27

GIO25

DDR_DQ7DDR_DQ10DDR_DQ13GIO42

GIO39

RSV2V

GIO22

RSV1

DD18_DDR

DDS33

DDA33_USB

SSA33_USB

SSA18_USB

USB_DM

DD18_DDR

DDS33

DD18_USB

N.B.

USB_VBUS

USB_DP

VDDA12LDO_

USB

SSA

PWRST

PWRCNTON

USB_ID

DDMXI

PWCTRO1PWCTRO2PWCTRO3

SS_MX1

MXI1

DD18_PRTCSS

PWCTRIO5

N.B.

PWCTRO0MXO1

DDS18

PWCTRIO6

DD12_PRTCSS

N.B.

DDA18_PLL

DDS33

GIO30

DDR_DQS1

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Figure 2-3. ZCE Pin Map [Quadrant B]

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DDR_A11

DDR_A8

DDR_A6

DDR_A2

DDR_BA0

DDR_WE

DDR_CLK

DDR_DQ4

EM_A11

EM_A13

DDR_A12

DDR_A10DDR_A5

DDR_A1DDR_BA2

DDR_CASDDR_DQ1

DDR_DQ3

EM_A10

EM_A12

N.B.

DDR_A9DDR_A4

DDR_A0

N.B.DDR_RASDDR_DQ0

N.B.

EM_A8

EM_A9

EM_A7

DDR_A7

DDR_A3

DDR_CS

DDR_DQM0

EM_A4

EM_A6

EM_BA1

EM_A5

EM_A3

DD_

AEMIF1_18_33

DDR_CKE

DD18_DDR

DDR_

PADREFP

DDR_DQ2

EM_D13

EM_D15

EM_BA0EM_D14EM_D12

DD18_DDR

EM_D9

EM_D10N.B.EM_D8

DD18_DDR

EM_A1

EM_A2

EM_CE[0]

EM_ADVEM_CLK

DDS18

EM_D5

EM_D6EM_A0EM_D7EM_D4

EM_D2

EM_D0N.B.

DDR_VREF V

DD18_DDR

DD_

AEMIF1_18_33

DDS33

DD_

AEMIF2_18_33

EM_D3

EM_D1

N.B.

EM_D11

N.B.

DDR_A13

DDR_BA1

DDR_DQS0

DD_

AEMIF2_18_33

TMS320DM368

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Figure 2-4. ZCE Pin Map [Quadrant C]

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19181716151413121110

EM_OE

MMCSD0_

DATA1

YOUT6

DDS18

EM_WAITEM_CE[1]

MMCSD0_CLK

EM_WE

MMCSD0_

DATA0

MMCSD0_

DATA3

MMCSD0_

CMD

VSYNC

N.B.

HSYNC

YOUT2

YOUT4YOUT1YOUT3

YOUT5

COUT6

COUT7COUT4

C_WE_

FIELD

VDDA12_DAC

VSSA18_

DAC

VDDA33_VC

COUT2COUT1COUT0

YIN0

YIN1

YIN4VREF

LCD_OEFIELD

N.B.CIN2

CIN6

HDN.B.YIN7

COMPPR

N.B.

VCLK

CIN1

CIN5

CIN4

CIN0

CIN3

YIN2

CIN7

YIN3

YIN5

YIN6

COMPY

COMPPB

IDACOUT

IREF

DDS18

DDS33

DDS18

MMCSD0_

DATA2

DD_ISIF18_33

SSA12_DAC

DDS33

COUT5

EXTCLK

VFB

TVOUT

DDA18_DAC

PCLK

COUT3

YOUT0V

YOUT7N.B.

N.B.

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Figure 2-5. ZCE Pin Map [Quadrant D]

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2.8 Terminal Functions

Table 2-5 provides a complete pin description list which shows external signal names, the associated pin

(ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see

Section 3.

Table 2-5. Pin Descriptions

Name BGA Type Group Power IPU Reset Description

(5)

CIN7

CIN6

CIN5

CIN4

CIN3

CIN2

(5)

A15 I/O ISIF V

C15 I/O ISIF V

B16 I/O ISIF V

A16 I/O ISIF V

A17 I/O ISIF V

C16 I/O ISIF V

(1)

(2)

Supply

DD_ISIF18_33

(3)

IPD

State

IPD Input Standard ISIF Analog Front End (AFE): raw[7]

YCC 16-bit: time multiplexed between chroma: CB/CR[07]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[6]

YCC 16-bit: time multiplexed between chroma: CB/CR[06]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[5]

YCC 16-bit: time multiplexed between chroma: CB/CR[05]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[4]

YCC 16-bit: time multiplexed between chroma: CB/CR[04]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[3]

YCC 16-bit: time multiplexed between chroma: CB/CR[03]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[2]

YCC 16-bit: time multiplexed between chroma: CB/CR[02]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]

(4)

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 6.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.) (4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized.

(5) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD

Configuration (CCDCFG) register (0x01C7 0136h). IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal . IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).

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Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

(5)

CIN1

(5)

CIN0

(5)

YIN7

/ GIO103 C12 I/O ISIF/ V

A18 I/O ISIF V

B17 I/O ISIF V

/SPI3_SCLK GIO /

(5)

YIN6

/ GIO102 A13 I/O ISIF / V

/SPI3_SIMO GIO /

(6)

YIN5

/ GIO101 B13 I/O ISIF / V

/SPI3_SCS[0] GIO /

(6)

YIN4

/ GIO100 / D12 I/O ISIF / V SPI3_SOMI / GIO / SPI3_SCS[1] SPI3

(1)

(2)

Supply

DD_ISIF18_33

(3)

IPD

State

IPD Input Standard ISIF Analog Front End (AFE): raw[1]

YCC 16-bit: time multiplexed between chroma: CB/CR[01]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[0]

YCC 16-bit: time multiplexed between chroma: CB/CR[00]

YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[15]

SPI3

YCC 16-bit: time multiplexed between luma: Y[07] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[07]

GIO: GIO[103] SPI3: Clock

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[14]

SPI3

YCC 16-bit: time multiplexed between luma: Y[06] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[06]

GIO: GIO[102] SPI3: Slave Input Master Output Data Signal

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[13]

SPI3

YCC 16-bit: time multiplexed between luma: Y[05] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[05]

GIO: GIO[101] SPI3: Chip Select 0

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[12]

YCC 16-bit: time multiplexed between luma: Y[04] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[04]

GIO: GIO[100] SPI3: Slave Output Master Input Data Signal SPI3: Chip Select 1

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(4)

(6) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD

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Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

(6)

YIN3

/ GIO99 A14 I/O ISIF / V

(1)

GIO

(2)

Supply

DD_ISIF18_33

(3)

IPD

State

IPD Input Standard ISIF Analog Front End (AFE): raw[11]

YCC 16-bit: time multiplexed between luma: Y[03] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[03]

GIO: GIO[99]

(6)

YIN2

/ GIO98 B15 I/O ISIF / V

GIO

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[10]

YCC 16-bit: time multiplexed between luma: Y[02] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[02]

GIO: GIO[98]

(6)

YIN1

/ GIO97 D14 I/O ISIF / V

GIO

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[09]

YCC 16-bit: time multiplexed between luma: Y[01] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[01]

GIO: GIO[97]

(7)

YIN0

/ GIO96 D15 I/O ISIF / V

GIO

DD_ISIF18_33

IPD Input Standard ISIF Analog Front End (AFE): raw[08]

YCC 16-bit: time multiplexed between luma: Y[00] YCC 08-bit (which allows for 2 simultaneous decoder

inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[00]

GIO: GIO[96]

HD / GIO95 C14 I/O ISIF / V

GIO an input (slave mode) or an output (master mode).

DD_ISIF18_33

IPD Input Horizontal synchronization signal that can be either

Tells the ISIF when a new line starts. GIO: GIO[95]

VD / GIO94 B14 I/O ISIF / V

GIO input (slave mode) or an output (master mode). Tells

DD_ISIF18_33

IPD Input Vertical synchronization signal that can be either an

the ISIF when a new frame starts. GIO: GIO[94]

C_WE_FIELD / E13 I/O ISIF / V GIO93 / CLKOUT0 GIO / (AFE/TG) to gate the DDR output of the ISIF module.

DD_ISIF18_33

IPD Input Write enable input signal is used by external device

/ USBDRVVBUS CLKOU

T / USB

Alternately, the field identification input signal is used by external device (AFE/TG) to indicate the which of two frames is input to the ISIF module for sensors with interlaced output. ISIF handles 1- or 2-field sensors in hardware.

GIO: GIO[93] CLKOUT0: Clock Output USB: Digital output to control external 5 V supply

PCLK D13 I/O/Z ISIF V

DD_ISIF18_33

IPD Input Pixel clock input (strobe for lines CI7 through YI0)

(4)

(7) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD

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Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

YOUT7(R7)

YOUT6(R6)

YOUT5(R5)

YOUT4(R4)

YOUT3(R3)

YOUT2(G7)

YOUT1(G6)

YOUT0(G5)

(8)

(10)

G16 I/O VENC V

G19 I/O VENC V

F15 I/O VENC V

F18 I/O VENC V

F16 I/O VENC V

F19 I/O VENC V

F17 I/O VENC V

E16 I/O VENC V

HSYNC / GIO84 G15 I/O VENC / V

VSYNC / GIO83 G18 I/O VENC / V

LCD_OE / GIO82 C19 I/O VENC / V

(1)

Supply

DDS33

(2)

IPD

(3)

State

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(9)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(11)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

DDS33

Input Digital Video Out: VENC settings determine

function

(11)

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

GIO

DDS33

Input Video Encoder: Horizontal Sync

GIO: GIO[84]

GIO

DDS33

Input Video Encoder: Vertical Sync

GIO: GIO[83]

GIO

DDS33

Output Video Encoder: Data valid duration

GIO: GIO[82]

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(4)

(11)

(8) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE

CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).

(9) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized.

(10) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE

(11) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized.

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SPRS668B–APRIL 2010–REVISED NOVEMBER 2010

Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

GIO80 / EXTCLK / B19 I/O GIO / V B2 / PWM3 VENC /

VCLK / GIO79 B18 I/O VENC / V

GIO92 / E18 I/O GIO / V COUT7(G4)

(10)

/ VENC /

PWM0 PWM0

GIO91 / E19 I/O GIO / V COUT6(G3)

(10)

/ VENC /

PWM1 PWM1

GIO90 / E15 I/O GIO / V COUT5(G2)

(10)

/ VENC

PWM2 / RTO0 /PWM2

GIO89 / E17 I/O GIO / V COUT4(B7)

(12)

/ VENC /

PWM2 / RTO1 PWM2 /

(1)

Supply

DDS33

(2)

IPD

(3)

State

IPD Input GIO: GIO[80]

PWM3

Video Encoder: External clock Input, used if clock rates > 27 MHz are needed, e.g. 74.25 MHz for HDTV digital output.

Digital Video Out: B2 For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM3: PWM3 Output

GIO

DDS33

Input Video Encoder: Video Output Clock

GIO: GIO[79]

DDS33

Input GIO: GIO[92]

Digital Video Out: VENC settings determine

(11)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM0: PWM0 Output

DDS33

Input GIO: GIO[91]

Digital Video Out: VENC settings determine

(11)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM1: PWM1 Output

DDS33

Input GIO: GIO[90]

/ RTO0

Digital Video Out: VENC settings determine

(11)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output RTO0: RTO0 Output

DDS33

Input GIO: GIO[89]

RTO1

Digital Video Out: VENC settings determine

(13)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output RTO1: RTO1 Output

(11)

(4)

(11)

(12) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE

(13) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized.

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SPRS668B–APRIL 2010–REVISED NOVEMBER 2010

Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

GIO88 / D16 I/O GIO / V COUT3(B6)

(12)

/ VENC /

PWM2 / RTO2 PWM2 /

GIO87 / D19 I/O GIO / V COUT2(B5)

(12)

/ VENC

PWM2 / RTO3 /PWM2

GIO86 / D18 I/O GIO / V COUT1(B4)

(12)

/ VENC /

PWM3 / STTRIG PWM3

GIO85 / D17 I/O GIO / V COUT0(B3)

(14)

/ VENC /

PWM3 PWM3

GIO81(OSCCFG) / C18 I/O GIO / V LCD_FIELD / R2 / VENC / PWM3 PWM3

(1)

Supply

DDS33

(2)

IPD

(3)

State

Input GIO: GIO[88]

RTO2

Digital Video Out: VENC settings determine

(13)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output RTO2: RTO2 Output

DDS33

Input GIO: GIO[87]

/ RTO3

Digital Video Out: VENC settings determine

(13)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output RTO3: RTO3 Output

DDS33

Input GIO: GIO[86]

Digital Video Out: VENC settings determine

(13)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM3: PWM3 Output STTRIG: Camera FLASH control trigger signal

DDS33

Input GIO: GIO[85]

Digital Video Out: VENC settings determine

(15)

function

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

PWM3: PWM3 Output

DDS33

Input GIO: GIO[81]

Note: This pin will be used as oscillator configuration (OSCCFG). The GIO81(OSCCFG) state is latched during reset, and it specifies the oscillation frequency range mode of the pin. See Section 3.7.6 for more details.

Video Encoder: Field identifier for interlaced display

(15)

formats

. For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9).

Digital Video Out: R2 PWM3: PWM3 Output

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(4)

(15)

(14) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE

(15) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized.

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SPRS668B–APRIL 2010–REVISED NOVEMBER 2010

Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

VREF D11 A I/O Video V

IREF A11 A I/O Video V

IDACOUT B11 A I/O Video V

VFB B10 A I/O Video V

TVOUT A10 A I/O Video V

COMPY B12 A O Video V

COMPPB A12 A O Video V

COMPPR C11 A O Video V

DDA18_DAC

DDA12_DAC

D10 PWR Video V

E12 PWR Video V

(1)

DAC For more details, see Section 6.12.2.4, DAC and

Supply

DDA18_DAC

(2)

IPD

(3)

State

Video DAC: Reference voltage for DAC.

Video Buffer Electrical Data/Timing.

Note: If the DAC peripheral is not used, this pin must be tied directly to VSSfor proper device operation.

DAC external resistor with nominal value, 2400 ohms, is

DDA18_DAC

Video DAC: Sets reference current for DAC. An connected between IREF and VSS.

For more details, see Section 6.12.2.4, DAC and

Video Buffer Electrical Data/Timing.

Note: If the DAC peripheral is not used, this pin must be tied directly to VSSfor proper device operation.

DAC external resistor with nominal value, 2100 ohms, is

DDA18_DAC

Video DAC: Current source input from DAC. An connected between IDACOUT and VFB.

For more details, see Section 6.12.2.4, DAC and

Video Buffer Electrical Data/Timing.

Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSSor be left open.

DAC resistor with nominal value, 2150 ohms, is connected

DDA18_DAC

Video DAC: Amplifier feedback node. An external between VFB and TVOUT.

For more details, see Section 6.12.2.4, DAC and

Video Buffer Electrical Data/Timing.

Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSSor be left open.

DAC with nominal value, 2150 ohms, is connected

DDA18_DAC

Video DAC: DAC1video output. An external resistor between TVOUT and VFB. This is the output node

that drives the load (75 ohms). For more details, see Section 6.12.2.4, DAC and

Video Buffer Electrical Data/Timing.

Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSSor be left open.

DAC

DDA18_DAC

Video DAC: Analog video signal component output Y Note: If the DAC peripheral is not used at all in the

application, this pin can either be connected to VSSor be left open.

DAC Pb

DDA18_DAC

Video DAC: Analog video signal component output

Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSSor be left open.

DAC Pr

DDA18_DAC

Video DAC: Analog video signal component output

Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSSor be left open.

DAC

DDA18_DAC

Video DAC: Analog 1.8-V power Note: If the DAC peripheral is not used, this pin must

be tied directly to VSSfor proper device operation.

Dac

DDA12_DAC

Video DAC: Analog 1.2-V power Note: If the DAC peripheral is not used, this pin must

be tied directly to VSSfor proper device operation.

(4)

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SPRS668B–APRIL 2010–REVISED NOVEMBER 2010

Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

SSA18_DAC

SSA12_DAC

E11 GND Video Video DAC: Analog 1.8-V ground

F11 GND Video Video DAC: Analog 1.2-V ground

DDR_CLK W11 O DDR V DDR_CLK W12 O DDR V DDR_RAS U12 O DDR V DDR_CAS V12 O DDR V DDR_WE W13 O DDR V DDR_CS T12 O DDR V DDR_CKE R13 O DDR V DDR_DQM[1] W6 O DDR V DDR_DQM[0] T11 O DDR V DDR_DQS[1] T7 I/O DDR V

DDR_DQS[0] T10 I/O DDR V

DDR_DQSN[1] U6 I/O DDR V

DDR_DQSN[0] U9 I/O DDR V

DDR_BA[2] V13 O DDR V

DDR_BA[1] T13 O DDR V

DDR_BA[0] W14 O DDR V

DDR_A13 T16 O DDR V DDR_A12 V17 O DDR V DDR_A11 W18 O DDR V DDR_A10 V16 O DDR V DDR_A9 U16 O DDR V DDR_A8 W17 O DDR V DDR_A7 T15 O DDR V DDR_A6 W16 O DDR V

(1)

DAC

Supply

(2)

IPD

(3)

State

Note: If the DAC peripheral is not used, this pin must

be tied directly to VSSfor proper device operation.

DAC

Note: If the DAC peripheral is not used, this pin must be tied directly to VSSfor proper device operation.

DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR

DDR Data Clock DDR Complementary Data Clock DDR Row Address Strobe DDR Column Address Strobe DDR Write Enable DDR Chip Select DDR Clock Enable Data mask input for DDR_DQ[15:8] Data mask input for DDR_DQ[7:0] Data strobe input/outputs for each byte of the 16-bit

data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers.

DDR_DQS1: For DDR_DQ[15:8]

DD18_DDR

Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers.

DDR_DQS0: For DDR_DQ[7:0]

DD18_DDR

DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers.

Note: This signal is used in double ended differential memory interfaces supported by the device.

DD18_DDR

DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers.

Note: This signal is used in double ended differential memory interfaces supported by the device.

DD18_DDR

DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR

Bank select outputs. Two are required for 1Gb DDR2 memories.

DDR Address Bus bit 13 DDR Address Bus bit 12 DDR Address Bus bit 11 DDR Address Bus bit 10 DDR Address Bus bit 09 DDR Address Bus bit 08 DDR Address Bus bit 07 DDR Address Bus bit 06

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Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

DDR_A5 V15 O DDR V DDR_A4 U15 O DDR V DDR_A3 T14 O DDR V DDR_A2 W15 O DDR V DDR_A1 V14 O DDR V DDR_A0 U14 O DDR V DDR_DQ15 V6 I/O DDR V DDR_DQ14 V7 I/O DDR V DDR_DQ13 R7 I/O DDR V DDR_DQ12 W7 I/O DDR V DDR_DQ11 V8 I/O DDR V DDR_DQ10 R8 I/O DDR V DDR_DQ9 U8 I/O DDR V DDR_DQ8 W8 I/O DDR V DDR_DQ7 R9 I/O DDR V DDR_DQ6 W9 I/O DDR V DDR_DQ5 V9 I/O DDR V DDR_DQ4 W10 I/O DDR V DDR_DQ3 V10 I/O DDR V DDR_DQ2 R10 I/O DDR V DDR_DQ1 V11 I/O DDR V DDR_DQ0 U11 I/O DDR V DDR_ T8 O DDR V

DQGATE0 Route to DDR and back to DDR_DQGATE1 with

(1)

Supply

DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR DD18_DDR

(2)

IPD

(3)

State

DDR Address Bus bit 05 DDR Address Bus bit 04 DDR Address Bus bit 03 DDR Address Bus bit 02 DDR Address Bus bit 01 DDR Address Bus bit 00 DDR Data Bus bit 15 DDR Data Bus bit 14 DDR Data Bus bit 13 DDR Data Bus bit 12 DDR Data Bus bit 11 DDR Data Bus bit 10 DDR Data Bus bit 09 DDR Data Bus bit 08 DDR Data Bus bit 07 DDR Data Bus bit 06 DDR Data Bus bit 05 DDR Data Bus bit 04 DDR Data Bus bit 03 DDR Data Bus bit 02 DDR Data Bus bit 01 DDR Data Bus bit 00 DDR: Loopback signal for external DQS gating.

same constraints as used for DDR clock and data.

DDR_ T9 I DDR V DQGATE1 Route to DDR and back to DDR_DQGATE0 with

DD18_DDR

DDR: Loopback signal for external DQS gating. same constraints as used for DDR clock and data.

DDR_VREF P11 PWR DDR V

DDR_PADREFP R11 O DDR V EM_A13 / GIO78 / V18 I/O/Z AEMIF / V

BTSEL[2] GIO /

DD_AEMIF1_18_

BTSEL[ d by

DD18_DDR

IPU/IPD Input Async EMIF: Address Bus bit[13]

disable

DDR: DDR_VREF is .5* V specific reference voltage.

DDR: External resistor ( 50 ohm to ground)

2] default

GIO: GIO[78] BTSEL[2]: See Section 3.2, Device Boot Modes for

system usage of these pins.

EM_A12 / GIO77 / U18 I/O/Z AEMIF / V BTSEL[1] GIO /

BTSEL[ d by

DD_AEMIF1_18_

IPU/IPD Input Async EMIF: Address Bus bit[12]

disable

1] default

GIO: GIO[77] BTSEL[1]: See Section 3.2, Device Boot Modes for

system usage of these pins.

EM_A11 / GIO76 / V19 I/O/Z AEMIF / V BTSEL[0] GIO /

BTSEL[ d by

DD_AEMIF1_18_

IPU/IPD Input Async EMIF: Address Bus bit[11]

disable

0] default

GIO: GIO[76] BTSEL[0]: See Section 3.2, Device Boot Modes for

system usage of these pins.

(4)

DD18_DDR

= 0.9V for SSTL2

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Table 2-5. Pin Descriptions (continued)

Name BGA Type Group Power IPU Reset Description

EM_A10 / GIO75 / U19 I/O/Z AEMIF / V AECFG[2] GIO /

EM_A9 / GIO74 / T18 I/O/Z AEMIF / V AECFG[1] GIO /

EM_A8 / GIO73 / T19 I/O/Z AEMIF / V AECFG[0] GIO /

(1)

AECFG d by

Supply

DD_AEMIF1_18_

[2] default

DD_AEMIF1_18_

AECFG d by

[1] default

DD_AEMIF1_18_

AECFG d by

[0] default

(2)

IPD

(3)

State

IPU/IPD Input Async EMIF: Address Bus bit[10]

disable

GIO: GIO[75] AECFG[2]: See Section 3.2, Device Boot Modes and

Table 3-14, AECFG (Async EMIF Configuration) for

system usage of these pins.

IPU/IPD Input Async EMIF: Address Bus bit[09]

disable

GIO: GIO[74] AECFG[1]: See Section 3.2, Device Boot Modes and

Table 3-14, AECFG (Async EMIF Configuration) for

system usage of these pins.

IPU/IPD Input Async EMIF: Address Bus bit[08]

disable

GIO: GIO[73] AECFG[0]: See Section 3.2, Device Boot Modes and

Table 3-14, AECFG (Async EMIF Configuration) for

system usage of these pins.

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(4)

EM_A7 / GIO72 / T17 I/O/Z AEMIF / V KEYA3 GIO /

KEYSC AN

EM_A6 / GIO71 / R18 I/O/Z AEMIF / V KEYA2 GIO /

KEYSC AN

EM_A5 / GIO70 / R16 I/O/Z AEMIF / V KEYA1 GIO /

KEYSC AN

EM_A4 / GIO69 / R19 I/O/Z AEMIF / V KEYA0 GIO/KE

YSCAN

EM_A3 / GIO68 / R15 I/O/Z AEMIF / V KEYB3 GIO/

KEYSC AN

DD_AEMIF1_18_

Input Async EMIF: Address Bus bit[07]

GIO: GIO[72] Keyscan: A3

Input Async EMIF: Address Bus bit[06]

GIO: GIO[71] Keyscan: A2

Input Async EMIF: Address Bus bit[05]

GIO: GIO[70] Keyscan: A1

Input Async EMIF: Address Bus bit[04]

GIO: GIO[69] Keyscan: A0

Input Async EMIF: Address Bus bit[03]

GIO: GIO[68] Keyscan: B3

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+ 177 hidden pages

Texas instruments TMS320DM368 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 TMS320DM368 Digital Media System-on-Chip (DMSoC)

1.1 Features

1.2 Description

1.3 Functional Block Diagram

2 Device Overview

2.1 Device Characteristics

2.2 Device Compatibility

2.3 ARM Subsystem Overview

2.3.1 Components of the ARM Subsystem

2.3.2 ARM926EJ-S RISC CPU

2.3.3 CP15

2.3.4 MMU

2.3.5 Caches and Write Buffer

2.3.6 Tightly Coupled Memory (TCM)

2.3.7 Advanced High-performance Bus (AHB)

2.3.8 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

2.3.9 ARM Memory Mapping

2.3.9.1 ARM Internal Memories

2.3.9.2 External Memories

2.3.10 Peripherals

2.3.11 ARM Interrupt Controller (AINTC)

2.4 System Control Module

2.5 Power Management

2.6 Memory Map Summary

2.7 Pin Assignments

2.7.1 Pin Map (Bottom View)

2.8 Terminal Functions