Texas Instruments TMS320C67X User Manual

TMS320C67x/C67x+ DSP

CPU and Instruction Set

Reference Guide

Literature Number: SPRU733

May 2005

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About This Manual

The TMS320C67x+™ DSP is an enhancement of the C67x™ DSP with added functionality and an expanded instruction set. This document describes the CPU architecture, pipeline, instruction set, and interrupts of the C67x and C67x+™ DSPs.

Notational Conventions

Preface

Read This First

This document uses the following conventions.

 Any reference to the C67x DSP or C67x CPU also applies, unless other-

wise noted, to the C67x+ DSP and C67x+ CPU, respectively.

 Hexadecimal numbers are shown with the suffix h. For example, the

following number is 40 hexadecimal (decimal 64): 40h.

Trademarks

iv SPRU733Read This First

TMS320C6000 Chip Support Library API Reference Guide (literature

number SPRU401) describes a set of application programming interfaces (APIs) used to configure and control the on-chip peripherals.

Code Composer Studio, C6000, C64x, C67x, C67x+, TMS320C2000, TMS320C5000, TMS320C6000, TMS320C62x, TMS320C64x, TMS320C67x, TMS320C67x+, TMS320C672x, and VelociTI are trademarks of Texas Instruments.

Trademarks are the property of their respective owners.

Contents

1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C67x DSP and lists their key features.

1.1 TMS320 DSP Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TMS320C6000 DSP Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 TMS320C67x DSP Features and Options 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 TMS320C67x DSP Architecture 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Central Processing Unit (CPU) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Internal Memory 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3 Memory and Peripheral Options 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 CPU Data Paths and Control 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Provides information about the data paths and control registers. The two register files and the data cross paths are described.

2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 General-Purpose Register Files 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Functional Units 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Register File Cross Paths 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Memory, Load, and Store Paths 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Data Address Paths 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Control Register File 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Register Addresses for Accessing the Control Registers 2-8. . . . . . . . . . . . . . . . . .

2.7.2 Pipeline/Timing of Control Register Accesses 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Addressing Mode Register (AMR) 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.4 Control Status Register (CSR) 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.5 Interrupt Clear Register (ICR) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.6 Interrupt Enable Register (IER) 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.7 Interrupt Flag Register (IFR) 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.8 Interrupt Return Pointer Register (IRP) 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.9 Interrupt Set Register (ISR) 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.10 Interrupt Service Table Pointer Register (ISTP) 2-21. . . . . . . . . . . . . . . . . . . . . . . . .

2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) 2-22. . . . . . . . . . . . .

2.7.12 E1 Phase Program Counter (PCE1) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Control Register File Extensions 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 Floating-Point Adder Configuration Register (FADCR) 2-23. . . . . . . . . . . . . . . . . . .

2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR) 2-27. . . . . . . . . . . . . . . . .

2.8.3 Floating-Point Multiplier Configuration Register (FMCR) 2-31. . . . . . . . . . . . . . . . .

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3 Instruction Set 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the assembly language instructions of the TMS320C67x DSP. Also described are parallel operations, conditional operations, resource constraints, and addressing modes.

3.1 Instruction Operation and Execution Notations 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Instruction Syntax and Opcode Notations 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Overview of IEEE Standard Single- and Double-Precision Formats 3-9. . . . . . . . . . . . . . . .

3.4 Delay Slots 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Parallel Operations 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Example Parallel Code 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 Branching Into the Middle of an Execute Packet 3-18. . . . . . . . . . . . . . . . . . . . . . . .

3.6 Conditional Operations 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Resource Constraints 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 Constraints on Instructions Using the Same Functional Unit 3-20. . . . . . . . . . . . . .

3.7.2 Constraints on the Same Functional Unit Writing in the

Same Instruction Cycle 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 Constraints on Cross Paths (1X and 2X) 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.4 Constraints on Loads and Stores 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.5 Constraints on Long (40-Bit) Data 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.6 Constraints on Register Reads 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.7 Constraints on Register Writes 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.8 Constraints on Floating-Point Instructions 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Addressing Modes 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 Linear Addressing Mode 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.2 Circular Addressing Mode 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.3 Syntax for Load/Store Address Generation 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 Instruction Compatibility 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Instruction Descriptions 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABS (Absolute Value With Saturation) 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSDP (Absolute Value, Double-Precision Floating-Point) 3-40. . . . . . . . . . . . . . . . . . . . . .

ABSSP (Absolute Value, Single-Precision Floating-Point) 3-42. . . . . . . . . . . . . . . . . . . . . . .

ADD (Add Two Signed Integers Without Saturation) 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDAB (Add Using Byte Addressing Mode) 3-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDAD (Add Using Doubleword Addressing Mode) 3-50. . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDAH (Add Using Halfword Addressing Mode) 3-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDAW (Add Using Word Addressing Mode) 3-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDDP (Add Two Double-Precision Floating-Point Values) 3-56. . . . . . . . . . . . . . . . . . . . .

ADDK (Add Signed 16-Bit Constant to Register) 3-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDSP (Add Two Single-Precision Floating-Point Values) 3-60. . . . . . . . . . . . . . . . . . . . . .

ADDU (Add Two Unsigned Integers Without Saturation) 3-63. . . . . . . . . . . . . . . . . . . . . . . .

ADD2 (Add Two 16-Bit Integers on Upper and Lower Register Halves) 3-65. . . . . . . . . . .

AND (Bitwise AND) 3-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B (Branch Using a Displacement) 3-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B (Branch Using a Register) 3-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B IRP (Branch Using an Interrupt Return Pointer) 3-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B NRP (Branch Using NMI Return Pointer) 3-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi SPRU733Contents

Contents

CLR (Clear a Bit Field) 3-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMPEQ (Compare for Equality, Signed Integers) 3-80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMPEQDP (Compare for Equality, Double-Precision Floating-Point Values) 3-82. . . . . . .

CMPEQSP (Compare for Equality, Single-Precision Floating-Point Values) 3-84. . . . . . . .

CMPGT (Compare for Greater Than, Signed Integers) 3-86. . . . . . . . . . . . . . . . . . . . . . . . . .

CMPGTDP (Compare for Greater Than, Double-Precision Floating-Point Values) 3-89. . CMPGTSP (Compare for Greater Than, Single-Precision Floating-Point Values) 3-91. . .

CMPGTU (Compare for Greater Than, Unsigned Integers) 3-93. . . . . . . . . . . . . . . . . . . . . .

CMPLT (Compare for Less Than, Signed Integers) 3-95. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMPLTDP (Compare for Less Than, Double-Precision Floating-Point Values) 3-98. . . . .

CMPLTSP (Compare for Less Than, Single-Precision Floating-Point Values) 3-100. . . . .

CMPLTU (Compare for Less Than, Unsigned Integers) 3-102. . . . . . . . . . . . . . . . . . . . . . . .

DPINT (Convert Double-Precision Floating-Point Value to Integer) 3-104. . . . . . . . . . . . . .

DPSP (Convert Double-Precision Floating-Point Value to

Single-Precision Floating-Point Value) 3-106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DPTRUNC (Convert Double-Precision Floating-Point Value to

Integer With Truncation) 3-108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXT (Extract and Sign-Extend a Bit Field) 3-110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTU (Extract and Zero-Extend a Bit Field) 3-113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE (Multicycle NOP With No Termination Until Interrupt) 3-116. . . . . . . . . . . . . . . . . . . . .

INTDP (Convert Signed Integer to Double-Precision Floating-Point Value) 3-117. . . . . . .

INTDPU (Convert Unsigned Integer to Double-Precision Floating-Point Value) 3-119. . . .

INTSP (Convert Signed Integer to Single-Precision Floating-Point Value) 3-121. . . . . . . .

INTSPU (Convert Unsigned Integer to Single-Precision Floating-Point Value) 3-122. . . . .

LDB(U) (Load Byte From Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LDB(U) (Load Byte From Memory With a 15-Bit Unsigned Constant Offset) 3-126. . . . . .

LDDW (Load Doubleword From Memory With an Unsigned Constant Offset or

Register Offset) 3-128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LDH(U) (Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LDH(U) (Load Halfword From Memory With a 15-Bit Unsigned Constant Offset) 3-134. . LDW (Load Word From Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LDW (Load Word From Memory With a 15-Bit Unsigned Constant Offset) 3-139. . . . . . . .

LMBD (Leftmost Bit Detection) 3-141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPY (Multiply Signed 16 LSB by Signed 16 LSB) 3-143. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPYDP (Multiply Two Double-Precision Floating-Point Values) 3-145. . . . . . . . . . . . . . . . .

MPYH (Multiply Signed 16 MSB by Signed 16 MSB) 3-147. . . . . . . . . . . . . . . . . . . . . . . . . .

MPYHL (Multiply Signed 16 MSB by Signed 16 LSB) 3-149. . . . . . . . . . . . . . . . . . . . . . . . . .

MPYHLU (Multiply Unsigned 16 MSB by Unsigned 16 LSB) 3-151. . . . . . . . . . . . . . . . . . . .

MPYHSLU (Multiply Signed 16 MSB by Unsigned 16 LSB) 3-152. . . . . . . . . . . . . . . . . . . . .

MPYHSU (Multiply Signed 16 MSB by Unsigned 16 MSB) 3-153. . . . . . . . . . . . . . . . . . . . .

MPYHU (Multiply Unsigned 16 MSB by Unsigned 16 MSB) 3-154. . . . . . . . . . . . . . . . . . . .

MPYHULS (Multiply Unsigned 16 MSB by Signed 16 LSB) 3-155. . . . . . . . . . . . . . . . . . . . .

MPYHUS (Multiply Unsigned 16 MSB by Signed 16 MSB) 3-156. . . . . . . . . . . . . . . . . . . . .

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MPYI (Multiply 32-Bit by 32-Bit Into 32-Bit Result) 3-157. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPYID (Multiply 32-Bit by 32-Bit Into 64-Bit Result) 3-159. . . . . . . . . . . . . . . . . . . . . . . . . . .

MPYLH (Multiply Signed 16 LSB by Signed 16 MSB) 3-161. . . . . . . . . . . . . . . . . . . . . . . . . .

MPYLHU (Multiply Unsigned 16 LSB by Unsigned 16 MSB) 3-163. . . . . . . . . . . . . . . . . . . .

MPYLSHU (Multiply Signed 16 LSB by Unsigned 16 MSB) 3-164. . . . . . . . . . . . . . . . . . . . .

MPYLUHS (Multiply Unsigned 16 LSB by Signed 16 MSB) 3-165. . . . . . . . . . . . . . . . . . . . .

MPYSP (Multiply Two Single-Precision Floating-Point Values) 3-166. . . . . . . . . . . . . . . . . .

MPYSPDP (Multiply Single-Precision Floating-Point Value by

Double-Precision Floating-Point Value) 3-168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPYSP2DP (Multiply Two Single-Precision Floating-Point Values for

Double-Precision Result) 3-170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPYSU (Multiply Signed 16 LSB by Unsigned 16 LSB) 3-172. . . . . . . . . . . . . . . . . . . . . . . .

MPYU (Multiply Unsigned 16 LSB by Unsigned 16 LSB) 3-174. . . . . . . . . . . . . . . . . . . . . . .

MPYUS (Multiply Unsigned 16 LSB by Signed 16 LSB) 3-176. . . . . . . . . . . . . . . . . . . . . . . .

MV (Move From Register to Register) 3-178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MVC (Move Between Control File and Register File) 3-180. . . . . . . . . . . . . . . . . . . . . . . . . .

MVK (Move Signed Constant Into Register and Sign Extend) 3-183. . . . . . . . . . . . . . . . . . .

MVKH and MVKLH (Move 16-Bit Constant Into Upper Bits of Register) 3-185. . . . . . . . . .

MVKL (Move Signed Constant Into Register and

Sign Extend—Used with MVKH) 3-187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NEG (Negate) 3-189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOP (No Operation) 3-190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NORM (Normalize Integer) 3-192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOT (Bitwise NOT) 3-194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OR (Bitwise OR) 3-195. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RCPDP (Double-Precision Floating-Point Reciprocal Approximation) 3-197. . . . . . . . . . . .

RCPSP (Single-Precision Floating-Point Reciprocal Approximation) 3-199. . . . . . . . . . . . .

RSQRDP (Double-Precision Floating-Point Square-Root

Reciprocal Approximation) 3-201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RSQRSP (Single-Precision Floating-Point Square-Root

Reciprocal Approximation) 3-203. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SADD (Add Two Signed Integers With Saturation) 3-205. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SAT (Saturate a 40-Bit Integer to a 32-Bit Integer) 3-208. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SET (Set a Bit Field) 3-210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SHL (Arithmetic Shift Left) 3-213. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SHR (Arithmetic Shift Right) 3-215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SHRU (Logical Shift Right) 3-217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMPY (Multiply Signed 16 LSB by Signed 16 LSB With

Left Shift and Saturation) 3-219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMPYH (Multiply Signed 16 MSB by Signed 16 MSB With

Left Shift and Saturation) 3-221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMPYHL (Multiply Signed 16 MSB by Signed 16 LSB With

Left Shift and Saturation) 3-222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMPYLH (Multiply Signed 16 LSB by Signed 16 MSB With

Left Shift and Saturation) 3-224. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPDP (Convert Single-Precision Floating-Point Value to

Double-Precision Floating-Point Value) 3-226. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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SPINT (Convert Single-Precision Floating-Point Value to Integer) 3-228. . . . . . . . . . . . . . .

SPTRUNC (Convert Single-Precision Floating-Point Value to

Integer With Truncation) 3-230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSHL (Shift Left With Saturation) 3-232. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSUB (Subtract Two Signed Integers With Saturation) 3-234. . . . . . . . . . . . . . . . . . . . . . . . .

STB (Store Byte to Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-236. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STB (Store Byte to Memory With a 15-Bit Unsigned Constant Offset) 3-238. . . . . . . . . . . .

STH (Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-240. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STH (Store Halfword to Memory With a 15-Bit Unsigned Constant Offset) 3-243. . . . . . . .

STW (Store Word to Memory With a 5-Bit Unsigned Constant Offset or

Register Offset) 3-245. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STW (Store Word to Memory With a 15-Bit Unsigned Constant Offset) 3-247. . . . . . . . . .

SUB (Subtract Two Signed Integers Without Saturation) 3-249. . . . . . . . . . . . . . . . . . . . . . .

SUBAB (Subtract Using Byte Addressing Mode) 3-253. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SUBAH (Subtract Using Halfword Addressing Mode) 3-255. . . . . . . . . . . . . . . . . . . . . . . . . .

SUBAW (Subtract Using Word Addressing Mode) 3-256. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SUBC (Subtract Conditionally and Shift—Used for Division) 3-258. . . . . . . . . . . . . . . . . . . .

SUBDP (Subtract Two Double-Precision Floating-Point Values) 3-260. . . . . . . . . . . . . . . . .

SUBSP (Subtract Two Single-Precision Floating-Point Values) 3-263. . . . . . . . . . . . . . . . . .

SUBU (Subtract Two Unsigned Integers Without Saturation) 3-266. . . . . . . . . . . . . . . . . . .

SUB2 (Subtract Two 16-Bit Integers on Upper and Lower Register Halves) 3-268. . . . . . .

XOR (Bitwise Exclusive OR) 3-270. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ZERO (Zero a Register) 3-272. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Pipeline 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes phases, operation, and discontinuities for the TMS320C67x CPU pipeline.

4.1 Pipeline Operation Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Fetch 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Decode 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 Execute 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.4 Pipeline Operation Summary 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Pipeline Execution of Instruction Types 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Single-Cycle Instructions 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 16 y 16-Bit Multiply Instructions 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Store Instructions 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4 Load Instructions 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5 Branch Instructions 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.6 Two-Cycle DP Instructions 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.7 Four-Cycle Instructions 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.8 INTDP Instruction 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.9 DP Compare Instructions 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.10 ADDDP/SUBDP Instructions 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4.2.11 MPYI Instruction 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.12 MPYID Instruction 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.13 MPYDP Instruction 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.14 MPYSPDP Instruction 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.15 MPYSP2DP Instruction 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Functional Unit Constraints 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 .S-Unit Constraints 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 .M-Unit Constraints 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.3 .L-Unit Constraints 4-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.4 .D-Unit Instruction Constraints 4-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Performance Considerations 4-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet 4-56. . . . . .

4.4.2 Multicycle NOPs 4-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.3 Memory Considerations 4-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Interrupts 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the TMS320C67x DSP interrupts, including reset and nonmaskable interrupts (NMI), and explains interrupt control, detection, and processing.

5.1 Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 Types of Interrupts and Signals Used 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2 Interrupt Service Table (IST) 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.3 Summary of Interrupt Control Registers 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Globally Enabling and Disabling Interrupts 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Individual Interrupt Control 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Enabling and Disabling Interrupts 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2 Status of Interrupts 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.3 Setting and Clearing Interrupts 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.4 Returning From Interrupt Servicing 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Interrupt Detection and Processing 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Setting the Nonreset Interrupt Flag 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2 Conditions for Processing a Nonreset Interrupt 5-16. . . . . . . . . . . . . . . . . . . . . . . . .

5.4.3 Actions Taken During Nonreset Interrupt Processing 5-18. . . . . . . . . . . . . . . . . . . .

5.4.4 Setting the RESET

5.4.5 Actions Taken During RESET

Interrupt Flag 5-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Processing 5-20. . . . . . . . . . . . . . . . . . . . . .

5.5 Performance Considerations 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.1 General Performance 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.2 Pipeline Interaction 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Programming Considerations 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 Single Assignment Programming 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.2 Nested Interrupts 5-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.3 Manual Interrupt Processing 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.4 Traps 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x SPRU733Contents

Contents

A Instruction Compatibility A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that are common to the C62x, C64x, and C67x DSPs.

B Mapping Between Instruction and Functional Unit B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute on each functional unit.

C .D Unit Instructions and Opcode Maps C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute in the .D functional unit and illustrates the opcode maps for these instructions.

C.1 Instructions Executing in the .D Functional Unit C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2 Opcode Map Symbols and Meanings C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.3 32-Bit Opcode Maps C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D .L Unit Instructions and Opcode Maps D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute in the .L functional unit and illustrates the opcode maps for these instructions.

D.1 Instructions Executing in the .L Functional Unit D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.2 Opcode Map Symbols and Meanings D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.3 32-Bit Opcode Maps D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E .M Unit Instructions and Opcode Maps E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute in the .M functional unit and illustrates the opcode maps for these instructions.

E.1 Instructions Executing in the .M Functional Unit E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E.2 Opcode Map Symbols and Meanings E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E.3 32-Bit Opcode Maps E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F .S Unit Instructions and Opcode Maps F-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute in the .S functional unit and illustrates the opcode maps for these instructions.

F.1 Instructions Executing in the .S Functional Unit F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.2 Opcode Map Symbols and Meanings F-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.3 32-Bit Opcode Maps F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G No Unit Specified Instructions and Opcode Maps G-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists the instructions that execute with no unit specified and illustrates the opcode maps for these instructions.

G.1 Instructions Executing With No Unit Specified G-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G.2 Opcode Map Symbols and Meanings G-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G.3 32-Bit Opcode Maps G-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiContentsSPRU733

Figures

1−1 TMS320C67x DSP Block Diagram 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 TMS320C67x CPU Data Paths 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Storage Scheme for 40-Bit Data in a Register Pair 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Addressing Mode Register (AMR) 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Control Status Register (CSR) 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 PWRD Field of Control Status Register (CSR) 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 Interrupt Clear Register (ICR) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 Interrupt Enable Register (IER) 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Interrupt Flag Register (IFR) 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Interrupt Return Pointer Register (IRP) 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Interrupt Set Register (ISR) 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 Interrupt Service Table Pointer Register (ISTP) 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 NMI Return Pointer Register (NRP) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 E1 Phase Program Counter (PCE1) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−14 Floating-Point Adder Configuration Register (FADCR) 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−15 Floating-Point Auxiliary Configuration Register (FAUCR) 2-27. . . . . . . . . . . . . . . . . . . . . . . . . .

2−16 Floating-Point Multiplier Configuration Register (FMCR) 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Single-Precision Floating-Point Fields 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Double-Precision Floating-Point Fields 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Basic Format of a Fetch Packet 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Examples of the Detectability of Write Conflicts by the Assembler 3-25. . . . . . . . . . . . . . . . . .

4−1 Pipeline Stages 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Fetch Phases of the Pipeline 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Decode Phases of the Pipeline 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Execute Phases of the Pipeline 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Pipeline Phases 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Pipeline Operation: One Execute Packet per Fetch Packet 4-6. . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Pipeline Phases Block Diagram 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Single-Cycle Instruction Phases 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 Single-Cycle Instruction Execution Block Diagram 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 Multiply Instruction Phases 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 Multiply Instruction Execution Block Diagram 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−12 Store Instruction Phases 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 Store Instruction Execution Block Diagram 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 Load Instruction Phases 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−15 Load Instruction Execution Block Diagram 4-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 Branch Instruction Phases 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 Branch Instruction Execution Block Diagram 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii SPRU733Figures

Figures

4−18 Two-Cycle DP Instruction Phases 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−19 Four-Cycle Instruction Phases 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 INTDP Instruction Phases 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 DP Compare Instruction Phases 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 ADDDP/SUBDP Instruction Phases 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 MPYI Instruction Phases 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−24 MPYID Instruction Phases 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−25 MPYDP Instruction Phases 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−26 MPYSPDP Instruction Phases 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−27 MPYSP2DP Instruction Phases 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−28 Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets 4-57. . . . . . .

4−29 Multicycle NOP in an Execute Packet 4-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−30 Branching and Multicycle NOPs 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−31 Pipeline Phases Used During Memory Accesses 4-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−32 Program and Data Memory Stalls 4-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−33 8-Bank Interleaved Memory 4-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−34 8-Bank Interleaved Memory With Two Memory Spaces 4-63. . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Interrupt Service Table 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Interrupt Service Fetch Packet 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 Interrupt Service Table With Branch to Additional Interrupt Service Code

Located Outside the IST 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 Nonreset Interrupt Detection and Processing: Pipeline Operation 5-17. . . . . . . . . . . . . . . . . . .

5−5 RESET

Interrupt Detection and Processing: Pipeline Operation 5-19. . . . . . . . . . . . . . . . . . . .

C−1 1 or 2 Sources Instruction Format C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−2 Extended .D Unit 1 or 2 Sources Instruction Format C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−3 Load/Store Basic Operations C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−4 Load/Store Long-Immediate Operations C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−1 1 or 2 Sources Instruction Format D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−2 1 or 2 Sources, Nonconditional Instruction Format D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−3 Unary Instruction Format D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−1 Extended M-Unit with Compound Operations E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−2 Extended .M Unit 1 or 2 Sources, Nonconditional Instruction Format E-4. . . . . . . . . . . . . . . . .

E−3 Extended .M-Unit Unary Instruction Format E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−1 1 or 2 Sources Instruction Format F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−2 Extended .S Unit 1 or 2 Sources Instruction Format F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−3 Extended .S Unit 1 or 2 Sources, Nonconditional Instruction Format F-4. . . . . . . . . . . . . . . . .

F−4 Unary Instruction Format F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−5 Extended .S Unit Branch Conditional, Immediate Instruction Format F-4. . . . . . . . . . . . . . . . .

F−6 Call Unconditional, Immediate with Implied NOP 5 Instruction Format F-5. . . . . . . . . . . . . . . .

F−7 Branch with NOP Constant Instruction Format F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−8 Branch with NOP Register Instruction Format F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−9 Branch Instruction Format F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−10 MVK Instruction Format F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−11 Field Operations F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G−1 Loop Buffer Instruction Format G-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G−2 NOP and IDLE Instruction Format G-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G−3 Emulation/Control Instruction Format G-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiiiFiguresSPRU733

Tables

1−1 Typical Applications for the TMS320 DSPs 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 40-Bit/64-Bit Register Pairs 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Functional Units and Operations Performed 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Control Registers 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Register Addresses for Accessing the Control Registers 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Addressing Mode Register (AMR) Field Descriptions 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 Block Size Calculations 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 Control Status Register (CSR) Field Descriptions 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Interrupt Clear Register (ICR) Field Descriptions 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Interrupt Enable Register (IER) Field Descriptions 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Interrupt Flag Register (IFR) Field Descriptions 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 Interrupt Set Register (ISR) Field Descriptions 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Interrupt Service Table Pointer Register (ISTP) Field Descriptions 2-21. . . . . . . . . . . . . . . . . .

2−13 Control Register File Extensions 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−14 Floating-Point Adder Configuration Register (FADCR) Field Descriptions 2-24. . . . . . . . . . . .

2−15 Floating-Point Auxiliary Configuration Register (FAUCR) Field Descriptions 2-27. . . . . . . . . .

2−16 Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions 2-31. . . . . . . . . .

3−1 Instruction Operation and Execution Notations 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Instruction Syntax and Opcode Notations 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 IEEE Floating-Point Notations 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Special Single-Precision Values 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Hexadecimal and Decimal Representation for Selected Single-Precision Values 3-12. . . . . .

3−6 Special Double-Precision Values 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Hexadecimal and Decimal Representation for Selected Double-Precision Values 3-13. . . . .

3−8 Delay Slot and Functional Unit Latency 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−9 Registers That Can Be Tested by Conditional Operations 3-19. . . . . . . . . . . . . . . . . . . . . . . . .

3−10 Indirect Address Generation for Load/Store 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 Address Generator Options for Load/Store 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 Relationships Between Operands, Operand Size, Signed/Unsigned,

3−13 Program Counter Values for Example Branch Using a Displacement 3-70. . . . . . . . . . . . . . . .

3−14 Program Counter Values for Example Branch Using a Register 3-72. . . . . . . . . . . . . . . . . . . .

3−15 Program Counter Values for B IRP Instruction 3-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 Program Counter Values for B NRP Instruction 3-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17 Data Types Supported by LDB(U) Instruction 3-123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Data Types Supported by LDB(U) Instruction (15-Bit Offset) 3-126. . . . . . . . . . . . . . . . . . . . . .

Functional Units, and Opfields for Example Instruction (ADD) 3-36. . . . . . . . . . . . . . . . . . . . . .

xiv SPRU733Tables

Tables

3−19 Data Types Supported by LDH(U) Instruction 3-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−20 Data Types Supported by LDH(U) Instruction (15-Bit Offset) 3-135. . . . . . . . . . . . . . . . . . . . . .

3−21 Register Addresses for Accessing the Control Registers 3-182. . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Operations Occurring During Pipeline Phases 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Execution Stage Length Description for Each Instruction Type 4-12. . . . . . . . . . . . . . . . . . . . .

4−3 Single-Cycle Instruction Execution 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−416 × 16-Bit Multiply Instruction Execution 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Store Instruction Execution 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Load Instruction Execution 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Branch Instruction Execution 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Two-Cycle DP Instruction Execution 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 Four-Cycle Instruction Execution 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 INTDP Instruction Execution 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 DP Compare Instruction Execution 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−12 ADDDP/SUBDP Instruction Execution 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 MPYI Instruction Execution 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 MPYID Instruction Execution 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−15 MPYDP Instruction Execution 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 MPYSPDP Instruction Execution 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 MPYSP2DP Instruction Execution 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−18 Single-Cycle .S-Unit Instruction Constraints 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−19 DP Compare .S-Unit Instruction Constraints 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 2-Cycle DP .S-Unit Instruction Constraints 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 ADDSP/SUBSP .S-Unit Instruction Constraints 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 ADDDP/SUBDP .S-Unit Instruction Constraints 4-38

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 Branch .S-Unit Instruction Constraints 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−24 16 × 16 Multiply .M-Unit Instruction Constraints 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−25 4-Cycle .M-Unit Instruction Constraints 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−26 MPYI .M-Unit Instruction Constraints 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−27 MPYID .M-Unit Instruction Constraints 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−28 MPYDP .M-Unit Instruction Constraints 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−29 MPYSP .M-Unit Instruction Constraints 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−30 MPYSPDP .M-Unit Instruction Constraints 4-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−31 MPYSP2DP .M-Unit Instruction Constraints 4-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−32 Single-Cycle .L-Unit Instruction Constraints 4-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−33 4-Cycle .L-Unit Instruction Constraints 4-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−34 INTDP .L-Unit Instruction Constraints 4-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−35 ADDDP/SUBDP .L-Unit Instruction Constraints 4-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−36 Load .D-Unit Instruction Constraints 4-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−37 Store .D-Unit Instruction Constraints 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−38 Single-Cycle .D-Unit Instruction Constraints 4-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−39 LDDW Instruction With Long Write Instruction Constraints 4-55. . . . . . . . . . . . . . . . . . . . . . . . .

4−40 Program Memory Accesses Versus Data Load Accesses 4-60. . . . . . . . . . . . . . . . . . . . . . . . . .

4−41 Loads in Pipeline from Example 4−2 4-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvTablesSPRU733

Tables

5−1 Interrupt Priorities 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Interrupt Control Registers 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−1 Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs A-1. . . . . . . . . . . . . .

B−1 Functional Unit to Instruction Mapping B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−1 Instructions Executing in the .D Functional Unit C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−2 .D Unit Opcode Map Symbol Definitions C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−3 Address Generator Options for Load/Store C-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−1 Instructions Executing in the .L Functional Unit D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−2 .L Unit Opcode Map Symbol Definitions D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−1 Instructions Executing in the .M Functional Unit E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−2 .M Unit Opcode Map Symbol Definitions E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−1 Instructions Executing in the .S Functional Unit F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−2 .S Unit Opcode Map Symbol Definitions F-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G−1 Instructions Executing With No Unit Specified G-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G−2 No Unit Specified Instructions Opcode Map Symbol Definitions G-2. . . . . . . . . . . . . . . . . . . . .

xvi SPRU733Tables

Examples

3−1 Fully Serial p-Bit Pattern in a Fetch Packet 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Fully Parallel p-Bit Pattern in a Fetch Packet 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Partially Serial p-Bit Pattern in a Fetch Packet 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 LDW Instruction in Circular Mode 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 ADDAH Instruction in Circular Mode 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Execute Packet in Figure 4−7 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Load From Memory Banks 4-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Relocation of Interrupt Service Table 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Code Sequence to Disable Maskable Interrupts Globally 5-12. . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 Code Sequence to Enable Maskable Interrupts Globally 5-12. . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 Code Sequence to Enable an Individual Interrupt (INT9) 5-13. . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 Code Sequence to Disable an Individual Interrupt (INT9) 5-13. . . . . . . . . . . . . . . . . . . . . . . . . .

5−6 Code to Set an Individual Interrupt (INT6) and Read the Flag Register 5-14. . . . . . . . . . . . . .

5−7 Code to Clear an Individual Interrupt (INT6) and Read the Flag Register 5-14. . . . . . . . . . . .

5−8 Code to Return From NMI 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 Code to Return from a Maskable Interrupt 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−10 Code Without Single Assignment: Multiple Assignment of A1 5-22. . . . . . . . . . . . . . . . . . . . . .

5−11 Code Using Single Assignment 5-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 Assembly Interrupt Service Routine That Allows Nested Interrupts 5-24. . . . . . . . . . . . . . . . . .

5−13 C Interrupt Service Routine That Allows Nested Interrupts 5-25. . . . . . . . . . . . . . . . . . . . . . . . .

5−14 Manual Interrupt Processing 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−15 Code Sequence to Invoke a Trap 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−16 Code Sequence for Trap Return 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xviiExamplesSPRU733

Chapter 1

Introduction

The TMS320C6000™ digital signal processor (DSP) platform is part of the TMS320™ DSP family. The TMS320C62x™ DSP generation and the TMS320C64x™ DSP generation comprise fixed-point devices in the C6000™ DSP platform, and the TMS320C67x™ DSP generation comprises floatingpoint devices in the C6000 DSP platform. All three DSP generations use the VelociTI™ architecture, a high-performance, advanced very long instruction word (VLIW) architecture, making these DSPs excellent choices for multichannel and multifunction applications.

The TMS320C67x+ DSP is an enhancement of the C67x DSP with added functionality and an expanded instruction set.

Any reference to the C67x DSP or C67x CPU also applies, unless otherwise noted, to the C67x+ DSP and C67x+ CPU, respectively.

Topic Page

1.1 TMS320 DSP Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TMS320C6000 DSP Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 TMS320C67x DSP Features and Options 1-4. . . . . . . . . . . . . . . . . . . . . . . .

1.4 TMS320C67x DSP Architecture 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1IntroductionSPRU733

TMS320 DSP Family Overview

TMS320 DSP Family Overview / TMS320C6000 DSP Family Overview

1.1 TMS320 DSP Family Overview

The TMS320™ DSP family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320™ DSPs have an architec- ture designed specifically for real-time signal processing.

Table 1−1 lists some typical applications for the TMS320™ family of DSPs. The TMS320™ DSPs offer adaptable approaches to traditional signal-processing problems. They also support complex applications that often require multiple operations to be performed simultaneously.

1.2 TMS320C6000 DSP Family Overview

With a performance of up to 6000 million instructions per second (MIPS) and an efficient C compiler, the TMS320C6000 DSPs give system architects unlimited possibilities to differentiate their products. High performance, ease of use, and affordable pricing make the C6000 generation the ideal solution for multichannel, multifunction applications, such as:

 Pooled modems  Wireless local loop base stations  Remote access servers (RAS)  Digital subscriber loop (DSL) systems  Cable modems  Multichannel telephony systems

The C6000 generation is also an ideal solution for exciting new applications; for example:

 Personalized home security with face and hand/fingerprint recognition

 Advanced cruise control with global positioning systems (GPS) navigation

and accident avoidance

 Remote medical diagnostics

 Beam-forming base stations

 Virtual reality 3-D graphics

 Speech recognition

 Audio

 Radar

 Atmospheric modeling

 Finite element analysis

 Imaging (examples: fingerprint recognition, ultrasound, and MRI)

Introduction1-2 SPRU733

TMS320C6000 DSP Family Overview

Table 1−1. Typical Applications for the TMS320 DSPs

Automotive Consumer Control

Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands

General-Purpose Graphics/Imaging Industrial

Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing

Instrumentation Medical Military

Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis

Digital radios/TVs Educational toys Music synthesizers Pagers Power tools Radar detectors Solid-state answering machines

3-D transformations Animation/digital maps Homomorphic processing Image compression/transmission Image enhancement Pattern recognition Robot vision Workstations

Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment

Disk drive control Engine control Laser printer control Motor control Robotics control Servo control

Numeric control Power-line monitoring Robotics Security access

Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing

Telecommunications Voice/Speech

1200- to 56600-bps modems Adaptive equalizers ADPCM transcoders Base stations Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) DTMF encoding/decoding Echo cancellation

Faxing Future terminals Line repeaters Personal communications

systems (PCS) Personal digital assistants (PDA) Speaker phones Spread spectrum communications Digital subscriber loop (xDSL) Video conferencing X.25 packet switching

Speaker verification Speech enhancement Speech recognition Speech synthesis Speech vocoding Text-to-speech Voice mail

1-3IntroductionSPRU733

TMS320C67x DSP Features and Options

1.3 TMS320C67x DSP Features and Options

The C6000 devices execute up to eight 32-bit instructions per cycle. The C67x CPU consists of 32 general-purpose 32-bit registers and eight functional units. These eight functional units contain:

 Two multipliers  Six ALUs

The C6000 generation has a complete set of optimized development tools, including an efficient C compiler, an assembly optimizer for simplified assembly-language programming and scheduling, and a Windows™ based debugger interface for visibility into source code execution characteristics. A hardware emulation board, compatible with the TI XDS510™ and XDS560™ emulator interface, is also available. This tool complies with IEEE Standard

1149.1−1990, IEEE Standard Test Access Port and Boundary-Scan Architecture.

Features of the C6000 devices include:

 Advanced VLIW CPU with eight functional units, including two multipliers

and six arithmetic units

 Executes up to eight instructions per cycle for up to ten times the

performance of typical DSPs

 Allows designers to develop highly effective RISC-like code for fast

development time

 Instruction packing

 Gives code size equivalence for eight instructions executed serially or

in parallel

 Reduces code size, program fetches, and power consumption

 Conditional execution of all instructions

 Reduces costly branching

 Increases parallelism for higher sustained performance

 Efficient code execution on independent functional units

 Industry’s most efficient C compiler on DSP benchmark suite

 Industry’s first assembly optimizer for fast development and improved

parallelization

 8/16/32-bit data support, providing efficient memory support for a variety

of applications

Introduction1-4 SPRU733

TMS320C67x DSP Features and Options

40-bit arithmetic options add extra precision for vocoders and other



computationally intensive applications

 Saturation and normalization provide support for key arithmetic

operations

 Field manipulation and instruction extract, set, clear, and bit counting

support common operation found in control and data manipulation applications.

The C67x devices include these additional features:

 Hardware support for single-precision (32-bit) and double-precision

(64-bit) IEEE floating-point operations.

 32 × 32-bit integer multiply with 32-bit or 64-bit result.

In addition to the features of the C67x device, the C67x+ device is enhanced for code size improvement and floating-point performance. These additional features include:

 Execute packets can span fetch packets.

 Register file size is increased to 64 registers (32 in each datapath).

 Floating-point addition and subtraction capability in the .S unit.

 Mixed-precision multiply instructions.

 32-KByte instruction cache that supports execution from both on-chip

RAM and ROM as well as from external memory through a VBUSP-based external memory interface (EMIF).

 Unified memory controller features support for flat on-chip data RAM and

ROM organizations for zero wait-state accesses from both load store units of the CPU. The memory controller supports different banking organizations for RAM and ROM arrays. The memory controller also supports VBUSP interfaces (two master and one slave) for transfer of data from the system peripherals to and from the CPU and internal memory. A VBUSPbased DMA controller can interface to the CPU for programmable bulk transfers through the VBUSP slave port.

1-5IntroductionSPRU733

TMS320C67x DSP Features and Options

The VelociTI architecture of the C6000 platform of devices make them the first off-the-shelf DSPs to use advanced VLIW to achieve high performance through increased instruction-level parallelism. A traditional VLIW architecture consists of multiple execution units running in parallel, performing multiple instructions during a single clock cycle. Parallelism is the key to extremely high performance, taking these DSPs well beyond the performance capabilities of traditional superscalar designs. VelociTI is a highly deterministic architecture, having few restrictions on how or when instructions are fetched, executed, or stored. It is this architectural flexibility that is key to the breakthrough efficiency levels of the TMS320C6000 Optimizing C compiler. VelociTI’s advanced features include:

 Instruction packing: reduced code size  All instructions can operate conditionally: flexibility of code  Variable-width instructions: flexibility of data types  Fully pipelined branches: zero-overhead branching.

Introduction1-6 SPRU733

1.4 TMS320C67x DSP Architecture

Figure 1−1 is the block diagram for the C67x DSP. The C6000 devices come with program memory, which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power-down logic, and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are on only certain devices. Check the data sheet for your device to determine the specific peripheral configurations you have.

Figure 1−1. TMS320C67x DSP Block Diagram

Program cache/program memory

32-bit address

256-bit data

TMS320C67x DSP Architecture

DMA, EMIF

Power

down

Data path A Data path B

Data cache/data memory

32-bit address

8-, 16-, 32-bit data

C6000 CPU

Program fetch

Instruction dispatch (See Note)

Instruction decode

.D1.M1.S1.L1

.D2 .M2 .S2 .L2

Control

registers

Control

logic

Test

Emulation

Interrupts

Additional

peripherals:

Timers,

serial ports,

etc.

1-7IntroductionSPRU733

TMS320C67x DSP Architecture

1.4.1 Central Processing Unit (CPU)

The C67x CPU, in Figure 1−1, is common to all the C62x/C64x/C67x devices. The CPU contains:

 Program fetch unit  Instruction dispatch unit  Instruction decode unit  Two data paths, each with four functional units  32 32-bit registers  Control registers  Control logic  Test, emulation, and interrupt logic

The program fetch, instruction dispatch, and instruction decode units can deliver up to eight 32-bit instructions to the functional units every CPU clock cycle. The processing of instructions occurs in each of the two data paths (A and B), each of which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general-purpose registers. The data paths are described in more detail in Chapter 2. A control register file provides the means to configure and control various processor operations. To understand how instructions are fetched, dispatched, decoded, and executed in the data path, see Chapter 4.

1.4.2 Internal Memory

The C67x DSP has a 32-bit, byte-addressable address space. Internal (on-chip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF).

The C67x DSP has two 32-bit internal ports to access internal data memory. The C67x DSP has a single internal port to access internal program memory, with an instruction-fetch width of 256 bits.

1.4.3 Memory and Peripheral Options

A variety of memory and peripheral options are available for the C6000 platform:

 Large on-chip RAM, up to 7M bits

 Program cache

 2-level caches

 32-bit external memory interface supports SDRAM, SBSRAM, SRAM,

and other asynchronous memories for a broad range of external memory requirements and maximum system performance.

Introduction1-8 SPRU733

TMS320C67x DSP Architecture

DMA Controller (C6701 DSP only) transfers data between address ranges



in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel.

 EDMA Controller performs the same functions as the DMA controller. The

EDMA has 16 programmable channels, as well as a RAM space to hold multiple configurations for future transfers.

 HPI is a parallel port through which a host processor can directly access

the CPU’s memory space. The host device has ease of access because it is the master of the interface. The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals.

 Expansion bus is a replacement for the HPI, as well as an expansion of

the EMIF. The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. The host port of the expansion bus can operate in either asynchronous slave mode, similar to the HPI, or in synchronous master/slave mode. This allows the device to interface to a variety of host bus protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may interface to the expansion bus.

 McBSP (multichannel buffered serial port) is based on the standard serial

port interface found on the TMS320C2000™ and TMS320C5000™ devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDNA controller. It also has multichannel capability compatible with the T1, E1, SCSA, and MVIP networking standards.

 Timers in the C6000 devices are two 32-bit general-purpose timers used

for these functions:

 Time events  Count events  Generate pulses  Interrupt the CPU  Send synchronization events to the DMA/EDMA controller.

 Power-down logic allows reduced clocking to reduce power consumption.

Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another. By preventing some or all of the chip’s logic from switching, you can realize significant power savings without losing any data or operational context.

For an overview of the peripherals available on the C6000 DSP, refer to the TM320C6000 DSP Peripherals Overview Reference Guide (SPRU190).

1-9IntroductionSPRU733

Chapter 2

CPU Data Paths and Control

This chapter focuses on the CPU, providing information about the data paths and control registers. The two register files and the data cross paths are described.

Topic Page

2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 General-Purpose Register Files 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Functional Units 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Register File Cross Paths 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Memory, Load, and Store Paths 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Data Address Paths 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Control Register File 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Control Register File Extensions 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1CPU Data Paths and ControlSPRU733

Introduction

Introduction / General-Purpose Register Files

2.1 Introduction

The components of the data path for the TMS320C67x CPU are shown in Figure 2−1. These components consist of:

 Two general-purpose register files (A and B)  Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2)  Two load-from-memory data paths (LD1 and LD2)  Two store-to-memory data paths (ST1 and ST2)  Two data address paths (DA1 and DA2)  Two register file data cross paths (1X and 2X)

2.2 General-Purpose Register Files

There are two general-purpose register files (A and B) in the C6000 data paths. For the C67x DSP, each of these files contains 16 32-bit registers (A0–A15 for file A and B0–B15 for file B), as shown in Table 2−1. For the C67x+ DSP, the register file size is doubled to 32 32-bit registers (A0–A31 for file A and B0–B21 for file B), as shown in Table 2−1. The general-purpose registers can be used for data, data address pointers, or condition registers.

The C67x DSP general-purpose register files support data ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating point data. Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored in register pairs. In these the 32 LSBs of data are placed in an evennumbered register and the remaining 8 or 32 MSBs in the next upper register (that is always an odd-numbered register). Packed data types store either four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values in a 64-bit register pair.

There are 16 valid register pairs for 40-bit and 64-bit data in the C67x DSP cores. In assembly language syntax, a colon between the register names denotes the register pairs, and the odd-numbered register is specified first.

The additional registers are addressed by using the previously unused fifth (msb) bit of the source and register specifiers. All 64-bit register writes and reads are performed over 2 cycles as per the current C67x devices.

Figure 2−2 shows the register storage scheme for 40-bit long data. Operations requiring a long input ignore the 24 MSBs of the odd-numbered register. Operations producing a long result zero-fill the 24 MSBs of the odd-numbered register. The even-numbered register is encoded in the opcode.

CPU Data Paths and Control2-2 SPRU733

Figure 2−1. TMS320C67x CPU Data Paths

LD1 32 MSB

ST1

Data path A

LD1 32 LSB

DA1

.L1

long dst

long src

long src long dst

.S1

.M1

.D1

src1

src2

dst

src1

src2

dst

src1

src2

dst

src1

src2

General-Purpose Register Files

(A0−A15)

Data path B

DA2

LD2 32 LSB

LD2 32 MSB

ST2

.D2

.M2

.S2

long dst

long src

long src long dst

.L2

src2

src1

dst

src2

src1

dst

src2

src1

dst

src2

src1

(B0−B15)

Control register

file

2-3CPU Data Paths and ControlSPRU733

General-Purpose Register Files

Table 2−1. 40-Bit/64-Bit Register Pairs

A B

A1:A0 B1:B0 C67x DSP

A3:A2 B3:B2

A5:A4 B5:B4

A7:A6 B7:B6

A9:A8 B9:B8

A11:A10 B11:B10

A13:A12 B13:B12

A15:A14 B15:B14

A17:A16 B17:B16 C67x+ DSP only

A19:A18 B19:B18

A21:A20 B21:B20

A23:A22 B23:B22

A25:A24 B25:B24

A27:A26 B27:B26

A29:A28 B29:B28

A31:A30 B31:B30

Devices

Figure 2−2. Storage Scheme for 40-Bit Data in a Register Pair

31 0 31 0

Odd register Even register

Ignored

Odd register Even register

Zero-filled

CPU Data Paths and Control2-4 SPRU733

Read from registers

39 32 31 0

Write to registers

39 32 31 0

40-bit data

+ 435 hidden pages

Texas Instruments TMS320C67X User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

IMPORTANT NOTICE

About This Manual

Notational Conventions

Read This First

Related Documentation From Texas Instruments

Trademarks

Contents

Figures

Tables

Examples

1.1 TMS320 DSP Family Overview

1.2 TMS320C6000 DSP Family Overview

1.3 TMS320C67x DSP Features and Options

1.4 TMS320C67x DSP Architecture

1.4.1 Central Processing Unit (CPU)

1.4.2 Internal Memory

1.4.3 Memory and Peripheral Options

2.1 Introduction

2.2 General-Purpose Register Files