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TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor

1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor

1.1 Features

1

• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library

• 375- and 456-MHz TMS320C674x VLIW DSP

• C674x Instruction Set Features
– Superset of the C67x+ and C64x+ ISAs
– Up to 3648 MIPS and 2736 MFLOPS C674x
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions

• C674x Two-Level Cache Memory Architecture
– 32KB of L1P Program RAM/Cache
– 32KB of L1D Data RAM/Cache
– 256KB of L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)

• Enhanced Direct Memory Access Controller 3
(EDMA3):

– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size

• TMS320C674x Fixed- and Floating-Point VLIW
DSP Core

– Load-Store Architecture with Nonaligned

Support
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32- and 40-Bit) Functional Units

– Supports 32-Bit Integer, SP (IEEE Single

Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point

– Supports up to Four SP Additions Per Clock,

Four DP Additions Every 2 Clocks

– Supports up to Two Floating-Point (SP or DP)

Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle

– Two Multiply Functional Units

– Mixed-Precision IEEE Floating Point Multiply

Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks

– Fixed-Point Multiply Supports Two 32 x 32-Bit

1

• 128KB of RAM Shared Memory (TMS320C6747

• 3.3-V LVCMOS I/Os (Except for USB Interfaces)

• Two External Memory Interfaces:

• Three Configurable 16550-Type UART Modules:

• LCD Controller (TMS320C6747 Only)

• Two Serial Peripheral Interfaces (SPIs) Each with

• Multimedia Card (MMC)/Secure Digital (SD) Card

• Two Master and Slave Inter-Integrated Circuit (I2C

• One Host-Port Interface (HPI) with 16-Bit-Wide

• Programmable Real-Time Unit Subsystem

Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle, and

Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop

Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and

Program Redirection
Only)

– EMIFA

– NOR (8- or 16-Bit-Wide Data)

– NAND (8- or 16-Bit-Wide Data)

– 16-Bit SDRAM with 128-MB Address Space

(TMS320C6747 Only)

– EMIFB

– 32-Bit or 16-Bit SDRAM with 256-MB

Address Space (TMS320C6747)

– 16-Bit SDRAM with 128-MB Address Space

(TMS320C6745)

– UART0 with Modem Control Signals
– Autoflow Control Signals (CTS, RTS) on UART0

Only
– 16-Byte FIFO
– 16x or 13x Oversampling Option

One Chip Select
Interface with Secure Data I/O (SDIO)
Bus™)
Muxed Address/Data Bus for High Bandwidth

(TMS320C6747 Only)
(PRUSS)

– Two Independent Programmable Realtime Unit

(PRU) Cores

– 32-Bit Load and Store RISC Architecture

– 4KB of Instruction RAM per Core

– 512 Bytes of Data RAM per Core

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

www.ti.com

– PRUSS can be Disabled via Software to

Save Power

– Standard Power-Management Mechanism

– Clock Gating
– Entire Subsystem Under a Single PSC Clock

Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource

• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
(TMS320C6747 Only)

• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client

(TMS320C6747)
– USB 2.0 Full-Speed Client (TMS320C6745)
– USB 2.0 High-, Full-, and Low-Speed Host

(TMS320C6747)
– USB 2.0 Full- and Low-Speed Host

(TMS320C6745)
– High-Speed Functionality Available on

TMS320C6747 Device Only
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or

ISOC) RX and TX

• Three Multichannel Audio Serial Ports (McASPs):
– TMS320C6747 Supports 3 McASPs
– TMS320C6745 Supports 2 McASPs
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO Buffers for Transmit and Receive

• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)

– RMII Media-Independent Interface
– Management Data I/O (MDIO) Module

• Real-Time Clock with 32-kHz Oscillator and
Separate Power Rail (TMS320C6747 Only)

• One 64-Bit General-Purpose Timer (Configurable
as Two 32-Bit Timers)

• One 64-Bit General-Purpose Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)

• Three Enhanced Pulse Width Modulators
(eHRPWMs):

– Dedicated 16-Bit Time-Base Counter with

Period and Frequency Control

– 6 Single Edge, 6 Dual Edge Symmetric, or 3

Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input

• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary

Pulse Width Modulator (APWM) Outputs

– Single-Shot Capture of up to Four Event Time-

Stamps

• Two 32-Bit Enhanced Quadrature Encoder Pulse
(eQEP) Modules

• TMS320C6747 Device:
– 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)

[ZKB Suffix], 1.0-mm Ball Pitch

• TMS320C6745 Device:
– 176-pin PowerPAD™ Plastic Quad Flat Pack

[PTP suffix], 0.5-mm Pin Pitch

• Commercial, Industrial, Extended, or Automotive
Temperature

1.2 Applications

• A/V Receivers

• Automotive Amplifiers

• Soundbars

1.3 Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set­associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.

2

TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal
Processor

• Home Theatre Systems

• Professional Audio

• Network Streaming Audio

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The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output
(MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers
and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a
configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general­purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other
peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit
enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an
asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a
higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the
TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10
Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for
PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Device Information

PART NUMBER PACKAGE BODY SIZE

TMS320C6745 HLQFP (176) 24.00 mm x 24.00 mm
TMS320C6747 BGA (256) 17.00 mm x 17.00 mm

(1) For more information on these devices, see Section 8, Mechanical Packaging and Orderable

Information.

(1)

Copyright © 2008–2014, Texas Instruments Incorporated

Product Folder Links: TMS320C6745 TMS320C6747

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Processor

3

Switched Central Resource (SCR)

BOOT ROM

256KB L2 RAM

32KB

L1 RAM

32KB

L1 Pgm

AET

C674x

DSP CPU

DSP Subsystem

JTAG Interface

Serial Interfaces

I C
(2)

2

SPI

(2)

UART

(3)

Audio Ports

McASP
w/FIFO

(2)

DMA

Peripherals

External Memory Interfaces

Connectivity

EDMA3

Control Timers

eHRPWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

USB2.0

OTG Ctlr

PHY

MMC/SD

(8b)

EMIFA(8b)

NAND/Flash

EMIFB

SDRAM Only

(16b)

GPIO

PRU

Subsystem

System Control

Input

Clock(s)

Power/Sleep

Controller

Memory

Protection

Pin

Multiplexing

PLL/Clock
Generator

w/OSC

General­Purpose

Timer

General­Purpose

Timer

(Watchdog)

Switched Central Resource (SCR)

BOOT ROM

256KB L2 RAM

32KB

L1 RAM

32KB

L1 Pgm

AET

C674x

DSP CPU

DSP Subsystem

JTAG Interface

Serial Interfaces

I C

(2)

2

SPI

(2)

UART

(3)

Audio Ports

McASP
w/FIFO

(3)

DMA

Peripherals

Display

Internal Memory

LCD

Ctlr

128KB

RAM

External Memory Interfaces

Connectivity

EDMA3

Control Timers

eHRPWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

USB1.1

OHCI Ctlr

PHY

USB2.0

OTG Ctlr

PHY

HPI

MMC/SD

(8b)

EMIFA(8b/16B)

NAND/Flash
16b SDRAM

EMIFB

SDRAM Only

(16b/32b)

GPIO

PRU

Subsystem

System Control

Input

Clock(s)

Power/Sleep

Controller

Memory

Protection

Pin

Multiplexing

RTC/

32-kHz

OSC

PLL/Clock
Generator

w/OSC

General­Purpose

Timer

General­Purpose

Timer

(Watchdog)

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

1.4 Functional Block Diagram

www.ti.com

Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.

Figure 1-1. TMS320C6747 Functional Block Diagram

4

Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.

TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal

Figure 1-2. TMS320C6745 Functional Block Diagram

Processor

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TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table of Contents

1 TMS320C6745, TMS320C6747 Fixed- and

Floating-Point Digital Signal Processor............. 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 4

2 Revision History ......................................... 6

3 Device Overview ......................................... 8

3.1 Device Characteristics................................ 8

3.2 Device Compatibility.................................. 9

3.3 DSP Subsystem..................................... 10

3.4 Memory Map Summary ............................. 21

3.5 Pin Assignments .................................... 26

3.6 Terminal Functions.................................. 28

4 Device Configuration .................................. 56

4.1 Boot Modes ......................................... 56

4.2 SYSCFG Module.................................... 57

4.3 Pullup/Pulldown Resistors .......................... 59

5 Device Operating Conditions ........................ 60

5.1 Absolute Maximum Ratings Over Operating Case
Temperature Range

(Unless Otherwise Noted) ................................. 60

5.2 Handling Ratings .................................... 60

5.3 Recommended Operating Conditions............... 61

5.4 Notes on Recommended Power-On Hours (POH) . 62

5.5 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 63

6 Peripheral Information and Electrical

Specifications........................................... 64

6.1 Parameter Information .............................. 64

6.2 Recommended Clock and Control Signal Transition

Behavior............................................. 65

6.3 Power Supplies...................................... 65

6.4 Reset ................................................ 66

6.5 Crystal Oscillator or External Clock Input........... 69

6.6 Clock PLLs .......................................... 71

6.7 Interrupts ............................................ 75

6.8 General-Purpose Input/Output (GPIO).............. 79

6.9 EDMA ............................................... 82

6.10 External Memory Interface A (EMIFA) .............. 87

6.11 External Memory Interface B (EMIFB) .............. 98

6.12 Memory Protection Units .......................... 106

6.13 MMC / SD / SDIO (MMCSD)....................... 109

6.14 Ethernet Media Access Controller (EMAC) ........ 112

6.15 Management Data Input/Output (MDIO)........... 117

6.16 Multichannel Audio Serial Ports (McASP0, McASP1,

and McASP2) ...................................... 119

6.17 Serial Peripheral Interface Ports (SPI0, SPI1)..... 132

6.18 Enhanced Capture (eCAP) Peripheral............. 151

6.19 Enhanced Quadrature Encoder (eQEP)

Peripheral .......................................... 154

6.20 Enhanced High-Resolution Pulse-Width Modulator

(eHRPWM)......................................... 156

6.21 LCD Controller ..................................... 160

6.22 Timers.............................................. 175

6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 177

6.24 Universal Asynchronous Receiver/Transmitter

(UART)............................................. 182

6.25 USB1 Host Controller Registers (USB1.1 OHCI) .. 184

6.26 USB0 OTG (USB2.0 OTG) ........................ 185

6.27 Host-Port Interface (UHPI)......................... 193

6.28 Power and Sleep Controller (PSC) ................ 200

6.29 Programmable Real-Time Unit Subsystem

(PRUSS) ........................................... 203

6.30 Emulation Logic .................................... 206

6.31 IEEE 1149.1 JTAG ................................ 209

6.32 Real Time Clock (RTC) ............................ 211

7 Device and Documentation Support.............. 214

7.1 Device Support..................................... 214

7.2 Documentation Support............................ 215

7.3 Support Resources ................................ 216

7.4 Related Links ...................................... 216

7.5 Trademarks ........................................ 216

7.6 Electrostatic Discharge Caution ................... 216

7.7 Glossary............................................ 216

8 Mechanical Packaging and Orderable

Information............................................. 217

8.1 Thermal Data for ZKB ............................. 217

8.2 Thermal Data for PTP ............................. 218

8.3 Supplementary Information About the 176-pin PTP

PowerPAD™ Package............................. 218

8.4 Packaging Information ............................. 219

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Table of ContentsCopyright © 2008–2014, Texas Instruments Incorporated

5

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the changes made to the SPRS377E device-specific data
manual to make it an SPRS377F revision.

Scope: Applicable updates to the TMS320C6747/C6745 Fixed- and Floating-Point Digital Signal
Processor device family, specifically relating to the TMS320C6747 and TMS320C6745 devices, which are
all now in the production data (PD) stage of development, have been incorporated.

SEE ADDITIONS/MODIFICATIONS/DELETIONS

• Turned on Navigation Icons on top of first page.

Global

Section 1.1

Features

Section 1.2

Applications

Section 1.3

Description

Section 3.3.2.3

C674x CPU

Section 3.6

Terminal Functions

Section 3.6.11

Universal
Asynchronous
Receiver/Transmitter
s (UART0, UART1,
UART2)

Section 3.6.21

Reserved and No
Connect

Section 3.6.23

Unused USB0
(USB2.0) and USB1
(USB1.1) Pin
Configurations

Section 5

Device Operating
Conditions

Section 5.4

Notes on
Recommended
Power-On Hours
(POH)

Section 6.10.6

EMIFA Electrical
Data/Timing

• Updated Features, Applications, and Description for consistency and translation.

• Moved Trademarks information from first page to within Section 7, Device and Documentation Support.

• Moved ESDS Warning to within Section 7, Device and Documentation Support.
Deleted Highlights section. Information was duplicated elsewhere in Features.

Added NEW section.

Added NEW Device Information Table.

Table 3-2, C674x Cache Registers:

• Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from
"...See the System reference Guide..." to "See the Technical Reference Manual..."

Table 3-21, Universal Serial Bus (USB) Terminal Functions:

• Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF
capacitor..." to "...is recommended to be connected via a 0.22-μF capacitor..."

Table 3-16, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:

• Updated/Changed footnote from "...DSP Reference Guide - Literature Number SPRUFK4..." to "...DSP
Technical Reference Manual (SPRUH91)..."

Table 3-26, Reserved and No Connect Terminal Functions:

• Updated/Changed RSV4 DESCRIPTION from "...This pin may be tied high or low." to "...For proper
device operation, this pin must be tied low or to CVDD."

Moved to within Section 3.6, Terminal Functions

Table 3-28, Unused USB0 and USB1 Pin Configurations:

• Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and
changing text to "Internal USB0 PHY output connected to an external..."

Section 5.2, Handling Ratings:

• Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings
table.

Table 5-1, Recommended Power-On Hours:

• Added Silicon Revision column.

Table 6-22, EMIFA Asynchronous Memory Switching Characteristics:

• Updated/Changed the MIN, NOM, and MAX equations for NO. 3, 10, 15, and 24 from "...(EWC*16)..." to
"...EWC..."

Section 5.3, Recommended Operating Conditions:

• Added "Unless specifically indicated" to "These I/O specifications apply to ..." footnote

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Revision History

6

Revision History Copyright © 2008–2014, Texas Instruments Incorporated

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Revision History (continued)

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Table 6-26, EMIFB SDRAM Interface Timing Requirements:

Section 6.11.3

EMIFB Electrical
Data/Timing

Section 6.16

Multichannel Audio
Serial Ports
(McASP0, McASP1,
and McASP2)

Section 7.4

Related Links

Section 7.7

Glossary

• Updated/Changed Parameter No. 19 from "t

• Added new column: "CVDD = 1.3V"

• Added new footnote containing "...range rated devices for 456 MHz max CPU operating..."

• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
operating ..."

Table 6-27, EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature

Range:

• Updated/Changed table title from "...Switching Characteristics..." to "...Switching Characteristics for
Commercial (Default) Temperature Range"

• Added new footnote containing "...range rated devices for 456 MHz max CPU operating ..."

• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
operating..."

• Updated/Changed CVDD = 1.3V MIN column values for Parameter No. 4, 6, 8, 10, 12, 14, 16, and 18
from "0.9" to "1.1"

• Updated/Changed CVDD = 1.3V MAX column values for Parameter No. 3, 5, 7, 9, 11, 13, 15, and 17
from "5.1" to "4.25"

• Populated CVDD = 1.2V column with values (was empty)

• Updated/Changed Parameter No. 18 from "t

Table 6-28, EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive

Temperature Ranges:

• Added NEW table

Table 6-45, McASP Registers Accessed Through DMA Port:

• Updated/Changed Read Accesses Register Description from "XBUSEL = 0 in XFMT" to "RBUSEL = 0 in
RFMT"

• Updated/Changed Write Accesses Register Description from "RBUSEL = 0 in RFMT" to "XBUSEL = 0 in
XFMT"

Added NEW section.

Added NEW section.

su(DV-CLKH)

ena(CLKH-DLZ)

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

" to "t

" to "t

(DV-CLKH)

"

(CLKH-DLZ)

"

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Revision HistoryCopyright © 2008–2014, Texas Instruments Incorporated

7

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the C6745/6747 low power digital signal processor. The table shows

significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.

Table 3-1. Characteristics of the C6745/C6747 Processor

HARDWARE FEATURES C6745 C6747

EMIFB 16bit, up to 128MB SDRAM 16/32bit, up to 256MB SDRAM

EMIFA

Flash Card Interface MMC and SD cards supported.
EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers

Timers
UART 3 (one with RTS and CTS flow control)

SPI 2 (each with one hardware chip select)
I2C 2 (both Master/Slave)
Multichannel Audio

Serial Port [McASP]

Peripherals
Not all peripherals pins

are available at the
same time (for more
detail, see the Device
Configurations section).

On-Chip Memory

10/100 Ethernet MAC
with Management Data
I/O

eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
eQEP 2 32-bit QEP channels with 4 inputs/channel
UHPI - 1 (16-bit multiplexed address/data)

USB 2.0 (USB0)

USB 1.1 (USB1) ­General-Purpose

Input/Output Port
LCD Controller - 1

RTC -

PRU Subsystem
(PRUSS)

Size (Bytes) 320 KB RAM 448 KB RAM

Organization

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Asynchronous (8-bit bus width) RAM,

Flash, NOR, NAND

2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable

as Watch Dog)

2 (each with transmit/receive, FIFO buffer,

16/9 serializers)

1 (RMII Interface)

Full Speed Host Or Device with On-Chip

PHY

8 banks of 16-bit

2 Programmable PRU Cores

32KB L1 Program (L1P)/Cache (up to 32KB)

32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)

DSP Memories can be made accessible to EDMA3, and other peripherals.

Asynchronous (8/16-bit bus width) RAM,

Flash, 16bit up to 128MB SDRAM, NOR,

NAND

3 (each with transmit/receive, FIFO buffer,

16/9 serializers)

High-Speed OTG Controller with on-chip

OTG PHY

Full-Speed OHCI (as host) with on-chip

PHY

1 (32 KHz oscillator and seperate power

trail. Provides time and date tracking and

alarm capability.)

DSP

C674x CPU ID + CPU
Rev ID

C674x Megamodule
Revision

8

Device Overview Copyright © 2008–2014, Texas Instruments Incorporated

Control Status Register
(CSR.[31:16])

Revision ID Register
(MM_REVID[15:0])

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ADDITIONAL MEMORY

128KB RAM

0x1400

0x0000

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-1. Characteristics of the C6745/C6747 Processor (continued)

HARDWARE FEATURES C6745 C6747

JTAG BSDL_ID DEVIDR0 register

CPU Frequency MHz 674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)

Voltage

Package

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

Core (V) 1.2V / 1.3V
I/O (V) 3.3 V

24 mm x 24 mm, 176-Pin, 0.5 mm pitch,

TQFP (PTP)

Product Preview (PP),
Advance Information
(AI),
or Production Data
(PD)

0x0B7D F02F (Silicon Revision 1.0)
0x8B7D F02F (Silicon Revision 1.1)

0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)

17 mm x 17 mm, 256-Ball 1 mm pitch,

PBGA (ZKB)

375 MHz Versions -PD

456 MHz Version - PD

3.2 Device Compatibility

The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.

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9

Instruction Fetch

C674x

Fixed/Floating Point CPU

Register

File A

Register

File B

Cache Control

Memory Protect

Bandwidth Mgmt

L1P

256

Cache Control

Memory Protect

Bandwidth Mgmt

L1D

64 64

8 x 32

32K Bytes
L1D RAM/

Cache

32K Bytes

L1P RAM/

Cache

256

Cache Control

Memory Protect

Bandwidth Mgmt

L2

256K Bytes

L2 RAM

256

Boot ROM

256

CFG

MDMA SDMA

EMC

Power Down

Interrupt

Controller

IDMA

256

256

256

256

256

64

High

Performance

Switch Fabric

64

64 64

Configuration

Peripherals

Bus

32

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3.3 DSP Subsystem

The DSP Subsystem includes the following features:

• C674x DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 32KB L1 Data (L1D)/Cache (up to 32KB)

• 256KB Unified Mapped RAM/Cache (L2)

• Boot ROM (cannot be used for application code)

• Little endian

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Figure 3-1. C674x Megamodule Block Diagram

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3.3.1 C674x DSP CPU Description

The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32­bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40­bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.

The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on
a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.

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• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free­running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)

• TMS320C64x Technical Overview (SPRU395)

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src2

src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

src1

src1

src1

even dst

even dst

odd dst

dst1

dst

src2

src2

src2

long src

DA1

ST1b

LD1b

LD1a

ST1a

Data path A

Odd

register

file A

(A1, A3,

A5...A31)

Odd

register

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a
LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a

ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB

32 LSB

dst2

(A)

32 MSB

32 LSB

2x

1x

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B)

(A)

8

8

8

8

32

32

32

32

(C)

(C)

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

(D)

(D)

(D)

(D)

A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

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Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths

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3.3.2 DSP Memory Mapping

The DSP memory map is shown in Section 3.4.

3.3.2.1 External Memories

The DSP has access to the following External memories:

• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)

• SDRAM (EMIFB)

3.3.2.2 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

3.3.2.3 C674x CPU

The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.

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Table 3-2 shows a memory map of the C674x CPU cache registers for the device.

Table 3-2. C674x Cache Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 0000 L2CFG

0x0184 0020 L1PCFG
0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register
0x0184 0040 L1DCFG
0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2

0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register
0x0184 4004 L2WWC L2 writeback word count register
0x0184 4010 L2WIBAR L2 writeback invalidate base address register
0x0184 4014 L2WIWC L2 writeback invalidate word count register
0x0184 4018 L2IBAR L2 invalidate base address register

0x0184 401C L2IWC L2 invalidate word count register

0x0184 4020 L1PIBAR L1P invalidate base address register
0x0184 4024 L1PIWC L1P invalidate word count register
0x0184 4030 L1DWIBAR L1D writeback invalidate base address register
0x0184 4034 L1DWIWC L1D writeback invalidate word count register

L2 Cache configuration register (See the Technical Reference Manual

SPRUH91 for the reset configuration)

L1P Size Cache configuration register (See the Technical Reference
Manual SPRUH91 for the reset configuration)

L1D Size Cache configuration register (See the Technical Reference
Manual SPRUH91 for the reset configuration)

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Table 3-2. C674x Cache Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 4038 - Reserved
0x0184 4040 L1DWBAR L1D writeback base address register
0x0184 4044 L1DWWC L1D writeback word count register
0x0184 4048 L1DIBAR L1D invalidate base address register

0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register
0x0184 5004 L2WBINV L2 writeback invalidate all register
0x0184 5008 L2INV L2 Global Invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P Global Invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D Global Writeback
0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate
0x0184 5048 L1DINV L1D Global Invalidate without writeback

0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 8100 – 0x0184 817F MAR64 – MAR95

0x0184 8180 – 0x0184 8187 MAR96 - MAR97

0x0184 8188 – 0x0184 818F MAR98 – MAR99

0x0184 8190 – 0x0184 8197 MAR100 – MAR101

0x0184 8198 – 0x0184 819F MAR102 – MAR103

0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF

0x0184 8200 MAR128

0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF
0x0184 8300 – 0x0184 837F MAR192 – MAR223
0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF

Memory Attribute Registers for EMIFA SDRAM Data (CS0)
0x4000 0000 – 0x5FFF FFFF

Memory Attribute Registers for EMIFA Async Data (CS2)
0x6000 0000 – 0x61FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS3)
0x6200 0000 – 0x63FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS4)
0x6400 0000 – 0x65FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS5)
0x6600 0000 – 0x67FF FFFF

Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF

Memory Attribute Registers for EMIFB SDRAM Data (CS0)
0xC000 0000 – 0xDFFF FFFF

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Table 3-3. C674x L1/L2 Memory Protection Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 A000 L2MPFAR L2 memory protection fault address register
0x0184 A004 L2MPFSR L2 memory protection fault status register
0x0184 A008 L2MPFCR L2 memory protection fault command register

0x0184 A00C - 0x0184 A0FF - Reserved

0x0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]
0x0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]
0x0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]

0x0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]

0x0184 A110 L2MPLKCMD L2 memory protection lock key command register
0x0184 A114 L2MPLKSTAT L2 memory protection lock key status register

0x0184 A118 - 0x0184 A1FF - Reserved

0x0184 A200 L2MPPA0

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L2 memory protection page attribute register 0
(controls memory address 0x0080 0000 - 0x0080 1FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 A204 L2MPPA1

0x0184 A208 L2MPPA2

0x0184 A20C L2MPPA3

0x0184 A210 L2MPPA4

0x0184 A214 L2MPPA5

0x0184 A218 L2MPPA6

0x0184 A21C L2MPPA7

0x0184 A220 L2MPPA8

0x0184 A224 L2MPPA9

0x0184 A228 L2MPPA10

0x0184 A22C L2MPPA11

0x0184 A230 L2MPPA12

0x0184 A234 L2MPPA13

0x0184 A238 L2MPPA14

0x0184 A23C L2MPPA15

0x0184 A240 L2MPPA16

0x0184 A244 L2MPPA17

0x0184 A248 L2MPPA18

0x0184 A24C L2MPPA19

0x0184 A250 L2MPPA20

0x0184 A254 L2MPPA21

0x0184 A258 L2MPPA22

0x0184 A25C L2MPPA23

0x0184 A260 L2MPPA24

0x0184 A264 L2MPPA25

0x0184 A268 L2MPPA26

0x0184 A26C L2MPPA27

0x0184 A270 L2MPPA28

L2 memory protection page attribute register 1
(controls memory address 0x0080 2000 - 0x0080 3FFF)

L2 memory protection page attribute register 2
(controls memory address 0x0080 4000 - 0x0080 5FFF)

L2 memory protection page attribute register 3
(controls memory address 0x0080 6000 - 0x0080 7FFF)

L2 memory protection page attribute register 4
(controls memory address 0x0080 8000 - 0x0080 9FFF)

L2 memory protection page attribute register 5
(controls memory address 0x0080 A000 - 0x0080 BFFF)

L2 memory protection page attribute register 6
(controls memory address 0x0080 C000 - 0x0080 DFFF)

L2 memory protection page attribute register 7
(controls memory address 0x0080 E000 - 0x0080 FFFF)

L2 memory protection page attribute register 8
(controls memory address 0x0081 0000 - 0x0081 1FFF)

L2 memory protection page attribute register 9
(controls memory address 0x0081 2000 - 0x0081 3FFF)

L2 memory protection page attribute register 10
(controls memory address 0x0081 4000 - 0x0081 5FFF)

L2 memory protection page attribute register 11
(controls memory address 0x0081 6000 - 0x0081 7FFF)

L2 memory protection page attribute register 12
(controls memory address 0x0081 8000 - 0x0081 9FFF)

L2 memory protection page attribute register 13
(controls memory address 0x0081 A000 - 0x0081 BFFF)

L2 memory protection page attribute register 14
(controls memory address 0x0081 C000 - 0x0081 DFFF)

L2 memory protection page attribute register 15
(controls memory address 0x0081 E000 - 0x0081 FFFF)

L2 memory protection page attribute register 16
(controls memory address 0x0082 0000 - 0x0082 1FFF)

L2 memory protection page attribute register 17
(controls memory address 0x0082 2000 - 0x0082 3FFF)

L2 memory protection page attribute register 18
(controls memory address 0x0082 4000 - 0x0082 5FFF)

L2 memory protection page attribute register 19
(controls memory address 0x0082 6000 - 0x0082 7FFF)

L2 memory protection page attribute register 20
(controls memory address 0x0082 8000 - 0x0082 9FFF)

L2 memory protection page attribute register 21
(controls memory address 0x0082 A000 - 0x0082 BFFF)

L2 memory protection page attribute register 22
(controls memory address 0x0082 C000 - 0x0082 DFFF)

L2 memory protection page attribute register 23
(controls memory address 0x0082 E000 - 0x0082 FFFF)

L2 memory protection page attribute register 24
(controls memory address 0x0083 0000 - 0x0083 1FFF)

L2 memory protection page attribute register 25
(controls memory address 0x0083 2000 - 0x0083 3FFF)

L2 memory protection page attribute register 26
(controls memory address 0x0083 4000 - 0x0083 5FFF)

L2 memory protection page attribute register 27
(controls memory address 0x0083 6000 - 0x0083 7FFF)

L2 memory protection page attribute register 28
(controls memory address 0x0083 8000 - 0x0083 9FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 A274 L2MPPA29

0x0184 A278 L2MPPA30

0x0184 A27C L2MPPA31

0x0184 A280 L2MPPA32

0x0184 A284 L2MPPA33

0x0184 A288 L2MPPA34

0x0184 A28C L2MPPA35

0x0184 A290 L2MPPA36

0x0184 A294 L2MPPA37

0x0184 A298 L2MPPA38

0x0184 A29C L2MPPA39

0x0184 A2A0 L2MPPA40

0x0184 A2A4 L2MPPA41

0x0184 A2A8 L2MPPA42

0x0184 A2AC L2MPPA43

0x0184 A2B0 L2MPPA44

0x0184 A2B4 L2MPPA45

0x0184 A2B8 L2MPPA46

0x0184 A2BC L2MPPA47

0x0184 A2C0 L2MPPA48

0x0184 A2C4 L2MPPA49

0x0184 A2C8 L2MPPA50

0x0184 A2CC L2MPPA51

0x0184 A2D0 L2MPPA52

0x0184 A2D4 L2MPPA53

0x0184 A2D8 L2MPPA54

0x0184 A2DC L2MPPA55

0x0184 A2E0 L2MPPA56

L2 memory protection page attribute register 29
(controls memory address 0x0083 A000 - 0x0083 BFFF)

L2 memory protection page attribute register 30
(controls memory address 0x0083 C000 - 0x0083 DFFF)

L2 memory protection page attribute register 31
(controls memory address 0x0083 E000 - 0x0083 FFFF)

L2 memory protection page attribute register 32
(controls memory address 0x0070 0000 - 0x0070 7FFF)

L2 memory protection page attribute register 33
(controls memory address 0x0070 8000 - 0x0070 FFFF)

L2 memory protection page attribute register 34
(controls memory address 0x0071 0000 - 0x0071 7FFF)

L2 memory protection page attribute register 35
(controls memory address 0x0071 8000 - 0x0071 FFFF)

L2 memory protection page attribute register 36
(controls memory address 0x0072 0000 - 0x0072 7FFF)

L2 memory protection page attribute register 37
(controls memory address 0x0072 8000 - 0x0072 FFFF)

L2 memory protection page attribute register 38
(controls memory address 0x0073 0000 - 0x0073 7FFF)

L2 memory protection page attribute register 39
(controls memory address 0x0073 8000 - 0x0073 FFFF)

L2 memory protection page attribute register 40
(controls memory address 0x0074 0000 - 0x0074 7FFF)

L2 memory protection page attribute register 41
(controls memory address 0x0074 8000 - 0x0074 FFFF)

L2 memory protection page attribute register 42
(controls memory address 0x0075 0000 - 0x0075 7FFF)

L2 memory protection page attribute register 43
(controls memory address 0x0075 8000 - 0x0075 FFFF)

L2 memory protection page attribute register 44
(controls memory address 0x0076 0000 - 0x0076 7FFF)

L2 memory protection page attribute register 45
(controls memory address 0x0076 8000 - 0x0076 FFFF)

L2 memory protection page attribute register 46
(controls memory address 0x0077 0000 - 0x0077 7FFF)

L2 memory protection page attribute register 47
(controls memory address 0x0077 8000 - 0x0077 FFFF)

L2 memory protection page attribute register 48
(controls memory address 0x0078 0000 - 0x0078 7FFF)

L2 memory protection page attribute register 49
(controls memory address 0x0078 8000 - 0x0078 FFFF)

L2 memory protection page attribute register 50
(controls memory address 0x0079 0000 - 0x0079 7FFF)

L2 memory protection page attribute register 51
(controls memory address 0x0079 8000 - 0x0079 FFFF)

L2 memory protection page attribute register 52
(controls memory address 0x007A 0000 - 0x007A 7FFF)

L2 memory protection page attribute register 53
(controls memory address 0x007A 8000 - 0x007A FFFF)

L2 memory protection page attribute register 54
(controls memory address 0x007B 0000 - 0x007B 7FFF)

L2 memory protection page attribute register 55
(controls memory address 0x007B 8000 - 0x007B FFFF)

L2 memory protection page attribute register 56
(controls memory address 0x007C 0000 - 0x007C 7FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 A2E4 L2MPPA57

0x0184 A2E8 L2MPPA58

0x0184 A2EC L2MPPA59

0x0184 A2F0 L2MPPA60

0x0184 A2F4 L2MPPA61

0x0184 A2F8 L2MPPA62

0x0184 A2FC L2MPPA63

0x0184 A300 - 0x0184 A3FF - Reserved

0x0184 A400 L1PMPFAR L1P memory protection fault address register
0x0184 A404 L1PMPFSR L1P memory protection fault status register
0x0184 A408 L1PMPFCR L1P memory protection fault command register

0x0184 A40C - 0x0184 A4FF - Reserved

0x0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]
0x0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]
0x0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]

0x0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]

0x0184 A510 L1PMPLKCMD L1P memory protection lock key command register

0x0184 A514 L1PMPLKSTAT L1P memory protection lock key status register
0x0184 A518 - 0x0184 A5FF - Reserved
0x0184 A600 - 0x0184 A63F - Reserved

0x0184 A640 L1PMPPA16

0x0184 A644 L1PMPPA17

0x0184 A648 L1PMPPA18

0x0184 A64C L1PMPPA19

0x0184 A650 L1PMPPA20

0x0184 A654 L1PMPPA21

0x0184 A658 L1PMPPA22

0x0184 A65C L1PMPPA23

0x0184 A660 L1PMPPA24

0x0184 A664 L1PMPPA25

0x0184 A668 L1PMPPA26

0x0184 A66C L1PMPPA27

L2 memory protection page attribute register 57
(controls memory address 0x007C 8000 - 0x007C FFFF)

L2 memory protection page attribute register 58
(controls memory address 0x007D 0000 - 0x007D 7FFF)

L2 memory protection page attribute register 59
(controls memory address 0x007D 8000 - 0x007D FFFF)

L2 memory protection page attribute register 60
(controls memory address 0x007E 0000 - 0x007E 7FFF)

L2 memory protection page attribute register 61
(controls memory address 0x007E 8000 - 0x007E FFFF)

L2 memory protection page attribute register 62
(controls memory address 0x007F 0000 - 0x007F 7FFF)

L2 memory protection page attribute register 63
(controls memory address 0x007F 8000 - 0x007F FFFF)

(1)

L1P memory protection page attribute register 16
(controls memory address 0x00E0 0000 - 0x00E0 07FF)

L1P memory protection page attribute register 17
(controls memory address 0x00E0 0800 - 0x00E0 0FFF)

L1P memory protection page attribute register 18
(controls memory address 0x00E0 1000 - 0x00E0 17FF)

L1P memory protection page attribute register 19
(controls memory address 0x00E0 1800 - 0x00E0 1FFF)

L1P memory protection page attribute register 20
(controls memory address 0x00E0 2000 - 0x00E0 27FF)

L1P memory protection page attribute register 21
(controls memory address 0x00E0 2800 - 0x00E0 2FFF)

L1P memory protection page attribute register 22
(controls memory address 0x00E0 3000 - 0x00E0 37FF)

L1P memory protection page attribute register 23
(controls memory address 0x00E0 3800 - 0x00E0 3FFF)

L1P memory protection page attribute register 24
(controls memory address 0x00E0 4000 - 0x00E0 47FF)

L1P memory protection page attribute register 25
(controls memory address 0x00E0 4800 - 0x00E0 4FFF)

L1P memory protection page attribute register 26
(controls memory address 0x00E0 5000 - 0x00E0 57FF)

L1P memory protection page attribute register 27
(controls memory address 0x00E0 5800 - 0x00E0 5FFF)

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(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x

megamaodule. These registers are not supported for this device.

18

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 A670 L1PMPPA28

0x0184 A674 L1PMPPA29

0x0184 A678 L1PMPPA30

0x0184 A67C L1PMPPA31

0x0184 A67F – 0x0184 ABFF - Reserved

0x0184 AC00 L1DMPFAR L1D memory protection fault address register
0x0184 AC04 L1DMPFSR L1D memory protection fault status register
0x0184 AC08 L1DMPFCR L1D memory protection fault command register

0x0184 AC0C - 0x0184 ACFF - Reserved

0x0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]
0x0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]
0x0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]
0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]
0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register

0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register
0x0184 AD18 - 0x0184 ADFF - Reserved
0x0184 AE00 - 0x0184 AE3F - Reserved

0x0184 AE40 L1DMPPA16

0x0184 AE44 L1DMPPA17

0x0184 AE48 L1DMPPA18

0x0184 AE4C L1DMPPA19

0x0184 AE50 L1DMPPA20

0x0184 AE54 L1DMPPA21

0x0184 AE58 L1DMPPA22

0x0184 AE5C L1DMPPA23

0x0184 AE60 L1DMPPA24

0x0184 AE64 L1DMPPA25

0x0184 AE68 L1DMPPA26

0x0184 AE6C L1DMPPA27

0x0184 AE70 L1DMPPA28

0x0184 AE74 L1DMPPA29

0x0184 AE78 L1DMPPA30

L1P memory protection page attribute register 28
(controls memory address 0x00E0 6000 - 0x00E0 67FF)

L1P memory protection page attribute register 29
(controls memory address 0x00E0 6800 - 0x00E0 6FFF)

L1P memory protection page attribute register 30
(controls memory address 0x00E0 7000 - 0x00E0 77FF)

L1P memory protection page attribute register 31
(controls memory address 0x00E0 7800 - 0x00E0 7FFF)

(2)

L1D memory protection page attribute register 16
(controls memory address 0x00F0 0000 - 0x00F0 07FF)

L1D memory protection page attribute register 17
(controls memory address 0x00F0 0800 - 0x00F0 0FFF)

L1D memory protection page attribute register 18
(controls memory address 0x00F0 1000 - 0x00F0 17FF)

L1D memory protection page attribute register 19
(controls memory address 0x00F0 1800 - 0x00F0 1FFF)

L1D memory protection page attribute register 20
(controls memory address 0x00F0 2000 - 0x00F0 27FF)

L1D memory protection page attribute register 21
(controls memory address 0x00F0 2800 - 0x00F0 2FFF)

L1D memory protection page attribute register 22
(controls memory address 0x00F0 3000 - 0x00F0 37FF)

L1D memory protection page attribute register 23
(controls memory address 0x00F0 3800 - 0x00F0 3FFF)

L1D memory protection page attribute register 24
(controls memory address 0x00F0 4000 - 0x00F0 47FF)

L1D memory protection page attribute register 25
(controls memory address 0x00F0 4800 - 0x00F0 4FFF)

L1D memory protection page attribute register 26
(controls memory address 0x00F0 5000 - 0x00F0 57FF)

L1D memory protection page attribute register 27
(controls memory address 0x00F0 5800 - 0x00F0 5FFF)

L1D memory protection page attribute register 28
(controls memory address 0x00F0 6000 - 0x00F0 67FF)

L1D memory protection page attribute register 29
(controls memory address 0x00F0 6800 - 0x00F0 6FFF)

L1D memory protection page attribute register 30
(controls memory address 0x00F0 7000 - 0x00F0 77FF)

TMS320C6745, TMS320C6747

(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x

megamaodule. These registers are not supported for this device.

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION

0x0184 AE7C L1DMPPA31
0x0184 AE80 – 0x0185 FFFF - Reserved

L1D memory protection page attribute register 31
(controls memory address 0x00F0 7800 - 0x00F0 7FFF)

See Table 3-4 for a detailed top level C6745/6747 memory map that includes the DSP memory space.

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

3.4 Memory Map Summary

Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined

behavior.

Table 3-4. C6747 Top Level Memory Map

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

0x0000 0000 0x0000 0FFF 4K - PRUSS Local

0x0000 1000 0x006F FFFF
0x0070 0000 0x007F FFFF 1024K DSP L2 ROM
0x0080 0000 0x0083 FFFF 256K DSP L2 RAM ­0x0084 0000 0x00DF FFFF ­0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM ­0x00E0 8000 0x00EF FFFF
0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM ­0x00F0 8000 0x017F FFFF
0x0180 0000 0x0180 FFFF 64K DSP Interrupt

Controller

0x0181 0000 0x0181 0FFF 4K DSP Powerdown

Controller
0x0181 1000 0x0181 1FFF 4K DSP Security ID ­0x0181 2000 0x0181 2FFF 4K DSP Revision ID ­0x0181 3000 0x0181 FFFF 52K - ­0x0182 0000 0x0182 FFFF 64K DSP EMC ­0x0183 0000 0x0183 FFFF 64K DSP Internal

Reserved

0x0184 0000 0x0184 FFFF 64K DSP Memory

System

0x0185 0000 0x01BF FFFF

0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller ­0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 ­0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 ­0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0 ­0x01C1 1000 0x01C1 1FFF 4K PLL Controller ­0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG ­0x01C1 5000 0x01C1 FFFF ­0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 ­0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 ­0x01C2 2000 0x01C2 2FFF 4K I2C 0 ­0x01C2 3000 0x01C2 3FFF 4K RTC ­0x01C2 4000 0x01C3 FFFF ­0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 ­0x01C4 1000 0x01C4 1FFF 4K SPI 0 ­0x01C4 2000 0x01C4 2FFF 4K UART 0 ­0x01C4 3000 0x01CF FFFF ­0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control ­0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control -

(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code

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(1)

Map

Address Space

-

-

-

-

-

Master

Peripheral

Mem Map

Device OverviewCopyright © 2008–2014, Texas Instruments Incorporated

LCDC

Mem

Map

21

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-4. C6747 Top Level Memory Map (continued)

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data ­0x01D0 3000 0x01D0 3FFF ­0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control ­0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control ­0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data ­0x01D0 7000 0x01D0 7FFF ­0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control ­0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Control ­0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data -

0x01D0 B000 0x01D0 BFFF ­0x01D0 C000 0x01D0 CFFF 4K UART 1 ­0x01D0 D000 0x01D0 DFFF 4K UART 2 ­0x01D0 E000 0x01DF FFFF -

0x01E0 0000 0x01E0 FFFF 64K USB0 -

0x01E1 0000 0x01E1 0FFF 4K UHPI -

0x01E1 1000 0x01E1 1FFF -

0x01E1 2000 0x01E1 2FFF 4K SPI 1 -

0x01E1 3000 0x01E1 3FFF 4K LCD Controller -

0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) -

0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) -

0x01E1 6000 0x01E1 FFFF -

0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM -

0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers -

0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers -

0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port -

0x01E2 5000 0x01E2 5FFF 4K USB1 -

0x01E2 6000 0x01E2 6FFF 4K GPIO -

0x01E2 7000 0x01E2 7FFF 4K PSC 1 -

0x01E2 8000 0x01E2 8FFF 4K I2C 1 -

0x01E2 9000 0x01EF FFFF -

0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 -

0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 -

0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 -

0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 -

0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 -

0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 -

0x01F0 6000 0x01F0 6FFF 4K ECAP 0 -

0x01F0 7000 0x01F0 7FFF 4K ECAP 1 -

0x01F0 8000 0x01F0 8FFF 4K ECAP 2 -

0x01F0 9000 0x01F0 9FFF 4K EQEP 0 -

0x01F0 A000 0x01F0 AFFF 4K EQEP 1 -

0x01F0 B000 0x116F FFFF -

0x1170 0000 0x117F FFFF 1024K DSP L2 ROM
0x1180 0000 0x1183 FFFF 256K DSP L2 RAM ­0x1184 0000 0x11DF FFFF -

0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM -

Map

(1)

Master

Peripheral

Mem Map

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LCDC

Mem

Map

-

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-4. C6747 Top Level Memory Map (continued)

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

Map

0x11E0 8000 0x11EF FFFF -

0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM -

0x11F0 8000 0x3FFF FFFF -

0x4000 0000 0x47FF FFFF 128M EMIFA SDRAM data (CS0) ­0x4800 0000 0x5FFF FFFF
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) ­0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) ­0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) ­0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) ­0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers ­0x6800 8000 0x7FFF FFFF ­0x8000 0000 0x8001 FFFF 128K Shared RAM -

0x8002 0000 0xAFFF FFFF ­0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers
0xB000 8000 0xBFFF FFFF ­0xC000 0000 0xCFFF FFFF 256M EMIFB SDRAM Data
0xD000 0000 0xDFFF FFFF -

Master

Peripheral

Mem Map

LCDC

Mem

Map

Table 3-5. C6745 Top Level Memory Map

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

0x0000 0000 0x0000 0FFF 4K - PRUSS Local

0x0000 1000 0x006F FFFF

0x0070 0000 0x007F FFFF 1024K DSP L2 ROM

0x0080 0000 0x0083 FFFF 256K DSP L2 RAM -

0x0084 0000 0x00DF FFFF ­0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM ­0x00E0 8000 0x00EF FFFF
0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM ­0x00F0 8000 0x017F FFFF

0x0180 0000 0x0180 FFFF 64K DSP Interrupt

Controller

0x0181 0000 0x0181 0FFF 4K DSP Powerdown

Controller
0x0181 1000 0x0181 1FFF 4K DSP Security ID ­0x0181 2000 0x0181 2FFF 4K DSP Revision ID ­0x0181 3000 0x0181 FFFF 52K - ­0x0182 0000 0x0182 FFFF 64K DSP EMC ­0x0183 0000 0x0183 FFFF 64K DSP Internal

Reserved

0x0184 0000 0x0184 FFFF 64K DSP Memory

System

0x0185 0000 0x01BF FFFF

0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller ­0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 -

(1)

Map

Address Space

-

-

-

-

-

Master

Peripheral

Mem Map

LCDC

Mem

Map

(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code

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TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-5. C6745 Top Level Memory Map (continued)

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

Map

0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 ­0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0 ­0x01C1 1000 0x01C1 1FFF 4K PLL Controller ­0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG ­0x01C1 5000 0x01C1 FFFF ­0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 ­0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 ­0x01C2 2000 0x01C2 2FFF 4K I2C 0 ­0x01C2 3000 0x01C3 FFFF ­0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 ­0x01C4 1000 0x01C4 1FFF 4K SPI 0 ­0x01C4 2000 0x01C4 2FFF 4K UART 0 ­0x01C4 3000 0x01CF FFFF ­0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control ­0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control ­0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data ­0x01D0 3000 0x01D0 3FFF ­0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control ­0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control ­0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data -

0x01D0 7000 0x01D0 BFFF ­0x01D0 C000 0x01D0 CFFF 4K UART 1 ­0x01D0 D000 0x01D0 DFFF 4K UART 2 ­0x01D0 E000 0x01DF FFFF -

0x01E0 0000 0x01E0 FFFF 64K USB0 -

0x01E1 0000 0x01E1 1FFF -

0x01E1 2000 0x01E1 2FFF 4K SPI 1 -

0x01E1 3000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) -

0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) -

0x01E1 6000 0x01E1 FFFF -

0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM -

0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers -

0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers -

0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port -

0x01E2 5000 0x01E2 6FFF 4K GPIO -

0x01E2 7000 0x01E2 7FFF 4K PSC 1 -

0x01E2 8000 0x01E2 8FFF 4K I2C 1 -

0x01E2 9000 0x01EF FFFF -

0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 -

0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 -

0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 -

0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 -

0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 -

0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 -

Master

Peripheral

Mem Map

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Mem

Map

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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Table 3-5. C6745 Top Level Memory Map (continued)

Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem

0x01F0 6000 0x01F0 6FFF 4K ECAP 0 -

0x01F0 7000 0x01F0 7FFF 4K ECAP 1 -

0x01F0 8000 0x01F0 8FFF 4K ECAP 2 -

0x01F0 9000 0x01F0 9FFF 4K EQEP 0 -

0x01F0 A000 0x01F0 AFFF 4K EQEP 1 -

0x01F0 B000 0x116F FFFF -

0x1170 0000 0x117F FFFF 1024K DSP L2 ROM
0x1180 0000 0x1183 FFFF 256K DSP L2 RAM -

0x1184 0000 0x11DF FFFF ­0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM ­0x11E0 8000 0x11EF FFFF ­0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM ­0x11F0 8000 0x3FFF FFFF -

0x4000 0000 0x5FFF FFFF

0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) -

0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) -

0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) -

0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) -

0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers -

0x6800 8000 0xAFFF FFFF ­0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers
0xB000 8000 0xBFFF FFFF ­0xC000 0000 0xC7FF FFFF 128M EMIFB SDRAM Data
0xC800 0000 0xDFFF FFFF -

Map

(1)

Master

Peripheral

Mem Map

LCDC

Mem

Map

-

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25

V

SS

V

SS

T

AXR1[0]/

GP4[0]

AXR1[11]/

GP5[11]

SPI0_CLK/

EQEP1I/

GP5[2]/

BOOT[2]

SPI1_CLK/

EQEP1S/

GP5[7]/

BOOT[7]

1 2 3 4 5 6

EMA_CS[3]/

AMUTE2/

GP2[6]

7

EMA_CS[0]
UHPI_HAS//

GP2[4]

8

EMA_A[0]/
LCD_D[7]/

GP1[0]

9

EMA_A[4]/
LCD_D[3]/

GP1[4]

10

EMA_A[8]/

LCD_PCLK/

GP1[8]

11

EMA_SDCKE/

GP2[0]

12

EMA_D[0]/

MMCSD_DAT[0]/

UHPI_HD[0]/

GP0[0]/

BOOT[12]

13

EMA_D[9]/

UHPI_HD[9]/

LCD_D[9]/

GP0[9]

14

V

SS

V

SS

15 16

DV

DD

R

AXR1[1]/

GP4[1]

UART0_RXD/

I2C0_SDA/

TM64P0_IN12/

GP5[8]/

BOOT[8]

SPI1_ENA/

UART2_RXD/

GP5[12]

SPI0_ENA

UART0_CTS//

EQEP0A/

GP5[3]/

BOOT[3]

SPIO_SOMI[0]/

EQEPOI/

GP5[0]/

BOOT[0]

EMA_OE

UHPI_HDS1//

AXR0[13]/

GP2[7]

EMA_BA[0]/

LCD_D[4]/

GP1[14]

EMA_A[1]/

MMCSD_CLK/

UHPI_HCNTL0/

GP1[1]

EMA_A[5]/
LCD_D[2]/

GP1[5]

EMA_A[9]/

LCD_HSYNC/

GP1[9]

EMA_CLK/

OBSCLK/

AHCLKR2/

GP1[15]

EMA_D[2]/

MMCSD_DAT[2]/

UHPI_HD[2]/

GP0[2]

EMA_D[10]/

UHPI_HD[10]/

LCD_D[10]/

GP0[10]

EMA_D[1]/

MMCSD_DAT[1]/

UHPI_HD[1]/

GP0[1]

DV

DD

P

AXR1[3]/
EQEP1A/

GP4[3]

AXR1[2]/

GP4[2]

UART0_TXD/

I2C0_SCL/

TM64P0_OUT12/

GP5[9]/

BOOT[9]

SPI1_SCS[0]/
UART2_TXD/

GP5[13]

SPI1_SOMI[0]/

I2C1_SCL/

GP5[5]/

BOOT[5]

SPI0_SIMO[0]/

EQEP0S/

GP5[1]/

BOOT[1]

EMA_CS[2]
UHPI_HCS//

GP2[5]/

BOOT[15]

EMA_BA[1]/

LCD_D[5]/

UHPI_HHWIL/

GP1[13]

EMA_A[2]/
MMCSD_CMD/
UHPI_HCNTL1/

GP1[2]

EMA_A[6]/
LCD_D[1]/

GP1[6]

EMA_A[11]/

/

GP1[11]

LCD_AC_

ENB_CS

EMA_WE_

DQM[1]

UHPI_HDS2//

AXR0[14]/

GP2[8]

EMA_D[4]/

MMCSD_DAT[4]/

UHPI_HD[4]/

GP0[4]

EMA_D[12]/

UHPI_HD[12]/

LCD_D[12]/

GP0[12]

EMA_D[3]/

MMCSD_DAT[3]/

UHPI_HD[3]/

GP0[3]

EMA_D[11]/

UHPI_HD[11]/

LCD_D[11]

GP0[11]

N

AXR1[5]/

EPWM2B/

GP4[5]

AXR1[4]/

EQEP1B/

GP4[4]

AXR1[10]/

GP5[10]

SPI0_SCS[0]
UART0_RTS//

EQEP0B/

GP5[4]/
BOOT[4]

SPI1_SIMO[0]/

I2C1_SDA/

GP5[6]/

BOOT[6]

EMA_WAIT[0]/

/

GP2[10]

UHPI_HRDY

EMA_RAS/

EMA_CS[5]/

GP2[2]

EMA_A[10]/

LCD_VSYNC/

GP1[10]

EMA_A[3]/
LCD_D[6]/

GP1[3]

EMA_A[7]/
LCD_D[0]/

GP1[7]

EMA_A[12]/

LCD_MCLK/

GP1[12]

EMA_D[8]/

UHPI_HD[8]/

LCD_D[8]/

GP0[8]

EMA_D[6]/

MMCSD_DAT[6]/

UHPI_HD[6]/

GP0[6]

EMA_D[14]/

UHPI_HD[14]/

LCD_D[14]/

GP0[14]

EMA_D[5]/

MMCSD_DAT[5]/

UHPI_HD[5]/

GP0[5]

EMA_D[13]/

UHPI_HD[13]/

LCD_D[13]/

GP0[13]

M

AXR1[9]/

GP4[9]

AXR1[8]/

EPWM1A/

GP4[8]

AXR1[7]/

EPWM1B/

GP4[7]

AXR1[6]/

EPWM2A/

GP4[6]

DV

DD

V

SS

V

SS

DV

DD

DV

DD

V

SS

V

SS

DV

DD

EMA_WEW/

UHPI_HR /

AXR0[12]/

GP2[3]/

BOOT[14]

EMA_WE_

DQM[0]

UHPI_HINT//

AXR0[15]/

GP2[9]

EMA_D[7]/

MMCSD_DAT[7]/

UHPI_HD[7]/

GP0[7]/

BOOT[13]

EMA_D[15]/

UHPI_HD[15]/

LCD_D[15]/

GP0[15]

L

AHCLKR1/

GP4[11]

ACLKR1/

ECAP2/
APWM2/
GP4[12]

AFSR1/
GP4[13]

AMUTE0/

RESETOUT

DV

DD

CV

DD

V

SS

V

SS

V

SS

V

SS

DV

DD

DVDDEMB_CAS EMB_D[22] EMB_D[23]

EMA_CAS

EMA_CS[4]//

GP2[1]

K

GP7[14]

AHCLKX1/
EPWM0B/

GP3[14]

ACLKX1/

EPWM0A/

GP3[15]

AFSX1/

EPWMSYNCI/

EPWMSYNCO/

GP4[10]

DV

DD

CV

DD

V

SS

V

SS

CV

DD

CV

DD

DVDDEMB_D[20]

EMB_WE_

DQM[0]/
GP5[15]

EMB_WE EMB_D[21]CV

DD

TMS

J

TDI

TDO TRST

EMU[0]/
GP7[15]

CV

DD

CV

DD

V

SS

V

SS

CV

DD

CV

DD

CV

DD

EMB_D[5]/

GP6[5]

EMB_D[19]

EMB_D[6]/

GP6[6]

EMB_D[7]/

GP6[7]

RTC_XI

H

RTC_XO

TCK

NC

USB0_

VDDA33

CV

DD

V

SS

V

SS

CV

DD

CV

DD

EMB_D[3]/

GP6[3]

EMB_D[17] EMB_D[18]

EMB_D[4]/

GP6[4]

RTC_CV

DD

G

RTC_V

SS

RESET USB0_DM

DV

DD

CV

DD

V

SS

V

SS

CV

DD

CV

DD

DV

DD

CV

DD

EMB_D[1]/

GP6[1]

EMB_D[31] EMB_D[16]

EMB_D[2]/

GP6[2]

OSCOUT

F

OSCIN

NC

USB0_DP

DV

DD

CV

DD

RSV1

V

SS

V

SS

V

SS

DV

DD

DV

DD

EMB_D[15]/

GP6[15]

EMB_D[29] EMB_D[30]

EMB_D[0]/

GP6[0]

PLL0_VSSA

E

OSCVSS

USB0_

VDDA18

USB0_

DRVVBUS/

GP4[15]

DV

DD

V

SS

V

SS

DV

DD

V

SS

V

SS

DV

DD

DV

DD

EMB_D[13]/

GP6[13]

EMB_D[27] EMB_D[28]

EMB_D[14]/

GP6[14]

PLL0_VDDA

D

USB0_ID

USB0_VBUS

AMUTE1/
EPWMTZ/

GP4[14]

AFSX0/

GP2[13]/

BOOT[10]

UART1_TXD/

AXR0[10]/

GP3[10]

AXR0[6]/

RMII_RXER/

ACLKR2/

GP3[6]

AXR0[2]/

RMII_TXEN/

AXR2[3]/

GP3[2]

EMB_CS[0]

EMB_A[0]/

GP7[2]

EMB_A[4]/

GP7[6]

EMB_A[8]/

GP7[10]

EMB_D[9]/

GP6[9]

EMB_D[10]/

GP6[10]

EMB_D[11]/

GP6[11]

EMB_D[12]/

GP6[12]

USB1_

VDDA33

C

USB1_

VDDA18

USB0_

VDDA12

AFSR0/
GP3[12]

ACLKX0/

ECAP0/
APWM0/
GP2[12]

UART1_RXD/

AXR0[9]/

GP3[9]

AXR0[5]/

RMII_RXD[1]/

AFSX2/

GP3[5]

AXR0[1]/

RMII_TXD[1]/

ACLKX2/

GP3[1]

EMB_BA[0]/

GP7[1]

EMB_A[1]/

GP7[3]

EMB_A[5]/

GP7[7]

EMB_A[9]/

GP7[11]

EMB_SDCKE EMB_CLK

EMB_WE_

DQM[1]/
GP5[14]

EMB_D[8]/

GP6[8]

B

RSV2 VSSUSB1_DM

ACLKR0/

ECAP1/

APWM1/

GP2[15]

AHCLKX0/
AHCLKX2/

USB_

REFCLKIN/

GP2[11]

AXR0[8]/
MDIO_D/

GP3[8]

AXR0[4]/

RMII_RXD[0]/

AXR2[1]/

GP3[4]

AXR0[0]/

RMII_TXD[0]/

AFSR2/

GP3[0]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

EMB_BA[1]/

GP7[0]

EMB_A[2]/

GP7[4]

EMB_A[6]/

GP7[8]

EMB_A[11]/

GP7[13]

EMB_WE_

DQM[2]

EMB_D[25]

EMB_A[12]/

GP3[13]

DV

DD

A

V

SS

V

SS

USB1_DP

AHCLKR0/

RMII_MHZ_

50_CLK/
GP2[14]/

BOOT[11]

AXR0[11]/
AXR2[0]/

GP3[11]

AXR0[7]/

MDIO_CLK/

GP3[7]

AXR0[3]/

RMII_CRS_DV/

AXR2[2]/

GP3[3]

EMB_RAS

EMB_A[10]/

GP7[12]

EMB_A[3]/

GP7[5]

EMB_A[7]/

GP7[9]

EMB_WE_

DQM[3]

EMB_D[24] EMB_D[26] V

SS

V

SS

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

RV

DD

RV

DD

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

3.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.

3.5.1 Pin Map (Bottom View)

Figure 3-3 and Figure 3-4 show the pin assignments for ZKB package and PTP package, respectively.

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Figure 3-3. Pin Map (ZKB)

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133

RSV2

134

USB0_VDDA12

135

USB0_VDDA18

136

NC

137

USB0_DP

138

USB0_DM

139

NC

140

USB0_VDDA33

141

PLL0_VDDA

142
143

OSCIN

144
145

OSCOUT

146

RESET

147
148

RSV4

149

RSV3

150

GP7[14]

152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

PLL0_VSSA

OSCVSS

CV

DD

TRST

TMS

TDI

TCK
TDO

RV

DD

AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]

DV

DD

AFSR1/GP4[13]

AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]

1

AXR1[0]/GP4[0]

2

UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]

3

UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]

4

AXR1[10]/GP5[10]

5

DV

DD

6

AXR1[11]/GP5[11]

7

SPI1_ENA/UART2_RXD/GP5[12]

8

SPI1_SCS[0]/UART2_TXD/GP5[13]

9

SPI0_SCS[0] UART0_RTS/ /EQEP0B/GP5[4]/BOOT[4]

10

11

SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]

12

13

SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]

14

SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]

15

16

SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]

17

SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]

18

19

EMA_WAIT[0]/GP2[10]

2021222324

25

EMA_BA[0]/GP1[14]

262728293031323334353637383940

41

CV

DD

SPI0_ENA UART0_CTS/ /EQEP0A/GP5[3]/BOOT[3]

DV

DD

SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]

CV

DD

EMA_CS[3]/GP2[6]

EMA_OE/AXR0[13]/GP2[7]

EMA_CS[2]/GP2[5]/BOOT[15]

DV

DD

EMA_BA[1]/GP1[13]

EMA_A[10]/GP1[10]

CV

DD

EMA_A[0]/GP1[0]

EMA_A[1]/MMCSD_CLK/GP1[1]

EMA_A[2]/MMCSD_CMD/GP1[2]

EMA_A[3]/GP1[3]

DV

DD

EMA_A[4]/GP1[4]

EMA_A[5]/GP1[5]

EMA_A[6]/GP1[6]

EMA_A[7]/GP1[7]

CV

DD

EMA_A[8]/GP1[8]

EMA_A[9]/GP1[9]

EMA_A[11]/GP1[11]

EMA_A[12]/GP1[12]

DV

DD

EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]

151

DV

DD

CV

DD

DV

DD

AHCLKX1/EPWM0B/GP3[14]

CV

DD

ACLKX1/EPWM0A/GP3[15]

ACLKR1/ECAP2/APWM2/GP4[12]

CV

DD

DV

DD

AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]

AXR1[2]/GP4[2]
AXR1[1]/GP4[1]

42

43

44

88

EMB_SDCKE

87

DV

DD

86

EMB_CLK

85

EMB_WE_DQM[1]/GP5[14]

84

EMB_D[8]/GP6[8]

83

EMB_D[9]/GP6[9]

82

EMB_D[10]/GP6[10]

81

DV

DD

80

EMB_D[11]/GP6[11]

79

EMB_D[12]/GP6[12]

78

EMB_D[13]/GP6[13]

77

CV

DD

76

EMB_D[14]/GP6[14]
75
74

EMB_D[15]/GP6[15]
73

EMB_D[0]/GP6[0]
72

EMB_D[1]/GP6[1]
71

DV

DD

70

EMB_D[2]/GP6[2]
69

CV

DD

68

EMB_D[3]/GP6[3]
67

RV

DD

66

EMB_D[4]/GP6[4]
65

DV

DD

64

EMB_D[5]/GP6[5]
63

EMB_D[6]/GP6[6]
62

EMB_D[7]/GP6[7]
61

CV

DD

60

EMB_WE_DQM[0]/GP5[15]
59

EMB_WE
58

DV

DD

57

EMB_CAS
56

CV

DD

55

EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
54

EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
53

DV

DD

52

EMA_D[6]/MMCSD_DAT[6]/GP0[6]
51

EMA_D[5]/MMCSD_DAT[5]/GP0[5]
50

CV

DD

49

EMA_D[4]/MMCSD_DAT[4]/GP0[4]
48

EMA_D[3]/MMCSD_DAT[3]/GP0[3]
47

DV

DD

46

EMA_D[2]/MMCSD_DAT[2]/GP0[2]
45

EMA_D[1]/MMCSD_DAT[1]/GP0[1]

DV

DD

132

AMUTE1/EPWMTZ/GP4[14]

131

AFSR0/GP3[12]

130

ACLKR0/ECAP1/APWM1/GP2[15]

129

AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]

128

DV

DD

127

AFSX0/GP2[13]/BOOT[10]

126

ACLKX0/ECAP0/APWM0/GP2[12]

125

AHCLKX0/USB_REFCLKIN/GP2[11]

124

AXR0[11]/GP3[11]

123

UART1_TXD/AXR0[10]/GP3[10]

122

UART1_RXD/AXR0[9]/GP3[9]

121

AXR0[8]/MDIO_D/GP3[8]

120

AXR0[7]/MDIO_CLK/GP3[7]

119

118

AXR0[6]/RMII_RXER/GP3[6]

117

AXR0[5]/RMII_RXD[1]/GP3[5]

116

AXR0[4]/RMII_RXD[0]/GP3[4]

115

AXR0[3]/RMII_CRS_DV/GP3[3]

114

113

AXR0[2]/RMII_TXEN/GP3[2]

112

AXR0[1]/RMII_TXD[1]/GP3[1]

111

AXR0[0]/RMII_TXD[0]/GP3[0]

110

EMB_RAS

109

DV

DD

108

EMB_CS[0]

107

EMB_BA[0]/GP7[1]

106

EMB_BA[1]/GP7[0]

105

EMB_A[10]/GP7[12]

104

103

EMB_A[0]/GP7[2]

102

EMB_A[1]/GP7[3]

101

EMB_A[2]/GP7[4]

100

EMB_A[3]/GP7[5]

99

98

EMB_A[4]/GP7[6]

97

EMB_A[5]/GP7[7]

96

EMB_A[6]/GP7[8]

95

EMB_A[7]/GP7[9]

94

EMB_A[8]/GP7[10]

93

92

EMB_A[9]/GP7[11]91EMB_A[11]/GP7[13]

90

89

EMB_A[12]/GP3[13]

DV

DD

DV

DD

CV

DD

DV

DD

CV

DD

CV

DD

V

(177)

SS

Thermal Pad

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TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

Figure 3-4. Pin Map (PTP)

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TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

3.6 Terminal Functions

to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

3.6.1 Device Reset and JTAG

Table 3-6. Reset and JTAG Terminal Functions

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SIGNAL NAME

RESET 146 G3 I Device reset input
AMUTE0/ RESETOUT - L4 O

TMS 152 J1 I IPU JTAG test mode select
TDI 153 J2 I IPU JTAG test data input
TDO 156 J3 O IPD JTAG test data output
TCK 155 H3 I IPU JTAG test clock
TRST 150 J4 I IPD JTAG test reset
EMU[0]/GP7[15] - J5 I/O IPU Emulation Signal

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Open drain mode for RESETOUT function.

PIN NO

PTP ZKB

TYPE

(1)

(3)

(2)

PULL

RESET

IPD Reset output

JTAG

DESCRIPTION

3.6.2 High-Frequency Oscillator and PLL

Table 3-7. High-Frequency Oscillator and PLL Terminal Functions

SIGNAL NAME

EMA_CLK/OBSCLK/AHCLKR
2/GP1[15]

OSCIN 143 F2 I Oscillator input
OSCOUT 145 F1 O Oscillator output
OSCVSS 144 E2 GND Oscillator ground (for filter only)

PLL0_VDDA 141 D1 PWR PLL analog VDD(1.2-V filtered supply)
PLL0_VSSA 142 E1 GND PLL analog VSS(for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP ZKB

- R12 O IPU PLL Observation Clock

(1)

TYPE

1.2-V OSCILLATOR

1.2-V PLL

PULL

(2)

DESCRIPTION

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3.6.3 Real-Time Clock and 32-kHz Oscillator

Table 3-8. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions

TMS320C6745, TMS320C6747

SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014

SIGNAL NAME

RTC_CVDD - G1 PWR RTC module core power (isolated from rest of chip CVDD)
RTC_XI - H1 I Low-frequency (32-kHz) oscillator receiver for real-time clock
RTC_XO - H2 O Low-frequency (32-kHz) oscillator driver for real-time clock
RTC_V

ss

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

PIN NO

PTP ZKB

- G2 GND Oscillator ground (for filter)

TYPE

(1)

PULL

(2)

DESCRIPTION

3.6.4 External Memory Interface A (ASYNC, SDRAM)

Table 3-9. External Memory Interface A (EMIFA) Terminal Functions

SIGNAL NAME

EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - M16 I/O IPD
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD

EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU

EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU

EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU

PIN NO

PTP ZKB

TYPE

(1)

PULL

(2)

MUXED DESCRIPTION

UHPI, LCD,
GPIO

MMC/SD,
UHPI, GPIO,
BOOT

MMC/SD,
UHPI, GPIO

MMC/SD,
UHPI, GPIO,
BOOT

EMIFA data bus

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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Table 3-9. External Memory Interface A (EMIFA) Terminal Functions (continued)

SIGNAL NAME

PIN NO

PTP ZKB

EMA_A[12]/LCD_MCLK/GP1[12] 42 N11 O IPU
EMA_A[11] /LCD_AC_ENB_CS/GP1[11] 41 P11 O IPU
EMA_A[10]/LCD_VSYNC/GP1[10] 27 N8 O IPU
EMA_A[9]/LCD_HSYNC/GP1[9] 40 R11 O IPU
EMA_A[8]/LCD_PCLK/GP1[8] 39 T11 O IPU
EMA_A[7]/LCD_D[0]/GP1[7] 37 N10 O IPD
EMA_A[6]/LCD_D[1]/GP1[6] 36 P10 O IPD
EMA_A[5]/LCD_D[2]/GP1[5] 35 R10 O IPD
EMA_A[4]/LCD_D[3]/GP1[4] 34 T10 O IPD
EMA_A[3]/LCD_D[6]/GP1[3] 32 N9 O IPD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 O IPU

EMA_A[0]/LCD_D[7]/GP1[0] 29 T9 O IPD LCD, GPIO
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] 26 P8 O IPU
EMA_BA[0]/LCD_D[4]/GP1[14] 25 R8 O IPU LCD, GPIO
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 O IPU

EMA_SDCKE/GP2[0] - T12 O IPU GPIO

EMA_RAS/EMA_CS[5]/GP2[2] - N7 O IPU

EMA_CAS/EMA_CS[4]/GP2[1] - L16 O IPU

EMA_RAS/EMA_CS[5] /GP2[2] - N7 O IPU
EMA_CAS/EMA_CS[4] /GP2[1] - L16 O IPU

EMA_CS[3]/AMUTE2/GP2[6] 21 T7 O IPU

EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] 23 P7 O IPU

EMA_CS[0]/UHPI_HAS/GP2[4] - T8 O IPU UHPI, GPIO

EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU

EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] - P12 O IPU

EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] - M14 O IPU

EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 O IPU

EMA_WAIT[0]/ UHPI_HRDY/GP2[10] 19 N6 I IPU UHPI, GPIO

TYPE

(1)

PULL

(2)

MUXED DESCRIPTION

LCD, GPIO EMIFA address bus

MMCSD,
UHPI, GPIO

LCD, UHPI,
GPIO

McASP2,
GPIO

EMIF A chip
select, GPIO

EMIF A
SDRAM, GPIO

McASP2,
GPIO

UHPI, GPIO,
BOOT

UHPI,
MCASP0,
GOPIO, BOOT

UHPI, McASP,
GPIO

UHPI,
McASP0,
GPIO

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EMIFA address busEMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O IPU

EMIFA bank address

EMIFA clock
EMIFA SDRAM clock

enable
EMIFA SDRAM row

address strobe
EMIFA SDRAM

column address
strobe

EMIFA Async Chip
Select

EMIFA SDRAM chip
select

EMIFA SDRAM write
enable

EMIFA write
enable/data mask for
EMA_D[15:8]

EMIFA write
enable/data mask for
EMA_D[7:0]

EMIFA output enable

EMIFA wait
input/interrupt

30

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