TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1.1Features
1
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 375- and 456-MHz TMS320C674x VLIW DSP
• C674x Instruction Set Features
– Superset of the C67x+ and C64x+ ISAs
– Up to 3648 MIPS and 2736 MFLOPS C674x
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
– 32KB of L1P Program RAM/Cache
– 32KB of L1D Data RAM/Cache
– 256KB of L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Fixed- and Floating-Point VLIW
DSP Core
– Load-Store Architecture with Nonaligned
Support
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32- and 40-Bit) Functional Units
– Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
– Supports up to Four SP Additions Per Clock,
Four DP Additions Every 2 Clocks
– Supports up to Two Floating-Point (SP or DP)
Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle
– Two Multiply Functional Units
– Mixed-Precision IEEE Floating Point Multiply
Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
– Fixed-Point Multiply Supports Two 32 x 32-Bit
1
• 128KB of RAM Shared Memory (TMS320C6747
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)
• Two External Memory Interfaces:
• Three Configurable 16550-Type UART Modules:
• LCD Controller (TMS320C6747 Only)
• Two Serial Peripheral Interfaces (SPIs) Each with
• Multimedia Card (MMC)/Secure Digital (SD) Card
• Two Master and Slave Inter-Integrated Circuit (I2C
• One Host-Port Interface (HPI) with 16-Bit-Wide
• Programmable Real-Time Unit Subsystem
Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle, and
Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
Only)
– EMIFA
– NOR (8- or 16-Bit-Wide Data)
– NAND (8- or 16-Bit-Wide Data)
– 16-Bit SDRAM with 128-MB Address Space
(TMS320C6747 Only)
– EMIFB
– 32-Bit or 16-Bit SDRAM with 256-MB
Address Space (TMS320C6747)
– 16-Bit SDRAM with 128-MB Address Space
(TMS320C6745)
– UART0 with Modem Control Signals
– Autoflow Control Signals (CTS, RTS) on UART0
Only
– 16-Byte FIFO
– 16x or 13x Oversampling Option
One Chip Select
Interface with Secure Data I/O (SDIO)
Bus™)
Muxed Address/Data Bus for High Bandwidth
(TMS320C6747 Only)
(PRUSS)
– Two Independent Programmable Realtime Unit
(PRU) Cores
– 32-Bit Load and Store RISC Architecture
– 4KB of Instruction RAM per Core
– 512 Bytes of Data RAM per Core
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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– PRUSS can be Disabled via Software to
Save Power
– Standard Power-Management Mechanism
– Clock Gating
– Entire Subsystem Under a Single PSC Clock
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
(TMS320C6747 Only)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
(TMS320C6747)
– USB 2.0 Full-Speed Client (TMS320C6745)
– USB 2.0 High-, Full-, and Low-Speed Host
(TMS320C6747)
– USB 2.0 Full- and Low-Speed Host
(TMS320C6745)
– High-Speed Functionality Available on
TMS320C6747 Device Only
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs):
– TMS320C6747 Supports 3 McASPs
– TMS320C6745 Supports 2 McASPs
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO Buffers for Transmit and Receive
• Commercial, Industrial, Extended, or Automotive
Temperature
1.2Applications
•A/V Receivers
•Automotive Amplifiers
•Soundbars
1.3Description
The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way setassociative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.
2
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal
Processor
The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output
(MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers
and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a
configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of generalpurpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other
peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit
enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an
asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a
higher speed memory interface (EMIFB) for SDRAM.
The EthernetMedia AccessController (EMAC)provides anefficient interfacebetweenthe
TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10
Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for
PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Device Information
PART NUMBERPACKAGEBODY SIZE
TMS320C6745HLQFP (176)24.00 mm x 24.00 mm
TMS320C6747BGA (256)17.00 mm x 17.00 mm
(1) For more information on these devices, see Section 8, Mechanical Packaging and Orderable
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal
Submit Documentation Feedback
Processor
3
Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2
SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(2)
DMA
Peripherals
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB2.0
OTG Ctlr
PHY
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
EMIFB
SDRAM Only
(16b)
GPIO
PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
PLL/Clock
Generator
w/OSC
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2
SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(3)
DMA
Peripherals
Display
Internal Memory
LCD
Ctlr
128KB
RAM
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI
MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
GPIO
PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
RTC/
32-kHz
OSC
PLL/Clock
Generator
w/OSC
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
1.4Functional Block Diagram
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Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
Figure 1-1. TMS320C6747 Functional Block Diagram
4
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS377E device-specific data
manual to make it an SPRS377F revision.
Scope: Applicable updates to the TMS320C6747/C6745 Fixed- and Floating-Point Digital Signal
Processor device family, specifically relating to the TMS320C6747 and TMS320C6745 devices, which are
all now in the production data (PD) stage of development, have been incorporated.
SEEADDITIONS/MODIFICATIONS/DELETIONS
•Turned on Navigation Icons on top of first page.
Global
Section 1.1
Features
Section 1.2
Applications
Section 1.3
Description
Section 3.3.2.3
C674x CPU
Section 3.6
Terminal Functions
Section 3.6.11
Universal
Asynchronous
Receiver/Transmitter
s (UART0, UART1,
UART2)
Section 3.6.21
Reserved and No
Connect
Section 3.6.23
Unused USB0
(USB2.0) and USB1
(USB1.1) Pin
Configurations
Section 5
Device Operating
Conditions
Section 5.4
Notes on
Recommended
Power-On Hours
(POH)
Section 6.10.6
EMIFA Electrical
Data/Timing
•Updated Features, Applications, and Description for consistency and translation.
•Moved Trademarks information from first page to within Section 7, Device and Documentation Support.
•Moved ESDS Warning to within Section 7, Device and Documentation Support.
Deleted Highlights section. Information was duplicated elsewhere in Features.
Added NEW section.
Added NEW Device Information Table.
Table 3-2, C674x Cache Registers:
•Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from
"...See the System reference Guide..." to "See the Technical Reference Manual..."
Table 3-21, Universal Serial Bus (USB) Terminal Functions:
•Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF
capacitor..." to "...is recommended to be connected via a 0.22-μF capacitor..."
•Updated/Changed footnote from "...DSP Reference Guide - Literature Number SPRUFK4..." to "...DSP
Technical Reference Manual (SPRUH91)..."
Table 3-26, Reserved and No Connect Terminal Functions:
•Updated/Changed RSV4 DESCRIPTION from "...This pin may be tied high or low." to "...For proper
device operation, this pin must be tied low or to CVDD."
Moved to within Section 3.6, Terminal Functions
Table 3-28, Unused USB0 and USB1 Pin Configurations:
•Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and
changing text to "Internal USB0 PHY output connected to an external..."
Section 5.2, Handling Ratings:
•Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings
table.
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on
a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
•Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
•Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a freerunning time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
The DSP has access to the following External memories:
•Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
•SDRAM (EMIFB)
3.3.2.2DSP Internal Memories
The DSP has access to the following DSP memories:
•L2 RAM
•L1P RAM
•L1D RAM
3.3.2.3C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
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Table 3-2 shows a memory map of the C674x CPU cache registers for the device.
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1Pin Map (Bottom View)
Figure 3-3 and Figure 3-4 show the pin assignments for ZKB package and PTP package, respectively.
to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
3.6.1Device Reset and JTAG
Table 3-6. Reset and JTAG Terminal Functions
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SIGNAL NAME
RESET146G3IDevice reset inputAMUTE0/ RESETOUT-L4O
TMS152J1IIPUJTAG test mode select
TDI153J2IIPUJTAG test data input
TDO156J3OIPDJTAG test data output
TCK155H3IIPUJTAG test clock
TRST150J4IIPDJTAG test reset
EMU[0]/GP7[15]-J5I/OIPUEmulation Signal
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Open drain mode for RESETOUT function.
PIN NO
PTPZKB
TYPE
(1)
(3)
(2)
PULL
RESET
IPDReset output
JTAG
DESCRIPTION
3.6.2High-Frequency Oscillator and PLL
Table 3-7. High-Frequency Oscillator and PLL Terminal Functions
RTC_CVDD-G1PWRRTC module core power (isolated from rest of chip CVDD)
RTC_XI-H1ILow-frequency (32-kHz) oscillator receiver for real-time clock
RTC_XO-H2OLow-frequency (32-kHz) oscillator driver for real-time clock
RTC_V
ss
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
PIN NO
PTPZKB
eCAP0
eCAP1
eCAP2
TYPE
(1)
PULL
(2)
MUXEDDESCRIPTION
enhanced capture 0
input or auxiliary
PWM 0 output
enhanced capture 1
input or auxiliary
PWM 1 output
enhanced capture 2
input or auxiliary
PWM 2 output
ACLKX1/EPWM0A/GP3[15]162K3I/OIPD
AHCLKX1/EPWM0B/GP3[14]160K2I/OIPDeHRPWM0 B output.
AMUTE1/EPWMTZ/GP4[14]132D4I/OIPD
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]163K4I/OIPD
AXR1[8]/EPWM1A/GP4[8]168M2I/OIPD
AXR1[7]/EPWM1B/GP4[7]169M3I/OIPDeHRPWM1 B output
AMUTE1/EPWMTZ/GP4[14]132D4I/OIPD
AXR1[6]/EPWM2A/GP4[6]170M4I/OIPD
AXR1[5]/EPWM2B/GP4[5]171N1I/OIPDeHRPWM2 B output
AMUTE1/EPWMTZ/GP4[14]132D4I/OIPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
PIN NO
PTPZKB
eHRPWM0
eHRPWM1
eHRPWM2
TYPE
(1)
PULL
(2)
MUXEDDESCRIPTION
McASP1, GPIO
McASP1, eHRPWM1,
GPIO, eHRPWM2
McASP1, eHRPWM0,
GPIO
McASP1, GPIO
McASP1, eHRPWM0,
GPIO, eHRPWM2
McASP1, GPIO
McASP1, eHRPWM0,
GPIO, eHRPWM2
eHRPWM0 A output
(with high-resolution)
eHRPWM0 trip zone
input
Sync input to
eHRPWM0 module or
sync output to
external PWM
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if
UART1 boot mode is used. Please see the TMS320C6745/C6747 DSP Technical Reference Manual (SPRUH91) for more for details on
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]14N5I/OIPU
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]13P5I/OIPUI2C1 serial clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Table 3-21. Universal Serial Bus (USB) Terminal Functions
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
SIGNAL NAME
PIN NO
PTP ZKB
TYPE
(1)
PULL
(2)
DESCRIPTION
USB0 2.0 OTG (USB0)
USB0_DM138G4AUSB0 PHY data minus
USB0_DP137F4AUSB0 PHY data plus
USB0_VDDA33140H5PWRUSB0 PHY 3.3-V supply
USB0_VDDA18135E3PWRUSB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
USB0_VDDA12
(3)
134C3PWR
For proper device operation, this pin is
recommended to be connected via a 0.22-μF
capacitor to VSS (GND), even if USB0 is not
being used.
USB0_ID-D2AUSB0 PHY identification (mini-A or mini-B plug)
USB0_VBUS-D3AUSB0 bus voltage
USB0_DRVVBUS/GP4[15]-E4OIPDUSB0 controller VBUS control output
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]125B5IIPDUSB_REFCLKIN. Optional clock input
USB1 1.1 OHCI (USB1)
USB1_DM-B3AUSB1 PHY data minus
USB1_DP-A3AUSB1 PHY data plus
USB1_VDDA33-C1PWRUSB1 PHY 3.3-V supply
USB1_VDDA18-C2PWRUSB1 PHY 1.8-V supply
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
If one or both USB modules on the device are not used, then some of the power supplies to those
modules may not be required. This can eliminate the requirement for a 1.8V power supply to the USB
modules. The required pin configurations for unused USB modules are shown below.
Table 3-28. Unused USB0 and USB1 Pin Configurations
TMS320C6745, TMS320C6747
SIGNAL NAMEConfiguration
USB0_DMNo connectUse as USB0 function
USB0_DPNo connectUse as USB0 function
USB0_VDDA33No connect3.3V
USB0_VDDA18No connect1.8V
USB0_IDNo connectUse as USB0 function
USB0_VBUSNo connectUse as USB0 function
USB0_DRVVBUS/GP4[15]No connect or use as alternate functionUse as USB0 or alternate function
USB0_VDDA12Internal USB0 PHY output connected to an external 0.22μF filter capacitor
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins.
The following boot modes are supported:
•NAND Flash boot
– 8-bit NAND
– 16-bit NAND
•NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
The following system level features of the chip are controlled by the SYSCFG peripheral:
•Readable Device, Die, and Chip Revision ID
•Control of Pin Multiplexing
•Priority of bus accesses different bus masters in the system
•Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
•Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 TC0 and TC1
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA and EMIFB
•Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function.
Many registers are accessible only by a host (DSP) when it is operating in its privileged mode. (ex. from
the kernel, but not from user space code).
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Table 4-1. System Configuration (SYSCFG) Module Register Access
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
•Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommendedthatanexternalpullup/pulldownresistorbeimplemented.Although,internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•Decide a target value for the net. For a pulldown resistor, this should be below the lowest VILlevel of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIHlevel of all
inputs on the net. A reasonable choice would be to target the VOLor VOHlevels for the logic family of
the limiting device; which, by definition, have margin to the VILand VIHlevels.
•Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
•For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•Remember to include tolerances when selecting the resistor value.
•For pullup resistors, also remember to include tolerances on the IO supply rail.
•For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
•For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
•For more detailed information on input current (II), and the low-/high-level input voltages (VILand VIH)
for the device, see Section 5.3, Recommended Operating Conditions.
•For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
Input or Output Voltages 0.3V above or below their respective power
rails. Limit clamp current that flows through the I/O's internal diode
-0.5 V to DVDD + 0.3V
20% of DVDD for up to
20% of the signal period
±20mA
protection cells.
Commercial0°C to 90°C
Operating Junction Temperature ranges,
T
J
Industrial (D suffix )-40°C to 90°C
Extended (A suffix)-40°C to 105°C
Automotive (T suffix)-40°C to 125°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a max of 24 hours.
(3)
(3)
5.2Handling Ratings
UNIT
Storage temperature
range, T
stg
ESD Stress Voltage,
(1)
V
ESD
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary
precautions are taken. Pins listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.
Transition time, 10%-90%, All Inputs (unless otherwise specified
in the electrical data sections)
Operating ambient
temperature range
DSP
F
SYSCLK1,6
Operating Frequency
(SYSCLK1)
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) When an external crystal is used, oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(3) Unless specifically indicated, these I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification. USB1 I/Os
adhere to USB1.1 specification.
(4) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
The information in the section below is provided solely for your convenience and does not extend
or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor
products.
To avoid significant degradation, the device power-on hours (POH) must be limited to the following:
Table 5-1. Recommended Power-On Hours
www.ti.com
Silicon
Revision
D300 MHz0 to 90 °C1.2V100,000
D300 MHz0 to 90 °C1.2V100,000
D375 MHz0 to 90 °C1.2V100,000
D375 MHz-40 to 105 °C1.2V75,000
D375 MHz-40 to 125 °C1.2V20,000
D456 MHz0 to 90 °C1.3V100,000
D456 MHz-40 to 90 °C1.3V100,000
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz.
Speed Grade
Operating Junction
Temperature (Tj)
Nominal CVDD Voltage (V)
Power-On Hours [POH]
Note: Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty
under TI’s standard terms and conditions for TI semiconductor products.
(1) These I/O specifications apply to regular 3.3V IOs and do not apply to USB0 or USB1 unless specifically indicated. USB0 I/Os adhere to
the USB 2.0 specification. USB1 I/Os adhere to the USB 1.1 specification.
(2) IIapplies to input-only pins and bi-directional pins. For input-only pins, IIindicates the input leakage current. For bi-directional pins, I
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current.
6Peripheral Information and Electrical Specifications
6.1Parameter Information
6.1.1Parameter Information Device-Specific Information
A.The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1. Test Load Circuit for AC Timing Measurements
www.ti.com
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1Signal Transition Levels
All input and output timing parameters are referenced to V
V
= 1.65 V. For 1.8 V I/O, V
ref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VILMAX and VIHMIN for input clocks,
VOLMAX and VOHMIN for output clocks.
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
6.2Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIHand VIL(or between VILand VIH) in a monotonic
manner.
6.3Power Supplies
6.3.1Power-on Sequence
The device should be powered-on in the following order:
1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
2. Core logic supplies:
a. CVDD core logic and RVDD supply
b. Other 1.2V logic supplies (PLL0_VDDA).
Groups 2a) and 2b) may be powered up together or 2a) first followed by 2b).
3. All 1.8V IO supplies (USB0_VDDA18, USB1_VDDA18).
4. All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33, USB1_VDDA33).
If both USB0 and USB1 are not used, USB0_VDDA33 and USB1_VDDA33 are not required and may
be left unconnected.
TMS320C6745, TMS320C6747
Group 3) and group 4) may be powered on in either order [3 then 4, or 4 then 3] but group 4) must be
powered-on after the core logic supplies.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
6.3.2Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT, which remains active
through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a reserved function, and
its behavior is not deterministic; the user should be aware that this pin will drive a level, and in fact may
toggle, during reset. RESETOUT is an output for use by other controllers in the system that indicates the
device is currently in reset.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
www.ti.com
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
A summary of the effects of Power-On Reset is given below:
•All internal logic (including emulation logic and the PLL logic) is reset to its default state
•Internal memory is not maintained through a POR
•RESETOUT goes active
•All device pins go to a high-impedance state
•The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC.
CAUTION: A watchdog reset triggers a POR.
6.4.2Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT, which
remains active through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a
reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a
level, and in fact may toggle, during reset. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
66
A summary of the effects of Warm Reset is given below:
•All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
•Internal memory is maintained through a warm reset
•The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the
RTC.
6.4.3Reset Electrical Data Timings
Table 6-1 assumes testing over the recommended operating conditions.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Table 6-1. Reset Timing Requirements
(1)(2)
No.MINMAXUNIT
1t
2t
3t
4t
RESETOUTH)
w(RSTL)
su(BPV-RSTH)
h(RSTH-BPV)
d(RSTH-
Pulse width, RESET/TRST low100ns
Setup time, boot pins valid before RESET/TRST high20ns
Hold time, boot pins valid after RESET/TRST high20ns
RESET high to RESETOUT high; Warm reset4096cycles
RESET high to RESETOUT high; Power-on Reset6192
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-6 for details.
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
(3)
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
The C6745/6747 device includes two choices to provide an external clock input, which is fed to the onchip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and
Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is
recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is
recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series
combination of C1 and C2.
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1,
the internal oscillator is disabled.
•Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
•Figure 6-7 illustrates the option that uses an external 1.2V clock input.
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
OSCIN frequency range (OSCIN)1250MHz
Cycle time, external clock driven on OSCIN20ns
Pulse width high, external clock on OSCIN0.4 t
Pulse width low, external clock on OSCIN0.4 t
Transition time, OSCIN0.25P or 10
The C6745/6747 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•Glitch-Free Transitions (on changing clock settings)
•Domain Clocks Alignment
•Clock Gating
•PLL power down
The various clock outputs given by the controller are as follows:
•Domain Clocks: SYSCLK [1:n]
•Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•Post-PLL Divider: POSTDIV
•SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•PLL Multiplier Control: PLLM
•Software programmable PLL Bypass: PLLEN
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.6.1PLL Device-Specific Information
The C6745/6747 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-
8.
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
OSCIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-4 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
PLLRST: Assertion time during
initialization
Lock time: The time that the application
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
PLL input frequency
( PLLREF)
(1)
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
Default
Value
N/A1000N/Ans
N/AN/A
x20x4x32
MINMAXUNIT
12
30 (if internal oscillator is used)
50 (if external clock source is used)
OSCIN
cycles
MHz
6.6.2Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
0x01C1 1140ALNCTLPLL Controller Clock Align Control Register
0x01C1 1144DCHANGEPLLDIV Ratio Change Status Register
0x01C1 1148CKENClock Enable Control Register
The C6745/6747 devices have a large number of interrupts to service the needs of its many peripherals
and subsystems.
6.7.1DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-7
summarizes the C674x interrupt controller registers and memory locations.
Table 6-6. C6745/6747 DSP Interrupts
EVT#INTERRUPT NAMESOURCE
0EVT0C674x Int Ctl 0
1EVT1C674x Int Ctl 1
2EVT2C674x Int Ctl 2
3EVT3C674x Int Ctl 3
4T64P0_TINT12Timer64P0 - TINT12
5SYSCFG_CHIPINT2SYSCFG_CHIPSIG Register
6PRU_EVTOUT0PRU Interrupt
7EHRPWM0HiResTimer/PWM0 Interrupt
8EDMA3_CC0_INT1EDMA3 Channel Controller 0 Region 1 interrupt
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The C6745/6747 GPIO peripheral supports the following:
•Up to 128 Pins on ZKB and up to 109 Pins on PTP package configurable as GPIO
•External Interrupt and DMA request Capability
– Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
– The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
– The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
•Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•Separate Input/Output registers
•Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
The memory map for the GPIO registers is shown in Table 6-8. See the TMS320C6745/C6747 DSPPeripherals Overview Reference Guide. (SPRUFK9) for more details.
0x01E2 6010DIR01GPIO Banks 0 and 1 Direction Register
0x01E2 6014OUT_DATA01GPIO Banks 0 and 1 Output Data Register
0x01E2 6018SET_DATA01GPIO Banks 0 and 1 Set Data Register
0x01E2 601CCLR_DATA01GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020IN_DATA01GPIO Banks 0 and 1 Input Data Register
0x01E2 6024SET_RIS_TRIG01GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028CLR_RIS_TRIG01GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602CSET_FAL_TRIG01GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
0x01E2 6034INTSTAT01GPIO Banks 0 and 1 Interrupt Status Register
0x01E2 6038DIR23GPIO Banks 2 and 3 Direction Register
0x01E2 603COUT_DATA23GPIO Banks 2 and 3 Output Data Register
0x01E2 6040SET_DATA23GPIO Banks 2 and 3 Set Data Register
0x01E2 6044CLR_DATA23GPIO Banks 2 and 3 Clear Data Register
0x01E2 6048IN_DATA23GPIO Banks 2 and 3 Input Data Register
0x01E2 604CSET_RIS_TRIG23GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050CLR_RIS_TRIG23GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054SET_FAL_TRIG23GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058CLR_FAL_TRIG23GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605CINTSTAT23GPIO Banks 2 and 3 Interrupt Status Register
0x01E2 6060DIR45GPIO Banks 4 and 5 Direction Register
0x01E2 6064OUT_DATA45GPIO Banks 4 and 5 Output Data Register
0x01E2 6068SET_DATA45GPIO Banks 4 and 5 Set Data Register
0x01E2 606CCLR_DATA45GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070IN_DATA45GPIO Banks 4 and 5 Input Data Register
0x01E2 6074SET_RIS_TRIG45GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078CLR_RIS_TRIG45GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607CSET_FAL_TRIG45GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080CLR_FAL_TRIG45GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084INTSTAT45GPIO Banks 4 and 5 Interrupt Status Register
0x01E2 6088DIR67GPIO Banks 6 and 7 Direction Register
0x01E2 608COUT_DATA67GPIO Banks 6 and 7 Output Data Register
0x01E2 6090SET_DATA67GPIO Banks 6 and 7 Set Data Register
0x01E2 6094CLR_DATA67GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098IN_DATA67GPIO Banks 6 and 7 Input Data Register
0x01E2 609CSET_RIS_TRIG67GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0CLR_RIS_TRIG67GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4SET_FAL_TRIG67GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
0x01E2 60A8CLR_FAL_TRIG67GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
0x01E2 60ACINTSTAT67GPIO Banks 6 and 7 Interrupt Status Register
Pulse duration, GPn[m] as input high2C
Pulse duration, GPn[m] as input low2C
(1) (2)
(1) (2)
ns
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have C6745/6747
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow C6745/6747
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 6-10. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-10)
No.PARAMETERMINMAXUNIT
3t
4t
w(GPOH)
w(GPOL)
Pulse duration, GPn[m] as output high2C
Pulse duration, GPn[m] as output low2C
(1) (2)
(1) (2)
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
Table 6-11. Timing Requirements for External Interrupts
No.PARAMETERMINMAXUNIT
1t
2t
w(ILOW)
w(IHIGH)
Width of the external interrupt pulse low2C
Width of the external interrupt pulse high2C
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have C6745/6747 recognize
the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow C6745/6747 enough
time to access the GPIO register through the internal bus.
0x01C0 0320EEVALError Evaluate Register
0x01C0 0340DRAE0DMA Region Access Enable Register for Region 0
0x01C0 0348DRAE1DMA Region Access Enable Register for Region 1
0x01C0 0350DRAE2DMA Region Access Enable Register for Region 2
0x01C0 0358DRAE3DMA Region Access Enable Register for Region 3
0x01C0 0380QRAE0QDMA Region Access Enable Register for Region 0
0x01C0 0384QRAE1QDMA Region Access Enable Register for Region 1
0x01C0 0388QRAE2QDMA Region Access Enable Register for Region 2
0x01C0 038CQRAE3QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043CQ0E0-Q0E15Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047CQ1E0-Q1E15Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600QSTAT0Queue 0 Status Register
0x01C0 0604QSTAT1Queue 1 Status Register
0x01C0 0620QWMTHRAQueue Watermark Threshold A Register
0x01C0 0640CCSTATEDMA3CC Status Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
Table 6-14 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-15 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-14. EDMA Parameter Set RAM
BYTE ADDRESS RANGEDESCRIPTION
0x01C0 4000 - 0x01C0 401FParameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403FParameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01cC0 405FParameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407FParameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409FParameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BFParameters Set 5 (8 32-bit words)
......
0x01C0 4FC0 - 0x01C0 4FDFParameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFFParameters Set 127 (8 32-bit words)
Table 6-15. Parameter Set Entries
BYTE OFFSET ADDRESS
WITHIN THE PARAMETER SET
0x0000OPTOption
0x0004SRCSource Address
0x0008A_B_CNTA Count, B Count
0x000CDSTDestination Address
0x0010SRC_DST_BIDXSource B Index, Destination B Index
0x0014LINK_BCNTRLDLink Address, B Count Reload
0x0018SRC_DST_CIDXSource C Index, Destination C Index
EMIFA is one of two external memory interfaces supported on the C6745/6747. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on C6745/6747 EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•SRAM memories
•NAND Flash memories
•NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB packageand 8 bits on the PTP package. Both
devices support up to fifteen address lines and an external wait/interrupt input. Up to four asynchronous
chip selects are supported by EMIFA (EMA_CS[5:2]) . All four chip selects are available on the ZKB
package. Two of the four are available on the PTP package (EMA_CS[3:2]).
Each chip select has the following individually programmable attributes:
•Data Bus Width
•Read cycle timings: setup, hold, strobe
•Write cycle timings: setup, hold, strobe
•Bus turn around time
•Extended Wait Option With Programmable Timeout
•Select Strobe Option
•NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.10.2 EMIFA Synchronous DRAM Memory Support
The C6745/6747 ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
•One, Two, and Four Bank SDRAM devices
•Devices with Eight, Nine, Ten, and Eleven Column Address
•CAS Latency of two or three clock cycles
•Sixteen Bit Data Bus Width
•3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the DSP. Powerdown
mode achieves even lower power, except the DSP must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 6-17 below shows the
supported SDRAM configurations for EMIFA.
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
6.10.4 EMIFA Connection Examples
Figure 6-12 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to
EMIFA of a C6745/6747 device simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that
the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this
example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,
but this must be supported by second stage boot code stored in the external flash.
A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-13.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it. Note that this example could also apply to the C6745 device; except only one multiplane
NAND could be supported with only EMA_CS[3:2] available.
Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising1.3ns
Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising1.5ns
Cycle time, EMIF clock EMA_CLK10ns
Pulse width, EMIF clock EMA_CLK high or low3ns
Delay time, EMA_CLK rising to EMA_CS[0] valid7ns
Output hold time, EMA_CLK rising to EMA_CS[0] invalid1ns
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid7ns
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid1ns
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid7ns
Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
invalid
1ns
Delay time, EMA_CLK rising to EMA_D[15:0] valid7ns
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid1ns
Delay time, EMA_CLK rising to EMA_RAS valid7ns
Output hold time, EMA_CLK rising to EMA_RAS invalid1ns
Delay time, EMA_CLK rising to EMA_CAS valid7ns
Output hold time, EMA_CLK rising to EMA_CAS invalid1ns
Delay time, EMA_CLK rising to EMA_WE valid7ns
Output hold time, EMA_CLK rising to EMA_WE invalid1ns
Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated7ns
Output hold time, EMA_CLK rising to EMA_D[15:0] driving1ns
Cycle time, EMIFA module clock10ns
Pulse duration, EM_WAIT assertion and deassertion2Ens
READS
12t
su(EMDV-EMOEH)
13t
h(EMOEH-EMDIV)
14t
su (EMOEL-EMWAIT)
Setup time, EM_D[15:0] valid before EM_OE high3ns
Hold time, EM_D[15:0] valid after EM_OE high0ns
Setup Time, EM_WAIT asserted before end of Strobe Phase
(2)
4E+3ns
WRITES
28t
su (EMWEL-EMWAIT)
Setup Time, EM_WAIT asserted before end of Strobe Phase
(2)
4E+3ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
EMIF read cycle time (EW = 1)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_OE low
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RS+RST+RH)*E
(RS+RST+RH+E
(RS+RST+RH)*E
- 3
(RS+RST+RH+EWC
WC)*E - 3
(RS)*E-3(RS)*E(RS)*E+3ns
-30+3ns
(RH)*E - 3(RH)*E(RH)*E + 3ns
-30+3ns
(RS)*E-3(RS)*E(RS)*E+3ns
(RH)*E-3(RH)*E(RH)*E+3ns
(RS)*E-3(RS)*E(RS)*E+3ns
(RH)*E-3(RH)*E(RH)*E+3ns
EMA_OE active low width (EW = 0)(RST)*E-3(RST)*E(RST)*E+3ns
EMA_OE active low width (EW = 1)(RST+EWC)*E-3(RST+EWC)*E (RST+EWC)*E+3ns
Delay time from EMA_WAIT deasserted to
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
EMIF write cycle time (EW = 1)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WS+WST+WH)*
(WS+WST+WH+
(WS+WST+WH)*E
E-3
(WS+WST+WH+EW
EWC)*E - 3
(WS)*E - 3(WS)*E(WS)*E + 3ns
-30+3ns
(WH)*E-3(WH)*E(WH)*E+3ns
-30+3ns
(WS)*E-3(WS)*E(WS)*E+3ns
(WH)*E-3(WH)*E(WH)*E+3ns
(WS)*E-3(WS)*E(WS)*E+3ns
(WH)*E-3(WH)*E(WH)*E+3ns
(WS)*E-3(WS)*E(WS)*E+3ns
(WH)*E-3(WH)*E(WH)*E+3ns
EMA_WE active low width (EW = 0)(WST)*E-3(WST)*E(WST)*E+3ns
EMA_WE active low width (EW = 1)(WST+EWC)*E-3(WST+EWC)*E (WST+EWC)*E+3ns
Delay time from EMA_WAIT deasserted to
EMA_WE high
Output setup time, EMA_D[15:0] valid to
Figure 6-20 illustrates a high-level view of the EMIFB and its connections within the device. Multiple
requesters have access to EMIFB through a switched central resource (indicated as crossbar in the
figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and
writes from the various requesters.
www.ti.com
Figure 6-20. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
6.11.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional
loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by
board simulation using IBIS models.
Figure 6-21 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
Figure 6-22 shows an interface between the EMIFB and a 2M × 32 × 4 bank SDRAM device and Figure 623 shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 624, as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 6-24, page size/column size (not indicated in the
table) is varied to get the required addressability range.