TEXAS INSTRUMENTS TMS320C6713, TMS320C6713B Technical data

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TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

D Highest-Performance Floating-Point Digital

Signal Processors (DSPs): C6713/C6713B

− Eight 32-Bit Instructions/Cycle

− 32/64-Bit Data Word

− 300-, 225-, 200-MHz (GDP), and 200-,

167-MHz (PYP) Clock Rates

− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times

− 2400/1800, 1800 /1350 , 1600 /1200 , and

1336 /1000 MIPS /MFLOPS

− Rich Peripheral Set, Optimized for Audio

− Highly Optimized C/C++ Compiler

D Advanced Very Long Instruction Word

(VLIW) TMS320C67x DSP Core

− Eight Independent Functional Units:

− Two ALUs (Fixed-Point)

− Four ALUs (Floating- and Fixed-Point)

− Two Multipliers (Floating- and

Fixed-Point)

− Load-Store Architecture With 32 32-Bit General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

D Instruction Set Features

− Native Instructions for IEEE 754

− Single- and Double-Precision

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation; Bit-Field Extract, Set, Clear;

Bit-Counting; Normalization

D L1/L2 Memory Architecture

− 4K-Byte L1P Program Cache (Direct-Mapped)

− 4K-Byte L1D Data Cache (2-Way)

− 256K-Byte L2 Memory Total: 64K-Byte

L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM

D Device Configuration

− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

− Endianness: Little Endian, Big Endian

D 32-Bit External Memory Interface (EMIF)

− Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM

− 512M-Byte Total Addressable External Memory Space

D Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

TMS320C67x and PowerPAD are trademarks of Texas Instruments.

C Bus is a trademark of Philips Electronics N.V. Corporation

I All trademarks are the property of their respective owners.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

‡

These values are compatible with existing 1.26V designs.

This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports

(McASPs)

− Two Independent Clock Zones Each (1 TX and 1 RX)

− Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones

− Each Clock Zone Includes:

− Programmable Clock Generator

− Programmable Frame Sync Generator

− TDM Streams From 2-32 Time Slots

− Support for Slot Size:

8, 12, 16, 20, 24, 28, 32 Bits

− Data Formatter for Bit Manipulation

− Wide Variety of I2S and Similar Bit

Stream Formats

− Integrated Digital Audio Interface Transmitter (DIT) Supports:

− S/PDIF, IEC60958-1, AES-3, CP-430

Formats

− Up to 16 transmit pins

− Enhanced Channel Status/User Data

− Extensive Error Checking and Recovery

D Two Inter-Integrated Circuit Bus (I

C Bus)

Multi-Master and Slave Interfaces

D Two Multichannel Buffered Serial Ports:

− Serial-Peripheral-Interface (SPI)

− High-Speed TDM Interface

− AC97 Interface

D Two 32-Bit General-Purpose Timers D Dedicated GPIO Module With 16 pins

(External Interrupt Capable)

D Flexible Phase-Locked-Loop (PLL) Based

Clock Generator Module

D IEEE-1149.1 (JTAG

†

)

Boundary-Scan-Compatible

D Package Options:

− 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP)

− 272-Ball, Ball Grid Array Package (GDP)

D 0.13-µm/6-Level Copper Metal Process

− CMOS Technology

D 3.3-V I/Os, 1.2

‡

-V Internal (GDP & PYP)

D 3.3-V I/Os, 1.4-V Internal (GDP) (300 MHz

only)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

Table of Contents

GDP 272-Ball BGA package (bottom view) 3. . . . . . . . . . . . .

PYP PowerPAD QFP package (top view) 8. . . . . . . . . . . . .

description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device characteristics 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

functional block and CPU (DSP core) diagram 12. . . . . . . . . .

CPU (DSP core) description 13. . . . . . . . . . . . . . . . . . . . . . . . .

memory map summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

peripheral register descriptions 17. . . . . . . . . . . . . . . . . . . . . . .

signal groups description 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .

device configurations 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

configuration examples 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

debugging considerations 45. . . . . . . . . . . . . . . . . . . . . . . . . . .

terminal functions 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

development support 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

documentation support 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU CSR register description 66. . . . . . . . . . . . . . . . . . . . . . . .

cache configuration (CCFG) register description (13B) 68. . .

interrupts and interrupt selector 69. . . . . . . . . . . . . . . . . . . . . . .

external interrupt sources 71. . . . . . . . . . . . . . . . . . . . . . . . . . . .

EDMA module and EDMA selector 72. . . . . . . . . . . . . . . . . . . .

PLL and PLL controller 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

multichannel audio serial port (McASP) peripherals 82. . . . .

I2C 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) 88. . . . . . . . . . . . . . . . . .

power-down mode logic 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply sequencing 91. . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply decoupling 92. . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 JTAG compatibility statement 92. . . . . . . . . . . . .

EMIF device speed 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF big endian mode correctness [C6713B only] 95. . .

bootmode 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating case

temperature range 97. . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions 98. . . . . . . . . . . . . . . .

electrical characteristics over recommended ranges of

supply voltage and operating case temperature 99.

parameter measurement information 100. . . . . . . . . . . . . .

signal transition levels 100. . . . . . . . . . . . . . . . . . . . . . . . . . .

timing parameters and board routing analysis 101. . . . . .

input and output clocks 103. . . . . . . . . . . . . . . . . . . . . . . . . .

asynchronous memory timing 107. . . . . . . . . . . . . . . . . . . .

synchronous-burst memory timing 110. . . . . . . . . . . . . . . .

synchronous DRAM timing 112. . . . . . . . . . . . . . . . . . . . . . .

HOLD

/HOLDA timing 118. . . . . . . . . . . . . . . . . . . . . . . . . . .

BUSREQ timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

reset timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

external interrupt timing 122. . . . . . . . . . . . . . . . . . . . . . . . .

multichannel audio serial port (McASP) timing 123. . . . . .

inter-integrated circuits (I2C) timing 126. . . . . . . . . . . . . . .

host-port interface timing 129. . . . . . . . . . . . . . . . . . . . . . . .

multichannel buffered serial port timing 133. . . . . . . . . . . .

timer timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) port timing 144. . . .

JTAG test-port timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . .

mechanical data 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

revision history 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

GDP 272-Ball BGA package (bottom view)

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

CVDDDV

ED19

ED20

ED22 ED21 ED23

ED24 ED25 DV

DVDDED27 ED26

ED28 ED29 ED30

SDA0 V

SCL0 ED31

CLKR1/

DR1/

AXR0[6]

SDA1

FSX1

AXR0[5]

DDVSS

DR0/

AXR0[0]

DX1/

ED18 BE2

FSR1/

AXR0[7]

CLKX1/

AMUTE0

CLKS0/

AHCLKR0

FSR0/

AFSR0

ED17

ED16

ARDY

BE3

DVDDCVDDDV

CE2

EA4

CE3 EA3 EA5 EA8 EA10

DDVSS

EA7 EA9 VSSEA14 EA16 EA18 DVDDEA20EA2

EA6 DV

ECLKOUT

SDRAS

AOE/

SSOE

CVDDCVDDDV

ECLKIN

ARE

SDCAS/

SSADS

CLKOUT2/

GP[2]

AWE/ SDWE/ SSWE

DDVSS

EA11

EA15

EA13

EA12

CVDDCVDDDV

EA17

DDVSS

CE1

EA19

CE0

EA21 BE1 V

ED13 ED15 ED14

CVDDDVDDED11 ED12

ED9 V

ED6 ED7 ED8

ED2 ED3 CV

ED0 ED1 V

HOLD

HOLDA

DDVSS

ED4 ED5

BUS REQ

BE0

ED10

HINT/

GP[1]

DX0/

FSX0/

AFSX0

TOUT0/

AXR0[2]

TOUT1/

AXR0[4]

CLKS1/

SCL1

GP[5]

(EXT_INT5)/

AMUTEIN0

1 23 45 67 89 1011121314151617181920

Shading denotes the GDP package pin functions that drop out on the PYP package.

AXR0[1]

TINP0/

AXR0[3]

TINP1/

AHCLKX0

GP[6]

(EXT_INT6)

GP[4]/

(EXT_INT4)/

AMUTEIN1

CVDDDV

CLKR0/

ACLKR0

CLKX0/

ACLKX0

DDCVDD

GP[7]

(EXT_INT7)

EMU2

CLKIN CV

CLK

MODE0

CVDDCV

PLLHV

RSV

RSV VSSEMU0 CLKOUT3 CV

TRST TMS

TCK

TDI TDO CVDDCV

EMU1

RSV VSSCVDDCVDDDV

HD14/

EMU4 RSV NMI

EMU5

RSV

RESET

EMU3

DDVSS

RSV

GP[14]

HD15/

GP[15]

HD12/

GP[12]

HD13/

GP[13]

DDVSS

HD9/

HD6/

GP[9]

AHCLKR1

HD10/

GP[10]

HD11/

GP[11]

HD8/ GP[8]

HCNTL0/ AXR1[3]

HDS2/

AXR1[5]

HAS/

ACLKX1

HD2/

AFSX1

HD5/

AHCLKX1

HD7/ GP[3]

HRDY/

ACLKR1

HCNTL1/

AXR1[1]

HDS1/

AXR1[6]

HD4/ GP[0]

DDVSS

HHWIL/ AFSR1

HR/W/

AXR1[0]

HCS/

AXR1[2]

HD0/

AXR1[4]

HD1/

AXR1[7]

HD3/

AMUTE1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

GDP 272-Ball BGA package (bottom view) (continued)

Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

A1 V

A2 V

A3 CLKIN C3 CV

A4 CV

A5 RSV C5 PLLHV

A6 TCK C6 V

A7 TDI C7 CV

A8 TDO C8 V

A9 CV

A10 CV

A11 V

A12 RSV C12 RSV

A13 RESET C13 NMI

A14 V

A15 HD13/GP[13] C15 HD12/GP[12]

A16 HD11/GP[11] C16 HD9/GP[9]

A17 DV

A18 HD7/GP[3] C18 CV

A19 V

A20 V

B1 V

B2 CV

B3 DV

B4 V

B5 RSV D5 CV

B6 TRST D6 CV

B7 TMS D7 RSV

B8 DV

B9 EMU1 D9 EMU0

B10 EMU3 D10 CLKOUT3

B11 RSV D11 CV

B12 EMU5 D12 RSV

B13 DV

B14 HD15/GP[15] D14 CV

B15 V

B16 HD10/GP[10] D16 DV

B17 HD8/GP[8] D17 V

B18 HD5/AHCLKX1 D18 HD2/AFSX1

B19 CV

B20 V

Shading denotes the GDP package pin functions that drop out on the PYP package.

C1 GP[5](EXT_INT5)/AMUTEIN0

C2 GP[4](EXT_INT4)/AMUTEIN1

C4 CLKMODE0

C9 V

C10 DV

C11 EMU4

C14 HD14/GP[14]

C17 HD6/AHCLKR1

C19 HD4/GP[0]

C20 HD3/AMUTE1

D1 DV

D2 GP[6](EXT_INT6)

D3 EMU2

D4 V

D8 V

D13 V

D15 CV

D19 DV

D20 HD1/AXR1[7]

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

E1 CLKS1/SCL1 J17 HOLD

E2 V

E3 GP[7](EXT_INT7) J19 BUSREQ

E4 V

E17 V

E18 HAS/ACLKX1 K2 V

E19 HDS1/AXR1[6] K3 CLKS0/AHCLKR0

E20 HD0/AXR1[4] K4 CV

F1 TOUT1/AXR0[4] K9 V

F2 TINP1/AHCLKX0 K10 V

F3 DV

F4 CV

F17 CV

F18 HDS2/AXR1[5] K18 ED0

F19 V

F20 HCS/AXR1[2] K20 V

G1 TOUT0/AXR0[2] L1 FSX1

G2 TINP0/AXR0[3] L2 DX1/AXR0[5]

G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0

G4 V

G17 V

G18 HCNTL0/AXR1[3] L10 V

G19 HCNTL1/AXR1[1] L11 V

G20 HR/W/AXR1[0] L12 V

H1 FSX0/AFSX0 L17 CV

H2 DX0/AXR0[1] L18 ED2

H3 CLKR0/ACLKR0 L19 ED3

H4 V

H17 V

H18 DV

H19 HRDY/ACLKR1 M3 FSR1/AXR0[7]

H20 HHWIL/AFSR1 M4 V

J1 DR0/AXR0[0] M9 V

J2 DV

J3 FSR0/AFSR0 M11 V

J4 V

J9 V

J10 V

J11 V

J12 V

Shading denotes the GDP package pin functions that drop out on the PYP package.

J18 HOLDA

J20 HINT/GP[1]

K1 CV

K11 V

K12 V

K17 CV

K19 ED1

L4 CV

L9 V

L20 CV

M1 CLKR1/AXR0[6]

M2 DR1/SDA1

M10 V

M12 V

M17 V

M18 DV

M19 ED4

M20 ED5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

N1 SCL0 U9 V

N2 SDA0 U10 CV

N3 ED31 U11 CV

N4 V

N17 V

U12 DV

U13 V

N18 ED6 U14 CV

N19 ED7 U15 CV

N20 ED8 U16 DV

P1 ED28 U17 V

P2 ED29 U18 EA21

P3 ED30 U19 BE1

P4 V

P17 V

U20 V

P18 ED9 V2 ED19

P19 V

P20 ED10 V4 ED16

R1 DV

R2 ED27 V6 CE3

R3 ED26 V7 EA3

R4 CV

R17 CV

R18 DV

V10 EA10

R19 ED11 V11 ARE/SDCAS/SSADS

R20 ED12 V12 AWE/SDWE/SSWE

T1 ED24 V13 DV

T2 ED25 V14 EA12

T3 DV

T4 V

T17 V

V15 DV

V16 EA17

V17 CE0

T18 ED13 V18 CV

T19 ED15 V19 DV

T20 ED14 V20 BE0

U1 ED22 W1 V

U2 ED21 W2 CV

U3 ED23 W3 DV

U4 V

U5 DV

U6 CV

U7 DV

U8 V

Shading denotes the GDP package pin functions that drop out on the PYP package.

V1 ED20

V3 CV

V5 BE3

V8 EA5

V9 EA8

W4 ED17

W5 V

W6 CE2

W7 EA4

W8 EA6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

W9 DV

W10 AOE/SDRAS/SSOE Y6 EA2

W11 V

W12 DV

W13 EA11 Y9 EA9

W14 EA13 Y10 ECLKOUT

W15 EA15 Y11 ECLKIN

W16 V

W17 EA19 Y13 V

W18 CE1 Y14 EA14

W19 CV

W20 V

Y1 V

Y2 V

Y3 ED18 Y19 V

Y4 BE2 Y20 V

Shading denotes the GDP package pin functions that drop out on the PYP package.

Y5 ARDY

Y7 DV

Y8 EA7

Y12 CLKOUT2/GP[2]

Y15 EA16

Y16 EA18

Y17 DV

Y18 EA20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

PYP PowerPAD QFP package (top view)

HD5/AHCLKX1

HD8/GP[8]

HD6/AHCLKR1

V HD7/GP[3] HD9/GP[9]

HD10/GP[10]

HD11/GP[11]

HD12/GP[12]

HD13/GP[13] HD14/GP[14] HD15/GP[15]

NMI

RESET

RSV

CLKOUT3

EMU1 EMU0

TDO

TDI TMS TCK

CV CV

TRST

RSV

V RSV

PLLHV

CLKIN

CLKMODE0

PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP)

( TOP VIEW )

HCS/AXR1[2]

HD0/AXR1[4]

HCNTL0/AXR1[3]

148

147

146

145

W/AXR1[0]

HCNTL1/AXR1[1]

HR/

144

143

142

141

HAS/ACLKX1

HDS1/AXR1[6]

HD3/AMUTE1

HD1/AXR1[7]

154

153

152

151

150

HDS2/AXR1[5]

149

HD4/GP[0]

HD2/AFSX1

156

155

157

158

159 160 161 162

163

164 165 166 167 168 169

DD SS

170

171 172 173 174 175 176 177

178 179 180 181 182

SS DD

183 184 185 186 187 188

DD SS

189

190 191 192 193

194

195

196 197 198

199 200

201 202

203 204 205 206

207

208

1234567891011121314151617181920212223242526272829303132333435363738394041

HRDY/ACLKR1

HOLDA

HOLD

HHWIL/AFSR1

140

139

138

137

/GP[1]

BUSREQ

HINT

136

135

134

110

BE0

EA21

109

BE1

108

107

106

105

104

CE1

103

CE0

102 101

EA20

100

EA19 EA17

EA18

EA15

EA12

EA16

EA13

EA14

EA11

AWE/SDWE/SSWE

CLKOUT2/GP[2]

ARE/SDCAS/SSADS

ECLKIN

ECLKOUT

EA10

AOE/SDRAS/SSOE

EA9

EA8

EA7

EA6

EA5

EA4

EA3

EA2

CE2

CE3

ARDY

ED0

ED1

ED2

133

132

131

130

ED3

129

ED5

128

ED4

127

126

ED8

ED7

125

124

123

122

ED6

121

ED10

120

ED9

119

ED12

118

ED11

117

ED14

ED15

ED13

111

116

115

114

113

112

434445464748495051

CLKS1/SCL1

GP[6](EXT_INT6)

GP[7](EXT_INT7)

GP[5](EXT_INT5)/AMUTEIN0

GP[4](EXT_INT4)/AMUTEIN1

TOUT1/AXR0[4]

TINP1/AHCLKX0

CLKX0/ACLKX0

DX0/AXR0[1]

TINP0/AXR0[3]

TOUT0/AXR0[2]

CLKR0/ACLKR0

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DDCVDD

FSX0/AFSX0

FSR0/AFSR0

DR0/AXR0[0]

FSX1

DX1/AXR0[5]

CLKX1/AMUTE0

CLKS0/AHCLKR0

DR1/SDA1

CLKR1/AXR0[6]

DDCVDDCVDD

SCL0

SDA0

FSR1/AXR0[7]

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

description

The TMS320C67xt DSPs (including the TMS320C6713 and TMS320C6713B devices†) compose the floating-point DSP generation in the TMS320C6000t DSP platform. The C6713 and C6713B devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713/13B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713/13B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM.

The C6713/13B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713/13B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713/13B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713/13B device has two bootmodes: from the HPI or from external asynchronous ROM. For

more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt kernel.

TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.

†

Throughout the remainder of this document, the TMS320C6713 and TMS320C6713B shall be referred to as TMS320C67x or C67x or 13/13B where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6713, C6713B, 13, or 13B, etc.

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TMS320C6713, TMS320C6713B

HARDWARE FEATURES

Peripherals

Not all

available at the same

Configuration section.)

dependent on chip-level

Voltage

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

device characteristics

Table 2 provides an overview of the C6713/C6713B DSPs. The table shows significant features of the each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 24 and Figure 12.

Table 2. Characteristics of the C6713 and C6713B Processors

HARDWARE FEATURES

Peripherals

peripheral pins are available at the same time. (For more details, see the Device Confi

uration section.)

Peripheral performance is

nn n hi-lv

configuration.

On-Chip Memory

CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203

BSDL File For the C6713/13B BSDL file, contact your Field Sales Representative.

Frequency MHz 300, 225, 200 200, 167

Cycle Time ns

Voltage

Clock Generator Options

Packages

†

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

‡

AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit.

This value is compatible with existing 1.26V designs.

EMIF SYSCLK3 or ECLKIN 1 (32 bit) 1 (16 bit)

EDMA (16 Channels)

HPI (16 bit) SYSCLK2 1

McASPs AUXCLK, SYSCLK2

I2Cs SYSCLK2 2

McBSPs SYSCLK2 2

32-Bit Timers 1/2 of SYSCLK2 2

GPIO Module SYSCLK2 1

Size (Bytes) 264K

Organization

Core (V)

I/O (V) 3.3 V

Prescaler Multiplier Postscaler

27 x 27 mm 272-Ball BGA (GDP) −

28 x 28 mm −

INTERNAL CLOCK

SOURCE

CPU clock frequency 1

‡

3.3 ns (C6713BGDP-300)

4.4 ns (C6713BGDP-225) 5 ns (C6713BGDPA-200)

4.4 ns (C6713GDP-225) 5 ns (C6713GDPA-200)

1.20§ V (C6713/C6713B)

GDP PYP

1.4 V (C6713B−300)

C6713/C6713B

(FLOATING-POINT DSPs)

4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB L2 Mapped RAM

5 ns (C6713BPYP-200)

6 ns (C6713BPYPA-167)

5 ns (C6713PYP-200)

6 ns (C6713PYPA-167)

1.2 V

/1, /2, /3, ..., /32

x4, x5, x6, ..., x25

/1, /2, /3, ..., /32

208-Pin PowerPAD

PQFP (PYP)

C67x is a trademark of Texas Instruments.

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Table 2. Characteristics of the C6713 and C6713B Processors (Continued)

HARDWARE FEATURES

Process Technology µm 0.13

Product Status

†

‡

AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit.

†

Product Preview (PP) Advance Information (AI) Production Data (PD)

INTERNAL CLOCK

SOURCE

PD (13) PD (13, 13B)

C6713/C6713B

(FLOATING-POINT DSPs)

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functional block and CPU (DSP core) diagram

C6713/13B Digital Signal Processors

Pin Multiplexing

EMIF

McASP1

McASP0

McBSP1

McBSP0

I2C1

I2C0

Timer 1

Timer 0

Enhanced

DMA

Controller

(16 channel)

L2 Cache/

Memory 4 Banks

64K Bytes

Total

(up to

4-Way)

Memory

192K

Bytes

L1P Cache Direct Mapped 4K Bytes Total

C67x CPU

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2

Clock Generator and PLL

x4 through x25 Multiplier

/1 through /32 Dividers

Data Path B

B Register File

L1D Cache

2-Way

Set Associative

4K Bytes

Power-Down

Control

Registers

Control

In-Circuit

Emulation

Interrupt

†

Control

Logic

Test

GPIO

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

EMIF interfaces to:

−SDRAM

−SBSRAM

−SRAM,

−ROM/Flash, and

HPI

McBSPs interface to:

−SPI Control Port

−High-Speed TDM Codecs

−AC97 Codecs

−Serial EEPROM

McASPs interface to:

−I2S Multichannel ADC, DAC, Codec, DIR

−DIT: Multiple Outputs

−I/O devices

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

CPU (DSP core) description

The TMS320C6713/13B floating-point digital signal processor is based on the C67x CPU. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

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CPU (DSP core) description (continued)

†

.L1

long dst long src

LD1 32 MSB

Data Path A

ST1

LD1 32 LSB

DA1

.S1

.M1

.D1

long src long dst

†

src1

src2

dst

src1 src2

dst

src1 src2

dst src1 src2

File A

(A0−A15)

Data Path B

DA2

LD2 32 LSB

LD2 32 MSB

ST2

.D2

.M2

.S2

.L2

src2 src1

dst

src2

†

src1

dst src2

src1

†

dst

long dst long src

long src long dst

dst

†

src2

src1

File B

(B0−B15)

Control

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 1. TMS320C67x CPU (DSP Core) Data Paths

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memory map summary

Table 3 shows the memory map address ranges of the C6713/13B devices.

Table 3. TMS320C6713/13B Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Internal RAM (L2) 192K 0000 0000 – 0002 FFFF

Internal RAM/Cache 64K 0003 0000 – 0003 FFFF

Reserved 24M – 256K 0004 0000 – 017F FFFF

External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF

L2 Registers 128K 0184 0000 – 0185 FFFF

Reserved 128K 0186 0000 – 0187 FFFF

HPI Registers 256K 0188 0000 – 018B FFFF

McBSP 0 Registers 256K 018C 0000 – 018F FFFF

McBSP 1 Registers 256K 0190 0000 – 0193 FFFF

Timer 0 Registers 256K 0194 0000 – 0197 FFFF

Timer 1 Registers 256K 0198 0000 – 019B FFFF

Interrupt Selector Registers 512 019C 0000 – 019C 01FF

Device Configuration Registers 4 019C 0200 – 019C 0203

Reserved 256K − 516 019C 0204 – 019F FFFF

EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF

Reserved 768K 01A4 0000 – 01AF FFFF

GPIO Registers 16K 01B0 0000 – 01B0 3FFF

Reserved 240K 01B0 4000 – 01B3 FFFF

I2C0 Registers 16K 01B4 0000 – 01B4 3FFF

I2C1 Registers 16K 01B4 4000 – 01B4 7FFF

Reserved 16K 01B4 8000 – 01B4 BFFF

McASP0 Registers 16K 01B4 C000 – 01B4 FFFF

McASP1 Registers 16K 01B5 0000 – 01B5 3FFF

Reserved 160K 01B5 4000 – 01B7 BFFF

PLL Registers 8K 01B7 C000 – 01B7 DFFF

Reserved 264K 01B7 E000 – 01BB FFFF

Emulation Registers 256K 01BC 0000 – 01BF FFFF

Reserved 4M 01C0 0000 – 01FF FFFF

QDMA Registers 52 0200 0000 – 0200 0033

Reserved 16M − 52 0200 0034 – 02FF FFFF

Reserved 720M 0300 0000 – 2FFF FFFF

McBSP0 Data Port 64M 3000 0000 – 33FF FFFF

McBSP1 Data Port 64M 3400 0000 – 37FF FFFF

Reserved 64M 3800 0000 – 3BFF FFFF

McASP0 Data Port 1M 3C00 0000 – 3C0F FFFF

McASP1 Data Port 1M 3C10 0000 – 3C1F FFFF

Reserved 1G + 62M 3C20 0000 – 7FFF FFFF

EMIF CE0

EMIF CE1

EMIF CE2

EMIF CE3

Reserved 1G C000 0000 – FFFF FFFF

†

The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.

†

256M 8000 0000 – 8FFF FFFF

256M 9000 0000 – 9FFF FFFF

256M A000 0000 – AFFF FFFF

256M B000 0000 – BFFF FFFF

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SPRS186I − DECEMBER 2001 − REVISED MAY 2004

L2 memory structure expanded

Figure 2 shows the detail of the L2 memory structure.

L2 Mode L2 Memory Block Base Address

000

256K SRAM (All)

011010001 111

0x0000 0000

192K-Byte RAM

192K SRAM

208K SRAM

224K SRAM

240K SRAM

0x0003 0000

16K-Byte RAM

16K

1-Way

Cache

32K

2-Way Cache

16K-Byte RAM

64K 4-Way Cache

48K 3-Way Cache

16K-Byte RAM

Figure 2. L2 Memory Configuration

0x0003 4000

0x0003 8000

0x0003 C000

0x0003 FFFF

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

peripheral register descriptions

Table 4 through Table 17 identify the peripheral registers for the C6713/C6713B devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the

TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

Table 4. EMIF Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0180 0000 GBLCTL EMIF global control

0180 0004 CECTL1 EMIF CE1 space control

0180 0008 CECTL0 EMIF CE0 space control

0180 000C − Reserved

0180 0010 CECTL2 EMIF CE2 space control

0180 0014 CECTL3 EMIF CE3 space control

0180 0018 SDCTL EMIF SDRAM control

0180 001C SDTIM EMIF SDRAM refresh control

0180 0020 SDEXT EMIF SDRAM extension

0180 0024 − 0183 FFFF − Reserved

Table 5. L2 Cache Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0184 0000 CCFG Cache configuration register

0184 4000 L2WBAR L2 writeback base address register

0184 4004 L2WWC L2 writeback word count register

0184 4010 L2WIBAR L2 writeback-invalidate base address register

0184 4014 L2WIWC L2 writeback-invalidate word count register

0184 4020 L1PIBAR L1P invalidate base address register

0184 4024 L1PIWC L1P invalidate word count register

0184 4030 L1DWIBAR L1D writeback-invalidate base address register

0184 4034 L1DWIWC L1D writeback-invalidate word count register

0184 5000 L2WB L2 writeback all register

0184 5004 L2WBINV L2 writeback-invalidate all register

0184 8200 MAR0 Controls CE0 range 8000 0000 − 80FF FFFF

0184 8204 MAR1 Controls CE0 range 8100 0000 − 81FF FFFF

0184 8208 MAR2 Controls CE0 range 8200 0000 − 82FF FFFF

0184 820C MAR3 Controls CE0 range 8300 0000 − 83FF FFFF

0184 8240 MAR4 Controls CE1 range 9000 0000 − 90FF FFFF

0184 8244 MAR5 Controls CE1 range 9100 0000 − 91FF FFFF

0184 8248 MAR6 Controls CE1 range 9200 0000 − 92FF FFFF

0184 824C MAR7 Controls CE1 range 9300 0000 − 93FF FFFF

0184 8280 MAR8 Controls CE2 range A000 0000 − A0FF FFFF

0184 8284 MAR9 Controls CE2 range A100 0000 − A1FF FFFF

0184 8288 MAR10 Controls CE2 range A200 0000 − A2FF FFFF

0184 828C MAR11 Controls CE2 range A300 0000 − A3FF FFFF

0184 82C0 MAR12 Controls CE3 range B000 0000 − B0FF FFFF

0184 82C4 MAR13 Controls CE3 range B100 0000 − B1FF FFFF

0184 82C8 MAR14 Controls CE3 range B200 0000 − B2FF FFFF

0184 82CC MAR15 Controls CE3 range B300 0000 − B3FF FFFF

0184 82D0 − 0185 FFFF − Reserved

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peripheral register descriptions (continued)

Table 6. Interrupt Selector Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

019C 0000 MUXH Interrupt multiplexer high

019C 0004 MUXL Interrupt multiplexer low

019C 0008 EXTPOL External interrupt polarity

019C 000C − 019F FFFF − Reserved

Table 7. Device Registers

HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION

019C 0200 DEVCFG Device Configuration

019C 0204 − 019F FFFF − Reserved

N/A CSR CPU Control Status Register

Selects which interrupts drive CPU interrupts 10−15 (INT10−INT15)

Selects which interrupts drive CPU interrupts 4−9 (INT04−INT09)

Sets the polarity of the external interrupts (EXT_INT4−EXT_INT7)

Allows the user to control peripheral selection. This register also offers the user control of the EMIF input clock source. For more detailed information on the device configuration register, see the Device Configurations section of this data sheet.

Identifies which CPU and defines the silicon revision of the CPU. This register also offers the user control of device operation. For more detailed information on the CPU Control Status Register, see the CPU CSR Register Description section of this data sheet.

Table 8. EDMA Parameter RAM

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event

01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event

01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event

01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event

01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event

01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event

01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event

01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event

01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event

01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event

01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event

01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event

01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event

01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event

01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event

01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event

01A0 0180 − 01A0 0197 − Reload/link parameters for Event 0−15

01A0 0198 − 01A0 01AF − Reload/link parameters for Event 0−15

... ...

01A0 07E0 − 01A0 07F7 − Reload/link parameters for Event 0−15

01A0 07F8 − 01A0 07FF − Scratch pad area (2 words)

†

The C6713/13B device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

†

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peripheral register descriptions (continued)

For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3.

31 0 EDMA Parameter

Word 0 EDMA Channel Options Parameter (OPT)

Word 1 EDMA Channel Source Address (SRC) SRC

Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT

Word 3 EDMA Channel Destination Address (DST) DST

Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX

Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD

Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event

Table 9. EDMA Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A0 0800 − 01A0 FEFC − Reserved

01A0 FF00 ESEL0 EDMA event selector 0

01A0 FF04 ESEL1 EDMA event selector 1

01A0 FF08 − 01A0 FF0B − Reserved

01A0 FF0C ESEL3 EDMA event selector 3

01A0 FF1F − 01A0 FFDC − Reserved

01A0 FFE0 PQSR Priority queue status register

01A0 FFE4 CIPR Channel interrupt pending register

01A0 FFE8 CIER Channel interrupt enable register

01A0 FFEC CCER Channel chain enable register

01A0 FFF0 ER Event register

01A0 FFF4 EER Event enable register

01A0 FFF8 ECR Event clear register

01A0 FFFC ESR Event set register

01A1 0000 − 01A3 FFFF – Reserved

OPT

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peripheral register descriptions (continued)

Table 10. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE

0200 0000 QOPT QDMA options parameter register

0200 0004 QSRC QDMA source address register

0200 0008 QCNT QDMA frame count register

0200 000C QDST QDMA destination address register

0200 0010 QIDX QDMA index register

0200 0014 − 0200 001C − Reserved

0200 0020 QSOPT QDMA pseudo options register

0200 0024 QSSRC QDMA pseudo source address register

0200 0028 QSCNT QDMA pseudo frame count register

0200 002C QSDST QDMA pseudo destination address register

0200 0030 QSIDX QDMA pseudo index register

†

All the QDMA and Pseudo registers are write-accessible only

ACRONYM REGISTER NAME

Table 11. PLL Controller Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01B7 C000 PLLPID Peripheral identification register (PID) [C6713/13B value: 0x00010801 for PLL Controller]

01B7 C004 − 01B7 C0FF − Reserved

01B7 C100 PLLCSR PLL control/status register

01B7 C104 − 01B7 C10F − Reserved

01B7 C110 PLLM PLL multiplier control register

01B7 C114 PLLDIV0 PLL controller divider 0 register

01B7 C118 PLLDIV1 PLL controller divider 1 register

01B7 C11C PLLDIV2 PLL controller divider 2 register

01B7 C120 PLLDIV3 PLL controller divider 3 register

01B7 C124 OSCDIV1 Oscillator divider 1 register

01B7 C128 − 01B7 DFFF − Reserved

†

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peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

HEX ADDRESS RANGE

McASP0 McASP1

3C00 0000 − 3C00 FFFF 3C10 0000 − 3C10 FFFF RBUF/XBUFx

01B4 C000 01B5 0000 MCASPPIDx

01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management register

01B4 C008 01B5 0008 − Reserved

01B4 C00C 01B5 000C − Reserved

01B4 C010 01B5 0010 PFUNCx Pin function register

01B4 C014 01B5 0014 PDIRx Pin direction register

01B4 C018 01B5 0018 PDOUTx Pin data out register

01B4 C01C 01B5 001C PDIN/PDSETx

01B4 C020 01B5 0020 PDCLRx Pin data clear register

01B4 C024 − 01B4 C040 01B5 0024 − 01B5 0040 − Reserved

01B4 C044 01B5 0044 GBLCTLx Global control register

01B4 C048 01B5 0048 AMUTEx Mute control register

01B4 C04C 01B5 004C DLBCTLx Digital Loop-back control register

01B4 C050 01B5 0050 DITCTLx DIT mode control register

01B4 C054 − 01B4 C05C 01B5 0054 − 01B5 005C − Reserved

01B4 C060 01B5 0060 RGBLCTLx

01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask register

01B4 C068 01B5 0068 RFMTx Receive bit stream format register

01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control register

01B4 C070 01B5 0070 ACLKRCTLx Receive clock control register

01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control register

01B4 C078 01B5 0078 RTDMx Receive TDM slot 0−31 register

01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control register

01B4 C080 01B5 0080 RSTATx Status register − Receiver

01B4 C084 01B5 0084 RSLOTx Current receive TDM slot register

01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control register

01B4 C08C − 01B4 C09C 01B5 008C − 01B5 009C − Reserved

01B4 C0A0 01B5 00A0 XGBLCTLx

01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask register

01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format register

01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control register

01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control register

01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control register

ACRONYM REGISTER NAME

McASPx receive buffer or McASPx transmit buffer via the Peripheral Data Bus. (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].)

Peripheral Identification register [13/13B value: 0x00100101 for McASP0 and for McASP1]

Pin data in / data set register Read returns: PDIN Writes affect: PDSET

Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive.

Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive.

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TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers (Continued)

HEX ADDRESS RANGE

McASP0

01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0−31 register

01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control register

01B4 C0C0 01B5 00C0 XSTATx Status register − Transmitter

01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot

01B4 C0C8 01B5 00C8 XCLKCHKx Transmit clock check control register

01B4 C0D0 − 01B4 C0FC 01B5 00CC − 01B5 00FC − Reserved

01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file

01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file

01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file

01B4 C10C 01B5 010C DITCSRA3x Left (even TDM slot) channel status register file

01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file

01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file

01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file

01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file

01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file

01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file

01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file

01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file

01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file

01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file

01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file

01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file

01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file

01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file

01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file

01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file

01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file

01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file

01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file

01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file

01B4 C160 − 01B4 C17C 01B5 0160 − 01B5 017C − Reserved

01B4 C180 01B5 0180 SRCTL0x Serializer 0 control register

01B4 C184 01B5 0184 SRCTL1x Serializer 1 control register

01B4 C188 01B5 0188 SRCTL2x Serializer 2 control register

01B4 C18C 01B5 018C SRCTL3x Serializer 3 control register

01B4 C190 01B5 0190 SRCTL4x Serializer 4 control register

01B4 C194 01B5 0194 SRCTL5x Serializer 5 control register

01B4 C198 01B5 0198 SRCTL6x Serializer 6 control register

01B4 C19C 01B5 019C SRCTL7x Serializer 7 control register

01B4 C1A0 − 01B4 C1FC 01B5 01A0 − 01B5 01FC − Reserved

McASP1

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peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers (Continued)

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

HEX ADDRESS RANGE

McASP0

McASP1

01B4 C200 01B5 0200 XBUF0x Transmit Buffer for Serializer 0 through configuration bus

01B4 C204 01B5 0204 XBUF1x Transmit Buffer for Serializer 1 through configuration bus

01B4 C208 01B5 0208 XBUF2x Transmit Buffer for Serializer 2 through configuration bus

01B4 C20C 01B5 020C XBUF3x Transmit Buffer for Serializer 3 through configuration bus

01B4 C210 01B5 0210 XBUF4x Transmit Buffer for Serializer 4 through configuration bus

01B4 C214 01B5 0214 XBUF5x Transmit Buffer for Serializer 5 through configuration bus

01B4 C218 01B5 0218 XBUF6x Transmit Buffer for Serializer 6 through configuration bus

01B4 C21C 01B5 021C XBUF7x Transmit Buffer for Serializer 7 through configuration bus

01B4 C220 − 01B4 C27C 01B5 C220 − 01B5 027C − Reserved

01B4 C280 01B5 0280 RBUF0x Receive Buffer for Serializer 0 through configuration bus

01B4 C284 01B5 0284 RBUF1x Receive Buffer for Serializer 1 through configuration bus

01B4 C288 01B5 0288 RBUF2x Receive Buffer for Serializer 2 through configuration bus

01B4 C28C 01B5 028C RBUF3x Receive Buffer for Serializer 3 through configuration bus

01B4 C290 01B5 0290 RBUF4x Receive Buffer for Serializer 4 through configuration bus

01B4 C294 01B5 0294 RBUF5x Receive Buffer for Serializer 5 through configuration bus

01B4 C298 01B5 0298 RBUF6x Receive Buffer for Serializer 6 through configuration bus

01B4 C29C 01B5 029C RBUF7x Receive Buffer for Serializer 7 through configuration bus

01B4 C2A0 − 01B4 FFFF 01B5 02A0 − 01B5 3FFF − Reserved

†

The transmit buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register).

‡

The receive buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register).

†

‡

Table 13. I2C0 and I2C1 Registers

HEX ADDRESS RANGE

I2C0 I2C1

01B4 0000 01B4 4000 I2COARx I2Cx own address register

01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register

01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register

01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register

01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register

01B4 0014 01B4 4014 I2CCNTx I2Cx data count register

01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register

01B4 001C 01B4 401C I2CSARx I2Cx slave address register

01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register

01B4 0024 01B4 4024 I2CMDRx I2Cx mode register

01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source register

01B4 002C 01B4 402C − Reserved

01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register

01B4 0034 01B4 4034

01B4 0038 01B4 4038

01B4 003C − 01B4 3FFF 01B4 403C − 01B4 7FFF − Reserved

ACRONYM REGISTER DESCRIPTION

I2CPID10

I2CPID11

I2CPID20 I2CPID21

I2Cx Peripheral Identification register 1 [C6713/13B value: 0x0000 0103

I2Cx Peripheral Identification register 2 [C6713/13B value: 0x0000 0005

]

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TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

peripheral register descriptions (continued)

Table 14. HPI Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

− HPID HPI data register Host read/write access only

− HPIA HPI address register Host read/write access only

0188 0000 HPIC HPI control register Both Host/CPU read/write access

0188 0004 − 018B FFFF − Reserved

Table 15. Timer 0 and Timer 1 Registers

HEX ADDRESS RANGE

TIMER 0 TIMER 1

0194 0000 0198 0000 CTLx Timer x control register

0194 0004 0198 0004 PRDx Timer x period register

0194 0008 0198 0008 CNTx Timer x counter register

0194 000C − 0197 FFFF 0198 000C − 019B FFFF − Reserved −

ACRONYM REGISTER NAME COMMENTS

Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.

Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency.

Contains the current value of the incrementing counter.

Table 16. McBSP0 and McBSP1 Registers

HEX ADDRESS RANGE

McBSP0 McBSP1

018C 0000 0190 0000 DRRx

3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus

018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus

3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus

018C 0008 0190 0008 SPCRx McBSPx serial port control register

018C 000C 0190 000C RCRx McBSPx receive control register

018C 0010 0190 0010 XCRx McBSPx transmit control register

018C 0014 0190 0014 SRGRx McBSPx sample rate generator register

018C 0018 0190 0018 MCRx McBSPx multichannel control register

018C 001C 0190 001C RCERx McBSPx receive channel enable register

018C 0020 0190 0020 XCERx McBSPx transmit channel enable register

018C 0024 0190 0024 PCRx McBSPx pin control register

018C 0028 − 018F FFFF 0190 0028 − 0193 FFFF − Reserved

ACRONYM REGISTER DESCRIPTION

McBSPx data receive register via Configuration Bus

The CPU and EDMA controller can only read this register; they cannot write to it.

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

peripheral register descriptions (continued)

Table 17. GPIO Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01B0 0000 GPEN GPIO enable register

01B0 0004 GPDIR GPIO direction register

01B0 0008 GPVAL GPIO value register

01B0 000C − Reserved

01B0 0010 GPDH GPIO delta high register

01B0 0014 GPHM GPIO high mask register

01B0 0018 GPDL GPIO delta low register

01B0 001C GPLM GPIO low mask register

01B0 0020 GPGC GPIO global control register

01B0 0024 GPPOL GPIO interrupt polarity register

01B0 0028 − 01B0 3FFF − Reserved

TMS320C6713, TMS320C6713B

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

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TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

signal groups description

CLKIN

CLKOUT2/GP[2]

CLKOUT3

CLKMODE0

PLLHV

TMS TDO

TDI

TCK

TRST EMU0 EMU1

EMU2 EMU3 EMU4 EMU5

†

Clock/PLL

Oscillator

IEEE Standard

1149.1

(JTAG)

Emulation

Reset and

Interrupts

Control/Status

RESET NMI GP[7](EXT_INT7) GP[6](EXT_INT6)

‡§

GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1

HD4/GP[0]

‡

‡§

HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12]

HD11/GP[11] HD10/GP[10]

HD9/GP[9] HD8/GP[8] HD7/GP[3]

Data

(Host-Port Interface)

Control

HAS HR/W HCS HDS1 HDS2 HRDY HINT

/ACLKX1

/AXR1[0]

/AXR1[2]

/AXR1[6] /AXR1[5]

/ACLKR1

/GP[1]

HD6/AHCLKR1

HPI

HD5/AHCLKX1

HD4/GP[0]

HD3/AMUTE1

HCNTL0/AXR1[3]

HCNTL1/AXR1[1]

HD2/AFSX1

HD1/AXR1[7]

HD0/AXR1[4]

†

These external pins are applicable to the GDP package only.

‡

The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the External

Half-Word

Select

HHWIL/AFSR1

Interrupt Sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).

All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Figure 4. CPU (DSP Core) and Peripheral Signals

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signal groups description (continued)

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

HD8/GP[8]

TOUT1/AXR0[4]

TINP1/AHCLKX0

CLKS1/SCL1

DR1/SDA1

†

GPIO

General-Purpose Input/Output (GPIO) Port

Timer 1 Timer 0

Timers

I2C1 I2C0

GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1

HD7/GP[3] CLKOUT2/GP[2] HINT

/GP[1]

HD4/GP[0]

TOUT0/AXR0[2] TINP0/AXR0[3]

SCL0

SDA0

I2Cs

†

The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Figure 5. Peripheral Signals

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TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

signal groups description (continued)

ED[31:16]

ED[15:0]

CE3 CE2 CE1 CE0

EA[21:2]

BE3 BE2

BE1 BE0

†

Data

Memory Map Space Select

Address

Byte Enables

(External Memory Interface)

McBSP1 McBSP0

Memory

Control

Bus

Arbitration

EMIF

ECLKIN ECLKOUT ARE/SDCAS/SSADS

AOE

/SDRAS/SSOE AWE/SDWE/SSWE ARDY

HOLD HOLDA

BUSREQ

CLKX1/AMUTE0

FSX1

DX1/AXR0[5]

CLKR1/AXR0[6]

FSR1/AXR0[7]

DR1/SDA1

CLKS1/SCL1

†

These external pins are applicable to the GDP package only.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Transmit Transmit

Receive Receive

Clock Clock

McBSPs

(Multichannel Buffered Serial Ports)

CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1]

CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0]

CLKS0/AHCLKR0

Figure 5. Peripheral Signals (Continued)

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signal groups description (continued)

(Transmit/Receive Data Pins)

FSR1/AXR0[7]

CLKR1/AXR0[6]

DX1/AXR0[5]

TOUT1/AXR0[4]

TINP0/AXR0[3]

TOUT0/AXR0[2]

DX0/AXR0[1] DR0/AXR0[0]

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

(Receive Bit Clock) (Transmit Bit Clock)

CLKR0/ACLKR0

CLKS0/AHCLKR0

(Receive Master Clock) (Transmit Master Clock)

FSR0/AFSR0

(Receive Frame Sync or

Left/Right Clock)

NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.

B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

Receive Clock

Generator

Receive Clock

Check Circuit

Receive

Frame Sync

Error Detect

(see Note A)

(Multichannel Audio Serial Port 0)

Auto Mute

McASP0

Transmit

Generator

Transmit

Clock Check

Frame Sync

Logic

Clock

Circuit

Transmit

CLKX0/ACLKX0

TINP1/AHCLKX0

FSX0/AFSX0

(Transmit Frame Sync or Left/Right Clock)

CLKX1/AMUTE0

GP[5](EXT_INT5)/AMUTEIN0

Figure 5. Peripheral Signals (Continued)

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TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

signal groups description (continued)

(Transmit/Receive Data Pins)

HD1/AXR1[7] HDS1/AXR1[6] HDS2

/AXR1[5]

HD0/AXR1[4]

HCNTL0/AXR1[3]

/AXR1[2]

HCS

HCNTL1/AXR1[1]

/AXR1[0]

HR/W

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

(Receive Bit Clock) (Transmit Bit Clock)

HRDY/ACLKR1

HD6/AHCLKR1

(Receive Master Clock) (Transmit Master Clock)

HHWIL/AFSR1

(Receive Frame Sync or

Left/Right Clock)

NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.

B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

Receive Clock

Generator

Receive Clock

Check Circuit

Receive

Frame Sync

Error Detect (see Note A)

McASP1

(Multichannel Audio Serial Port 1)

Transmit

Generator

Transmit

Clock Check

Frame Sync

Auto Mute

Logic

Clock

Circuit

Transmit

HAS/ACLKX1 HD5/AHCLKX1

HD2/AFSX1

(Transmit Frame Sync or Left/Right Clock)

HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1

Figure 5. Peripheral Signals (Continued)

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TEXAS INSTRUMENTS TMS320C6713, TMS320C6713B Technical data

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