Texas Instruments TMS320C6201, TMS320C6701, TMS320C6711, TMS320C6211, TMS320C6202 Reference Manual

TMS320C6000 Peripherals

Reference Guide

Literature Number: SPRU190C

April 1999

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify , before placing orders, that the information being relied
on is current.

TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI’s standard warranty . T esting and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death,
personal injury , or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer .
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.

In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright  1999, Texas Instruments Incorporated

About This Manual

Preface

Read This First

This reference guide describes the on-chip peripherals of the TMS320C6000
digital signal processors (DSPs). Main topics are the program memory, the data
memory , the direct memory access (DMA) controller, the enhanced DMA control­ler (EDMA), the host-port interface (HPI), the exansion bus, the external memory
interface (EMIF), the boot configuration, the multichannel buffered serial ports
(McBSPs), the timers, the interrupt selector and external interrupts, and the pow­er-down modes.

The TMS320C62x (’C62x) and the TMS320C67x (’C67x) generations of digi­tal signal processors make up the TMS320C6000 platform of the TMS320
family of digital signal processors. The ’C62x devices are fixed-point DSPs,
and the ’C67x devices are floating-point DSPs. The TMS320C6000 (’C6000)
is the first DSP to use the VelociTI architecture, a high-performance,
advanced VLIW (very long instruction word) architecture. The VelocTI archite­chure makes the ’C6x an excellent choice for multichannel, multifunction, and
high data rate applications.

Notational Conventions

This document uses the following conventions:

- Program listings, program examples, names are shown in a special

-

. Here is a sample program listing:

font
LDW .D1 *A0,A1

ADD .L1 A1,A2,A3
NOP 3
MPY .M1 A1,A4,A5

Throughout this book MSB means

least significant bit

.

most significant bit,

Contents

and LSB means

iii

Notational Conventions / Related Documentation From Texas Instruments

Registers are described throughout this book in register diagrams. Each
diagram shows a rectangle divided into fields that represent the fields of the
register. Each field is labeled with its name inside, its beginning and ending bit
numbers above, and its properties below. A legend explains the notation used
for the properties. For example:

31 25 24 23 22 21 20 18 17 16

FIELDA FIELDB FIELDC R, +1 RW, +0

RW, +0 RC, +x R, +0 R, +1 HRW, +0

Note: R = Readable by the CPU, W = Writeable by the CPU, +x = V alue undefined after reset, +0 = Value is 0 after reset,

+1 = Value is 1 after reset, C = Clearable by the CPU, H = reads/writes performed by the host

Related Documentation From Texas Instruments

The following documents describe the TMS320C6x family and related support
tools. To obtain a copy of any of these TI documents, call the Texas Instru­ments Literature Response Center at (800) 477–8924. When ordering, please
identify the book by its title and literature number.

TMS320C6000 Technical Brief

introduction to the ’C6000 platform of digital signal processors, develop­ment tools, and third-party support.

TMS320C6000 CPU and Instruction Set Reference Guide

number SPRU189) describes the ’C6000 CPU architecture, instruction
set, pipeline, and interrupts for these digital signal processors.

TMS320C6000 Programmer’s Guide

describes ways to optimize C and assembly code for the TMS320C6000
DSPs and includes application program examples.

TMS320C6000 Assembly Language Tools User’s Guide

SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the ’C6000 generation of devices.

TMS320C6000 Optimizing C Compiler User’s Guide

SPRU187) describes the ’C6000 C compiler and the assembly optimizer .
This C compiler accepts ANSI standard C source code and produces as­sembly language source code for the ’C6000 generation of devices. The
assembly optimizer helps you optimize your assembly code.

TMS320C6x C Source Debugger User’s Guide

SPRU188) tells you how to invoke the ’C6x simulator and emulator
versions of the C source debugger interface. This book discusses
various aspects of the debugger, including command entry, code
execution, data management, breakpoints, profiling, and analysis.

(literature number SPRU197) gives an

(literature

(literature number SPRU198)

(literature number

(literature number

(literature number

iv

Related Documents / Trademarks

TMS320C6201, TMS320C6201B Digital Signal Processors Data Sheet

(literature number SPRS051) describes the features of the
TMS320C6201 and TMS320C6201B fixed-point DSPs and provides
pinouts, electrical specifications, and timings for the devices.

Trademarks

TMS320C6202 Digital Signal Processor Data Sheet

(literature number
SPRS072) describes the features of the TMS320C6202 fixed-point DSP
and provides pinouts, electrical specifications, and timings for the de­vice.

TMS320C6701 Digital Signal Processor Data Sheet

(literature number
SPRS067) describes the features of the TMS320C6701 floating-point
DSP and provides pinouts, electrical specifications, and timings for the
device.

TMS320C6211 Digital Signal Processor Data Sheet

(literature number
SPRS073) describes the features of the TMS320C621 1 fixed-point DSP
and provides pinouts, electrical specifications, and timings for the de­vice.

TMS320C6711 Digital Signal Processor Data Sheet

(literature number
SPRS088) describes the features of the TMS320C671 1 fixed-point DSP
and provides pinouts, electrical specifications, and timings for the de­vice.

320 Hotline On-line, VelociTI, and XDS510 are trademarks of Texas
Instruments Incorporated.

PC is a trademark of International Business Machines Corporation.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SPI is a trademark of Motorola, Inc.
ST-BUS is a trademark of Mitel.
Windows and Windows NT are registered trademarks of Microsoft Corporation.

Read This First

v

If You Need Assistance

If You Need Assistance . . .

- World-Wide Web Sites

TI Online http://www.ti.com
Semiconductor Product Information Center (PIC) http://www.ti.com/sc/docs/pic/home.htm
DSP Solutions http://www.ti.com/dsps
320 Hotline On-linet http://www.ti.com/sc/docs/dsps/support.htm

- North America, South America, Central America

Product Information Center (PIC) [phone]
TI Literature Response Center U.S.A. [phone]
Software Registration/Upgrades [phone] Fax: [phone]
U.S.A. Factory Repair/Hardware Upgrades [phone]
U.S. T echnical T raining Organization [phone]
DSP Hotline Email: [e-mail]
DSP Internet BBS via anonymous ftp to ftp://ftp.ti.com/pub/tms320bbs

- Europe, Middle East, Africa

European Product Information Center (EPIC) Hotlines:

Multi-Language Support [phone] Fax: [phone]

Email: [e-mail]

Deutsch [phone] or [phone]
English [phone]
Francais [phone]

Italiano [phone]
EPIC Modem BBS [phone]
European Factory Repair [phone]
Europe Customer Training Helpline Fax: [phone]

- Asia-Pacific

Literature Response Center [phone] Fax: [phone]
Hong Kong DSP Hotline [phone] Fax: [phone]
Korea DSP Hotline [phone] Fax: [phone]
Korea DSP Modem BBS [phone]
Singapore DSP Hotline Fax: [phone]
Taiwan DSP Hotline [phone] Fax: [phone]
Taiwan DSP Modem BBS [phone]
Taiwan DSP Internet BBS via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/TI/

- Japan

Product Information Center +0120-81-0026 (in Japan) Fax: [phone] (in Japan)

DSP Hotline [phone] or (INTL) 813-3769-8735 Fax: [phone] or (INTL) 813-3457-7071
DSP BBS via Nifty-Serve Type “Go TIASP”

- Documentation

When making suggestions or reporting errors in documentation, please include the following information that is on the title
page: the full title of the book, the publication date, and the literature number.

Mail: Texas Instruments Incorporated Email: [e-mail]

Technical Documentation Services, MS 702
P.O. Box 1443
Houston, Texas 77251-1443

Note: When calling a Literature Response Center to order documentation, please specify the literature number of the

vi

book.

+03-3457-0972 or (INTL) 813-3457-0972 Fax: [phone] or (INTL) 813-3457-1259

Contents

Contents

1 Introduction 1Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320C6201 and TMS320C6701 DSPs and lists their key features.

1.1 TMS320 Family Overview 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 History of TMS320 DSPs 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Typical Applications for the TMS320 Family 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Overview of the TMS320C6000 Platform of DSPs 1Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Features and Options of the TMS320C6000 Devices 1Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Overview of TMS320C6000 Memory 1Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Overview of TMS320C6000 Peripherals 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 TMS320C6201/C6701 Program and Data Memory 2Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the program and data memory system for the TMS320C6201/C6701. This includes
program memory organization,cache modes, DMA and peripheral bus operation.

2.1 Program Memory Controller 2Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Internal Program Memory 2Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Internal Program Memory Modes 2Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Cache Architecture 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 DMA Controller Access to Program Memory 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Data Memory Controller 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Data Memory Access 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Internal Data Memory Organization 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 TMS320C6201 Revision 2 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 TMS320C6201 Revision 3 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 TMS320C6701 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.4 Data Alignment 2Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.5 Dual CPU Accesses to Internal Memory 2Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.6 DMA Accesses to Internal Memory 2Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.7 Data Endianness 2Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Peripheral Bus 2Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Byte and Halfword Access 2 Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 CPU Wait States 2Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Arbitration Between the CPU and the DMA Controller 2Ć22. . . . . . . . . . . . . . . . . . .

vii

Contents

3 TMS320C6202 Program and Data Memory 3Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the 6202 program memory controller.

3.1 TMS320C6202 Program Memory Controller 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Memory Mapped Operation 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Cache Operation 3Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Bootload Operation 3Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 TMS320C6202 Data Memory Controller 3Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 TMS320C6211/C671 1

Two-Level Internal Memory 4Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the program and data memory for the TMS320C6211/C6711.

4.1 Overview 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Internal Memory Control Registers 4Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 L1P Description 4Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 L1D Description 4Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 L2 Description 4Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 L2 Interfaces 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 L2 Operation 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 L2 EDMA Service 4Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.4 L2 Invalidation 4Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Direct Memory Access (DMA) Controller 5Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the direct memory access controller operation.

5.1 Overview 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 DMA Registers 5Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 DMA Channel Control Registers 5Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Memory Map 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Initiating a Block Transfer 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 DMA Autoinitialization 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Transfer Counting 5Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Synchronization: Triggering DMA Transfers 5Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 Latching of DMA Channel Event Flags 5Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.2 Automated Event Clearing 5Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.3 Synchronization Control 5Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Address Generation 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Basic Address Adjustment 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Address Adjustment With the Global Index Registers 5Ć23. . . . . . . . . . . . . . . . . . . .

5.7.3 Element Size, Alignment, and Endianness 5Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.4 Using a Frame Index to Reload Addresses 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.5 Transferring a Large Single Block 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.6 Sorting 5Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Split-Channel Operation 5Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.1 Split DMA Operation 5Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.2 Split Address Generation 5Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

Contents

5.9 Resource Arbitration and Priority Configuration 5Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.1 DMA Auxiliary Control Register and Priority Between Channels 5Ć30. . . . . . . . . . .

5.9.2 Switching Channels 5Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 DMA Channel Condition Determination 5Ć33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.1 Definition of Channel Conditions 5Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 DMA Controller Structure 5Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.1 Read and Write Buses 5Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.2 DMA FIFO 5Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.3 Internal Holding Registers 5Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.4 DMA Performance 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 DMA Action Complete Pins 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 Emulation 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 EDMA Controller 6

This chapter describes the new enhanced DMA for the TMS320C6211/6711.

6.1 Overview 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 EDMA Terminology 6Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Event Processing and EDMA Control Registers 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Event Encoder 6Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Parameter RAM (PaRAM) 6Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.1 EDMA Transfer Parameter Entry 6Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 EDMA Transfer Parameters 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.1 Options Parameter 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.2 SRC/DST Address 6Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.3 Element Count 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.4 Frame/Array Count 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.5 Element/(Frame/Array) Index 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.6 Element Count Reload 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.7 Link Address 6Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Initiating an EDMA Transfer 6Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7.1 Synchronization of EDMA Transfers 6Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Types of EDMA Transfers 6Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.1 Non-2Dimensional Transfers 6Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.2 2-Dimensional Transfers 6Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Linking EDMA Transfers 6Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Element Size and Alignment 6Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11 Element and Frame/Array Count Updates 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11.1 Element Count Reload (ECRLD) 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12 Src/Dst Address Updates 6Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13 EDMA Interrupt Generation 6Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.1 EDMA Interrupt Servicing by the CPU 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.2 Chaining EDMA Channels by an Event 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.14 Resource Arbitration and Priority Processing 6Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15 EDMA Performance 6Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

ix

Contents

6.16 Quick DMA (QDMA) 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.1 QDMA Registers 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.2 QDMA Register Access 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.3 Pseudo Mappings 6 Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.4 QDMA Performance 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.5 QDMA Stalls and Priority 6Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Host-Port Interface 7Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the host-port interface (HPI) used to access ’C6201 and ’C6701 memory-map space
by external processors.

7.1 Overview 7Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 HPI Signal Descriptions 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Data Bus: HD[15:0] 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2 Access Control Select: HCNTL[1:0] 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3 Halfword Identification Select: HHWIL 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.4 Byte Enables: HBE[1:0] 7Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.5 Read/Write Select: HR/W 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.6 Ready: HRDY

7.2.7 Strobes: HCS

, HDS1, HDS2 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.8 Address Strobe Input: HAS

7.2.9 Interrupt to Host: HINT 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.10 HPI Bus Access 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 HPI Registers 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 HPI Control Register (HPIC) 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.2 Software Handshaking Using HRDY and FETCH 7Ć17. . . . . . . . . . . . . . . . . . . . . . .

7.3.3 Host Device Using DSPINT to Interrupt the CPU 7Ć18. . . . . . . . . . . . . . . . . . . . . . .

7.3.4 CPU Using HINT to Interrupt the Host 7Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Host Access Sequences 7Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Host Initialization of HPIC and HPIA 7Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 HPID Read Access Without Autoincrement 7Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.3 HPID Read Access With Autoincrement 7Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.4 Host Data Write Access Without Autoincrement 7Ć23. . . . . . . . . . . . . . . . . . . . . . . .

7.4.5 HPID Write Access With Autoincrement 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.6 Single Halfword Cycles 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Memory Access Through the HPI During Reset 7Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Expansion Bus 8Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the expansion bus used by CPU to access off-chip peripherals, FIFOs and PCI
interface chips.

8.1 Overview 8Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Expansion Bus Signals 8Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Expansion Bus Registers 8Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.1 Expansion Bus Host Port Registers 8Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.2 Expansion Bus Global Control Register 8Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

Contents

8.3.3 XCE Space Control Registers 8Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Expansion Bus I/O Port Operation 8Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.1 Asynchronous Mode 8Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.2 Synch FIFO Modes 8Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.3 DMA Transfer Examples 8Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Expansion Bus Host Port Operation 8Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5.1 Expansion Bus Host Port Registers Description 8Ć23. . . . . . . . . . . . . . . . . . . . . . . .

8.5.2 Synchronous Host Port Mode 8Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5.3 Asynchronous Host Port Mode 8Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 Expansion Bus Arbitration 8Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6.1 Internal Bus Arbiter Enabled 8Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6.2 Internal Bus Arbiter Disabled 8Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6.3 Expansion Bus Requestor Priority 8Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7 Boot Configuration Control via Expansion Bus 8Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 External Memory Interface 9

Describes the external memory interface (EMIF) that the CPU uses to access off-chip memory .

9.1 Overview 9Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Resetting the EMIF 9Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 EMIF Registers 9Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.1 Global Control Register 9Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.2 EMIF CE Space Control Registers 9Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.3 EMIF SDRAM Control Register 9Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.4 EMIF SDRAM Timing Register 9Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.5 TMS320C6211/C6711 SDRAM Extension Register 9Ć18. . . . . . . . . . . . . . . . . . . . .

9.4 SDRAM Interface 9Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.1 SDRAM Initialization 9Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.2 Monitoring Page Boundaries 9Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.3 SDRAM Refresh 9Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.4 Mode Register Set 9Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.5 Address Shift 9Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.6 Timing Requirements 9Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.7 SDRAM Deactivation 9Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.8 SDRAM Read 9Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.9 SDRAM Write 9Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.10 TMS320C6211/C6711 Seamless Data Access 9Ć41. . . . . . . . . . . . . . . . . . . . . . . . .

9.5 SBSRAM Interface 9Ć43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5.1 SBSRAM Reads 9Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5.2 SBSRAM Writes 9 Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6 Asynchronous Interface 9Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.1 TMS320C6201/C6202/C6701 ROM Modes 9Ć52. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.2 Programmable ASRAM Parameters 9Ć53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.3 Asynchronous Reads 9Ć54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.4 Asynchronous Writes 9Ć56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xi

Contents

9.6.5 Ready Input 9Ć57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.7 Hold Interface 9 Ć60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.8 Memory Request Priority 9Ć61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.8.1 TMS320C6201/C6202/C6701 Memory Request Priority 9Ć61. . . . . . . . . . . . . . . . .

9.8.2 TMS320C6211/C6711 Memory Request Priority 9Ć62. . . . . . . . . . . . . . . . . . . . . . . .

9.9 Boundary Conditions When Writing to EMIF Registers 9Ć63. . . . . . . . . . . . . . . . . . . . . . . . . .

9.10 Clock Output Enabling 9Ć64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.11 Emulation Halt Operation 9Ć64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.12 Power Down 9Ć64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Boot Modes and Configuration 10

Describes the boot modes and associated memory maps.

10.1 Overview 10Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Device Reset 10Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Boot Configuration 10Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1 Memory Map 10Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.2 Memory at Reset Address 10Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.3 Boot Processes 10Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Device Configuration 10Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.1 Input Clock Mode 10Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.2 Endian Mode 10Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.3 TMS320C6202 Expansion Bus 10Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Multichannel Buffered Serial Ports 11

Describes the features and operation of the two multichannel buffered serial ports.

11.1 Features 11Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 McBSP Interface Signals and Registers 1 1 Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1 Serial Port Configuration 11Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.2 Receive and Transmit Control Registers: RCR and XCR 11Ć14. . . . . . . . . . . . . . . .

11.3 Data Transmission and Reception 11Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.1 Resetting the Serial Port: (R/X

11.3.2 Determining Ready Status 11Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.3 CPU Interrupts: (R/X)INT 11Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.4 Frame and Clock Configuration 11Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.5 McBSP Standard Operation 11Ć33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.6 Frame Synchronization Ignore 11Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.7 Serial Port Exception Conditions 11Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.8 Receive Data Justification and Sign Extension: RJUST 11Ć49. . . . . . . . . . . . . . . . .

1 1.3.9 32-Bit Bit Reversal: (R/X)WDREVRS 11Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1.4 µ-LAW/A-LAW Companding Hardware Operation 11Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4.1 Companding Internal Data 11Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5 Programmable Clock and Framing 11Ć53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5.1 Sample Rate Generator Clocking and Framing 11Ć54. . . . . . . . . . . . . . . . . . . . . . . .

11.5.2 Data Clock Generation 11Ć57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

)RST, GRST , and RESET 11Ć18. . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

Contents

11.5.3 Frame Sync Signal Generation 11Ć61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1.5.4 Clocking Examples 11Ć65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6 Multichannel Selection Operation 11Ć68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.1 Multichannel Operation Control Registers 11Ć68. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.2 Enabling Multichannel Selection 1 1Ć71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.3 Enabling and Masking of Channels 1 1 Ć71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1.6.4 DX Enabler: DXENA 1 1Ć78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1.7 SPI Protocol: CLKSTP 11Ć80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7.1 McBSP Operation as the SPI Master 11Ć84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7.2 McBSP Operation as the SPI Slave 11Ć85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7.3 McBSP Initialization for SPI Mode 11Ć86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8 McBSP Pins as General-Purpose I/O 11Ć87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Timers 12

Describes the 32-bit timers.

12.1 Overview 12Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Timer Registers 12Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 T imer Control Register 12Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.2 T imer Period Register 12Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.3 T imer Counter Register 12Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Resetting the T imers and Enabling Counting: GO and HLD

12.4 Timer Counting 12Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5 Timer Clock Source Selection: CLKSRC 12Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6 Timer Pulse Generation 12Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7 Boundary Conditions in the Control Registers 12Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.8 Timer Interrupts 12Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.9 Emulation Operation 12Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Interrupt Selector and External Interrupts 13

12Ć7. . . . . . . . . . . . . . . . . . . . .

Describes the interrupt selector external interrupt operation.

13.1 Available Interrupt Sources 13Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 External Interrupt Signal Timing 13Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 Interrupt Selector Registers 13Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.1 External Interrupt Polarity Register 13Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.2 Interrupt Multiplexer Register 13Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 Configuring the Interrupt Selector 13Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Power-Down Logic 14

Describes the power-down modes.

14.1 Overview 14Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.2 Triggering, Wake-Up, and Effects 14Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3 Additional Power-Saving Modes for the TMS320C6202 14Ć6. . . . . . . . . . . . . . . . . . . . . . . . .

Contents

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

Contents

15 Designing for JTAG Emulation 15Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the JTAG emulator cable. Tells you how to construct a 14-pin connector on your
target system and how to connect the target sysem to the emulator.

15.1 Designing Your Target System’s Emulator Connector (14-Pin Header) 15Ć2. . . . . . . . . . . .

15.2 Bus Protocol 15Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.3 IEEE 1149.1 Standard 15Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.4 JTAG Emulator Cable Pod Logic 15Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.5 JTAG Emulator Cable Pod Signal Timing 15Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.6 Emulation Timing Calculations 15Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.7 Connections Between the Emulator and the Target System 15Ć8. . . . . . . . . . . . . . . . . . . . .

15.7.1 Buffering Signals 15Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.7.2 Using a Target-System Clock 15Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.7.3 Configuring Multiple Processors 15Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.8 Mechanical Dimensions for the 14-Pin Emulator Connector 15Ć12. . . . . . . . . . . . . . . . . . . .

15.9 Emulation Design Considerations 15Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.9.1 Using Scan Path Linkers 15Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.9.2 Emulation T iming Calculations for SPL 15Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.9.3 Using Emulation Pins 15Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.9.4 Performing Diagnostic Applications 15Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

Figures

Figures

1–1 TMS320C6201/C6202/C6701 Block Diagram 1Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 TMS320C6211/C6711 Block Diagram 1

2–1 TMS320C6201/C6701 Program Memory Controller in the Block Diagram 2Ć2. . . . . . . . . . . . .

2–2 Logical Mapping of Cache Address 2Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 TMS320C6x Block Diagram 2
2–4 Data Memory Controller Interconnect to Other Banks

(TMS320C6201 Revision 2) 2Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Data Memory Controller Interconnect to Other Banks

(TMS320C6201 Revision 3) 2Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Data Memory Controller Interconnect to Other Blocks (TMS320C6701) 2
2–7 Conflicting Internal Memory Accesses to the Same Block

(TMS320C6201 Revisions 2 and 3) 2Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Conflicting Internal Memory Accesses to the Same Block (TMS320C6701) 2Ć17. . . . . . . . . .

3–1 TMS320C6202 Program Memory Controller Block Diagram 3

3–2 TMS320C6202 Data Memory Controller Block Diagram 3Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 TMS320C6211/C6711 Block Diagram 4

4–2 TMS320C6211 Internal Memory Block Diagram 4Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 TMS320C6711 Internal Memory Block Diagram 4Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 L1P Address Allocation 4

4–5 L1P Direct Mapped Cache Diagram 4Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 L1P Flush Base Address Register Fields (L1PFBAR) 4Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 L1P Flush Word Count Register Fields (L1PFWC) 4

4–8 L1D Address Allocation 4Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 L1D 2–Way Set Associative Cache Diagram 4

4–10 L1D Flush Base Address Register Fields (L1DFBAR) 4Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 L1D Flush Word Count Register Fields (L1DFWC) 4Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Cache Configuration Register Fields (CCFG) 4

4–13 L2 Memory Configuration 4Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–14 L2 Cache Data Request Flow Chart 4Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 L2 CE Space Allocation Register Fields 4

4–16 L2 Flush Register Fields (L2FLUSH) 4Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–17 L2 Clean Register Fields (L2CLEAN) 4Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 L2 Flush Base Address Register Fields (L2FBAR) 4

4–19 L2 Flush Word Count Register Fields (L2FWC) 4Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 L2 Clean Base Address Register Fields (L2CBAR) 4

4–21 L2 Clean Word Count Register Fields (L2CWC) 4Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć14. . . . . . . . . . . . .

Ć3. . . . . . . . . . . . . . . . . . . . . . . .

Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xv

Figures

5–1 DMA Controller Interconnect to TMS320C6201/C6202/C6701

Memory-Mapped Modules 5Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 DMA Channel Primary Control Register 5Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 DMA Channel Secondary Control Register 5Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 TMS320C6202 Secondary Control Register 5Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 DMA Channel Transfer Counter Register 5Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 DMA Global Count Reload Register Used As Transfer Counter Reload 5Ć16. . . . . . . . . . . . . .

5–7 Synchronization Flags 5Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 DMA Channel Source Address Register 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 DMA Channel Destination Address Register 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 DMA Global Index Register 5Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 DMA Global Address Register Used for Split Address 5Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 DMA Auxiliary Control Register 5Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Generation of DMA Interrupt for Channel x From Conditions 5Ć33. . . . . . . . . . . . . . . . . . . . . . .

5–14 DMA Controller Data Bus Block Diagram 5 Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 TMS320C6211/C6711 Block Diagram 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 EDMA Controller 6Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Event Register (ER) 6 Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Event Enable Register (EER) 6Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Event Clear Register (ECR) 6Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 Event Set Register (ESR) 6Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 Parameter Storage for an EDMA Event 6Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–8 Options Bit-Fields 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 Non-2D R/W Sync EDMA Transfer Without Frame Sync 6Ć21. . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 Non-2D EDMA Transfer With Frame Sync 6 Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–11 Read/Write Synchronized 2-D Transfer (No Frame Sync) 6Ć23. . . . . . . . . . . . . . . . . . . . . . . . . .

6–12 Frame Synchronized 2-D Transfer 6Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–13 Linked EDMA Transfer 6Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–14 Channel Interrupt Pending Register (CIPR) 6Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–15 Channel Interrupt Enable Register (CIER) 6Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–16 Channel Chain Enable Register (CCER) 6Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–17 Priority Queue Status Register(PQSR) 6Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–18 QDMA Memory-Mapped Registers 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–19 QDMA Pseudo Registers 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–20 QDMA Options Register (QDMA_OPT, QDMA_S_OPT) 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 TMS320C6201/C6701 Block Diagram 7Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 TMS320C6211/C6711 Block Diagram 7Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 HPI Block Diagram 7Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 HPI Block Diagram of TMS320C6211/C6711 7Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Select Input Logic 7Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 HPI Read Timing (HAS Not Used, Tied High) 7Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 HPI Read Timing (HAS Used) 7Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 HPI Write Timing (HAS Not Used, Tied High) 7Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 HPI Write Timing (HAS Used) 7Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

Figures

7–10 HPIC Register 7Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 Expansion Bus Block Diagram 8Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 The Expansion Bus Interface in the TMS320C6202 Block Diagram 8

8–3 Expansion Bus Global Control Register 8Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Expansion Bus XCE(0/1/2/3) Space Control Register Diagram 8Ć9. . . . . . . . . . . . . . . . . . . . . .

8–5 Example of the Expansion Bus Interface to Four 8-Bit FIFOs 8Ć11. . . . . . . . . . . . . . . . . . . . . .

8–6 Example of the Expansion Bus Interface to Two 16-Bit FIFOs 8

8–7 Glueless Write FIFO Interface 8Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–8 Read and Write FIFO Interface With Glue 8Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–9 FIFO Write Cycles 8Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–10 Glueless Read FIFO Interface 8Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–11 FIFO Read Mode – Read Timing (glueless case) 8

8–12 FIFO Read Mode – With Glue 8Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–13 Expansion Bus Host Port Interface Block Diagram 8Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–14 Expansion Bus Data Register 8Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–15 Expansion Bus Internal Slave Address Register (XBISA) 8Ć23. . . . . . . . . . . . . . . . . . . . . . . . . .

8–16 Expansion Bus Internal Master Address Register 8

8–17 Expansion Bus External Address Register 8 Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–18 Expansion Bus Host Port Interface Control (XBHC) Register 8
8–19 Read Transfer Initiated by the TMS320C6202 and Throttled by

8–20 Write Transfer Initiated by the TMS320C6202 and Throttled by

8–21 External Device Requests the Bus From the TMS320C6202 Using XBOFF 8Ć33. . . . . . . . . .

8–22 The Expansion Bus Master Writes a Burst of Data to the TMS320C6202 8Ć37. . . . . . . . . . . .

8–23 The Bus Master Reads a Burst of Data From the TMS320C6202 8Ć39. . . . . . . . . . . . . . . . . . .

8–24 Timing Diagrams for Asynchronous Host Port Mode of the Expansion Bus 8
8–25 Timing Diagrams for Bus Arbitration–XHOLD/XHOLDA

8–26 Timing Diagrams for Bus Arbitration XHOLD/XHOLDA
8–27 XHOLD Timing When the External Host Starts a Transfer to DSP Instead of
8–28 Expansion Bus Boot Configuration via Pull Up/Pull Down Resistors on XD[31:0] 8

9–1 External Memory Interface in the TMS320C6201/C6202/C6701BlockDiagram 9Ć3. . . . . . . .

9–2 External Memory Interface in the TMS320C6211/C6711BlockDiagram 9Ć3. . . . . . . . . . . . . . .

9–3 TMS320C6201/C6701 External Memory Interface 9Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–4 TMS320C6202 External Memory Interface 9Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–5 TMS320C6211/C6711 External Memory Interface 9

9–6 EMIF Global Control Register Diagram 9Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–7 TMS320C6201/C6202/C6701 EMIF CE Space Control Register Diagram 9Ć12. . . . . . . . . . .

9–8 TMS320C6211/C6711 EMIF CE Space Control Register 9Ć12. . . . . . . . . . . . . . . . . . . . . . . . . .

9–9 TMS320C6211/C6711 Byte Alignment by Endianness 9Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–10 TMS320C6201/C6202/C6701 EMIF SDRAM Control Register 9

9–11 TMS320C6211/C6711 EMIF SDRAM Control Register 9Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

XWAIT

XWAIT and XRDY (Internal Bus Arbiter Disabled) 8Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Internal Bus Arbiter Enabled) 8Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Internal Bus Arbiter Disabled) 8Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Granting the DSP Access to the Expansion Bus(Internal Bus Arbiter Disabled) 8Ć46. . . . . . .

and XRDY (Internal Bus Arbiter Disabled) 8Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć4. . . . . . . . . . . . . . . . . .

Ć12. . . . . . . . . . . . . . . . . . . . . .

Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć25. . . . . . . . . . . . . . . . . . . . . . .

Ć43. . . . . . . . . . .

Ć49. . . . . .

Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć15. . . . . . . . . . . . . . . . . . . . .

Contents

xvii

Figures

9–12 EMIF SDRAM Timing Register 9Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–13 TMS320C6211/C6711 SDRAM Extension Register 9Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–14 TMS320C6201/C6202/C6701 EMIF to 16M-Bit SDRAM Interface 9Ć21. . . . . . . . . . . . . . . . . .

9–15 TMS320C6211/C6711 EMIF to 16M-Bit SDRAM Interface 9Ć21. . . . . . . . . . . . . . . . . . . . . . . . .

9–16 TMS320C6201/C6202/C6701 EMIF to 64M-Bit SDRAM Interface 9

9–17 SDRAM Refresh 9Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–18 TMS320C6201/C6202/C6701 Mode Register Value 9
9–19 TMS320C6211/C6711 Mode Register Value (0032h) 9

9–20 TMS320C6211/C6711 Mode Register Value (0022h) 9Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–21 SDRAM Mode Register Set: MRS Command 9
9–22 SDRAM DCAB — Deactivate all Banks 9
9–23 TMS320C6211/C6711 SDRAM DEAC — Deactivate Single Bank 9

9–24 TMS3206201/C6202/C6701 SDRAM Read 9Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–25 TMS320C6211 SDRAM Read 9
9–26 TMS320C6201/C6202/C6701 SDRAM Three Word Write 9

9–27 TMS320C6211/C6711 SDRAM Three Word Write 9Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–28 Burst Reads to 2 Pages of SDRAM 9Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–29 Seamless SDRAM Write 9Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–30 TMS320C6201/C6202/C6701 SBSRAM Interface 9Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–31 TMS320C6211/C6711 SBSRAM interface 9Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–32 SBSRAM Four-Word Read 9Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–33 TMS320C6211/C6711 SBSRAM Six-Word Read 9
9–34 TMS320C6201/C6202/C6701 SBSRAM Four Word Write 9
9–35 TMS320C6211/C6711 SBSRAM Write 9

9–36 TMS6201/C6202/C6701 EMIF to 32-bit SRAM Interface 9Ć50. . . . . . . . . . . . . . . . . . . . . . . . . .

9–37 TMS320C6211/C6711 EMIF to 16-bit SRAM (Big Endian) 9

9–38 EMIF to 8-Bit ROM Interface 9Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–39 EMIF to 16-Bit ROM Interface 9Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–40 EMIF to 32-Bit ROM Interface 9

9–41 Asynchronous Read Timing Example 9Ć55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–42 Asynchronous Write Timing Example 9Ć57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–43 TMS320C6201/C6202/C6701 Ready Operation 9Ć58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–44 TMS320C6211/C6711 Ready Operation 9Ć59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–1 McBSP Block Diagram 11

11–2 Serial Port Control Register (SPCR) 11 Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–3 Pin Control Register (PCR) 11Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–4 Receive Control Register (RCR) 11

11–5 Transmit Control Register (XCR) 11Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–6 Frame and Clock Operation 11Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–7 Receive Data Clocking 11Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–8 Dual-Phase Frame Example 11

11–9 Inter-IC Sound (IIS) Timing 11Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–10 Single-Phase Frame of Four 8-Bit Elements 11Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–11 Single-Phase Frame of One 32-Bit Element 11

Ć22. . . . . . . . . . . . . . . . . .

Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć36. . . . . . . . . . . . . . . . . .

Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć39. . . . . . . . . . . . . . . . . . . . . . . . .

Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć48. . . . . . . . . . . . . . . . . . . . . . . . .

Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć50. . . . . . . . . . . . . . . . . . . . . . . . .

Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xviii

Figures

11–12 Data Delay 11Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–13 2-Bit Data Delay Used to Discard Framing Bit 11Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–14 AC97 Dual-Phase Frame Format 11

11–15 AC97 Bit Timing Near Frame Synchronization 11Ć33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–16 McBSP Standard Operation 11Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–17 Receive Operation 11Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–18 Transmit Operation 11

11–19 Maximum Frame Frequency Transmit and Receive 11Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–20 Unexpected Frame Synchronization With (R/X)FIG = 0 11

11–21 Unexpected Frame Synchronization With (R/X)FIG = 1 11Ć38. . . . . . . . . . . . . . . . . . . . . . . . . .

11–22 Maximum Frame Frequency Operation With 8-Bit Data 11Ć39. . . . . . . . . . . . . . . . . . . . . . . . . .

11–23 Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 11

11–24 Serial Port Receive Overrun 11Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–25 Serial Port Receive Overrun Avoided 11

11–26 Decision Tree Response to Receive Frame Synchronization Pulse 11Ć44. . . . . . . . . . . . . . . .

1 1–27 Unexpected Receive Synchronization Pulse 11Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–28 Transmit With Data Overwrite 11

11–29 Transmit Empty 11Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–30 Transmit Empty Avoided 11Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–31 Response to Transmit Frame Synchronization 11

11–32 Unexpected Transmit Frame Synchronization Pulse 11Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–33 Companding Flow 11

11–34 Companding Data Formats 11Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–35 Transmit Data Companding Format in DXR 11Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–36 Companding of Internal Data 11

11–37 Clock and Frame Generation 11Ć53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–38 Sample Rate Generator 11

11–39 Sample Rate Generator Register (SRGR) 11Ć55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–40 CLKG Synchronization and FSG Generation When GSYNC = 1

and CLKGDV = 1 11Ć59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–41 CLKG Synchronization and FSG Generation When GSYNC = 1

and CLKGDV = 3 11

11–42 Programmable Frame Period and Width 11Ć62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–43 ST-BUS and MVIP Example 11Ć65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–44 Single-Rate Clock Example 11

11–45 Double-Rate Clock Example 1 1Ć67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–46 Multichannel Control Register 11

11–47 Element Enabling by Subframes in Partitions A and B 11Ć72. . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–48 XMCM Operation 11Ć74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–49 Receive Channel Enable Register (RCER) 11

11–50 Transmit Channel Enable Register (XCER) 11Ć76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–51 DX Timing for Multichannel Operation 11Ć78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–52 SPI Configuration: McBSP as the Master 11

11–53 SPI Configuration: McBSP as the Slave 11Ć81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć37. . . . . . . . . . . . . . . . . . . . . . . . . .

Ć40. . . . . . . . . . . . . . . . . . .

Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xix

Figures

11–54 SPI Transfer with CLKSTP = 10b 11Ć82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–55 SPI Transfer with CLKSTP = 11b 1 1Ć82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–1 Timer Block Diagram 12Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–2 Timer Control Register 12Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–3 Timer Period Register 12Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–4 Timer Counter Register 12Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–5 Timer Operation in Pulse Mode (C/P = 0) 12Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–6 Timer Operation in Clock Mode (C/P = 1) 12Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1 Timing of External Interrupt Related Signals 13Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–2 External Interrupt Polarity Register 13Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–3 Interrupt Multiplexer Low Register Diagram 13Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–4 Interrupt Multiplexer High Register Diagram 13Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–1 Power-Down Mode Logic 14Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–2 PWRD Field of the CSR Register 14Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–3 Peripheral Power-Down Control Fields for the TMS320C6202 14Ć6. . . . . . . . . . . . . . . . . . . . .

15–1 14-Pin Header Signals and Header Dimensions 15Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–2 JTAG Emulator Cable Pod Interface 15Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–3 JTAG Emulator Cable Pod Timings 15Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–4 Target-System-Generated Test Clock 15Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–5 Multiprocessor Connections 15Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–6 Pod/Connector Dimensions 15Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–7 14-Pin Connector Dimensions 15Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–8 Connecting a Secondary JTAG Scan Path to an SPL 15Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–9 EMU0/1 Configuration 15

15–10 EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements 15Ć21. . . . .

15–11 Suggested Timings for the EMU0 and EMU1 Signals 15Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–12 EMU0/1 Configuration Without Global Stop 15Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–13 TBC Emulation Connections for n JTAG Scan Paths 15Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xx

Tables

Tables

1–1 Typical Applications for the TMS320 DSPs 1Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 TMS320C6000 Peripherals 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Internal Program Memory Mode Summary 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Data Memory Organization (TMS320C6201 Revision 2) 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Data Memory Organization (TMS320C6201 Revision 3) 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Data Memory Organization 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Register Contents After Little-Endian or Big-Endian Data Loads
2–6 Register Contents After Little-Endian or Big-Endian Data Loads
2–7 Memory Contents After Little-Endian or Big-Endian Data Stores

2–8 Memory Contents After Little-Endian or Big-Endian Data Stores 2Ć21. . . . . . . . . . . . . . . . . . . .

3–1 TMS320C6201/C6701/C6202 Internal Memory Configurations 3Ć2. . . . . . . . . . . . . . . . . . . . . .

3–2 TMS320C6201/C6701/C6202 Cache Architectures 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Internal Program RAM Address Mapping in Memory Mapped Mode 3Ć4. . . . . . . . . . . . . . . . .

3–4 Internal Program RAM Address Mapping in Cache Mode 3Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Internal Data RAM Address Mapping 3Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 TMS320C6211/C6711 Internal Memory Configurations 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 TMS320C6211/C6711 Cache Architectures 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Internal Memory Control Register Addresses 4Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Level 1 Program Cache Mode Settings 4Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Level 1 Data Cache Mode Settings 4Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Cache Configuration Register Field Description 4Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Memory Attribute Register Functions 4Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 L2 Flush Register Fields Description 4Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 L2 Clean Register Fields Description 4Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 DMA Control Registers by Address 5Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 DMA Control Registers by Register Name 5Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 DMA Channel Primary Control Register Field Descriptions 5Ć8. . . . . . . . . . . . . . . . . . . . . . . . .

5–4 DMA Channel Secondary Control Register Field Descriptions 5Ć10. . . . . . . . . . . . . . . . . . . . .

5–5 Synchronization Configuration Options 5Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Synchronization Events 5Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Sorting Example in Order of DMA Transfers 5Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Sorting in Order of First by Address 5Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 DMA Auxiliary Control Register Field Descriptions 5Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 DMA Channel Condition Descriptions 5Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(TMS320C6201 and TMS320C6701) 2Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(TMS320C6701 only) 2Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(TMS320C6201/C6701) 2Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxi

Tables

6–1 EDMA Control Registers 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 EDMA Parameter RAM Contents 6Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 EDMA Channel Options Field Description 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 EDMA Channel Association with Sync Events 6Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Link Conditions 6Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 EDMA Element and Frame/Array Count Updates 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 EDMA SRC Address Parameter Updates 6Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–8 EDMA DST Address Parameter Updates 6Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 Transfer Complete Code (TCC) to DMA Interrupt Mapping 6Ć33. . . . . . . . . . . . . . . . . . . . . . . .

6–10 Programmable Priority Levels for Data Requests 6Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 HPI External Interface Signals 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 HPI Input Control Signals Function Selection Descriptions 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 HPI Data Write Access 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Byte Enables for HPI Data Write Access 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 HPI Registers 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 HPI Control Register (HPIC) Bit Descriptions 7Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Initialization of HWOB = 1 and HPIA 7Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Initialization of HWOB = 0 and HPIA 7Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Data Read Access to HPI Without Autoincrement: HWOB = 1 7Ć21. . . . . . . . . . . . . . . . . . . . . .

7–10 Data Read Access to HPI Without Autoincrement: HWOB = 0 7Ć21. . . . . . . . . . . . . . . . . . . . . .

7–11 Read Access to HPI With Autoincrement: HWOB = 1 7Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–12 Read Access to HPI With Autoincrement: HWOB = 0 7Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–13 Data Write Access to HPI Without Autoincrement: HWOB = 1 7Ć24. . . . . . . . . . . . . . . . . . . . . .

7–14 Data Write Access to HPI Without Autoincrement: HWOB = 0 7Ć24. . . . . . . . . . . . . . . . . . . . . .

7–15 Write Access to HPI With Autoincrement: HWOB = 1 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–16 Write Access to HPI With Autoincrement: HWOB = 0 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 Expansion Bus Signals 8Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 Expansion Bus Memory Mapped Registers 8Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 Expansion Bus Host Port Registers 8Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Expansion Bus Global Control Register Field Description 8Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Expansion Bus XCE(0/1/2/3) Space Control Register Field Description 8Ć9. . . . . . . . . . . . . . .

8–6 Addressing Scheme – Case When Expansion Bus is Interfaced to Four

8-Bit FIFOs 8Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 Addressing Scheme – Case When the Expansion Bus is Interfaced to Two

16-Bit FIFOs 8Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–8 Synch FIFO Pin Description 8Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–9 Content of Relevant Registers (single frame transfer) 8 Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–10 Content of DMA Channel Primary Control Register Fields 8Ć20. . . . . . . . . . . . . . . . . . . . . . . . .

8–11 Content of Relevant Registers (multiple frame transfer) 8Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–12 Content of TMS320C6202 DMA Primary Control Register 8Ć21. . . . . . . . . . . . . . . . . . . . . . . . .

8–13 Content of TMS320C6202 DMA Secondary Control Register 8Ć21. . . . . . . . . . . . . . . . . . . . . .

8–14 XBISA Register Description 8Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–15 XBHC Register Description 8Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–16 Expansion Bus Pin Description (Synchronous Host Port Mode) 8Ć26. . . . . . . . . . . . . . . . . . . .

xxii

Tables

8–17 Expansion Bus Pin Description (Asynchronous Host Port Mode) 8Ć41. . . . . . . . . . . . . . . . . . .

8–18 XARB Bit Value and XHOLD/XHOLDA Signal Functionality 8Ć44. . . . . . . . . . . . . . . . . . . . . . . .

8–19 Possible Expansion Bus Arbitration Scenarios (Internal Bus Arbiter Disabled) 8Ć46. . . . . . . .

8–20 Description of Expansion Bus Boot Configuration via Pull Up/Pull Down

Resistors on XD[31:0] 8Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–1 EMIF Signal Descriptions 9Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–2 EMIF Memory-Mapped Registers 9Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–3 EMIF Global Control Register Field Descriptions 9Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–4 EMIF CE Space Control Registers Field Descriptions 9Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–5 EMIFtoSDRAMControlRegisterFieldDescription 9Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–6 EMIFSDRAM Timing Register Field Descriptions 9Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–7 TMS320C6211/C6711 SDRAM Extension Register Field Descriptions 9Ć19. . . . . . . . . . . . . . .

9–8 TMS320C6201/C6202/C6701 EMIF SDRAM Commands 9Ć20. . . . . . . . . . . . . . . . . . . . . . . . . .

9–9 TMS320C6201/C6202/C6701 SDRAM Memory Population 9Ć22. . . . . . . . . . . . . . . . . . . . . . . .

9–10 SDRAM Control Pins 9Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–11 TMS320C6201/C6202/C6701 Implied SDRAM Configuration by MRS Value 9Ć29. . . . . . . . .

9–12 TMS320C6211/C6711 Implied SDRAM Configuration by MRS 9Ć30. . . . . . . . . . . . . . . . . . . . .

9–13 TMS320C6201/C6202/C6701 Byte Address to EA Mapping for

SDRAM RAS

and CAS 9Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–14 TMS320C6211/C6711 Byte Address to EA Mapping for 32-bit Interface 9Ć33. . . . . . . . . . . . .

9–15 TMS320C6201/C6202/C6701 SDRAM Timing Parameters 9Ć34. . . . . . . . . . . . . . . . . . . . . . . .

9–16 SBSRAM in Linear Burst Mode 9Ć43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–17 EMIF SBSRAM Pins 9Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–18 EMIF Asynchronous Interface Pins 9Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–19 Byte Address to EA Mapping for Asynchronous Memory Widths 9Ć52. . . . . . . . . . . . . . . . . . . .

9–20 TMS320C6201/C6202/C6701 EMIF Prioritization of Requests 9Ć61. . . . . . . . . . . . . . . . . . . . .

9–21 TMS320C6211/C6711 EMIF Prioritization of Requests 9Ć62. . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–1 Boot Configuration Summary 10Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–2 TMS320C6211/C6711 Boot Configuration Summary 10Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–3 TMS320C6201/C6701 Memory Map Summary 10Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–4 TMS320C6202 Memory Map Summary 10Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–5 TMS320C6211/C6711 Memory Map Summary 10Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–6 DLL Multiplier Select 10Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–1 McBSP Interface Signals 11Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–2 McBSP Registers 11Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–3 TMS320C6211/C6711 Data Receive and Transmit Registers (DRR/DXR) Mapping 11Ć6. . .

11–4 McBSP CPU Interrupts and DMA Synchronization Events 11Ć7. . . . . . . . . . . . . . . . . . . . . . . . .

11–5 Serial Port Control Register (SPCR) Field Descriptions 11Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . .

11–6 Pin Control Register (PCR) Field Descriptions 11Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–7 Receive/Transmit Control Register (RCR/XCR) Field Descriptions 11Ć15. . . . . . . . . . . . . . . .

11–8 Reset State of McBSP Pins 11Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–9 RCR/XCR Fields Controlling Elements per Frame and Bits per Element 11Ć26. . . . . . . . . . . .

11–10 McBSP Receive/Transmit Frame Length 1/2 Configuration 11Ć27. . . . . . . . . . . . . . . . . . . . . . .

11–11 McBSP Receive/Transmit Element Length Configuration 1 1Ć28. . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxiii

Tables

11–12 Effect of RJUST Values With 12-Bit Example Data ABCh 11Ć49. . . . . . . . . . . . . . . . . . . . . . . . .

11–13 Justification of Expanded Data in DRR 11Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–14 Sample Rate Generator Register (SRGR) Field Summary 11Ć55. . . . . . . . . . . . . . . . . . . . . . .

11–15 Receive Clock Selection 11Ć60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–16 Transmit Clock Selection 11Ć61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–17 Receive Frame Synchronization Selection 11Ć63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–18 Transmit Frame Synchronization Selection 11 Ć64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–19 Multichannel Control Register Field Descriptions 11Ć69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–20 Receive/Transmit Channel Enable Register Field Description 11Ć77. . . . . . . . . . . . . . . . . . . . .

11–21 SPI-Mode Clock Stop Scheme 11Ć81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–22 Configuration of Pins as General Purpose I/O 11Ć87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–1 Timer Registers 12Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–2 Timer Control Register Field Descriptions 12Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–3 Timer GO and HLD Field Operation 12Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–4 TSTAT Parameters in Pulse and Clock Modes 12Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1 TMS320C6201/C6202/C6701 Available Interrupts 13Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–2 TMS320C6211/C6711 Available Interrupts 13Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–3 Interrupt Selector Registers 13Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–4 Default Interrupt Mapping 13Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–1 Power-Down Mode and Wake-Up Selection 14Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–2 Characteristics of the Power-Down Modes 14Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–3 TMS320C6202 Peripheral Power-Down Memory-Mapped Register 14Ć6. . . . . . . . . . . . . . . . .

14–4 Description of TMS320C6202 Power-Down Control Fields 14Ć7. . . . . . . . . . . . . . . . . . . . . . . . .

15–1 14-Pin Header Signal Descriptions 15Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–2 Emulator Cable Pod Timing Parameters 15Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxiv

Chapter 1

Introduction

The TMS320C6000 (‘C6000) platform of devices consists of the first off-the­shelf digital signal processors (DSPs) to use advanced very long instruction
word (VLIW) to achieve high performance through increased instruction-level
parallelism. The VelociTI advanced very long instruction word (VLIW) archi-
tecture uses multiple execution units operating in parallel to execute multiple
instructions during a single clock cycle. Parallelism is the key to extremely high
performance, taking these DSPs well beyond the performance capabilities of
traditional designs.

This chapter introduces the TMS320 family of DSPs and the ’C6000 platform
of this family, and it describes the features, memory, and peripherals of the
’C6000 devices.

Topic Page

1.1 The TMS320 Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Overview of the TMS320C6000 Platform of DSPs 1-4. . . . . . . . . . . . . . . .

1.3 Features and Options of the TMS320C6000 Devices 1-5. . . . . . . . . . . . .

1.4 Overview of TMS320C6000 Memory 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Overview of TMS320C6000 Peripherals 1-8. . . . . . . . . . . . . . . . . . . . . . . . .

1-1

TMS320 Family Overview

1.1 TMS320 Family Overview

The TMS320 family consists of fixed-point, floating-point, and multiprocessor
digital signal processors (DSPs). TMS320 DSPs are specifically designed for
real-time signal processing.

1.1.1 History of TMS320 DSPs

In 1982, Texas Instruments introduced the TMS32010—the first fixed-point
DSP in the TMS320 family. Before the end of the year,
magazine awarded the TMS32010 the title “Product of the Year”. Today, the
TMS320 family consists of these generations: ’C1x, ’C2x, ’C27x, ’C5x, and
’C54x, ’C55x fixed-point DSPs; ’C3x and ’C4x floating-point DSPs; and ’C8x
multiprocessor DSPs. Now there is a new generation of DSPs, the
TMS320C6000 platform, with performance and features that are reflective of
Texas Instruments’ commitment to lead the world in DSP solutions.

1.1.2 Typical Applications for the TMS320 Family

Table 1-1 lists some typical applications for the TMS320 family of DSPs. The
TMS320 DSPs offer adaptable approaches to traditional signal-processing
problems. They also support complex applications that often require multiple
operations to be performed simultaneously.

Electronic Products

1-2

TMS320 Family Overview

Table 1–1. Typical Applications for the TMS320 DSPs

Automotive Consumer Control

Adaptive ride control
Antiskid brakes
Cellular telephones
Digital radios
Engine control
Global positioning
Navigation
Vibration analysis
Voice commands

General Purpose Graphics/Imaging Industrial

Adaptive filtering
Convolution
Correlation
Digital filtering
Fast Fourier transforms
Hilbert transforms
Waveform generation
Windowing

Instrumentation Medical Military

Digital filtering
Function generation
Pattern matching
Phase-locked loops
Seismic processing
Spectrum analysis
Transient analysis

Telecommunications Voice/Speech

Digital radios/TVs
Educational toys
Music synthesizers
Pagers
Power tools
Radar detectors
Solid-state answering machines

3-D computing
Animation/digital maps
Homomorphic processing
Image compression/transmission
Image enhancement
Pattern recognition
Robot vision
Workstations

Diagnostic equipment
Fetal monitoring
Hearing aids
Patient monitoring
Prosthetics
Ultrasound equipment

Disk drive control
Engine control
Laser printer control
Motor control
Robotics control
Servo control

Numeric control
Power-line monitoring
Robotics
Security access

Image processing
Missile guidance
Navigation
Radar processing
Radio frequency modems
Secure communications
Sonar processing

1200- to 56 600-bps modems
Adaptive equalizers
ADPCM transcoders
Base stations
Cellular telephones
Channel multiplexing
Data encryption
Digital PBXs
Digital speech interpolation (DSI)
DTMF encoding/decoding
Echo cancellation

Faxing
Future terminals
Line repeaters
Personal communications

systems (PCS)
Personal digital assistants (PDA)
Speaker phones
Spread spectrum communications
Digital subscriber loop (xDSL)
Video conferencing
X.25 packet switching

Speaker verification
Speech enhancement
Speech recognition
Speech synthesis
Speech vocoding
Text-to-speech
Voice mail

Introduction

1-3

Overview of the TMS320C6000 Platform of DSPs

1.2 Overview of the TMS320C6000 Platform of DSPs

With a performance of up to 2000 million instructions per second (MIPS) and
an efficient C compiler , the TMS320C6000 DSPs give system architects unlim­ited possibilities to differentiate their products from others. High performance,
ease of use, and affordable pricing make the TMS320C6000 platform the ideal
solution for multichannel, multifunction applications, such as:

- Pooled modems

- Wireless local loop base stations

- Remote access servers (RAS)

- Digital subscriber loop (DSL) systems

- Cable modems

- Multichannel telephony systems

The TMS320C6000 platform is also an ideal solution for exciting new applica­tions, for example:

- Personalized home security with face and hand/fingerprint recognition

- Advanced cruise control with GPS navigation and accident avoidance

- Remote medical diagnostics

- Beam-forming base stations

- Virtual reality 3-D graphics

- Speech recognition

- Audio

- Radar

- Atmospheric modeling

- Finite element analysis

- Imaging (for example, fingerprint recognition, ultrasound, and MRI)

1-4

Features and Options of the TMS320C6000 Devices

1.3 Features and Options of the TMS320C6000 Devices

The ’C6000 devices execute up to eight 32-bit instructions per cycle. The de­vice’s core CPU consists of 32 general-purpose registers of 32-bit-word length
and eight functional units:

- Two multipliers

- Six arithmetic logic units ( ALUs)

The ’C6000 generation has a complete set of optimized development tools,
including an efficient C compiler , an assembly optimizer for simplified assem­bly-language programming and scheduling, and a Windows based debug­ger interface for visibility of source code execution characteristics.

Features of the ’C6000 devices include:

- Advanced VLIW CPU with eight functional units, including two multipliers

and six arithmetic units

J Executes up to eight instructions per cycle for up to ten times the per-

formance of other DSPs

J Allows designers to develop highly effective RISC-like code for rapid

development

- Instruction packing
J Gives code size equivalence for eight instructions executed serially or

in parallel

J Reduces code size, program fetches, and power consumption

- Conditional execution of all instructions
J Reduces costly branching
J Increases parallelism for higher sustained performance

- Efficient code execution on independent functional units
J Industry’s most efficient C compiler on DSP benchmark suite
J Industry’s first assembly optimizer for fast development and improved

parallelism

Introduction

1-5

Features and Options of the TMS320C6000 Devices

Features and Options of the TMS320C6000 Devices / Overview of TMS320C6000 Memory

- 8/16/32-bit data support, providing efficient memory support for a variety

of applications

- 40-bit arithmetic options, which add extra precision for vocoders and other

computationally intensive applications

- Saturation and normalization, which provide support for key arithmetic op-

erations

- Field manipulation and instruction extract, set, clear, and bit counting,

which support common operations found in control and data manipulation
applications.

- Hardware support for IEEE single-precision and double-precision instruc-

tions. (’C6701 only)

- Pin-compatible fixed-point and floating-point DSPs.

For more information on features and options of the TMS320C6000, see the

TMS320C6000 CPU and Instruction Set Reference Guide

1.4 Overview of TMS320C6000 Memory

The internal memory configuration varies between the different ’C6000 de­vices. All devices include:

.

- Internal data/program memory

- Internal peripherals

- External memory accessed through the external memory interface (EMIF)

TMS320C6201/C6202/C6701: The ‘C6201, ‘C6202, and ‘C6701 each have
separate data and program memories. The internal program memory can be
mapped into the CPU address space or operated as a program cache. A
256-bit-wide path is provided from to the CPU to allow a continuous stream of
eight 32-bit instructions for maximum performance.

Data memory is accessed through the data memory controller, which controls
the following functions:

- The CPU and the direct memory access (DMA) controller accesses to the

internal data memory, and performs the necessary arbitration.

- The CPU data access to the EMIF

- The CPU access to on-chip peripherals

The internal data memory is divided into 16-bit-wide banks. The data memory
controller performs arbitration between the CPU and the DMA controller inde­pendently for each bank, allowing both sides of the CPU and the DMA to ac­cess different memory locations simultaneously without contention. The data
memory controller supports configurable endianness. The LENDIAN pin on
the device selects the endianness of the device.

1-6

Features and Options of the TMS320C6000 Devices

Overview of TMS320C6000 Memory

TMS320C6211/C6711: The ‘C6211/C6711 is a cache-based architecture,
with separate level-one program and data caches. These cache spaces are
not included in the memory map and are enabled at all times. The level-one
caches are only accessible by the CPU.

The level-one program cache (L1P) controller interfaces the CPU to the L1P.
A 256-bit wide path is provided from to the CPU to allow a continuous stream
of 8 32-bit instructions for maximum performance.

The level-one data cache (L1D) controller provides the interface between the
CPU and the L1D. The L1D is a dual-ported memory, which allows simulta­neous access by both sides of the CPU.

On a miss to either L1D or L1P, the request is passed to the L2 controller. The
L2 controller facilitates:

- The CPU and the enhanced direct memory access (EDMA) controller ac-

cesses to the internal memory, and performs the necessary arbitration

- The CPU data access to the EMIF

- The CPU accesses to on-chip peripherals

- Sends request to EMIF for an L2 data miss

The internal SRAM of the ‘C621 1/C6711 is a unified program and data memory
space. The L2 memory space may be configured as all memory-mapped
SRAM, all cache, or a combination of the two.

Introduction

1-7

Overview of TMS320C6000 Peripherals

1.5 Overview of TMS320C6000 Peripherals

Peripherals available on the TMS320C6000 devices are shown in Table 1-2.

Table 1–2. TMS320C6000 Peripherals

Peripheral C6201 C6202 C6211 C6701 C6711
Direct memory access (DMA)

controller

Y Y N Y N

Enhanced direct memory access
(EDMA) controller

Host-port interface (HPI) Y N Y Y Y
Expansion bus N Y N N N
External memory interface (EMIF) Y Y Y Y Y
Boot configuration Y Y Y Y Y
Multichannel buffered serial ports

(McBSPs)
Interrupt selector Y Y Y Y Y
32-bit timers 2 2 2 2 2
Power-down logic Y Y Y Y Y

N N Y N Y

23222

The user-accessible peripherals are configured via a set of memory-mapped
control registers. The peripheral bus controller performs the arbitration for ac­cesses of on-chip peripherals. The Boot Configuration logic is interfaced
through external signals only , and the Power-down logic is accessed directly
by the CPU.

Figure 1-1 shows the peripherals in the block diagram for the TMS320C6201,
‘C6202, and ‘C6701 devices. Figure 1-2 shows a block diagram for the
TMS320C6211 and ’C6711 devices.

1-8

Figure 1–1. TMS320C6201/C6202/C6701 Block Diagram

Program
memory/

External
memory

interface

(EMIF)

Timer 0

Timer 1

Multichannel

buffered

serial port 0

(McBSP 0)

Multichannel

buffered

serial port 1

(McBSP 1)

Host port/

expansion

bus

Program bus

Data bus

DMA buses

Direct memory access

controller (DMA)

cache

controller

Instruction fetch

Instruction dispatch

Instruction decode In-circuit emulation

Data path A

A register file

.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2

12

Data memory

Power down

logic

PLL

configuration

Overview of TMS320C6000 Peripherals

Internal program memory

CPU

Expansion bus control

registers

Control registers

Data path B

B register file

Interrupt control

controller

Internal data

memory

Boot

Introduction

1-9

Overview of TMS320C6000 Peripherals

Figure 1–2. TMS320C6211/C6711 Block Diagram

External
memory

interface

(EMIF)

Multichannel

buffered

serial port 1

(McBSP 1)

Multichannel

buffered

serial port 0

(McBSP 0)

Host port

interface

(HPI)

Power down logic

L1P cache

direct mapped

4K bytes

CPU

Control

registers

In–circuit

emulation

Data path 2

B register file

L2S2M2D2

Interrupt control

Enhanced

DMA

controller

L2 memory

4 banks

64K bytes

Instruction fetch

Instruction dispatch

Instruction decode

Data path 1

A register file

L1 S1 M1 D1

Timer 0Timer 1

L1D cache

2–way set

associative

4K bytes

DMA Controller: The DMA controller transfers data between address ranges
in the memory map without intervention by the CPU. The DMA controller has
four programmable channels and a fifth auxiliary channel.

EDMA Controller: The EDMA controller performs the same functions as the
DMA controller. The EDMA has sixteen programmable channels, as well as
a RAM space to hold multiple configurations for future transfers.

1-10

HPI: The HPI is a parallel port through which a host processor can directly ac­cess the CPU’s memory space. The host device has ease of access because
it is the master of the interface. The host and the CPU can exchange informa­tion via internal or external memory . In addition, the host has direct access to
memory-mapped peripherals.

Expansion Bus: The expansion bus is a replacement for the HPI, as well as
an expansion of the EMIF. The expansion provides two distinct areas of
functionality , (host port and I/O port) which can co-exist in a system. The host
port of the expansion bus can operate in either asynchronous slave mode,
similar to the HPI, or in synchronous master/slave mode. This allows the
device to interface to a variety of host bus protocols. Synchronous FIFOs and
asynchronous peripheral I/O devices may interface to the expansion bus.

Overview of TMS320C6000 Peripherals

EMIF: The EMIF supports a glueless interface to several external devices, in­cluding:

- Synchronous burst SRAM (SBSRAM)

- Synchronous DRAM (SDRAM)

- Asynchronous devices, including SRAM, ROM, and FIFOs

- An external shared-memory device

Boot Configuration: The TMS320C62x and TMS320C67x provide a variety
of boot configurations that determine what actions the DSP performs after de­vice reset to prepare for initialization. These include loading in code from an
external ROM space on the EMIF and loading code through the HPI/expan­sion bus from an external host.

McBSP: The multichannel buf fered serial port (McBSP) is based on the stan­dard serial port interface found on the TMS320C2000 and ’C5000 platform de­vices. In addition, the port can buffer serial samples in memory automatically
with the aid of the DMA/EDMA controller. It also has multichannel capability
compatible with the T1, E1, SCSA, and MVIP networking standards. Like its
predecessors, it provides:

- Full-duplex communication

- Double-buffered data registers that allow a continuous data stream

- Independent framing and clocking for receive and transmit

- Direct interface to industry-standard codecs, analog interface chips

(AICs), and other serially connected A/D and D/A devices

In addition, the McBSP has the following capabilities:

- Direct interface to:
J T1/E1 framers
J ST-BUSt compliant devices
J IOM-2 compliant devices
J AC97 compliant devices
J IIS compliant devices
J SPI devices

- Multichannel transmission and reception of up to 128 channels

- A wider selection of data sizes including 8-, 12-, 16-, 20-, 24-, and 32-bits

- µ-law and A-law companding

- 8-bit data transfers with LSB or MSB first

- Programmable polarity for both frame synchronization and data clocks

- Highly programmable internal clock and frame generation

Introduction

1-1 1

Overview of TMS320C6000 Peripherals

Timer: The ’C6000 devices have two 32-bit general-purpose timers that are
used to:

- Time events

- Count events

- Generate pulses

- Interrupt the CPU

- Send synchronization events to the DMA/EDMA controller

Interrupt Selector: The ’C6000 peripheral set produces 14–16 interrupt
sources. The CPU has 12 interrupts available. The interrupt selector allows
you to choose which 12 interrupts your system needs. The interrupt selector
also allows you to change the polarity of external interrupt inputs.

Power-down: The power-down logic allows reduced clocking to reduce pow­er consumption. Most of the operating power of CMOS logic dissipates during
circuit switching from one logic state to another. By preventing some or all of
the chip’s logic from switching, you can realize significant power savings with­out losing any data or operational context.

1-12

Chapter 2

TMS320C6201/C6701

Program and Data Memory

This chapter describes the program memory organization, the program
memory and cache modes, and access of program memory through the DMA
controller for the TMS320C6201/C6701.

Topic Page

2.1 Program Memory Controller 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Internal Program Memory 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 DMA Controller Access to Program Memory 2-6. . . . . . . . . . . . . . . . . . . .

2.4 Data Memory Controller 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Data Memory Access 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Internal Data Memory Organization 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Peripheral Bus 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Program Memory Controller

2.1 Program Memory Controller

The program memory controller, shown in Figure 2–1 performs the following
tasks:

- Performs CPU and DMA requests to internal program memory and the

necessary arbitration

- Performs CPU requests to external memory through the external memory

interface (EMIF)

- Manages the internal program memory when it is configured as cache.

Figure 2–1. TMS320C6201/C6701 Program Memory Controller in the Block Diagram

’C6201/C6701

Timers

Interrupt selector

McBSPs

HPI control
DMA control
EMIF control

Host port

PLL

Power

down

Boot

configuration

EMIF

Peripheral

bus

controller

DMA

controller

Data memory

Data memory

controller

CPU core

Program fetch

Instruction dispatch

Instruction decode

Data path

1

Program memory controller

Program memory/cache

Data path

2

2-2

2.2 Internal Program Memory

The internal program memory contains 64K bytes of RAM or, equivalently, 2K
256-bit fetch packets or 16K 32-bit instructions. The CPU, through the pro­gram memory controller, has a single-cycle throughput, 256-bit-wide connec­tion to internal program memory.

2.2.1 Internal Program Memory Modes

The internal program memory can be used in any of four modes which are se­lected by the program cache control (PCC) field (bits 7–5) in the CPU control
and status register (CSR) as shown in Table 2–1. The modes are:

- Mapped: Depending on the memory map selected, the program memory

is located at one of these addresses:

J 0000 0000h–0000 FFFFh for map 1
J 0140 0000h–0140 FFFFh for map 0

In mapped mode, program fetches from the internal program memory ad­dress return the fetch packet at that address. In the other modes, CPU
accesses to this address range return undefined data. Mapped mode is
the default state of the internal program memory at reset. The CPU cannot
access internal program memory through the data memory controller.
(See Chapter 7,
tion about how to select the memory map.)

Boot Configuration, Reset, and Memory Map

Internal Program Memory

, for informa-

- Cache enabled: In cache enabled mode, any initial program fetch at an ad-

dress causes a cache miss. In a cache miss, the fetch packet is loaded from
the external memory interface (EMIF) and stored in the internal cache
memory, one 32-bit instruction at a time. While the fetch packet is being
loaded, the CPU is halted. The number of wait states incurred depends on
the type of external memory used, the state of that memory, and any conten­tion for the EMIF with other requests, such as the DMA controller or a CPU
data access. Any subsequent read from a cached address causes a cache
hit, and that fetch packet is sent to the CPU from the internal program
memory without any wait states. Changing from program memory mode to
cache enabled mode flushes the program cache. This mode transition is the
only means to flush the cache.

- Cache freeze: During a cache freeze, the cache retains its current state.

A program read of a frozen cache is identical to a read of an enabled cache
except that on a cache miss the data read from the external memory inter­face is not stored in the cache. A subsequent read of the same address
causes a cache miss, and the data is again fetched from external memory .

TMS320C6201/C6701 Program and Data Memory

2-3

Internal Program Memory

Cache freeze ensures that critical program data is not overwritten in the
cache.

- Cache bypass: When the cache is bypassed, any program read fetches

data from external memory . The data is not stored in the cache memory.
As in cache freeze, the cache retains its state in cache bypass. This mode
ensures that external program data is being fetched.

Table 2–1. Internal Program Memory Mode Summary

Internal Program
Memory Mode

Mapped 000 Cache disabled (default state at reset)
Cache enabled 010 Cache accessed and updated on reads
Cache freeze 011 Cache accessed but not updated on reads
Cache bypass 100 Cache not accessed or updated on reads

PCC

Value

Other Reserved

Description

Note:

If you change the operation mode of the PMEMC, you should use the follow­ing assembly routine to ensure correct operation of the PMEMC. This routine
enables the cache. To change the PMEMC operation mode to a state other
than cache enable, you should modify line four of the routine to correspond
the the value of PCC that you want moved into B5. For example, to put the
cache into mapped mode 0000h should be moved into B5. The CPU regis­ters used in this example have no significance. Any of the registers A0–A15
or B0–B15 can be used in the program.

.align 32
MVC .S2 CSR,B5 ;copy control status register

|| MVK .S1 0xff1f,A5

AND .L1x A5,B5,A5 ;clear PCC field of CSR value

|| MVK S2 0x0040,B5 ;set cache enable mask

OR .L2x A5,B5,B5 ;set cache enable bit
MVC .S2 B5,CSR ;update CSR to enable cache
NOP 4
NOP

2.2.2 Cache Architecture

The architecture of the cache is directly mapped. The 64K byte cache contains
2K fetch packets, thus, 2K frames. The width of the cache (the frame size) is
256 bits. Each frame in the cache is one fetch packet.

2-4

2.2.2.1 Cache Usage of CPU Address

Figure 2–2 shows how the cache uses the fetch packet address from the CPU:

- 5-bit fetch packet alignment: The five LSBs of the address are assumed to

be 0 because all program fetch requests are aligned on fetch packet
boundaries (eight words or 32 bytes).

- 1 1-bit tag block offset: Because the cache is directly mapped, any external

address maps to only one of the 2K frames. Any two fetch packets that are
separated by an integer multiple of 64K bytes map to the same frame.
Thus, bits 15–5 of the CPU address create the 1 1-bit block offset that de­termines which of the 2K frames any particular fetch packet maps to.

- 10-bit tag: The cache assumes a maximum external address space of

64M bytes (from 0000 0000h–03FFFFFFh). Thus, bits 25–16 of the ad­dress correspond to the tag that determines the original location of the
fetch packet in external memory space. The cache also has a separate
2K × 1 1 tag RAM that holds all the tags. Each address location in this RAM
contains a 10-bit tag plus a valid bit that is used to record frame validity
information.

Internal Program Memory

Figure 2–2. Logical Mapping of Cache Address

31 26 25 16 15 54 0

Outside external range.

assumed to be 0

2.2.2.2 Cache Flush

A dedicated valid bit in each address location of the tag RAM indicates whether
the contents of the corresponding cache frame is valid data. During a cache
flush, all of the valid bits are cleared to indicate that no cache frames have valid
data. Cache flushes occur only at the transition of the internal program
memory from mapped mode to cache enabled mode. Y ou initiate this transition
by setting the cache enable pattern in the PCC field of the CPU control and
status register.

2.2.2.3 Frame Replacement

A cache miss is detected when the tag corresponding to the block offset of
the fetch packet address requested by the CPU does not correspond to bits
25–16 of the fetch packet address or if the valid bit at the block offset location
is clear . If enabled, the cache loads the fetch packet into the corresponding
frame, sets the valid bit, sets the tag to bits 25–16 of the requested address,
and delivers this fetch packet to the CPU after all eight instructions are
available.

Tag Block offset

Fetch packet alignment.

assumed 0

TMS320C6201/C6701 Program and Data Memory

2-5

DMA Controller Access to Program Memory

2.3 DMA Controller Access to Program Memory

The DMA controller can read and write to internal program memory when the
memory is configured in mapped mode. The CPU always has priority over the
DMA controller for access to internal program memory regardless of the value
of the PRI bit for that DMA channel. DMA controller accesses are postponed
until the CPU stops making requests. To avoid losing future requests that occur
after arbitration and while a DMA controller access is in progress, the CPU in­curs one wait state per DMA controller access. The maximum throughput to the
DMA is one access every other cycle. In a cache mode, a DMA controller write
is ignored by the program memory controller , and a read returns an undefined
value. For both DMA reads and writes in cache modes, the DMA controller is
signaled that its request has finished. At reset, the program memory system is
in mapped mode, allowing the DMA controller to boot load code into the internal
program memory.

See Chapter 7,
ing code.

TMS320C6000 Boot Modes,

for more information on bootload-

2-6

2.4 Data Memory Controller

As shown inFigure 2–3, the data memory controller connects:

- The CPU and direct memory access (DMA) controller to internal data

memory and performs the necessary arbitration.

- CPU to the external memory interface (EMIF).

- The CPU to the on chip peripherals through the peripheral bus controller.

The peripheral bus controller performs arbitration between the CPU and DMA
for the on-chip peripherals.

Figure 2–3. TMS320C6x Block Diagram

Data Memory Controller

Timers

Interrupt selector

MCSPs

HPI control
DMA control
EMIF control

Host port

PLL

Power

down

Boot

Configuration

EMIF

Peripheral

bus

controller

DMA

controller

Data memory

Data memory

controller

CPU core

Program fetch

Instruction dispatch

Instruction decode

Data path

1

Program memory controller

Program memory/cache

Data path

2

TMS320C6201/C6701 Program and Data Memory

2-7

Data Memory Access

2.5 Data Memory Access

The data memory controller services all CPU and DMA controller data re­quests to internal data memory . Figure 2–4, Figure 2–5, and Figure 2–6 show
the directions of data flow and the master (requester) and slave (resource)
relationships between the modules:

- The CPU requests data reads and writes to:
J Internal data memory
J On-chip peripherals through the peripheral bus controller
J EMIF

- The DMA controller requests reads and writes to internal data memory.

- The CPU cannot access internal program memory through the data

memory controller.

The CPU sends requests to the data memory controller through the two address
buses (DA1 and DA2). Store data is transmitted through the CPU data store
buses (ST1 and ST2). Load data is received through the CPU data load buses
(LD1 and LD2). The CPU data requests are mapped, based on address, to
either the internal data memory, internal peripheral space (through the peripher­al bus controller), or the external memory interface. The data memory controller
also connects the DMA controller to the internal data memory and performs ar­bitration between the CPU and DMA controller.

2-8

Internal Data Memory Organization

2.6 Internal Data Memory Organization

The following sections describe the memory organization of each device in the
’C6x generation of DSPs ’C6201 and ’C6701 devices.

2.6.1 TMS320C6201 Revision 2

The 64K bytes of internal data RAM are organized as one block of 64K bytes lo­cated from address 8000 0000h to 8000 FFFFh. This block is organized as four
8K banks of 16-bit halfwords. Both the CPU and the DMA controller can simulta­neously access data that resides in different banks. This organization allows the
two CPU data ports, A and B, to simultaneously access neighboring 16-bit data
elements inside the block without a resource conflict.

Table 2–2. Data Memory Organization (TMS320C6201 Revision 2)

Bank 0 Bank 1 Bank 2 Bank 3

First address 80000000

80000008

8000FFF0

80000001
80000009

S
S
S

S
S
S

8000FFF1

80000002
8000000A

S
S
S

8000FFF2

80000003
8000000B

S
S
S

8000FFF3

80000004
8000000C

S
S
S

8000FFF4

80000005
8000000D

S
S
S

8000FFF5

80000006
8000000E

S
S
S

8000FFF6

80000007
8000000F

S
S
S

8000FFF7

Last address 8000FFF8 8000FFF9 8000FFFA 8000FFFB 8000FFFC 8000FFFD 8000FFFE 8000FFFF

TMS320C6201/C6701 Program and Data Memory

2-9

Internal Data Memory Organization

Figure 2–4. Data Memory Controller Interconnect to Other Banks

(TMS320C6201 Revision 2)

’C6201 CPU

Side ASide B

3232 32 32

Control

DA2 address

Peripheral

bus

controller

ST2 store data

LD2 load data

Data memory controller

(DMEMC)

Control

External
memory

interface

DA1 address

ST1 store data

LD1 load data

16

16

16

16

323232

DMA

controller

64 K bytes

0 1 2 3 4 5 6 7

8 9 A B C D E F

8000 0000

8000 FFFF

Bank 3

Bank 2

Bank 1

Bank 0

2-10

Internal Data Memory Organization

2.6.2 TMS320C6201 Revision 3

The 64K bytes of internal data RAM are organized as two blocks of 32K bytes
located from address 8000 0000h to 8000 7FFFh and 8000 8000h to
8000 FFFFh. The DMA controller or side A and side B of the CPU can simulta­neously access any portion of the internal memory without conflict, when using
different blocks. Both blocks are organized as four 4K banks of 16-bit halfwords.
Therefore you do not have to consider the address within a block if simultaneous
accesses occur to different blocks. Accesses to different blocks never cause per­formance penalties. Both CPU and DMA can still simultaneously access data that
resides in different banks within the same block without a performance penalty.
To avoid performance penalties, you have to pay attention to address LSBs
when the two accesses involve data in the same block. Thi s or ganization also
allows the two CPU data ports, A and B, to simultaneously access neighboring
16-bit data elements inside the block without a resource conflict.

Table 2–3. Data Memory Organization (TMS320C6201 Revision 3)

Bank 0 Bank 1 Bank 2 Bank 3

First address
(Block 0)

80000000
80000008

S
S
S

80007FF0

80000001
80000009

S
S
S

80007FF1

80000002
8000000A

S
S
S

80007FF2

80000003
8000000B

S
S
S

80007FF3

80000004
8000000C

S
S
S

80007FF4

80000005
8000000D

S
S
S

80007FF5

80000006
8000000E

S
S
S

80007FF6

80000007
8000000F

S
S
S

80007FF7

Last address
(Block 0)

First address
(Block 1)

Last address
(Block 1)

80007FF8 80007FF9 80007FFA 80007FFB 80007FFC 80007FFD 80007FFE 80007FFF

80008000
80008008

8000FFF0
8000FFF8 8000FFF9 8000FFFA 8000FFFB 8000FFFC 8000FFFD 8000FFFE 8000FFFF

80008001
80008009

S
S
S

S
S
S

8000FFF1

80008002
8000800A

8000FFF2

S
S
S

80008003
8000800B

S
S
S

8000FFF3

80008004
8000800C

S
S
S

8000FFF4

80008005
8000800D

S
S
S

8000FFF5

TMS320C6201/C6701 Program and Data Memory

80008006
8000800E

S
S
S

8000FFF6

80008007
8000800F

S
S
S

8000FFF7

2-1 1

Internal Data Memory Organization

Figure 2–5. Data Memory Controller Interconnect to Other Banks

(TMS320C6201 Revision 3)

’C6201 CPU

Side ASide B

3232 32 32

Bank 3

Bank 2

Bank 1

Bank 0

Block 1

8000 8000

E

DF

2134657

0

8A9BC

8000 FFFF

16

16

16

16

Peripheral

controller

Control

DA2 address

bus

ST2 store data

LD2 load data

Data memory controller

Control

(DMEMC)

External
memory
interface

DA1 address

ST1 store data

LD1 load data

16

16

16

16

323232

DMA

controller

Block 0
(32K bytes)(32K bytes)

2134657

0

8000 0000

A9BCEDF

8

8000 7FFF

Bank 3

Bank 2

Bank 1

Bank 0

2-12

2.6.3 TMS320C6701

The 64K bytes of internal data RAM are organized as two blocks of 32K bytes
located from address 8000 0000h to 8000 7FFFh and 8000 8000h to
8000 FFFFh. Side A and side B of the CPU or the DMA Controller can simulta­neously access any portion of the internal data memory without conflict, when
using different blocks. Therefore, you do not have to consider the address
within a block if simultaneous accesses occur to different blocks. Accesses to
different blocks never cause performance penalties. You only have to pay
attention to the address when the two accesses occur in different blocks. Both
blocks are organized as eight 2K banks of 16-bit halfwords. Both the CPU and
DMA controller can still simultaneously access data that resides in different
banks within the same block without performance penalty. To avoid perfor­mance penalties, you have to pay attention to address LSBs when two ac­cesses involve data in the same block. This organization also allows the two
CPU data ports, A and B, to simultaneously access neighboring 16-bit data
elements inside the same block without a resource conflict.

Table 2–4. Data Memory Organization

Bank 0 Bank 1 Bank 2 Bank 3

First address
(Block 0)

80000000 80000001 80000002 80000003 80000004 80000005 80000006 80000007

Internal Data Memory Organization

Last address
(Block 0)

First address
(Block 0)

Last address
(Block 0)

First address
(Block 1)

Last address
(Block 1)

First address
(Block 1)

Last address
(Block 1)

80007FF0 80007FF1 80007FF2 80007FF3 80007FF4 80007FF5 80007FF6 80007FF7

Bank 4 Bank 5 Bank 6 Bank 7

80000008 80000009 8000000A 8000000B 8000000C 8000000D 8000000E 8000000F

80007FF8 80007FF9 80007FFA 80007FFB 80007FFC 80007FFD 80007FFE 80007FFF

Bank 0 Bank 1 Bank 2 Bank 3

80008000 80008001 80008002 80008003 80008004 80008005 80008006 80008007

8000FFF0 8000FFF1 8000FFF2 8000FFF3 8000FFF4 8000FFF5 8000FFF6 8000FFF7

Bank 4 Bank 5 Bank 6 Bank 7

80008008 80008009 8000800A 8000800B 8000800C 8000800D 8000800E 8000800F

8000FFF8 8000FFF9 8000FFFA 8000FFFB 8000FFFC 8000FFFD 8000FFFE 8000FFFF

TMS320C6201/C6701 Program and Data Memory

2-13

Internal Data Memory Organization

Figure 2–6. Data Memory Controller Interconnect to Other Blocks (TMS320C6701)

’C6701CPU

Side ASide B

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

Bank 0

Block 1

32 64 64

Control

DA2 address

ST2 store data

8000 FFFF

16

DCBA01234567 98FE

16

16

16

16

16

16

16

LD2 load data

Data memory controller

(DMEMC)

Control

DA1 address

32

ST1 store data

LD1 load data

323232

16

16

16

16

16

16

16

16

Block 0
(32K bytes)(32K bytes)

8000 7FFF

Bank 7

DCBA01234567 98FE

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

Bank 0

2-14

8000 8000

Peripheral

bus

controller

External
memory
interface

DMA

controller

8000 0000

2.6.4 Data Alignment

The following data alignment restrictions apply:
Doublewords: (’C6701 only) Doublewords are aligned on even 8-byte (dou-

bleword) boundaries, and always start at a byte address where the three LSBs
are 0. Doublewords are used only on loads triggered by the LDDW instruction.
Store operations do not use doublewords.

Words: Words are aligned on even 4-byte (word) boundaries, and always start
at a byte address where the two LSBs are 0. A word access requires two adja­cent 16-bit-wide banks.

Halfwords: Halfwords are aligned on even 2-byte (halfword) boundaries, and
always start at byte addresses where the LSB is 0. Halfword accesses require
the entire 16-bit-wide bank.

Bytes: There are no alignment restrictions on byte accesses.

2.6.5 Dual CPU Accesses to Internal Memory

Internal Data Memory Organization

Both the CPU and DMA can read and write 8-bit bytes, 16-bit halfwords, and
32-bit words. The data memory controller performs arbitration individually for
each 16-bit bank. Although arbitration is performed on 16-bit-wide banks, the
banks have byte enables to support byte-wide accesses. However, a byte ac­cess prevents the entire 16 bits containing the byte from simultaneously being
used by another access.

As long as multiple requesters access data in separate banks, all accesses are
performed simultaneously with no penalty . Also, when two memory accesses
involve separate 32K byte memory blocks, there are no memory conflicts, re­gardless of the address. For multiple data accesses within the same block, the
memory organization also allows simultaneous multiple memory accesses as
long as they involve different banks. In one CPU cycle, two simultaneous ac­cesses to two different internal memory banks occur without wait states. T wo
simultaneous accesses to the same internal memory bank stall the entire CPU
pipeline for one CPU clock, providing two accesses in two CPU clocks. These
rules apply regardless of whether the accesses are loads or stores.

TMS320C6201/C6701 Program and Data Memory

2-15

Internal Data Memory Organization

Loads and stores from the same execute packet are seen by the data memory
controller during the same CPU cycle. Loads and stores from future or pre­vious CPU cycles do not cause wait states for the internal data memory ac­cesses in the current cycle. Thus, internal data memory access causes a wait
state only when a conflict occurs between instructions in the same fetch packet
accessing the same 16-bit wide bank. This conflict is an internal memory con­flict. The data memory controller stalls the CPU for one CPU clock, serializes
the accesses, and performs each access separately . In prioritizing the two ac­cesses, any load occurs before any store access. A load in parallel with a store
always has priority over the store. If both the load and the store access the
same resource (for example, the EMIF, or peripheral bus, internal memory
block), the load always occurs before the store. If both accesses are stores,
the access from DA1 takes precedence over the access from DA2. If both ac­cesses are loads, the access from DA2 takes precedence over the access
from DA1. Figure 3–3 shows what access conditions cause internal memory
conflicts when the CPU makes two data accesses (on DA1 and DA2).

Figure 2–7. Conflicting Internal Memory Accesses to the Same Block

(TMS320C6201 Revisions 2 and 3)

DA1 Byte Halfword Word

DA2 2:0 000 001 010 011 100 101 110 111 000 010 100 110 000 100
Byte 000

001
010

011
100
101

110

111

Halfword 000

010
100

110

Word 000

100

Note: Conflicts shown in shaded areas.

2-16

Internal Data Memory Organization

y

e

a

f

d

Figure 2–8. Conflicting Internal Memory Accesses to the Same Block (TMS320C6701)

Double

DA1 Byte Halfword Word

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

D
A

2

B
y

t

e

H

a

l

f
w
o

r

d

W
o

r

d

D
W

3–0

0000
0001
0010

0011
0100
0101

0110

0111
1000
1001
1010

1011

1100

1101

1110

1111
0000
0010
0100

0110
1000
1010

1100

1110
0000
0100
1000

1100
0000
1000

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

1

1

1

0

1

0

0

0

0

0

0

1

0

0

0

0

-word

1

1

0

0

1

0

0

0

0

0

0

0

1
0
0
0

Note: Conflicts shown in shaded areas.

TMS320C6201/C6701 Program and Data Memory

2-17

Internal Data Memory Organization

2.6.6 DMA Accesses to Internal Memory

The DMA controller can accesss any portion of one block of internal data
memory while the CPU is simultaneously accessing any portion of another
block. If both the CPU and the DMA controller are accessing the same block,
and portions of both accesses are to the same 16-bit bank, the DMA operation
can take place first or last, depending on the CPU/DMA priority settings. You
can use Figure 3–3 to determine DMA versus CPU conflicts. Assume that one
axis represents the DMA access and the other represents the CPU access
from one CPU data port. Then, perform this analysis again for the other data
port. If both comparisons yield no conflict, then there is no CPU/DMA internal
memory conflict. If either comparison yields a conflict, then there is a CPU/
DMA internal memory conflict. In this case, the priority is resolved by the PRI
bit of the DMA channel as described in Chapter 4,

Internal Memory

CPU (PRI = 1), any CPU accesses are postponed until the DMA accesses fin­ish and the CPU incurs a 1-CPU-clock wait state. If both CPU ports and the
DMA access the same memory block, the number of wait states increases to
two. If the DMA has multiple consecutive requests to the block required by the
CPU, the CPU is held off until all DMA accesses to the necessary blocks finish.
In contrast, if the CPU has higher priority (PRI = 0), then the DMA access is
postponed until the both CPU data ports stop accessing that bank. In this con­figuration, a DMA access request never causes a wait state.

. If the DMA channel is configured as higher priority than the

TMS320C621 1 Two-Level

2.6.7 Data Endianness

Two standards for data ordering in byte-addressable microprocessors exist:

- Little-endian ordering, in which bytes are ordered from right to left, the

- Big-endian ordering, in which bytes are ordered from left to right, the most

Both the CPU and the DMA controller support a programmable endianness.
This endianness is selected by the LENDIAN pin on the device.
LENDIAN = 1 selects little endian, and LENDIAN big. Byte ordering within word
and half word data resident in memory is identical for little-endian and big-en­dian data. Table 2–5 shows which bits of a data word in memory are loaded
into which bits of a destination register for all possible CPU data loads from big­or little-endian data. The data in memory is assumed to be the same data that
is in the register results from the LDW instruction in the first row. Table 2–7 and
T able 2–8 show which bits of a register are stored in which bits of a destination
memory word for all possible CPU data stores from big- and little-endian data.
The data in the source register is assumed to be the same data that is in the
memory results from the STW instruction in the first row.

2-18

most significant byte having the highest address

significant byte having the lowest address

Internal Data Memory Organization

Table 2–5. Register Contents After Little-Endian or Big-Endian Data Loads

(TMS320C6201 and TMS320C6701)

Address Bits

Instruction

LDW 00 BA987654h BA987654h
LDH 00 FFFFBA98h 00007654h
LDHU 00 0000BA98h 00007654h
LDH 10 00007654h FFFFBA98h
LDHU 10 00007654h 0000BA98h
LDB 00 FFFFFFBAh 00000054h
LDBU 00 000000BAh 00000054h
LDB 01 FFFFFF98h 00000076h
LDBU 01 00000098h 00000076h
LDB 10 00000076h FFFFFF98h
LDBU 10 00000076h 00000098h
LDB 11 00000054h FFFFFFBAh
LDBU

Note: The contents of the word in data memory at location xxxx xx00 is BA987654h.

(1:0)

11 00000054h 000000BAh

Big-Endian
Register Result

Little-Endian
Register Result

TMS320C6201/C6701 Program and Data Memory

2-19

Internal Data Memory Organization

Table 2–6. Register Contents After Little-Endian or Big-Endian Data Loads

(TMS320C6701 only)

Address Bits

Instruction

LDDW
(’C6701 only)

LDW 000 FEDC BA98h 7654 3210h
LDW

Note: The contents of the doubleword in data memory at location xxxx x000 before the ST

instruction executes is FEDC BA98 7654 3210h.

(2:0)

000 FEDC BA98

100 7654 3210h FEDC BA98h

Big-Endian
Memory Result

7654 3210h

Little-Endian
Memory Result

FEDC BA98
7654 3210h

Table 2–7. Memory Contents After Little-Endian or Big-Endian Data Stores

(TMS320C6201/C6701)

Big-Endian

Instruction Address Bits (1:0)

STW 00 BA98 7654h BA98 7654h
STH 00 7654 1970h 0112 7654h
STH 10 01 12 7654h 7654 1970h
STB 00 5412 1970h 0112 1954h
STB 01 0154 1970h 0112 5470h
STB 10 0112 5470h 0154 1970h

Memory Result

Little-Endian
Memory Result

2-20

STB

Note: The contents of the word in data memory at location xxxx xx00 before the ST instruction

executes is 01121970h. The contents of the source register is BA987654h.

11 0112 1954h 5412 1970h

2.7 Peripheral Bus

The peripherals are controlled by the CPU and the DMA controller through ac­cesses of control registers. The CPU and the DMA controller access these reg­isters through the peripheral data bus. The DMA controller directly accesses
the peripheral bus controller, whereas the CPU accesses it through the data
memory controller.

2.7.1 Byte and Halfword Access

The peripheral bus controller converts all peripheral bus accesses to word
accesses. However, on read accesses both the CPU and the DMA controller
can extract the correct portions of the word to perform byte and halfword ac­cesses properly . Any side-effects caused by a peripheral control register read
occur regardless of which bytes are read. In contrast, for byte or halfword
writes, the values the CPU and the DMA controller only provide correct values
in the enabled bytes. The values that are always correct are shown in
Table 2–8. Undefined results are written to the nonenabled bytes. If you are
not concerned about the values in the disabled bytes, this is acceptable. Other­wise, access the peripheral registers only via word accesses.

Peripheral Bus

Table 2–8. Memory Contents After Little-Endian or Big-Endian Data Stores

Access
Type

Word 00 XXXXXXXX XXXXXXXX
Halfword 00 XXXX???? ????XXXX
Halfword 10 ????XXXX XXXX????
Byte 00 XX?????? ??????XX
Byte 01 ??XX???? ????XX??
Byte 10 ????XX?? ??XX????
Byte

Note: X indicates nybbles correctly written, ? indicates nybbles with undefined value after

write

Address Bits

(1:0)

11 ??????XX XX??????

Big-Endian
Register

Little-Endian
Memory Result

TMS320C6201/C6701 Program and Data Memory

2-21

Peripheral Bus

2.7.2 CPU Wait States

Isolated peripheral bus controller accesses from the CPU causes six CPU wait
states. These wait states are inserted to allow pipeline registers to break up
the paths between traversing the on-chip distances between the CPU and
peripherals as well as for arbitration time.

2.7.3 Arbitration Between the CPU and the DMA Controller

As shown in Figure 2–5 and Figure 2–6, the peripheral bus controller performs
arbitration between the CPU and the DMA controller for the peripheral bus.
Like internal data access, the PRI bits in the DMA controller determine the
priority between the CPU and the DMA controller. If a conflict occurs between
the CPU (via the data memory controller) the lower priority requester is held
off until the higher priority requester completes all accesses to the peripheral
bus controller. The peripheral bus is arbitrated as a single resource, so the low­er priority resource is blocked from accessing all peripherals, not just the one
accessed by the higher priority requester.

2-22

Chapter 3

TMS320C6202 Program and Data Memory

This chapter describes the TMS320C6202 program memory and data
memory controller. Program memory modes including cache operation and
bootload operation are discussed.

Topic Page

3.1 TMS320C6202 Program Memory Controller 3-2. . . . . . . . . . . . . . . . . . . . .

3.2 Memory Mapped Operation 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Cache Operation 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Bootload Operation 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 TMS320C6202 Data Memory Controller 3-7. . . . . . . . . . . . . . . . . . . . . . . . .

3-1

TMS320C6202 Program Memory Controller

3.1 TMS320C6202 Program Memory Controller

The TMS320C6202 program memory controller (PMEMC) provides all of the
functionality available in the TMS320C6201 revision 3. The PMEMC operates
as either a 128K byte memory or direct-mapped cache. In addition to the
memory/cache, the C6202 provides 128K bytes of memory that operates as
a memory-mapped block. To achieve this functionality, the block of program
memory has been expanded to 128K bytes. A second 128K byte block of pro­gram memory has been added. These two blocks can be accessed indepen­dently , allowing for program fetch from one block by the CPU to occur in paral­lel and without interfering with a DMA transfer with the other block of program
memory. Table 3–1 and Table 3–2 compare the internal memory and cache
configurations available on the current TMS320C6000 devices. Figure 3–1
shows a block diagram of the connections between the C6202 CPU, PMEMC,
and memory blocks. The addresses shown in Figure 3–1 are for operation in
memory map mode 1.

Table 3–1. TMS320C6201/C6701/C6202 Internal Memory Configurations

Internal

Device CPU

Memory
Architecture

T otal Memory
(Bytes)

Program Memory
(Bytes)

Data Memory
(Bytes)

’C6201 6200 Harvard 128K 64K (map/cache) 64K (map)
’C6701 6700 Harvard 128K 64K (map/cache) 64K (map)
’C6202

6200 Harvard 384K 128K (map)

128K (map/cache)

128K (map)

Table 3–2. TMS320C6201/C6701/C6202 Cache Architectures

Cache Space Size (Bytes) Associativity Line Size (Bytes)

’C6201 program 64K Direct mapped 32
’C6701 program 64K Direct mapped 32

128K Direct mapped 32

3-2

’C6202 program

TMS320C6202 Program Memory Controller

Figure 3–1. TMS320C6202 Program Memory Controller Block Diagram

C62x CPU

Program fetch

Program Address

256

Control

Program Data

Block 0
(128K bytes)

0000 0000h

mapped

0001 FFFFh

Program memory

controller
(PMEMC)

External
memory

interface

DMA

bus

controller

Block 1
(128K bytes)

0002 0000h

256256

cached or

mapped

0003 FFFFh

TMS320C6202 Program and Data Memory

3-3

Memory Mapped Operation

3.2 Memory Mapped Operation

When the PCC field of the CPU control status register is programmed for
Mapped mode, both blocks of internal program RAM are mapped into internal
program space. Table 3–3 shows the address space for both blocks of RAM
for the map mode selected at device reset.

Table 3–3. Internal Program RAM Address Mapping in Memory Mapped Mode

Map 0 Map 1
Block 0 0140 0000h – 0141 FFFFh 0000 0000h – 0x0001 FFFFh
Block 1 0142 0000h – 0143 FFFFh 0002 0000h – 0x0003 FFFFh

In mapped mode, both the CPU and the DMA can access all locations in both
blocks of RAM. Any access outside of the address space that the internal RAM
is mapped to is forwarded to the EMIF. The DMA can only access one of the
two blocks of RAM at a time. The CPU and DMA can access the internal RAM
without interference as long as each accesses a different block. If the CPU and
DMA attempt to access the same block of RAM at the same time, then the DMA
is stalled until the CPU completes its accesses to that block. After the CPU ac­cess is complete, the DMA is allowed to access the RAM. The DMA cannot
cross between Block 0 and Block 1 in a single transfer. You must use separate
DMA transfers to cross block boundaries.

3-4

3.3 Cache Operation

When the PCC field of the CPU Control Status Register is programmed for one
of the Cache modes, block 1 operates as a cache while block 0 remains
mapped into internal program space. Table 3–4 shows the addresses occu­pied by the RAM that is not used for cache, for each Map Mode.

Table 3–4. Internal Program RAM Address Mapping in Cache Mode

Map 0 Map 1

Block 0 0140 0000h – 0141 FFFFh 0000 0000h – 0001 FFFFh

The cache on the C6202 operates identically to the C6201 cache. Any CPU
or DMA access to the memory range that was occupied by the cache RAM
returns undefined results. As in mapped mode, simultaneous accesses to
block 0 by the CPU and DMA stalls the DMA until the CPU has completed its
access. A DMA access to block 0 while the cache is flushed continues without
stalling. The CPU is halted during a cache flush. Y ou must ensure that all DMA
accesses to block 1 have completed before the cache is enabled.

Note:

Cache Operation

If you change the operation mode of the PMEMC, you should use the follow­ing assembly routine to ensure correct operation of the PMEMC. This routine
enables the cache. To change the PMEMC operation mode to a state other
than cache enable, you should modify line four of the routine to correspond
the the value of PCC that you want moved into B5. For example, to put the
cache into mapped mode 0000h should be moved into B5. The CPU regis­ters used in this example have no significance. Any of the registers A0–A15
or B0–B15 can be used in the program.

.align 32
MVC .S2 CSR,B5 ;copy control status register

|| MVK .S1 0xff1f,A5

AND .L1x A5,B5,A5 ;clear PCC field of CSR value

|| MVK S2 0x0040,B5 ;set cache enable mask

OR .L2x A5,B5,B5 ;set cache enable bit
MVC .S2 B5,CSR ;update CSR to enable cache
NOP 4
NOP

TMS320C6202 Program and Data Memory

3-5

Bootload Operation

3.4 Bootload Operation

The ’C6202 bootload operates identically to the C6201 revision 3. During ROM
bootload, a 64K byte block of data is transferred from the beginning of CE1 to
memory at address 0. During HPI bootload, the host can read or write any in­ternal or external memory location, including the entire internal program
space.

3-6

TMS320C6202 Data Memory Controller

3.5 TMS320C6202 Data Memory Controller

The TMS320C6202 data memory controller (DMEMC) provides all of the func­tionality available in the TMS320C6201 revision 3. The C6202 DMEMC con­tains 128K bytes of RAM organized in two blocks of four banks each. Each
bank is 16 bits wide. The DMEMC for the C6202 operates identically to the
C6201 DMEMC, the DMA controller or side A or side B of the CPU can simulta­neously access two different banks without conflict. Figure 3–2 shows a block
diagram of the connections between the C6202 CPU, DMEMC, and memory
blocks. T able 3–5 shows the memory range occupied by each block of internal
data RAM.

Figure 3–2. TMS320C6202 Data Memory Controller Block Diagram

C62x CPU

Data path AData path B

3232 32 32

Bank 3

Bank 2

Bank 1

Bank 0

Block 0

8000 0000h

E

DF

2134657

0

8A9BC

8000 FFFFh

16

16

16

16

Control

DA2 address

Peripheral

bus

controller

ST2 store data

LD2 load data

Data memory controller

Control

(DMEMC)

External
memory

interface

Table 3–5. Internal Data RAM Address Mapping

Block 0 8000 0000h – 8000 FFFFh
Block 1 8001 0000h – 8001 FFFFh

DA1 address

ST1 store data

LD1 load data

DMA bus
controller

Block 1
(64K bytes)(64K bytes)

16

16

16

2134657

A9BCEDF

16

0

8

323232

8001 0000h

8001 FFFFh

Bank 3

Bank 2

Bank 1

Bank 0

TMS320C6202 Program and Data Memory

3-7

Chapter 4

TMS320C6211/C6711

Two-Level Internal Memory

The TMS320C6211/C6711 provides a two level memory architecture for the
internal program and data busses. The first level memory for both the internal
program and data bus is a 4K byte cache, designated L1P for the program
cache and L1D for the data cache. The second level memory is a 64K byte
memory block that is shared by both the program and data memory buses,
designated L2.

Topic Page

4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Internal Memory Control Registers 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 L1P Description 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 L1D Description 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 L2 Description 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

Overview

4.1 Overview

Figure 4–1 illustrates how the L1P, L1D, and L2 are arranged in the
TMS320C6211/C6711. Figure 4–2 illustrates the bus connections between
the CPU, internal memories, and the enhanced DMA for the ’C6211, and.

Figure 4–1. TMS320C6211/C6711 Block Diagram

External
memory

interface

(EMIF)

Multichannel

buffered

serial port 1

(McBSP 1)

Multichannel

buffered

serial port 0

(McBSP 0)

Host port

interface

(HPI)

Power down logic

Enhanced

DMA

controller

L2 memory

4 banks

64K bytes

Timer 0Timer 1

L1P cache

direct mapped

4K bytes

C6200B CPU

Instruction fetch

Instruction dispatch

Instruction decode

Data path 1

A register file

L1 S1 M1 D1

L1D cache

2-way set

associative

4K bytes

registers

In-circuit

emulation

Data path 2

B register file

Table 4–1. TMS320C6211/C6711 Internal Memory Configurations

Internal

Device CPU

Memory
Architecture

T otal Memory
(Bytes)

Program Memory
(Bytes)

Data Memory
(Bytes)

Control

Interrupt control

L2S2M2D2

Unified Memory
(Bytes)

’C6211/
C671 1

6200 Harvard (L1)

Unified (L2)

72K 4K (cache) 4K (cache) 64K (map/cache)

Table 4–2. TMS320C6211/C6711 Cache Architectures

Cache Space Size (Bytes) Associativity Line Size (Bytes)

L1P 4K Direct mapped 64
L1D 4K 2-way 32
L2 64K 1- to 4-way 128

4-2

Figure 4–2. TMS320C6211 Internal Memory Block Diagram

snoop address

Overview

Cache RAM

4K Bytes

Cache RAM

4K bytes

256

64

64

L1 program cache

controller

program data

program address

Program fetch

C62x CPU

Data path A Data path B

32 32 32 32

ST1 store data

DA1 address

L1 data cache

controller

LD1 load data

256

DA2 address

ST2 store data

address

LD2 load data

address
data
data

snoop address

256data

L2 cache
controller

128128

256

128

64
64

RAM

64K Bytes

EDMA

TMS320C6211/C6711 Two-Level Internal Memory

4-3

Overview

Figure 4–3. TMS320C6711 Internal Memory Block Diagram

snoop address

Cache RAM

4K bytes

Cache RAM

4K bytes

256

64

64

L1 program cache

controller

program data

program address

256

Program fetch

C67x CPU

Data path A Data path B

32 64 32 64

ST1 store data

DA1 address

LD1 load data

L1 data cache

controller

DA2 address

ST2 store data

address

LD2 load data

address
data
data

snoop address

256data

L2 cache
controller

128128

256

128

64
64

RAM

64K bytes

EDMA

4-4

4.2 Internal Memory Control Registers

The L1P, L1D, and L2 are controlled by a set of memory configuration regis­ters. The CPU can read and write to the internal memory control registers. The
EDMA (and thus the HPI) can only read these registers. Table 4–3 lists these
control registers and their associated addresses. You should initialize a
memory attribute register by setting the appropriate MAR bits, and then read
that memory attribute register before continuing execution to insure proper
operation.

Table 4–3. Internal Memory Control Register Addresses

Internal Memory Control Registers

Register Address
(byte)

0184 0000h CCFG Cache configuration register
0184 4000h

0184 4004h L2FWC L2 flush word count register
0184 4010h L2CBAR L2 clean base address register
0184 4014h L2CWC L2 clean word count register
0184 4020h L1PFBAR L1P flush base address register
0184 4024h L1PFWC L1P flush word count register
0184 4030h L1DFBAR L1D flush base address register
0184 4034h L1DFWC L1D flush word count register
0184 5000h L2FLUSH L2 flush register
0184 5004h L2CLEAN L2 clean register
0184 8200h MAR0 Memory attribute register – Region 0
0184 8204h MAR1 Memory attribute register – Region 1
0184 8208h MAR2 Memory attribute register – Region 2
0184 820Ch MAR3 Memory attribute register – Region 3
0184 8240h MAR4 Memory attribute register – Region 4
0184 8244h MAR5 Memory attribute register – Region 5
0184 8248h MAR6 Memory attribute register – Region 6
0184 824Ch MAR7 Memory attribute register – Region 7
0184 8280h MAR8 Memory attribute register – Region 8
0184 8284h MAR9 Memory attribute register – Region 9
0184 8288h MAR10 Memory attribute register – Region 10
0184 828Ch MAR11 Memory attribute register – Region 11
0184 82C0h MAR12 Memory attribute register – Region 12
0184 82C4h MAR13 Memory attribute register – Region 13
0184 82C8h MAR14 Memory attribute register – Region 14
0184 82CCh MAR15 Memory attribute register – Region 15

Register
Mnemonic

Register Name

L2FBAR L2 flush base address register

TMS320C6211/C6711 Two-Level Internal Memory

4-5

L1P Description

4.3 L1P Description

The L1P is organized as a 64 line direct mapped cache with a 64 byte (2 fetch
packet) line size. The L1P data request size is one line, thus the six least
significant bits of a requested address are ignored. The next six bits of the ad­dress are used to reference the set within the cache that the addressed data
maps to. The remaining bits of the address are used as a unique tag for the
requested data. Figure 4–4 illustrates how a 32 bit address is allocated to pro­vide the set index and tag data for the L1P.

Figure 4–4. L1P Address Allocation

31 12 11 6 5 0

Tag Set Offset

A cache hit returns data to the CPU in a single cycle. Unlike the
TMS320C6201, the L1P only operates as a cache and cannot be memory
mapped. The L1P does not support freeze or bypass modes. The only values
allowed for the program cache control (PCC) field in the CPU control and sta­tus register (CSR) are 000b and 010b. All other values for PCC are reserved,
as shown in Table 4–4.

Table 4–4. Level 1 Program Cache Mode Settings

Cache Mode PCC value Description

Cache enable 010b Direct mapped cache
Cache enable 000b Direct mapped cache

other Reserved

Any initial program fetch of an address causes a cache miss to occur. The data
is requested from the L2 and stored in the internal cache memory . Any subse­quent read from a cached address causes a cache hit and that data is loaded
from the L1P memory. Figure 4–5 illustrates the organization of a direct
mapped cache.

4-6

Figure 4–5. L1P Direct Mapped Cache Diagram

Tag Set Offset

L1P Description

Address

Tag RAM

Data out

=

Address

Cache data

Data out

L2

data

1 0

Program

data

There are two methods for user-controlled invalidation of data in the L1P . Writ­ing a 1 to the IP bit of the cache configuration register (CCFG) invalidates all
of the cache tags in the L1P tag RAM. This is a write-only bit, a read of this
bit will always return a 0. Any CPU access to the L1P while invalidation is being
processed stalls the CPU until the invalidation has completed and the CPU re­quest has been fetched. Figure 4–12 shows the format for the CCFG register.
Table 4–6 describes the operation of this register.

TMS320C6211/C6711 Two-Level Internal Memory

4-7

L1P Description

The second method for invalidating the L1P requires the L1PFBAR and
L1PFWC registers. This is useful for invalidating a block of data in the L1P.
Y ou must first write a word–aligned address into the L1PFBAR. This value is
the starting address for the invalidation. The number of words to be invali­dated will be equal to the value written into the L1PFWC register. The L1P
searches for and invalidates all lines whose external memory address falls
within the range from L1PFBAR to L1PFBAR+L1PFWC–4. If L1PFBAR or
L1PFWC are not aligned to the L1P line size (16 words), all lines which contain
any address in the specified range are invalidated. Using this block invalida­tion will not stall any pending CPU accesses. The block invalidation begins
when the L1PFWC is written, therefore you should take care to ensure that the
L1PFBAR register is set up correctly prior to writing the L1PFWC. Figure 4–6
and Figure 4–7 show the format for the L1PFBAR and L1PFWC.

Figure 4–6. L1P Flush Base Address Register Fields (L1PFBAR

31 0

L1P flush base address

RW,+x

Figure 4–7. L1P Flush Word Count Register Fields (L1PFWC

31 16 15 0

rsvd
R,+x RW,+x

L1P flush word count

)

)

4-8

4.4 L1D Description

The L1D is organized as a 64 set 2–way set associative cache with a 32 byte
line size. The two least significant bits of a requested address are ignored by
the L1D since the smallest access size is for a word. The next bit of the address
is used to address the correct word. Bits four and three select one of the four
8 byte sublines in the addressed set. The next six bits select the set within the
cache that the addressed data maps to. The remaining bits of the address are
used as a unique tag for the requested data. Figure 4–8 illustrates how a 32
bit address is allocated to provide the word index, subline index, set index and
tag data for the L1D.

Figure 4–8. L1D Address Allocation

31 11 10 5 4 3 2 1 0

Tag Set Subline Word Offset

A cache hit returns data to the CPU in a single cycle. Operation on a cache
miss depends on the direction of the access. On a read miss, the L1D sends
a read request to the L2 to fetch the data. When the data is returned from the
L2, the L1D analyzes the set that the addressed data maps to in each way.
The L1D controller stores the new data into the set that was least recently used
(LRU). If the data in that set has been modified but the corresponding address
has not be updated (the cache line is dirty), that data is written out to the L2.
In this way, cached data that has been modified will not be discarded before
it is updated in its original address. If two read misses occur in the same cycle,
they are serialized by the L1D so that only one request is presented to the L2
at a time. On a write miss, the L1D sends the write request to the L2. The data
is not stored in the L1D. Write requests from the L1D to the L2 are buffered.
If a write request is still pending from the L1D when a read miss occurs, this
buffer is allowed to empty before the read request is sent to the L2.

L1D Description

The L1D only operates as a cache and cannot be memory mapped. The L1D
does not support freeze or bypass modes. The only values allowed for the data
cache control (DCC) field in the CPU control and status register (CSR) are
000b and 010b. All other values for DCC are reserved, as shown in T able 4–5.

TMS320C6211/C6711 Two-Level Internal Memory

4-9

L1D Description

Table 4–5. Level 1 Data Cache Mode Settings

Cache Mode DCC value Description

Cache enable 000b 2-way cache
Cache enable 010b 2-way cache

Other Reserved

Any initial load of an address causes a cache miss to occur. The data is loaded
and stored in the internal cache memory . Any subsequent read from a cached
address will cause a cache hit and that data will be loaded from the internal
cache memory . Figure 4–9 illustrates the organization for a 2-way set associa­tive cache.

4-10

Figure 4–9. L1D 2–Way Set Associative Cache Diagram.

Way 1

L1D Description

Way 0

Address

Tag RAM

Data out

Address

Tag RAM

Address

Cache

data

Data out

=

Address

Cache

data

L2

Data

Data out

Tag Set OffsetWordSubline

Data out

=

TMS320C6211/C6711 Two-Level Internal Memory

0 1

1 0

256

64

32

Data

4-11

L1D Description

There are two methods for user-controlled invalidation of data in the L1D. Writ­ing a 1 to the ID bit of the cache configuration register (CCFG) invalidates all
the cache tags in the L1D tag RAM. This is a write-only bit, a read of this bit
returns a 0. Any CPU access to the L1D while invalidation is being processed
stalls until the invalidation has completed and the CPU request has been
fetched.

The second method for invalidating the L1D requires the L1DFBAR and
L1DFWC registers. This is useful for invalidating a block of data in the L1D.
You must first write a word-aligned address into the L1DFBAR. This value is
used as the starting address for the invalidation. The number of words invali­dated equals the value written into the L1DFWC register. The L1D searches
for and invalidate all lines whose external memory address falls within the
range from L1DFBAR to L1DFBAR+L1DFWC–4. The data in these lines is
sent to the L2 to be stored in the original memory location. In this way , the L2
and external memory will remain coherent with the data that is invalidated.
If L1DFBAR or L1DFWC are not aligned to the L1D line size (8 words) all lines
which contain data in the address range specified are invalidated. However
only those words that are contained in the range from L1DFBAR to
L1DFBAR+L1DFWC–4 will be saved to the L2. This block invalidation will oc­cur in the background and not stall any pending CPU accesses. The block in­validation begins when the L1DFWC is written, therefore you should take care
to ensure that the L1DFBAR register is set up correctly prior to writing the
L1DFWC. This is the preferred method for writing data that has been cached
in the L1D to the external memory space. Figure 4–10 and Figure 4–11 show
the format for the L1DFBAR and L1DFWC.

Figure 4–10. L1D Flush Base Address Register Fields (L1DFBAR)

31 0

L1D flush base address

RW,+x

Figure 4–11. L1D Flush Word Count Register Fields (L1DFWC)

31 16 15 0

L1D flush word count

4-12

rsvd
R,+x RW,+x

L2 Description

4.5 L2 Description

The L2 is accessible from both the L1P and the L1D. On a cache miss from
the L1P or L1D, the request is first sent to the L2 to be serviced. How the L2
services the request depends on the selected operation mode of the L2.
T able 4–6 shows the supported operation modes for the L2. Figure 4–13 illus­trates the division of the L2 memory space according to the L2 Mode.

Writing to the L2MODE field of the cache configuration register (CCFG) sets
the L2 mode. Figure 4–12 shows the format for the CCFG register . T able 4–6
describes the operation of this register.

Figure 4–12. Cache Configuration Register Fields (CCFG)

31 30 10 9 8 7 3 2 0

P

RW,+0 R,+x W,+0 W,+0 R,+0 0000 RW,+000

Table 4–6. Cache Configuration Register Field Description

Field Description

L2MODE L2 Operation Mode

rsvd IP ID rsvd L2MODE

L2MODE = 000b: 64K bytes SRAM
L2MODE = 001b: 16K bytes 1-way cache / 48 Kbytes mapped RAM
L2MODE = 010b: 32K bytes 2-way cache / 32 Kbytes mapped RAM
L2MODE = 011b: 48K bytes 3-way cache / 16 Kbytes mapped RAM
L2MODE = 111b: 64K bytes 4-way cache
L2MODE = other: Reserved

ID Invalidate L1D

ID = 0: Normal L1D operation
ID = 1: All L1D lines invalidated

IP Invalidate LIP

IP = 0: Normal L1P operation
IP = 1: All L1P lines invalidated

P L2 Requestor Priority

P = 0: CPU accesses prioritized over enhanced DMA accesses
P = 1: Enhanced DMA accesses prioritized over CPU accesses

TMS320C6211/C6711 Two-Level Internal Memory

4-13

L2 Description

The reset value of the L2MODE field is 000b, thus the L2 RAM is configured
as 64K bytes of mapped memory at reset to support bootloading. Any L2 RAM
that is configured as cache is no longer in the memory map. For example, in
L2 Mode 010b, the address space from 0000 8000h to 0000 FFFFh is no
longer mapped. The associativity of the L2 cache RAM is a function of the L2
Mode. Each 16K byte block of RAM included in the cache adds one way to
the associativity. The line size for the L2 cache is 128 bytes. Figure 4–13
shows the cache associativity for each L2 Mode.

Figure 4–13. L2 Memory Configuration

000 011010001

All SRAM

3/4 SRAM

1/2 SRAM2-way cache

3-way cache

111

1/4 SRAM

4-way cache

L2 memory

16K bytes

16K bytes

16K bytes

16K bytes

Block base addressL2 mode

0000 0000h

0000 4000h

0000 8000h

0000 C000h

4-14

1-way cache

4.5.1 L2 Interfaces

4.5.2 L2 Operation

L2 Description

The L2 Controller services requests from three different requestors – the L1P,
the L1D, and the Enhanced DMA. Since the L1P only sends read requests,
a single 256 bit wide data bus transfers data from the L2 to the L1P. The L1D
to L2 interface consists of a 128 bit read bus from the L2 to the L1D and a 128
bit write bus from the L1D to the L2. The L2 transfers data to and from the
EDMA through a 64 bit read and a 64 bit write bus.

Each L1D access to the L2 memories takes two cycles. Since the line size of
L1D cache is twice the width of the bus between the cache and the L2, a miss
to the L2 requires two accesses. Therefore, a miss from L1D to the L2 takes
four cycles to complete if the data is available in the L2. A miss from the L1P
to the L2 completes in five cycles.

The L2 memories are organized as four 64 bit wide banks. Two accesses can
be serviced at the same time if the two accesses do not use the same bank.
Since the L1P data bus is 256 bits wide, any L1P request that occurs at the
same time as an L1D or EDMA request will cause a bank collision and there­fore a stall. Concurrent accesses between the L1D and EDMA busses to differ­ent banks can be serviced without stalling.

The priority bit (P) in the Cache Configuration Register (CCFG) determines the
priority when a bank collision occurs between requestors. If the P bit is set to
0, CPU accesses (L1P and L1D) are given priority over an EDMA request.
Thus, any pending CPU request will complete before the EDMA request is ser­viced. If this bit is set to 1, EDMA requests are prioritized over CPU accesses.
When an L1P and L1D access collide, the L1P request is always given priority .

When an L2 location is operating as mapped RAM, an access to that location
operates like a standard RAM. A read request reads the value stored in that
location and a write request updates that location with the new data. When
an L2 location is enabled as a cache, the operation is similar to the L1D cache.
If a read request is made to the L2, the tag RAM for each of the cached blocks
is searched for that address. If a tag hit occurs, that data is sent to the request­or. If the data is not in the L2 the requestor is stalled and the data is requested
from the Enhanced DMA. T o fulfill an L1P request, the L2 controller must make
eight 64 bit requests to the EDMA. Similarly, four requests to the EDMA are
required to service an L1D request.

TMS320C6211/C6711 Two-Level Internal Memory

4-15

L2 Description

The L2 uses a least recently used (LRU) replacement strategy to replace old
cached data with new data. To determine which cache lines to replace, the
address for the new data is used to calculate the set which that address maps
to. Each external address maps to one set in each cache way . Then, that set
in each way is interrogated to determine which way contains the least recently
used (LRU) data. The new data is stored at that location. If the cache location
to be replaced contains valid data, the previous data is evicted. An eviction
occurs as follows. The L2 first polls the L1D to determine if the evicted address
is also cached in the L1D. This is referred to as snooping the L1D. If data is
returned from the L1D, it is written out to the EDMA. Then, both the L1D and
L2 lines are invalidated. If the L1D does not cache the evicted address, the
data in the L2 to written out to the EDMA. In this case, only the L2 line is
invalidated. Finally, the requested data is stored in the L2 and sent to the re­questor. This mechanism ensures that the CPU does not access stale data
and that no data is lost. Figure 4–14 diagrams the decision process used by
the L2 controller to service a data request from the CPU when the L2 is operat­ing as a cache. The L2 performs evictions for read and write requests.

4-16

Figure 4–14. L2 Cache Data Request Flow Chart

L2 Description

CPU requests

data

Write replaced

data from L1D

to EDMA

Invalidate

L1D line

Yes

Fetch data

from EDMA

Determine LRU

location

Is valid

data in LRU

location?

Yes

Is replaced

data in L1D?

No

Write replaced

data from L2

to EDMA

Is data in L2?

No

YesNo

Fetch data

from L2

Invalidate

L2 line

Store data to L2 Send data to CPU

Done

TMS320C6211/C6711 Two-Level Internal Memory

4-17

L2 Description

The memory attribute registers (MARs) can be programmed to turn on caching
of each of the external chip enable (CE) spaces. In this way , you can perform
single word reads to external mapped devices. Without this feature any
external read would always read an entire L2 line of data. Each of the four CE
spaces is divided into four ranges, each of which maps the least significant bit
of an MAR register. If an MAR register is set, the corresponding address range
is cached by the L2. At reset, the MAR registers are set to 0. T o begin caching
data in the L2, you must initialize the appropriate MAR register to 1. The MAR
registers define cacheability for the EMIF only. Addresses accessed by the
EMIF which are not defined by the MAR registers are always cacheable.
Figure 4–15 shows the format for the MARs. Table 4–3 illustrates which ad­dress range each MAR bit enables for caching.

Figure 4–15. L2 CE Space Allocation Register Fields

MAR0

31 10

rsvd

R,+x RW,+0

MAR1

31 10

rsvd

R,+x RW,+0

MAR2

31 10

rsvd

R,+x RW,+0

MAR3

31 10

rsvd

R,+x RW,+0

CE 0.0

CE 0.1

CE 0.2

CE 0.3

MAR4

31 10

rsvd

R,+x RW,+0

MAR5

31 10

rsvd

R,+x RW,+0

4-18

CE 1.0

CE 1.1

L2 Description

Figure 4–15.L2 CE Space Allocation Register Fields (Continued)

MAR6

31 10

rsvd

R,+x RW,+0

MAR7

31 10

rsvd

R,+x RW,+0

MAR8

31 10

rsvd

R,+x RW,+0

MAR9

31 10

rsvd

R,+x RW,+0

CE 1.2

CE 1.3

CE 2.0

CE 2.1

MAR10

31 10

rsvd

R,+x RW,+0

MAR1 1

31 10

rsvd

R,+x RW,+0

MAR12

31 10

rsvd

R,+x RW,+0

MAR12

31 10

rsvd

R,+x RW,+0

CE 2.2

CE 2.3

CE 3.0

CE 3.1

TMS320C6211/C6711 Two-Level Internal Memory

4-19

L2 Description

Figure 4–15.L2 CE Space Allocation Register Fields (Continued)

MAR14

31 10

rsvd

R,+x RW,+0

MAR15

31 10

rsvd

R,+x RW,+0

CE 3.2

CE 3.3

Table 4–7. Memory Attribute Register Functions

MAR Address Range Enabled CE Space

15 B300 0000h – B3FF FFFFh CE3
14 B200 0000h – B2FF FFFFh CE3
13 B100 0000h – B1FF FFFFh CE3
12 B000 0000h – B0FF FFFFh CE3
1 1 A300 0000h – A3FF FFFFh CE2
10 A200 0000h – A2FF FFFFh CE2

9 A100 0000h – A1FF FFFFh CE2
8 A000 0000h – A0FF FFFFh CE2
7 9300 0000h – 93FF FFFFh CE1
6 9200 0000h – 92FF FFFFh CE1
5 9100 0000h – 91FF FFFFh CE1
4 9000 0000h – 90FF FFFFh CE1
3 8300 0000h – 83FF FFFFh CE0
2 8200 0000h – 82FF FFFFh CE0
1 8100 0000h – 81FF FFFFh CE0
0 8000 0000h – 80FF FFFFh CE0

4-20

4.5.3 L2 EDMA Service

EDMA accesses are only allowed to L2 space that is configured as mapped
RAM. When the EDMA makes a read request to the L2, the L2 snoops the data
from the L1D and stalls the EDMA until a response is returned. If data that
must be updated is returned, that data is placed in the L2 and the EDMA re­quest proceeds. In this case, the L1D line is invalidated to maintain coherency .
If the L1D does not return data to the L2 then the data is read from the L2. The
L2 does not snoop the L1P for data when a EDMA read request is received
because the CPU cannot modify data in L1P so it’s data will not be incoherent.

When the EDMA makes a write request to the L2, both the L1P and the L1D
are snooped for the data. Both the L1P and the L1D must be notified of the
write because the L2 has no knowledge of the type of data being written by the
EDMA, whether program or data. If the L1P responds that it is caching the ad­dressed data, then that line is invalidated and the data is written into L2. Simi­larly , if the L1D is caching that address, then that line in the L1D is invalidated
and the data is written to L2. By invalidating the lines in the L1P or the L1D,
the correct data will be fetched from the L2 on the next CPU request of that
data.

L2 Description

4.5.4 L2 Invalidation

The method for user controlled invalidation of data in the L2 is similar to those
for the L1P and the L1D. For the L2, however, there are two types of invalida­tion. The first type of invalidation is an L2 flush. During a flush, the contents
of the L2 are copied out through the enhanced DMA. Like an EDMA read or
L2 data eviction, the L1D is snooped for any modified (dirty) data that is being
copied out by the flush. The second type of L2 invalidation is a clean. The
clean operation copies data from the L2 through the EDMA to the external
memory space and snoops data from the L1D. In addition, the clean operation
invalidates any line in the L1P , L1D, or L2 that caches data that is copied to the
external memory space.

To initiate an L2 flush of the entire L2 cache space, write a 1 to the F bit of the
L2FLUSH register. This bit remains set to 1 until the flush is complete at which
time the register is cleared to 0 by the L2 controller. Figure 4–16 shows the
fields of the L2FLUSH register. Table 4–8 describes the operation of the
L2FLUSH register. Similarly, to initiate an L2 clean of the entire L2 cache
space set the C bit of the L2CLEAN register to 1. This bit remains set to 1 until
the clean is complete at which time the register is cleared to 0. Figure 4–17
shows the fields of the L2CLEAN register. Table 4–9 describes the operation
of the L2CLEAN register.

TMS320C6211/C6711 Two-Level Internal Memory

4-21

L2 Description

Figure 4–16. L2 Flush Register Fields (L2FLUSH)

31 10

rsvd

R,+x RW,+0

F

Table 4–8. L2 Flush Register Fields Description

Field Description

F

Flush L2
F = 0: Normal L2 operation

F = 1: All L2 lines flushed

Figure 4–17. L2 Clean Register Fields (L2CLEAN)

31 10

rsvd

R,+x RW,+0

C

Table 4–9. L2 Clean Register Fields Description

Field Description

C

Clean L2
C = 0: Normal L2 operation

C = 1: All L2 lines cleaned

It is also possible to flush and clean a range of addresses from the L2. T o flush
a range of address from the L2, write the word–aligned address for the start
of the flush into the L2FBAR. The number of words to be flushed is equal to
the value written into the L2FWC register. The L2 controller then searches all
L2 cache blocks for all lines whose external memory address falls within the
range from L2FBAR to L2FBAR+L2FWC–4 and copies that data through the
EDMA to the external memory space. The L1D is snooped to ensure that the
correct data is stored in the original memory location. The L2 flush occurs in
the background and does not stall any pending CPU accesses. The flush be­gins when the L2FWC is written, therefore you should take care to ensure that
the L2FBAR register is set up correctly prior to writing the L2FWC. Figure 4–18
shows the fields in the L2FBAR register. Figure 4–19 shows the fields in the
L2FWC register.

Figure 4–18. L2 Flush Base Address Register Fields (L2FBAR)

31 0

L2 Flush Base Address

RW,+x

4-22

Figure 4–19. L2 Flush Word Count Register Fields (L2FWC)

31 16 15 0

rsvd

R,+x R,+x

To clean a range of address from the L2, write the word-aligned address for
the start of the clean into the L2CBAR. The number of words to clean is equal
to the value written into the L2CWC register. The L2 controller then searches
all L2 cache blocks for all lines whose external memory address falls within the
range from L2CBAR to L2CBAR+L2CWC–4 and copies that data through the
EDMA to external memory space. The L1D is snooped to ensure that the
correct data is stored in the original memory location. In addition to snooping
data from the L1D, any L1P or L1D lines that cache a cleaned address are
invalidated. The L2 clean occurs in the background and does not stall any
pending CPU accesses. The clean begins when the L2CWC is written,
therefore you should take care to ensure that the L2CBAR register is set up
correctly prior to writing the L2CWC. If L2CBAR or L2CWC are not aligned to
the L2 line size (32 words), all lines which contain the words specified are inval­idated. However only those words that are contained in the range from
L2CBAR to L2CBAR + L2CWC–4 are saved to the external memory space.
Figure 4–20 shows the fields in the L2CBAR register. Figure 4–21 shows the
fields in the L2CWC register.

L2 Flush Word Count

L2 Description

Figure 4–20. L2 Clean Base Address Register Fields (L2CBAR)

31 0

L2 Clean Base Address

RW,+x

Figure 4–21. L2 Clean Word Count Register Fields (L2CWC)

31 16 15 0

rsvd

R,+x R,+x

If more than one block invalidation, block flush, or block clean is requested at
one time, the CPU is stalled until all are completed. For example, if an L1P
invalidate is being processed and you set up an L2 clean by writing to the
L2CWC register, the CPU is stalled until both the L1P invalidate and L2 clean
are complete.

TMS320C6211/C6711 Two-Level Internal Memory

L2 Clean Word Count

4-23

Chapter 5

Direct Memory Access (DMA) Controller

This chapter describes the direct memory access channels and registers
available for the TMS320C6201/C6202/C6701 devices.

Topic Page

5.1 Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 DMA Registers 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Memory Map 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Initiating a Block Transfer 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Transfer Counting 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Synchronization: Triggering DMA Transfers 5-17. . . . . . . . . . . . . . . . . . . .

5.7 Address Generation 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Split-Channel Operation 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Resource Arbitration and Priority Configuration 5-30. . . . . . . . . . . . . . . .

5.10 DMA Channel Condition Determination 5-33. . . . . . . . . . . . . . . . . . . . . . . .

5.11 DMA Controller Structure 5-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 DMA Action Complete Pins 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 Emulation 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

Overview

5.1 Overview

The direct memory access (DMA) controller transfers data between regions
in the memory map without intervention by the CPU. The DMA controller al­lows movement of data to and from internal memory, internal peripherals, or
external devices to occur in the background of CPU operation. The DMA con­troller has four independent programmable channels, allowing four different
contexts for DMA operation. In addition, a fifth (auxiliary) channel allows the
DMA controller to service requests from the host port interface (HPI). In dis­cussing DMA operations, several terms are important:

- Read transfer: The DMA controller reads a data element from a source

location in memory.

- Write transfer: The DMA controller writes the data element that was read

during a read transfer to its destination in memory.

- Element transfer: This form refers to the combined read and write transfer

for a single data element.

- Frame transfer: Each DMA channel has an independently programmable

number of elements per frame. In completing a frame transfer, the DMA
controller moves all elements in a single frame.

- Block transfer: Each DMA channel also has an independently program-

mable number of frames per block. In completing a block transfer, the
DMA controller moves all frames that it has been programmed to move.

- Transmit element transfer: In split mode, data elements are read from the

source address, and writing it to the split destination address. See section

5.8 for details.

- Receive element transfer: In split mode, data elements are read from the

split source address, and writing it to the destination address. See section

5.8 for details.

The DMA controller has the following features:

- Background operation: The DMA controller operates independently of the

CPU.

- High throughput: Elements can be transferred at the CPU clock rate. See

section 5.11,

- Four channels: The DMA controller can keep track of the contexts of four

Structure

independent block transfers. See section 5.2,

, on page 5-35 for more information.

DMA Registers

, on page
5-5 for more information about saving the contents of multiple block
transfers.

5-2

Overview

- Auxiliary channel: This channel allows the host port to make requests into

the CPU’s memory space. The auxiliary channel requests may be priori ­tized relative to other channels and the CPU.

- Split-channel operation: A single channel can be used to perform both the

receive and transmit element transfers from or to a peripheral simulta­neously , effectively acting like two DMA channels. See section 5.8 on page
5-28 for more information.

- Multiframe transfer: Each block transfer can consist of multiple frames of

a programmable size. See Section 5.5,

- Programmable priority: Each channel has independently programmable

Transfer Counting

.

priorities versus the CPU.

- Programmable address generation: Each channel’s source and destination

address registers can have configurable indexes for each rea d a n d w r i t e
transfer. The address can remain constant, increment, decrement, or be
adjusted by a programmable value. The programmable value allows an in­dex for the last transfer in a frame distinct from that used for the preceding
transfers. See section 5.7.1 on page 5-22 for more information.

- Full 32-bit address range: The DMA controller can access any region in

the memory map:

J On-chip data memory
J On-chip program memory when it is mapped into memory space

rather than being used as cache

J On-chip peripherals
J External memory via the EMIF
J Expansion memory via the expansion bus

- Programmable width transfers: Each channel can be independently con-

figured to transfer either bytes, 16-bit halfwords, or 32-bit words. See sec­tion 5.7.3 on page 5-23 for more information.

- Autoinitialization: Once a block transfer is complete, a DMA channel can

automatically reinitialize itself for the next block transfer. See section 5.4.1
on page 5-13 for more information.

- Event synchronization: Each read, write, or frame transfer may be initiated

by selected events. See Section 5.6 on page 5-17 for more information.

- Interrupt generation: On completion of each frame transfer or block transfer,

as well as on various error conditions, each DMA channel can send an inter­rupt to the CPU. See section 5.10 on page 5-33 for more information.

Direct Memory Access (DMA) Controller

5-3

Overview

Figure 5–1 shows the ’C6000 block diagram with the DMA-related compo­nents shaded.

Figure 5–1. DMA Controller Interconnect to TMS320C6201/C6202/C6701

Memory-Mapped Modules

Timers

Interrupt selector

McBSPs

HPI control
DMA control
EMIF control

Host port/

Expansion bus

PLL

Power

down

Boot

configuration

EMIF

Peripheral

bus

controller

DMA

controller

Data memory

Data memory

controller

CPU core

Program fetch

Instruction dispatch

Instruction decode

Data path

1

Program memory controller

Program memory/cache

Data path

2

5-4

5.2 DMA Registers

DMA Registers

The DMA registers configure the operation of the DMA controller. Table 5–1
and Table 5–2 show how the DMA control registers are mapped in memory.
These registers include the DMA global data, count reload, index, and address
registers, as well as independent control registers for each channel.

Direct Memory Access (DMA) Controller

5-5

DMA Registers

Table 5–1. DMA Control Registers by Address

Hex Byte
Address

0184 0000 DMA channel 0 primary control 5.2.1
0184 0004 DMA channel 2 primary control 5.2.1
0184 0008 DMA channel 0 secondary control 5.10
0184 000C DMA channel 2 secondary control 5.10
0184 0010 DMA channel 0 source address 5.7
0184 0014 DMA channel 2 source address 5.7
0184 0018 DMA channel 0 destination address 5.7
0184 001C DMA channel 2 destination address 5.7
0184 0020 DMA channel 0 transfer counter 5.5
0184 0024 DMA channel 2 transfer counter 5.5
0184 0028 DMA global count reload register A 5.5
0184 002C DMA global count reload register B 5.5
0184 0030 DMA global index register A 5.7.2
0184 0034 DMA global index register B 5.7.2
0184 0038 DMA global address register A 5.8
0184 003C DMA global address register B 5.8

Name

Described
in Section

5-6

0184 0040 DMA channel 1 primary control 5.2.1
0184 0044 DMA channel 3 primary control 5.2.1
0184 0048 DMA channel 1 secondary control 5.10
0184 004C DMA channel 3 secondary control 5.10
0184 0050 DMA channel 1 source address 5.7
0184 0054 DMA channel 3 source address 5.7
0184 0058 DMA channel 1 destination address 5.7
0184 005C DMA channel 3 destination address 5.7
0184 0060 DMA channel 1 transfer counter 5.5
0184 0064 DMA channel 3 transfer counter 5.5
0184 0068 DMA global address register C 5.8
0184 006C DMA global address register D 5.8
0184 0070

DMA auxiliary control register 5.9.1

Table 5–2. DMA Control Registers by Register Name

DMA Registers

Hex Byte

Name

DMA auxiliary control register 0184 0070 5.9.1
DMA channel 0 destination address 0184 0018 5.7
DMA channel 0 primary control 0184 0000 5.2.1
DMA channel 0 secondary control 0184 0008 5.10
DMA channel 0 source address 0184 0010 5.7
DMA channel 0 transfer counter 0184 0020 5.5
DMA channel 1 destination address 0184 0058 5.7
DMA channel 1 primary control 0184 0040 5.2.1
DMA channel 1 secondary control 0184 0048 5.10
DMA channel 1 source address 0184 0050 5.7
DMA channel 1 transfer counter 0184 0060 5.5
DMA channel 2 destination address 0184 001C 5.7
DMA channel 2 primary control 0184 0004 5.2.1
DMA channel 2 secondary control 0184 000C 5.10
DMA channel 2 source address 01840014 5.7
DMA channel 2 transfer counter 0184 0024 5.5

Address

Described
in Section

DMA channel 3 destination address 0184 005C 5.7
DMA channel 3 primary control 0184 0044 5.2.1
DMA channel 3 secondary control 0184 004C 5.10
DMA channel 3 source address 0184 0054 5.7
DMA channel 3 transfer counter 0184 0064 5.5
DMA global address register A 0184 0038 5.8
DMA global address register B 0184 003C 5.8
DMA global address register C 0184 0068 5.8
DMA global address register D 0184 006C 5.8
DMA global count reload register A 0184 0028 5.5
DMA global count reload register B 0184 002C 5.5
DMA global index register A 0184 0030 5.7.2
DMA global index register B

0184 0034 5.7.2

Direct Memory Access (DMA) Controller

5-7

DMA Registers

5.2.1 DMA Channel Control Registers

The DMA channel primary and secondary control registers (Figure 5–2 and
Figure 5–3) contain-fields that control each DMA channel independently . These
fields are summarized in Table 5–3 and T able 5–4.

Figure 5–2. DMA Channel Primary Control Register

31 30 29 28 27 26 25 24 23 19 18 16

DST RELOAD

RW, +0 RW, +0 RW,+0 RW,+0 RW, +0 RW, +0 RW, +0 RW , +0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSYNC

RW, +0 RW, +0 RW, +0 RW, +0 RW, +0 RW, +0 RW, +0 R, +0 RW, +0

SRC RELOAD EMOD FS TCINT PRI WSYNC RSYNC

CNT

INDEX

RELOAD

SPLIT ESIZE DST DIR SRC DIR STATUS START

Table 5–3. DMA Channel Primary Control Register Field Descriptions

Field Description Section

DST RELOAD,
SRC RELOAD

Source/destination address reload for autoinitialization
SRC/DST RELOAD = 00b: do not reload during autoinitialization

SRC/DST RELOAD = 01b: use DMA global address register B as reload
SRC/DST RELOAD = 10b: use DMA global address register C as reload
SRC/DST RELOAD = 11b: use DMA global address register D as reload

5.4.1.1

EMOD

FS

TCINT

PRI

WSYNC,
RSYNC

5-8

Emulation mode
EMOD = 0: DMA channel keeps running during an emulation halt

EMOD = 1: DMA channel pauses during an emulation halt
Frame synchronization

FS = 0: disable
FS = 1: RSYNC event used to synchronize entire frame

Transfer controller interrupt
TCINT = 0: interrupt disabled

TCINT = 1: interrupt enabled
Priority mode: DMA versus CPU

PRI = 0: CPU priority
PRI = 1: DMA priority

Read transfer/write transfer synchronization
(R/W)SYNC = 00000b: no synchronization

(R/W)SYNC = other: sets synchronization event

5.13

5.6

5.10

5.9

5.6

DMA Registers

Table 5–3. DMA Channel Primary Control Register Field Descriptions (Continued)

Field SectionDescription

INDEX

Selects the DMA global data register to use as a programmable index
INDEX = 0: use DMA global index register A

INDEX = 1: use DMA global index register B

5.7.2

CNT RELOAD

SPLIT

ESIZE

DST DIR,
SRC DIR

STATUS

Transfer counter reload for autoinitialization and multiframe transfers
CNT RELOAD = 0: reload with DMA global count reload register A

CNT RELOAD = 1: reload with DMA global count reload register B
Split channel mode

SPLIT = 00b: split-channel mode disabled
SPLIT = 01b: split-channel mode enabled; use DMA global address register A as

split address

SPLIT = 10b: split-channel mode enabled; use DMA global address register B as

split address

SPLIT = 1 1b: split-channel mode enabled; use DMA global address register C as

split address

Element size
ESIZE = 00b: 32-bit

ESIZE = 01b: 16-bit
ESIZE = 10b: 8-bit
ESIZE = 11b: reserved

Source/destination address modification after element transfers
SRC/DST DIR = 00b: no modification

SRC/DST DIR = 01b: increment by element size in bytes
SRC/DST DIR = 10b: decrement by element size in bytes
SRC/DST DIR = 11b: adjust using DMA global index register selected by INDEX

ST ATUS = 00b: stopped
ST ATUS = 01b: running without autoinitialization
ST ATUS = 10b: paused
ST ATUS = 11b: running with autoinitialization

5.4.1.1

5.8

5.7.3

5.7.1,

5.7.2

5.4

STAR T

ST ART = 00b: stop
ST ART = 01b: start without autoinitialization
ST ART = 10b: pause
ST AR T = 11b: start with autoinitialization

Direct Memory Access (DMA) Controller

5.4

5-9

DMA Registers

Figure 5–3. DMA Channel Secondary Control Register

31 19 18 16

Reserved

R, +0000 0000 0000 0 RW, +000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WSYNC

RSYNC

RSYNC

WSYNC

STAT

CLR

RW,+0RW,+0RW,+0RW,

CLR

STAT

+0

WDROPIEWDROP

RW,

+0

RDROPIERDROP

COND

RW,+0RW,+0RW,+0RW,+1RW,+0RW,+0RW,+0RW,+0RW,+0RW,+0RW,

COND

BLOCKIEBLOCK

COND

LASTIELAST

COND

FRAMEIEFRAME

DMAC EN

CONDSXIESXCOND

Table 5–4. DMA Channel Secondary Control Register Field Descriptions

Field Description Section

+0

SX COND
FRAME COND
LAST COND
BLOCK COND

DMA condition. Each bit indicates a separate condition.
A0 value indicates that the condition is not detected.

A1 value indicates that the condition is detected.

RDROP COND
WDROP COND

SX IE
FRAME IE
LAST IE
BLOCK IE

DMA condition interrupt enable
IE = 0: associated condition does not enable DMA channel interrupt

IE = 1: associated condition enables DMA channel interrupt

RDROP IE
WDROP IE

RSYNC STAT
WSYNC STAT

Read or write synchronization status
ST AT = 0: synchronization is not received

STAT = 1: synchronization is received

DMAC EN DMAC pin control

DMAC EN = 000b: DMAC pin is held low.
DMAC EN = 001b: DMAC pin is held high.
DMAC EN = 010b: DMAC reflects RSYNC STAT.
DMAC EN = 011b: DMAC reflects WSYNC STAT.
DMAC EN = 100b: DMAC reflects FRAME COND.
DMAC EN = 101b: DMAC reflects BLOCK COND.
DMAC EN = other: reserved

5.10

5.10.1

5.6.1

5.12

RSYNC CLR
WSYNC CLR

5-10

Read or write synchronization status clear

5.6.1

Read as 0 write 1 to clear associated status

DMA Registers

The DMA channel secondary control register of the ‘C6202 has been expand­ed to include three new fields: WSPOL, RSPOL, and FSIG. This field is used
to add control to a frame-synchronized data transfer. The ‘C6202 secondary
control register is shown in Figure 5–4; the new field is shown in gray.
Table 5–5 describes the possible configurations of the new field.

Figure 5–4. TMS320C6202 Secondary Control Register

31 22 21 20 19 18 16

Reserved

R, +0 RW, +0 RW, +0 RW, +0 RW, +000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WSYNC

WSYNC

CLR

RW, +0 RW, +0 RW, +0 RW, +0 RW , +0 RW, +0 RW, +0 RW, +0 RW, +1 RW, +0 RW,+0 RW,+0 RW, +0 RW, +0 RW,+0 RW,+0

STAT

RSYNC

CLR

RSYNC

STAT

WDROPIEWDROP

COND

RDROPIERDROP

COND

WSPOL RSPOL FSIG DMAC

BLOCKIEBLOCK

COND

LASTIELAST

COND

FRAMEIEFRAME

CONDSXIESXCOND

Table 5–5. Synchronization Configuration Options

Field Description Section

WSPOL/
RSPOL

Synchronization event polarity .

Selects the polarity of an external sync event:
1 = active low, 0 = active high
This field is valid only if EXT_INTx is selected.

5.6.3

FSIG Frame sync ignore.

Setting FSIG = 1 causes the DMA channel to
ignore any event transitions during a current
burst. Synchronization is level triggered instead
of edge triggered.

Direct Memory Access (DMA) Controller

5.6.3

5-11

Memory Map

5.3 Memory Map

The DMA controller assumes the device memory map shown in Chapter 10,

Configuration, Reset, and Memory Maps

. Requests are sent to one of five re -

Boot

sources:

- Expansion bus

- External memory interface

- Internal program memory

- Internal peripheral bus

- Internal data memory

The source address is assumed to point to one of these four spaces throughout
a block transfer. This constraint also applies to the destination address.

5-12