Texas instruments TMS320C6672 Data Manual

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

Data Manual

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

Literature Number: SPRS708

November 2010

TMS320C6672

Data Manual

SPRS708—November 2010

Release History

Release Date Chapter/Topic Description/Comments

1.0 November 2010 All Initial Release

www.ti.com

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 KeyStone Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2 DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.5 Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.5.3 PLL Boot Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.9 Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.3.2 Device Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.3.11 NMI Even Generation to CorePac (NMIGRx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

3.3.12 IPC Generation (IPCGRx) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4 System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.1 Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.2 Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.3 Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5 C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.1.4 MSMC SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

5.5 C66x CorePac Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

5.6 C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.7 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

6.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7 TMS320C6672 Peripheral Information and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.1.2 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.3.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.3.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.4 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.4.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.4.2 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.4.3 EDMA3 Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

7.5.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

7.5.2 INTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

7.5.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.5.4 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.6 MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.6.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.6.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.7 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

7.7.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

7.7.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

7.7.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

7.7.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.7.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.7.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.7.7 Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.8 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.8.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.8.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.8.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.9 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.9.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.9.2 DDR3 PLL Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

7.9.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

7.10 PASS PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

7.10.1 PASS PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

7.10.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

7.11 DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

7.11.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.12 I

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.12.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.12.2 I

7.12.3 I

C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

www.ti.com

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.17 TSIP Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.18 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.19 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.20 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.21 Ethernet MAC (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

7.22 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.23 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.23.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.23.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.24 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

7.25 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.25.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.25.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.26 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.27 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.27.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.27.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.27.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

8 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

8.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

8.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

8.3 Package CYP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

SPRS708—November 2010

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

List of Figures

Figure 1-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 2-1 TMS320C6672 DSP Core Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 2-2 Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 2-3 Sleep / EMIF16 Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 2-4 Ethernet (SGMII) Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 2-5 Serial Rapid I/O Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-6 PCI Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-7 I Figure 2-8 I

Figure 2-9 SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 2-10 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-11 CYP 841-Pin BGA Package Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 3-1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 3-2 Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 3-3 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 3-6 Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 3-8 Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 3-9 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 3-10 NMI Generation Register (NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 3-11 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 3-12 IPC Acknowledgement Registers (IPCARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 3-13 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 3-14 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 3-15 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 3-16 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 3-17 Reset Mux Register RSTMUXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 4-1 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 5-1 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 5-2 TMS320C6672 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 5-3 TMS320C6672 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 5-4 TMS320C6672 L2 Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 7-1 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 7-4 Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 7-5 POR Figure 7-6 POR Figure 7-7 RESETFULL Figure 7-8 RESETFULL

Figure 7-9 SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Figure 7-10 SmartReflex I Figure 7-11 SmartReflex I

Figure 7-12 TMS320C6672 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Figure 7-13 NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 7-14 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 7-15 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 7-16 Programmable Range n End Address Register (PROGn_MPEAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

Figure 7-17 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

C Interface Receive Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

C Interface Transmit Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Figure 7-18 Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-19 Full-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-20 Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-21 Soft-Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-22 Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-23 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-24 PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Figure 7-25 PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Figure 7-26 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Figure 7-27 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Figure 7-28 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Figure 7-29 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Figure 7-30 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 7-31 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-32 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-33 Main PLL Control Register (MAINPLLCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Figure 7-34 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Figure 7-35 PLL Transition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

Figure 7-36 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Figure 7-37 DDR3 PLL Control Register (DDR3PLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Figure 7-38 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

Figure 7-39 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Figure 7-40 PASS PLL Control Register (PASSPLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Figure 7-41 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Figure 7-42 I Figure 7-43 I Figure 7-44 I

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Figure 7-45 SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

Figure 7-46 SPI Additional Timings for 4 Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

Figure 7-47 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

Figure 7-48 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

Figure 7-49 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

Figure 7-50 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Figure 7-51 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Figure 7-52 UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Figure 7-53 UART RTS (Request-to-Send Output) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Figure 7-54 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Figure 7-55 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Figure 7-56 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Figure 7-57 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Figure 7-58 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

Figure 7-59 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

Figure 7-60 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Figure 7-61 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Figure 7-62 HS-RTDX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Figure 8-1 CYP (S–PBGA–N841) Pb-Free Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

SPRS708—November 2010

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

List of Tables

Table 2-1 Characteristics of the TMS320C6672 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 2-2 Memory Map Summary for TMS320C6672. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 2-3 Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 2-4 Sleep / EMIF16 Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 2-5 Ethernet (SGMII) Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 2-6 Serial Rapid I/O Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 2-7 PCI Device Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 2-8 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 2-9 I Table 2-10 I

Table 2-11 SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 2-12 HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 2-13 C66x DSP System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 2-14 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 2-15 Terminal Functions — Signals and Control by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-16 Terminal Functions — Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 2-17 Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 2-18 Terminal Functions

Table 3-1 TMS320C6672 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 3-3 Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 3-4 Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 3-5 JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 3-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 3-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 3-8 Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 3-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 3-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 3-11 Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 3-12 NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 3-13 IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 3-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 3-15 IPC Generation Registers (IPCGRH) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-16 IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-17 Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 3-18 Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 3-19 Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 4-1 DSP/2 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 4-2 DSP/3 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 4-3 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 5-1 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 5-2 C66x CorePac Reset (Global or Local). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 5-3 CorePac Revision ID Register (MM_REVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 5-4 CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 6-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 6-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 7-1 Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 7-2 Power Supply Rails on TMS320C6672 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 7-3 POR

C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

— By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 7-4 POR-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Table 7-5 RESETFULL Table 7-6 RESETFULL

-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 7-7 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 7-8 SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Table 7-9 SmartReflex I Table 7-10 SmartReflex I

C Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

C Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 7-11 EDMA3 Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 7-12 TPCC0 Events for C6672 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 7-13 TPCC1 Events for C6672 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 7-14 TPCC3 Events for C6672 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 7-15 EDMA3 Channel Controller 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Table 7-16 EDMA3 Channel Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Table 7-17 EDMA3 Channel Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-18 EDMA3 Channel Controller 0 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-19 EDMA3 Channel Controller 1 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-20 EDMA3 Channel Controller 2 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-21 EDMA3 TPCC0 Transfer Controller 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-22 EDMA3 TPCC0 Transfer Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 7-23 EDMA3 TPCC 1 Transfer Controller 0 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Table 7-24 EDMA3 TPCC1 Transfer Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Table 7-25 EDMA3 TPCC1 Transfer Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Table 7-26 EDMA3 TPCC1 Transfer Controller 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 7-27 EDMA3 TPCC2 Transfer Controller 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Table 7-28 EDMA3 TPCC2 Transfer Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Table 7-29 EDMA3 TPCC2 Transfer Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Table 7-30 EDMA3 TPCC2 Transfer Controller 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table 7-31 TMS320C6672 System Event Mapping — C66x CorePac Primary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Table 7-32 INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 7-33 INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-34 INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Table 7-35 INTC0/INTC1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Table 7-36 INTC2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Table 7-37 INTC3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-38 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-39 NMI and Local Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Table 7-40 MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-41 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-42 Device Master Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-43 MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-44 MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Table 7-45 MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-46 MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-47 Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-48 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU0). . . . . . . . . . . . . . . . . . . . . . . .192

Table 7-49 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .193

Table 7-50 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU2) . . . . . . . . . . . . . . . . . . . . . . . .193

Table 7-51 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU3). . . . . . . . . . . . . . . . . . . . . . . .194

Table 7-52 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU0). . . . . . . . . . . . . . . . . . .

Table 7-53 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-54 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU2). . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-55 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU3) . . . . . . . . . . . . . . . . . . . . . . . .196

Table 7-56 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions. . . . . . . . . . . .197

Table 7-57 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .199

SPRS708—November 2010

. . . . . .194

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 7-58 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Table 7-59 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

Table 7-60 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Table 7-61 Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-62 Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Table 7-63 PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Table 7-64 PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Table 7-65 PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Table 7-66 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Table 7-67 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Table 7-68 SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Table 7-69 Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Table 7-70 Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Table 7-71 Reset Configuration Register (RSTCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Table 7-72 Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Table 7-73 Main PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Table 7-74 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Table 7-75 DDR3 PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Table 7-76 DDR3 PLL DDRREFCLK(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

Table 7-77 PASS PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Table 7-78 PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Table 7-79 I Table 7-80 I Table 7-81 I

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

Table 7-82 SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Table 7-83 SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Table 7-84 HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

Table 7-85 HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

Table 7-86 UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Table 7-87 UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Table 7-88 MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Table 7-89 MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Table 7-90 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Table 7-91 MDIO Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Table 7-92 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

Table 7-93 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

Table 7-94 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

Table 7-95 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

Table 7-96 Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

Table 7-97 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Table 7-98 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Table 7-99 HS-RTDX Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Table 8-1 Thermal Resistance Characteristics (PBGA Package) [CMH/GMH] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

www.ti.com

1Features

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

• Two TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each with

– 1.25 GHz C66x Fixed/Floating-Point CPU Core

› 40 GMAC/Core for Fixed Point @ 1.25 GHz › 20 GFLOP/Core for Floating Point @ 1.25 GHz

–Memory

› 32K Byte L1P Per Core › 32K Byte L1D Per Core › 512K Byte Local L2 Per Core

• Multicore Shared Memory Controller (MSMC) – 4096 KB MSM SRAM Memory Shared by Two DSP

C66x CorePacs

– Memory Protection Unit for Both MSM SRAM and

DDR3_EMIF

• Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue

Manager

– Packet-Based DMA for Zero-Overhead Transfers

• Network Coprocessors – Packet Accelerator Enables Support for

› Transport Plane IPsec, GTP-U, SCTP, PDCP › L2 User Plane PDCP (RoHC, Air Ciphering) › 1 Gbps Wire Speed Throughput at 1.5M Packets

Per Second

– Security Accelerator Engine Enables Support for

› IPSec, SRTP, 3GPP, WiMAX Air Interface, and

SSL/TLS Security

› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,

CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5

› Up to 2.8 Gbps Encryption Speed

• Peripherals – Four Lanes of SRIO 2.1

› 1.24/2.5/3.125/5 GBaud Operation Supported

Per Lane

› Supports Direct I/O, Message Passing › Supports Four 1×, Two 2×, One 4×, and Two 1x +

One 2x Link Configurations

– Two Lanes PCIe Gen2

› Supports Up To 5 GBaud Per Lane

–HyperLink

› Supports Connections to Other KeyStone

Architecture Devices Providing Resource Scalability

› Supports up to 50 Gbaud

– Ethernet MAC Subsystem (EMAC)

›Two SGMII Ports › Supports 10/100/1000 Mbps operation

– 64-Bit DDR3 Interface (DDR3-1600)

› 8G Byte Addressable Memory Space

–16-Bit EMIF

› Support For Up To 256MB NAND Flash and

16MB NOR Flash

› Support For Asynchronous SRAM up to 1MB

– Two Telecom Serial Ports (TSIP)

› Supports 1024 DS0s Per TSIP › Supports 2/4/8 Lanes at 32.768/16.384/8.192

Mbps Per Lane

–UART Interface

–I

C Interface –16 GPIO Pins –SPI Interface – Semaphore Module – Four 64-Bit Timers – Three On-Chip PLLs

• Commercial Temperature: – 0°C to 100°C

• Extended Temperature: – - 40°C to 105°C

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

1.1 KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched

ADVANCE INFORMATION

central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

1.2 Device Description

www.ti.com

The TMS320C6672 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore architecture. Integrated with the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and automation and other applications requiring high performance, TI's TMS320C6672 DSP offers 2.5 GHz cumulative DSP and enables a platform that is power efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

TI's Keystone architecture provides a programmable platform integrating various subsystems (C66x cores, Memory subsystem, Peripherals and accelerators) and uses several innovative components and techniques to maximize intra device and inter device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore navigator that allow for efficient data management between the various chip components, Teranet switch fabric that is a 2 TB non-blocking switch fabric enabling fast and contention free internal data movement, as well as the Multicore shared memory controller that allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed point use, the C66x core has 4X the multiply accumulate (MAC) capability of current generation C64x+ cores. In addition, the C66x core integrates floating point capability and the per core raw computational performance is an industry-leading 32 MACS/cycle and 16 flops/cycle. It can execute 8 single precision floating point MAC operations per cycle and can perform double and mixed precision operations and is IEEE754 compliant. The C66x core incorporates 90 new instructions targeted for floating point and vector math oriented processing, compared to the C64x+ core. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6672 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory this device includes 64 bit DDR-3 running at 1600MHz and has ECC DRAM support.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2 and Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I and a 16 bit EMIF interface, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, this device also sports a 50Gbps FD interface called Hyperlink. Adding to the network awareness of this device is a network co-processor which includes both packet and optional security acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for the entire multicore C6672 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities.

The C6672 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

C, UART, Telecom Serial Port (TSIP)

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320C6672 device.

Figure 1-1 Functional Block Diagram

www.ti.com

Memory Subsystem

64-Bit

DDR3 EMIF

SRAM

MSMC

ADVANCE INFORMATION

Debug & Trace

Boot ROM

Semaphore

Power

Management

PLL

´3

EDMA

´3

HyperLink

32KB L1 P-Cache

512KB L2 Cache

4MB

MSM

C66x™

CorePac

32KB L1 D-Cache

2 Cores @ up to 1.25 GHz

TeraNet

C66x™

CorePac

32KB L1 P-Cache

512KB L2 Cache

C6672

32KB L1 D-Cache

Multicore Navigator

EMIF 16

GPIO

Queue

Manager

SPI

UART

PCIe 2

TSIP

Switch

SRIO 4

Ethernet

SGMII

Network Coprocessor

Switch

Packet

DMA

Security

Accelerator

Packet

Accelerator

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320C6672 DSP. The table shows significant features of the device,

including the capacity of on-chip RAM, the peripherals, the DSP frequency, and the package and pin count.

Table 2-1 Characteristics of the TMS320C6672 Processor

HARDWARE FEATURES TMS320C6672

DDR3 Memory Controller (64-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P)

EDMA3 (16 independent channels) [DSP/2 clock rate] 1

EDMA3 (64 independent channels) [DSP/3 clock rate] 2

High-speed 1×/2x/4× Serial RapidIO Port (4 lanes) 1

PCIe (2 lanes) 1

10/100/1000 Ethernet MAC (EMAC) 2

Management Data Input/Output (MDIO) 1

Peripherals

Accelerators

On-Chip Memory

C66x CorePac Revision ID

JTAG BSDL_ID JTAGID register (address location: 0262 0018h)

Frequency MHz

Cycle Time ns 1 ns

Voltage

Process Technology μm 0.040 μm

Product Status

End of Table 2-1

1 The Crypto Accelerator function is subject to export control and will be enabled only for approved device shipments. 2 PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

(2)

HyperLink 1

EMIF16 1

TSIP 2

SPI 1

UART 1

64-Bit Timers (Configurable) (internal clock source = DSP/6 clock frequency)

General-Purpose Input/Output Port (GPIO) 16

Packet Accelerator 1

Security Accelerator

Size (Bytes) 5376KB

Organization

CorePac Revision ID Register (address location: 0181 2000h) See Section 5.6 ‘‘C66x CorePac Revision’’ on page 87.

Core (V) SmartReflex variable supply

I/O (V) 1.0 V, 1.5 V, and 1.8 V

Product Preview (PP), Advance Information (AI), or Production Data (PD)

(1)

4 64-bit (each configurable as 2 32-bit timers)

64KB L1 Program Memory [SRAM/Cache]

64KB L1 Data Memory [SRAM/Cache]

1024KB L2 Unified Memory/Cache

4096KB MSM SRAM

128KB L3 ROM

See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register

Description’’ on page 65

1250 (1.25 GHz)

1000 (1.0 GHz)

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.2 DSP Core Description

The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP

ADVANCE INFORMATION

programmers through the use of TI's optimized C/C++ compiler.

The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data. 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3 upper registers.

www.ti.com

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions that multiply a complex number with a complex conjugate of another number with rounding capability. Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability. A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.

Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one the following floating-point operations each clock cycle: one, two, or four single-precision multiplies or a complex single-precision multiply.

The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number.

The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall until the completion of all the DSP-triggered memory transactions, including:

• Cache line fills

• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints

• Victim write backs

• Block or global coherence operations

•Cache mode changes

• Outstanding XMC prefetch requests

This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations.

For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following documents:

• C66x CPU and Instruction Set Reference Guide (literature number SPRUGH7)

• C66x DSP Cache User Guide (literature number SPRUGY8)

• C66x CorePac User Guide (literature number SPRUGW0)

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Figure 2-1 shows the DSP core functional units and data paths.

Figure 2-1 TMS320C6672 DSP Core Data Paths

Note: Default bus width is 64 bits (i.e. a register pair)

ST1

ADVANCE INFORMATION

.L1

.S1

src1

src2

dst

src1

src2

dst

www.ti.com

File A

(A0, A1, A2,

...A31)

Data Path A

Data Path B

LD1

DA1

DA2

LD2

ST2

src1

src1_hi

.M1

.D1

.D2

.M2

.S2

.L2

src2

src2_hi

dst2

dst1

src1

dst

src2

src1

dst1

dst2

src2_hi

src2

src1_hi

src1

src2

src1

src2

dst

File B

(B0, B1, B2,

...B31)

src1

Control

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the TMS320C6672 device.

Table 2-2 Memory Map Summary for TMS320C6672 (Part 1 of 7)

Address

Bytes DescriptionStart End

00000000 007FFFFF 8M Reserved

00800000 0087FFFF 512K Local L2 SRAM

00880000 00DFFFFF 5M+512K Reserved

00E00000 00E07FFF 32K Local L1P SRAM

00E08000 00EFFFFF 1M-32K Reserved

00F00000 00F07FFF 32K L1D SRAM

00F08000 017FFFFF 9M-32K Reserved

01800000 01BFFFFF 4M C66x CorePac Registers

01C00000 01CFFFFF 1M Reserved

01D00000 01D0007F 128 Tracer 0

01D00080 01D07FFF 32K-128 Reserved

01D08000 01D0807F 128 Tracer 1

01D08080 01D0FFFF 32K-128 Reserved

01D10000 01D1007F 128 Tracer 2

01D10080 01D17FFF 32K-128 Reserved

01D18000 01D1807F 128 Tracer3

01D18080 01D1FFFF 32K-128 Reserved

01D20000 01D2007F 128 Tracer 4

01D20080 01D27FFF 32K-128 Reserved

01D28000 01D2807F 128 Tracer 5

01D28080 01D2FFFF 32K-128 Reserved

01D30000 01D3007F 128 Tracer 6

01D30080 01D37FFF 32K-128 Reserved

01D38000 01D3807F 128 Tracer 7

01D38080 01D3FFFF 32K-128 Reserved

01D40000 01D4007F 128 Tracer 8

01D40080 01D47FFF 32K-128 Reserved

01D48000 01D4807F 128 Tracer 9

01D48080 01D4FFFF 32K-128 Reserved

01D50000 01D5007F 128 Tracer 10

01D50080 01D57FFF 32K-128 Reserved

01D58000 01D5807F 128 Tracer 11

01D58080 01D5FFFF 32K-128 Reserved

01D60000 01D6007F 128 Tracer 12

01D60080 01D67FFF 32K-128 Reserved

01D68000 01D6807F 128 Tracer 13

01D68080 01D6FFFF 32K-128 Reserved

01D70000 01D7007F 128 Tracer 14

01D70080 01D77FFF 32K-128 Reserved

01D78000 01D7807F 128 Tracer 15

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-2 Memory Map Summary for TMS320C6672 (Part 2 of 7)

Address

Bytes DescriptionStart End

01D78080 01D7FFFF 32K-128 Reserved

01D80000 01D8007F 128 Tracer 16

01D80080 01DFFFFF 512K-128 Reserved

01E00000 01E3FFFF 256K Telecom Serial Interface Port (TSIP) 0

01E40000 01E7FFFF 256K Reserved

01E80000 01EBFFFF 256K Telecom Serial Interface Port (TSIP) 1

ADVANCE INFORMATION

01EC0000 01FFFFFF 1M +256K Reserved

02000000 0209FFFF 640K Packet Accelerator Subsystem Configuration

020A0000 021FFFFF 1M + 384K Reserved

02200000 0220007F 128 Timer0

02200080 0220FFFF 64K-128 Reserved

02210000 0221007F 128 Timer1

02210080 0221FFFF 64K-128 Reserved

02220000 0222007F 128 Timer2

02220080 0222FFFF 64K-128 Reserved

02230000 0223007F 128 Timer3

02230080 0223FFFF 64K-128 Reserved

02240000 0224007F 128 Reserved

02240080 0224FFFF 64K-128 Reserved

02250000 0225007F 128 Reserved

02250080 0225FFFF 64K-128 Reserved

02260000 0226007F 128 Reserved

02260080 0226FFFF 64K-128 Reserved

02270000 0227007F 128 Reserved

02270080 0227FFFF 64K-128 Reserved

02280000 0228007F 128 Reserved

02280080 0228FFFF 64K-128 Reserved

02290000 0229007F 128 Reserved

02290080 0229FFFF 64K-128 Reserved

022A0000 022A007F 128 Reserved

022A0080 022AFFFF 64K-128 Reserved

022B0000 022B007F 128 Reserved

022B0080 022BFFFF 64K-128 Reserved

022C0000 022C007F 128 Reserved

022C0080 022CFFFF 64K-128 Reserved

022D0000 022D007F 128 Reserved

022D0080 022DFFFF 64K-128 Reserved

022E0000 022E007F 128 Reserved

022E0080 022EFFFF 64K-128 Reserved

022F0000 022F007F 128 Reserved

022F0080 022FFFFF 64K-128 Reserved

02300000 0230FFFF 64K Reserved

02310000 023101FF 512 PLL Controller

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-2 Memory Map Summary for TMS320C6672 (Part 3 of 7)

Address

Bytes DescriptionStart End

02310200 0231FFFF 64K-512 Reserved

02320000 023200FF 256 GPIO

02320100 0232FFFF 64K-256 Reserved

02330000 023303FF 1K SmartRlex

02330400 0234FFFF 127K Reserved

02350000 02350FFF 4K Power Sleep Controller (PSC)

02351000 0235FFFF 64K-4K Reserved

02360000 023603FF 1K Memory Protection Unit (MPU) 0

02360400 02367FFF 31K Reserved

02368000 023683FF 1K Memory Protection Unit (MPU) 1

02368400 0236FFFF 31K Reserved

02370000 023703FF 1K Memory Protection Unit (MPU) 2

02370400 02377FFF 31K Reserved

02378000 023783FF 1K Memory Protection Unit (MPU) 3

02378400 0237FFFF 31K Reserved

02380000 0243FFFF 768K Reserved

02440000 02443FFF 16K DSP Trace Formatter 0

02444000 0244FFFF 48K Reserved

02450000 02453FFF 16K DSP Trace Formatter 1

02454000 0245FFFF 48K Reserved

02460000 02463FFF 16K Reserved

02464000 0246FFFF 48K Reserved

02470000 02473FFF 16K Reserved

02474000 0247FFFF 48K Reserved

02480000 02483FFF 16K Reserved

02484000 0248FFFF 48K Reserved

02490000 02493FFF 16K Reserved

02494000 0249FFFF 48K Reserved

024A0000 024A3FFF 16K Reserved

024A4000 024AFFFF 48K Reserved

024B0000 024B3FFF 16K Reserved

024B4000 024BFFFF 48K Reserved

024C0000 0252FFFF 448K Reserved

02530000 0253007F 128 I

02530080 0253FFFF 64K-128 Reserved

02540000 0254003F 64 UART

02540400 0254FFFF 64K-64 Reserved

02550000 025FFFFF 704K Reserved

02600000 02601FFF 8K Secondary Interrupt Controller (INTC) 0

02602000 02603FFF 8K Reserved

02604000 02605FFF 8K Reserved

02606000 02607FFF 8K Reserved

02608000 02609FFF 8K Secondary Interrupt Controller (INTC) 2

C Data & Control

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-2 Memory Map Summary for TMS320C6672 (Part 4 of 7)

Address

Bytes DescriptionStart End

0260A000 0260BFFF 8K Reserved

0260C000 0260DFFF 8K Secondary Interrupt Controller (INTC) 3

0260E000 0261FFFF 72K Reserved

02620000 026207FF 2K Chip-Level Registers (boot cfg)

02620800 0263FFFF 126K Reserved

02640000 026407FF 2K Semaphore

ADVANCE INFORMATION

02640800 0264FFFF 64K-2K Reserved

02650000 026FFFFF 704K Reserved

02700000 02707FFF 32K EDMA Channel Controller (TPCC) 0

02708000 0271FFFF 96K Reserved

02720000 02727FFF 32K EDMA Channel Controller (TPCC) 1

02728000 0273FFFF 96K Reserved

02740000 02747FFF 32K EDMA Channel Controller (TPCC) 2

02748000 0275FFFF 96K Reserved

02760000 027603FF 1K EDMA TPCC0 Transfer Controller (TPTC) 0

02760400 02767FFF 31K Reserved

02768000 027683FF 1K EDMA TPCC0 Transfer Controller (TPTC) 1

02768400 0276FFFF 31K Reserved

02770000 027703FF 1K EDMA TPCC1 Transfer Controller (TPTC) 0

02770400 02777FFF 31K Reserved

02778000 027783FF 1K EDMA TPCC1 Transfer Controller (TPTC) 1

02780400 0277FFFF 31K Reserved

02780000 027803FF 1K EDMA TPCC1 Transfer Controller (TPTC) 2

02780400 02787FFF 31K Reserved

02788000 027883FF 1K EDMA TPCC1Transfer Controller (TPTC) 3

02788400 0278FFFF 31K Reserved

02790000 027903FF 1K EDMA TPCC2 Transfer Controller (TPTC) 0

02790400 02797FFF 31K Reserved

02798000 027983FF 1K EDMA TPCC2 Transfer Controller (TPTC) 1

02798400 0279FFFF 31K Reserved

027A0000 027A03FF 1K EDMA TPCC2 Transfer Controller (TPTC) 2

027A0400 027A7FFF 31K Reserved

027A8000 027A83FF 1K EDMA TPCC2 Transfer Controller (TPTC) 3

027A8400 027AFFFF 31K Reserved

027B0000 027CFFFF 128K Reserved

027D0000 027D3FFF 16K TI Embedded Trace Buffer (TETB) core 0

027D4000 027DFFFF 48K Reserved

027E0000 027E3FFF 16K TI Embedded Trace Buffer (TETB) core 1

027E4000 027EFFFF 48K Reserved

027F0000 027F3FFF 16K Reserved

027F4000 027FFFFF 48K Reserved

02800000 02803FFF 16K Reserved

02804000 0280FFFF 48K Reserved

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-2 Memory Map Summary for TMS320C6672 (Part 5 of 7)

Address

Bytes DescriptionStart End

02810000 02813FFF 16K Reserved

02814000 0281FFFF 48K Reserved

02820000 02823FFF 16K Reserved

02824000 0282FFFF 48K Reserved

02830000 02833FFF 16K Reserved

02834000 0283FFFF 48K Reserved

02840000 02843FFF 16K Reserved

02844000 0284FFFF 48K Reserved

02850000 02857FFF 32K TI Embedded Trace Buffer (TETB) — system

02858000 0285FFFF 32K Reserved

02860000 028FFFFF 640K Reserved

02900000 02907FFF 32K Serial RapidIO (SRIO) Configuration

02908000 029FFFFF 1M-32K Reserved

02A00000 02BFFFFF 2M Queue Manager Subsystem Configuration

02C00000 07FFFFFF 84M Reserved

08000000 0800FFFF 64K Extended Memory Controller (XMC) Configuration

08010000 0BBFFFFF 60M-64K Reserved

0BC00000 0BCFFFFF 1M Multicore Shared Memory Controller (MSMC) Config

0BD00000 0BFFFFFF 3M Reserved

0C000000 0C3FFFFF 4M Multicore Shared Memory

0C400000 107FFFFF 68 M Reserved

10800000 1087FFFF 512K Core0 L2 SRAM

10880000 108FFFFF 512K Reserved

10900000 10DFFFFF 5M Reserved

10E00000 10E07FFF 32K Core0 L1P SRAM

10E08000 10EFFFFF 1M-32K Reserved

10F00000 10F07FFF 32K Core0 L1D SRAM

10F08000 117FFFFF 9M-32K Reserved

11800000 1187FFFF 512K Core1 L2 SRAM

11880000 118FFFFF 512K Reserved

11900000 11DFFFFF 5M Reserved

11E00000 11E07FFF 32K Core1 L1P SRAM

11E08000 11EFFFFF 1M-32K Reserved

11F00000 11F07FFF 32K Core1 L1D SRAM

11F08000 127FFFFF 9M-32K Reserved

12800000 1287FFFF 512K Reserved

12880000 128FFFFF 512K Reserved

12900000 12DFFFFF 5M Reserved

12E00000 12E07FFF 32K Reserved

12E08000 12EFFFFF 1M-32K Reserved

12F00000 12F07FFF 32K Reserved

12F08000 137FFFFF 9M-32K Reserved

13800000 1387FFFF 512K Reserved

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-2 Memory Map Summary for TMS320C6672 (Part 6 of 7)

Address

Bytes DescriptionStart End

13880000 138FFFFF 512K Reserved

13900000 13DFFFFF 5M Reserved

13E00000 13E07FFF 32K Reserved

13E08000 13EFFFFF 1M-32K Reserved

13F00000 13F07FFF 32K Reserved

13F08000 147FFFFF 9M-32K Reserved

ADVANCE INFORMATION

14800000 1487FFFF 512K Reserved

14880000 148FFFFF 512K Reserved

14900000 14DFFFFF 5M Reserved

14E00000 14E07FFF 32K Reserved

14E08000 14EFFFFF 1M-32K Reserved

14F00000 14F07FFF 32K Reserved

14F08000 157FFFFF 9M-32K Reserved

15800000 1587FFFF 512K Reserved

15880000 158FFFFF 512K Reserved

15900000 15DFFFFF 5M Reserved

15E00000 15E07FFF 32K Reserved

15E08000 15EFFFFF 1M-32K Reserved

15F00000 15F07FFF 32K Reserved

15F08000 167FFFFF 9M-32K Reserved

16800000 1687FFFF 512K Reserved

16880000 168FFFFF 512K Reserved

16900000 16DFFFFF 5M Reserved

16E00000 16E07FFF 32K Reserved

16E08000 16EFFFFF 1M-32K Reserved

16F00000 16F07FFF 32K Reserved

16F08000 177FFFFF 9M-32K Reserved

17800000 1787FFFF 512K Reserved

17880000 178FFFFF 512K Reserved

17900000 17DFFFFF 5M Reserved

17E00000 17E07FFF 32K Reserved

17E08000 17EFFFFF 1M-32K Reserved

17F00000 17F07FFF 32K Reserved

17F08000 1FFFFFFF 129M-32K Reserved

20000000 200FFFFF 1M System Trace Manager (STM) Configuration

20100000 20AFFFFF 10M Reserved

20B00000 20B1FFFF 128K Boot ROM

20B20000 20BEFFFF 832K Reserved

20BF0000 20BF03FF 1K SPI

20BF0400 20BFFFFF 63K Reserved

20C00000 20C000FF 256 EMIF-16 Config

20C00100 20FFFFFF 12M - 256 Reserved

21000000 210000FF 256 DDR3 EMIF Configuration

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-2 Memory Map Summary for TMS320C6672 (Part 7 of 7)

Address

Bytes DescriptionStart End

21000100 213FFFFF 4M-256 Reserved

21400000 214003FF 1K HyperLink Config

21400400 217FFFFF 4M-1K Reserved

21800000 21807FFF 32K PCIe Config

21808000 33FFFFFF 296M-32K Reserved

34000000 341FFFFF 2M Queue Manager Subsystem Data

34200000 3FFFFFFF 190M Reserved

40000000 4FFFFFFF 256M HyperLink data

50000000 5FFFFFFF 256M Reserved

60000000 6FFFFFFF 256M PCIe Data

70000000 73FFFFFF 64M EMIF16 CS2 Data NAND Memory

74000000 77FFFFFF 64M EMIF16 CS3 Data NAND Memory

78000000 7BFFFFFF 64M EMIF16 CS4 Data NOR Memory

7C000000 7FFFFFFF 64M EMIF16 CS5 Data SRAM Memory

80000000 8FFFFFFF 256M DDR3_ Data

90000000 9FFFFFFF 256M DDR3_ Data

A0000000 AFFFFFFF 256M DDR3_ Data

B0000000 BFFFFFFF 256M DDR3_ Data

C0000000 CFFFFFFF 256M DDR3_ Data

D0000000 DFFFFFFF 256M DDR3_ Data

E0000000 EFFFFFFF 256M DDR3_ Data

F0000000 FFFFFFFF 256M DDR3_ Data

End of Table 2-2

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section

‘‘Reset Controller’’.

The C6672 supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide (literature number

SPRUGY5).

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.5 Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

• Public ROM Boot - C66x CorePac 0 is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I then begins execution from the provided boot entry point, other C66x CorePac’s are released from reset based on interrupts generated by C66x CorePac 0, see the Bootloader for the C66x DSP User Guide (literature number

SPRUGY5) for more details.

ADVANCE INFORMATION

• Secure ROM Boot - On secure devices, the C66x CorePac 0 is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C66x CorePac 0 initiates the boot process. The C66x CorePac 0 performs any authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C66x CorePac 0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac 0 reads this value, and then executes the associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].

Figure 2-2 Boot Mode Pin Decoding

12 11 10 9 8 7 6 5 4 3 2 1 0

PLL Mult

C /SPI Ext Dev Cfg

C ROM, Ethernet, or RapidIO), the C66x CorePac 0

Boot Mode Pins

Device Configuration

www.ti.com

Boot Device

2.5.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot modes.

Table 2-3 Boot Mode Pins: Boot Device Values

Bit Field Value Description

2-0 Boot Device 0 Sleep / test modes / EMIF16

1Serial Rapid I/O

2 Ethernet (SGMII) (PA driven from core clk)

3 Ethernet (SGMII) (PA driver from PA clk)

4PCI

6SPI

7HyperLink

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

2.5.2 Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode

2.5.2.1 Sleep / EMIF16 Boot Device Configuration

Figure 2-3 Sleep / EMIF16 Configuration Bit Fields

9 8 7 6 5 4 3

Reserved Wait Enable Sub-Mode Reserved

Table 2-4 Sleep / EMIF16 Configuration Bit Field Descriptions

Bit Field Value Description

9-8 Reserved 0-3 Reserved

7 Wait Enable 0

6-5 Sub-Mode 0

4-3 Reserved 0-3 Reserved

Wait enable disabled (EMIF16 sub mode)

Wait enable enabled (EMIF16 sub mode)

Sleep boot

EMIF16 boot

SPRS708—November 2010

2.5.2.2 Ethernet (SGMII) Boot Device Configuration

Figure 2-4 Ethernet (SGMII) Device Configuration Bit Fields

9 8 7 6 5 4 3

SerDes Clock Mult Ext connection Device ID Reserved

Table 2-5 Ethernet (SGMII) Configuration Bit Field Descriptions

Bit Field Value Description

9-8 SerDes Clock Mult

7-6 Ext connection 0

5 Device ID 0-7 This value is used in the device ID field of the Ethernet-ready frame.

4-3 Reserved 0-3 Reserved

The output frequency of the PLL must be 1.25 GBs.

×8 for input clock of 156.25 MHz

×5 for input clock of 250 MHz

×4 for input clock of 312.5 MHz

Reserved

Mac to Mac connection, master with auto negotiation

Mac to Mac connection, slave, and Mac to Phy

Mac to Mac, forced link

Mac to fiber connection

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.5.2.3 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-5 Serial Rapid I/O Device Configuration Bit Fields

9 8 7 6 5 4 3

Lane Setup Data Rate Ref Clock Reserved

Table 2-6 Serial Rapid I/O Configuration Bit Field Descriptions

Bit Field Value Description

ADVANCE INFORMATION

9Lane Setup 01Port Configured as 4 ports each 1 lane wide (4 -1× ports)

Port Configured as 2 ports 2 lanes wide (2 – 2× ports)

8-7 Data Rate 0

6-5 Ref Clock 0

4-3 Reserved 0-3 Reserved

Data Rate = 1.25 GBs

Data Rate = 2.5 GBs

Data Rate = 3.125 GBs

Data Rate = 5.0 GBs

Reference Clock = 156.25 MHz

Reference Clock = 250 MHz

Reference Clock = 312.5 MHz

www.ti.com

In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.

2.5.2.4 PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.

Figure 2-6 PCI Device Configuration Bit Fields

9 8 7 6 5 4 3

Reserved BAR Config Reserved

Table 2-7 PCI Device Configuration Bit Field Descriptions

Bit Field Value Description

9 Reserved Reserved

8-5 Bar Config 0-0xf See Table 2-8.

4-3 Reserved 0-3 Reserved

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-8 BAR Config / PCIe Window Sizes

32-Bit Address Translation 64-Bit Address Translation

BAR cfg BAR0

0b0000PCIe MMRs32323232Clone of BAR4

0b0001 16163264

0b0010 16323264

0b0011 32323264

0b0100 16166464

0b0101 16326464

0b0110 32326464

0b0111 32 32 64 128

0b1000 64 64 128 256

0b1001 4 128 128 128

0b1010 4 128 128 256

0b1011 4 128 256 256

0b1100

0b1101 512 512

0b1110 1024 1024

0b1111 2048 2048

BAR1 BAR2 BAR3 BAR4 BAR5 BAR1/2 BAR3/4

SPRS708—November 2010

256 256

2.5.2.5 I2C Boot Device Configuration

2.5.2.5.1 I2C Master Mode

In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device will make the initial read of the I

C EEPROM while the PLL is in bypass mode.

The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

Figure 2-7 I2C Master Mode Device Configuration Bit Fields

12 11 10 9 8 7 6 5 4 3

Reserved Speed Address Mode

(0)

Table 2-9 I2C Master Mode Device Configuration Field Descriptions

Bit Field Value Description

12 Reserved Reserved

11 Speed 0

10 Address 0

9 Mode 0

8-3 Parameter Index 0-63 Identifies the index of the configuration table initially read from the I

4-3 Reserved 0-3 Reserved

C data rate set to approximately 20 kHz

C fast mode. Data rate set to approximately 400 kHz (will not exceed)

Boot from I

Master mode

Passive mode (see section I

C EEPROM at I2C bus address 0x50

C EEPROM at I2C bus address 0x51

C Passive Mode)

Parameter Index

C EEPROM

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.5.2.5.2 I2C Passive Mode

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

Figure 2-8 I2C Passive Mode Device Configuration Bit Fields

9 8 7 6 5 4 3

Mode (1) Receive I

Table 2-10 I2C Passive Mode Device Configuration Field Descriptions

Bit Field Value Description

ADVANCE INFORMATION

9Mode 01Master Mode (See ‘‘I2C Master Mode’’ on page 29)

Passive Mode

8-5 Receive I

4-3 Reserved 0-3 Reserved

C Address 0-15 The I2C Bus address the device will listen to for data

2.5.2.6 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.

C Address Reserved

www.ti.com

Figure 2-9 SPI Device Configuration Bit Fields

12 11 10 9 8 7 6 5 4 3

Mode 4, 5 Pin Addr Width Chip Select Parameter Table Index Reserved

Table 2-11 SPI Device Configuration Field Descriptions

Bit Field Value Description

12-11 Mode

10 4, 5 Pin 014-pin mode used

9 Addr Width 0116-bit address values are used

8-7 Chip Select 0-3 The chip select field value

6-5 Parameter Table Index 0-3 Specifies which parameter table is loaded

4-3 Reserved 0-3 Reserved

Clk Pol / Phase

Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.

Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.

Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.

5-pin mode used

24-bit address values are used

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

2.5.2.7 HyperLink Boot Device Configuration

Figure 2-10 HyperLink Boot Device Configuration Fields

9 8 7 6 5 4 3

Reserved Data Rate Ref Clock Reserved

Table 2-12 HyperLink Boot Device Configuration Field Descriptions

Bit Field Value Description

9 Reserved Reserved

8-7 Data Rate 0

6-5 Ref Clocks 0

4-3 Reserved 0-3 Reserved

1.25 GBs

3.125 GBs

6.25 GBs

12.5 GBs

156.25 MHz

250 MHz

312.5 MHz

TMS320C6672

SPRS708—November 2010

2.5.3 PLL Boot Configuration Settings

The PLL default settings are determined by the BOOTMODE[12:10] bits. The Table 2-13 shows settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device.

CLK = CLKIN × (PLLM+1) ÷ (2 × (PLLD+1))

The PA configuration is also shown. The PA is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the PA SerDes clock). See Table 2-3 for details on configuring Ethernet boot mode. See section 7.8 ‘‘Main PLL and PLL Controller’’ on page 207 for further details

Table 2-13 C66x DSP System PLL Configuration

BOOTMODE

[12:10]

0b000 50.00 0 31 800 0 39 1000 0 47 1200 0 41 1050

0b001 66.67 0 23 800.04 0 29 1000.05 0 35 1200.06 1 62 1050.053

0b010 80.00 0 19 800 0 24 1000 0 29 1200 3 104 1050

0b011 100.00 0 15 800 0 19 1000 0 23 1200 0 20 1050

0b100 156.25 24 255 800 4 63 1000 24 383 1200 24 335 1050

0b101 250.00 4 31 800 0 7 1000 4 47 1200 4 41 1050

0b110 312.50 24 127 800 4 31 1000 24 191 1200 24 167 1050

0b111 122.88 47 624 800 28 471 999.989 31 624 1200 11 204 1049.6

Input Clock

Freq (MHz)

800 MHz Device 1000 MHz Device 1200 MHz Device PA = 350 MHz

PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ

ADVANCE INFORMATION

2.6 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.7 Terminals

Figure 2-11 Shows the TMS320C6672CYP ball grid area (BGA) package (bottom view)

Figure 2-11 CYP 841-Pin BGA Package Bottom View

ADVANCE INFORMATION

2 4

6 810

www.ti.com

12 14

151719

16 18 20

22 24

252729

26 28

2.8 Terminal Functions

The terminal functions table (Table 2-15) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table (Table 2-16) lists the various power supply pins and ground pins and gives functional pin descriptions. Table 2-17 shows all pins arranged by signal name. Table 2-18 shows all pins arranged by ball number.

There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.

Use the symbol definitions in Table 2-14 when reading Table 2-15.

Table 2-14 I/O Functional Symbol Definitions

Functional

Symbol

Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can

IPD or IPU

AAnalog signal Type

GND Ground Type

IInput terminal Type

OOutput terminal Type

S Supply voltage Type

Z Three-state terminal or high impedance Type

End of Table 2-14

be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for KeyStone Devices (literature number SPRABI2).

Definition

Table 2-15

Column Heading

IPD/IPU

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 1 of 13)

Signal Name Ball No. Type IPD/IPU Description

Boot Configuration Pins

LENDIAN † H25 IOZ UP Endian configuration pin (Pin shared with GPIO[0])

BOOTMODE00 † J28 IOZ Down

BOOTMODE01† J29 IOZ Down

BOOTMODE02 † J26 IOZ Down

BOOTMODE03 † J25 IOZ Down

BOOTMODE04 † J27 IOZ Down

BOOTMODE05 † J24 IOZ Down

BOOTMODE06 † K27 IOZ Down

BOOTMODE07 † K28 IOZ Down

BOOTMODE08 † K26 IOZ Down

BOOTMODE09 † K29 IOZ Down

BOOTMODE10 † L28 IOZ Down

BOOTMODE11 † L29 IOZ Down

BOOTMODE12 † K25 IOZ Down

PCIESSMODE0 † K24 IOZ Down

PCIESSMODE1 † L27 IOZ Down

PCIESSEN † L24 I Down PCIe module enable (Pin shared with TIMI0)

CORECLKP AG3 I

CORECLKN AG4 I

SRIOSGMIICLKP AG6 I

SRIOSGMIICLKN AJ6 I

DDRCLKP G29 I

DDRCLKN H29 I

PCIECLKP AG5 I

PCIECLKN AH5 I

MCMCLKP W2 I

MCMCLKN Y2 I

PASSCLKP AJ5 I

PASSCLKN AJ4 I

AVDDA1 H22 P SYS_CLK PLL Power Supply Pin

AVDDA2 AC6 P DDR_CLK PLL Power Supply Pin

AVDDA3 AD5 P PS_SS_CLK PLL Power Supply Pin

SYSCLKOUT AE3 OZ Down System Clock Output to be used as a general purpose output clock for debug purposes

PACLKSEL AE4 I Down PA clock select to choose between core clock and PASSCLK pins

HOUT AD20 OZ UP Interrupt output pulse created by IPCGRH

NMI

LRESET

LRESETNMIEN

M25 I UP Non-maskable Interrupt

N26 I UP Warm Reset

M27 I UP Enable for core selects

See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 26 for more details

(Pins shared with GPIO[1:13])

PCIe Mode selection pins (Pins shared with GPIO[14:15])

Clock / Reset

Core Clock Input to main PLL.

RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes

DDR Reference Clock Input to DDR PLL (

PCIe Clock Input to drive PCIe SerDes

HyperLink Reference Clock to drive the HyperLink SerDes

Packet Sub-system Reference Clock

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 2 of 13)

Signal Name Ball No. Type IPD/IPU Description

CORESEL0 AF2 I Down

CORESEL1 AD4 I Down

CORESEL2 AE6 I Down

CORESEL3 AE5 I Down

RESETFULL

RESET

POR

ADVANCE INFORMATION

RESETSTAT

BOOTCOMPLETE AE2 OZ Down Boot progress indication output

PTV15 G22 A PTV Compensation NMOS Reference Input

DDRDQM0 E29 OZ

DDRDQM1 C27 OZ

DDRDQM2 A25 OZ

DDRDQM3 A22 OZ

DDRDQM4 A10 OZ

DDRDQM5 A8 OZ

DDRDQM6 B5 OZ

DDRDQM7 B2 OZ

DDRDQM8 A20 OZ

DDRDQS0P C28 IOZ

DDRDQS0N C29 IOZ

DDRDQS1P A27 IOZ

DDRDQS1N B27 IOZ

DDRDQS2P A24 IOZ

DDRDQS2N B24 IOZ

DDRDQS3P A21 IOZ

DDRDQS3N B21 IOZ

DDRDQS4P A9 IOZ

DDRDQS4N B9 IOZ

DDRDQS5P B6 IOZ

DDRDQS5N A6 IOZ

DDRDQS6P B3 IOZ

DDRDQS6N A3 IOZ

DDRDQS7P D1 IOZ

DDRDQS7N C1 IOZ

DDRDQS8P A19 IOZ

DDRDQS8N B19 IOZ

N25 I UP Full Reset

M29 I UP Warm Reset of non isolated portion on the IC

AC20 I Power-on Reset

N27 O UP Reset Status Output

Select for the target core for LRESET and NMI. For more details see Table 7-39‘‘NMI and

Local Reset Timing Requirements’’ on page 185

DDR EMIF Data Masks

DDR EMIF Data Strobe

www.ti.com

DDR

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 3 of 13)

Signal Name Ball No. Type IPD/IPU Description

DDRCB00 E19 IOZ

DDRCB01 C20 IOZ

DDRCB02 D19 IOZ

DDRCB03 B20 IOZ

DDRCB04 C19 IOZ

DDRCB05 C18 IOZ

DDRCB06 B18 IOZ

DDRCB07 A18 IOZ

DDR EMIF Check Bits

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 4 of 13)

Signal Name Ball No. Type IPD/IPU Description

DDRD00 E28 IOZ

DDRD01 D29 IOZ

DDRD02 E27 IOZ

DDRD03 D28 IOZ

DDRD04 D27 IOZ

DDRD05 B28 IOZ

DDRD06 E26 IOZ

ADVANCE INFORMATION

DDRD07 F25 IOZ

DDRD08 F24 IOZ

DDRD09 E24 IOZ

DDRD10 E25 IOZ

DDRD11 D25 IOZ

DDRD12 D26 IOZ

DDRD13 C26 IOZ

DDRD14 B26 IOZ

DDRD15 A26 IOZ

DDRD16 F23 IOZ

DDRD17 F22 IOZ

DDRD18 D24 IOZ

DDRD19 E23 IOZ

DDRD20 A23 IOZ

DDRD21 B23 IOZ

DDRD22 C24 IOZ

DDRD23 E22 IOZ

DDRD24 D21 IOZ

DDRD25 F20 IOZ

DDRD26 E21 IOZ

DDRD27 F21 IOZ

DDRD28 D22 IOZ

DDRD29 C21 IOZ

DDRD30 B22 IOZ

DDRD31 C22 IOZ

DDRD32 E10 IOZ

DDRD33 D10 IOZ

DDRD34 B10 IOZ

DDRD35 D9 IOZ

DDRD36 E9 IOZ

DDRD37 C9 IOZ

DDRD38 B8 IOZ

DDRD39 E8 IOZ

DDRD40 A7 IOZ

DDRD41 D7 IOZ

DDR EMIF Data Bus

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 5 of 13)

Signal Name Ball No. Type IPD/IPU Description

DDRD42 E7 IOZ

DDRD43 C7 IOZ

DDRD44 B7 IOZ

DDRD45 E6 IOZ

DDRD46 D6 IOZ

DDRD47 C6 IOZ

DDRD48 C5 IOZ

DDRD49 A5 IOZ

DDRD50 B4 IOZ

DDRD51 A4 IOZ

DDRD52 D4 IOZ

DDRD53 E4 IOZ

DDRD54 C4 IOZ

DDRD55 C3 IOZ

DDRD56 F4 IOZ

DDRD57 D2 IOZ

DDRD58 E2 IOZ

DDRD59 C2 IOZ

DDRD60 F2 IOZ

DDRD61 F3 IOZ

DDRD62 E1 IOZ

DDRD63 F1 IOZ

DDRCE0

DDRCE1

DDRBA0 A13 OZ

DDRBA2 C13 OZ

DDRA00 A14 OZ

DDRA01 B14 OZ

DDRA02 F14 OZ

DDRA03 F13 OZ

DDRA04 A15 OZ

DDRA05 C15 OZ

DDRA06 B15 OZ

DDRA07 D15 OZ

DDRA08 F15 OZ

DDRA09 E15 OZ

DDRA10 E16 OZ

DDRA11 D16 OZ

DDRA12 E17 OZ

DDRA13 C16 OZ

DDRA14 D17 OZ

DDRA15 C17 OZ

DDRCAS

C11 OZ

C12 OZ

D12 OZ DDR EMIF Column Address Strobe

DDR EMIF Data Bus

DDR EMIF Chip Enables

DDR EMIF Bank AddressDDRBA1 B13 OZ

DDR EMIF Address Bus

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 6 of 13)

Signal Name Ball No. Type IPD/IPU Description

DDRRAS C10 OZ DDR EMIF Row Address Strobe

DDRWE

DDRCKE0 D11 OZ DDR EMIF Clock Enable

DDRCKE1 E18 OZ DDR EMIF Clock Enable

DDRCLKOUTP0 A12 OZ

DDRCLKOUTN0 B12 OZ

DDRCLKOUTP1 A16 OZ

ADVANCE INFORMATION

DDRCLKOUTN1 B16 OZ

DDRODT0 D13 OZ DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDRODT1 E13 OZ DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDRRESET

DDRSLRATE0 G27 I Down

DDRSLRATE1 H27 I Down

VREFSSTL E14 P Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)

EMIFRW

EMIFCE0

EMIFCE1

EMIFCE2

EMIFCE3

EMIFOE

EMIFWE

EMIFBE0

EMIFBE1

EMIFWAIT0 T29 I Down

EMIFWAIT1 T28 I Down

E12 OZ DDR EMIF Write Enable

DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

E11 OZ DDR Reset signal

DDR Slew rate control

P26 O UP

P25 O UP

R27 O UP

R28 O UP

R25 O UP

R26 O UP

P24 O UP

R24 O UP

R23 O UP

EMIF16 Control Signals

www.ti.com

EMIF16

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 7 of 13)

Signal Name Ball No. Type IPD/IPU Description

EMIFA00 T27 O Down

EMIFA01 T24 O Down

EMIFA02 U29 O Down

EMIFA03 T25 O Down

EMIFA04 U27 O Down

EMIFA05 U28 O Down

EMIFA06 U25 O Down

EMIFA07 U24 O Down

EMIFA08 V28 O Down

EMIFA09 V29 O Down

EMIFA10 V27 O Down

EMIFA11 V26 O Down

EMIFA12 V25 O Down

EMIFA13 V24 O Down

EMIFA14 W28 O Down

EMIFA15 W27 O Down

EMIFA16 W29 O Down

EMIFA17 W26 O Down

EMIFA18 W25 O Down

EMIFA19 W24 O Down

EMIFA20 W23 O Down

EMIFA21 Y29 O Down

EMIFA22 Y28 O Down

EMIFA23 U23 O Down

EMIFD00 Y27 IOZ Down

EMIFD01 AB29 IOZ Down

EMIFD02 AA29 IOZ Down

EMIFD03 Y26 IOZ Down

EMIFD04 AA27 IOZ Down

EMIFD05 AB27 IOZ Down

EMIFD06 AA26 IOZ Down

EMIFD07 AA25 IOZ Down

EMIFD08 Y25 IOZ Down

EMIFD09 AB25 IOZ Down

EMIFD10 AA24 IOZ Down

EMIFD11 Y24 IOZ Down

EMIFD12 AB23 IOZ Down

EMIFD13 AB24 IOZ Down

EMIFD14 AB26 IOZ Down

EMIFD15 AC25 IOZ Down

EMIF16 Address

EMIF16 Data

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 8 of 13)

Signal Name Ball No. Type IPD/IPU Description

EMU00 AC29 IOZ UP

EMU01 AC28 IOZ UP

EMU02 AC27 IOZ UP

EMU03 AC26 IOZ UP

EMU04 AD29 IOZ UP

EMU05 AD28 IOZ UP

ADVANCE INFORMATION

EMU06 AD27 IOZ UP

EMU07 AE29 IOZ UP

EMU08 AE28 IOZ UP

EMU09 AF29 IOZ UP

EMU10 AE27 IOZ UP

EMU11 AF28 IOZ UP

EMU12 AG29 IOZ UP

EMU13 AD26 IOZ UP

EMU14 AG28 IOZ UP

EMU15 AG27 IOZ UP

EMU16 AJ27 IOZ UP

EMU17 AF27 IOZ UP

EMU18 AH27 IOZ UP

GPIO00 H25 IOZ UP

GPIO01 J28 IOZ Down

GPIO02 J29 IOZ Down

GPIO03 J26 IOZ Down

GPIO04 J25 IOZ Down

GPIO05 J27 IOZ Down

GPIO06 J24 IOZ Down

GPIO07 K27 IOZ Down

GPIO08 K28 IOZ Down

GPIO09 K26 IOZ Down

GPIO10 K29 IOZ Down

GPIO11 L28 IOZ Down

GPIO12 L29 IOZ Down

GPIO13 K25 IOZ Down

GPIO14 K24 IOZ Down

GPIO15 L27 IOZ Down

Emulation and Trace Port

General Purpose Input/Output (GPIO)

General Purpose Input/Output

These GPIO pins have secondary functions assigned to them as mentioned in the ‘‘Boot

Configuration Pins’’ on page 33.

www.ti.com

EMU

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 9 of 13)

Signal Name Ball No. Type IPD/IPU Description

HyperLink

MCMRXN0 U2 I

MCMRXP0 T2 I

MCMRXN1 T1 I

MCMRXP1 R1 I

MCMRXN2 M1 I

MCMRXP2 N1 I

MCMRXN3 P2 I

MCMRXP3 N2 I

MCMTXN0 M5 O

MCMTXP0 N5 O

MCMTXN1 T4 O

MCMTXP1 U4 O

MCMTXN2 R5 O

MCMTXP2 T5 O

MCMTXN3 N4 O

MCMTXP3 P4 O

MCMRXFLCLK W3 O Down

MCMRXFLDAT W4 O Down

MCMTXFLCLK AA1 I Down

MCMTXFLDAT AA3 I Down

MCMRXPMCLK Y3 I Down

MCMRXPMDAT Y4 I Down

MCMTXPMCLK AA2 O Down

MCMTXPMDAT AA4 O Down

MCMREFCLKOUTP Y1 O

MCMREFCLKOUTN W1 O

SCL AD3 IOZ I

SDA AC4 IOZ I

TCK N29 I UP JTAG Clock Input

TDI P27 I UP JTAG Data Input

TDO R29 OZ UP JTAG Data Output

TMS P29 I UP JTAG Test Mode Input

TRST

MDIO G26 IOZ UP MDIO Data

MDCLK H26 O Down MDIO Clock

PCIERXN0 AH7 I

PCIERXP0 AH8 I

PCIERXN1 AJ9 I

PCIERXP1 AJ8 I

P28 I Down JTAG Reset

Serial HyperLink Receive Data

Serial HyperLink Transmit Data

Serial HyperLink Sideband Signals

HyperLink Reference clock output for daisy chain connection

C Clock

C Data

PCIexpress Receive Data (2 links)

JTAG

MDIO

PCIe

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 10 of 13)

Signal Name Ball No. Type IPD/IPU Description

PCIETXN0 AF8 O

PCIETXP0 AF7 O

PCIETXN1 AG9 O

PCIETXP1 AG8 O

RIORXN0 AJ11 I

RIORXP0 AJ12 I

ADVANCE INFORMATION

RIORXN1 AH10 I

RIORXP1 AH11 I

RIORXN2 AH14 I

RIORXP2 AH13 I

RIORXN3 AJ15 I

RIORXP3 AJ14 I

RIOTXN0 AF10 O

RIOTXP0 AF11 O

RIOTXN1 AG11 O

RIOTXP1 AG12 O

RIOTXN2 AG15 O

RIOTXP2 AG14 O

RIOTXN3 AF14 O

RIOTXP3 AF13 O

SGMII0RXN AJ18 I

SGMII0RXP AJ17 I

SGMII0TXN AG18 O

SGMII0TXP AG17 O

SGMII1RXN AH17 I

SGMII1RXP AH16 I

SGMII1TXN AF17 O

SGMII1TXP AF16 O

VCL M24 IOZ Voltage Control I

VD M23 IOZ Voltage Control I

VCNTL0 L23 OZ

VCNTL1 K23 OZ

VCNTL2 J23 OZ

VCNTL3 H23 OZ

SPISCS0 AG1 OZ UP SPI Interface Enable 0

SPISCS1 AG2 OZ UP SPI Interface Enable 1

SPICLK AE1 OZ Down SPI Clock

SPIDIN AD2 I Down SPI Data In

SPIDOUT AB1 OZ Down SPI Data Out

PCIexpress Transmit Data (2 links)

Serial RapidIO Receive Data (2 links)

Serial RapidIO Transmit Data (2 links)

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

Voltage Control Outputs to variable core power supply

Serial RapidIO

SGMII

SmartReflex

C Clock

C Data

SPI

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 11 of 13)

Signal Name Ball No. Type IPD/IPU Description

Timer

TIMI0 L24 I Down

TIMI1 L26 I Down

TIMO0 L25 OZ Down

TIMO1 M26 OZ Down

CLKA0 AF25 I Down

CLKB0 AG25 I Down

FSA0 AJ26 I Down

FSB0 AG26 I Down

TR00 AH26 I Down

TR01 AJ25 I Down

TR02 AD23 I Down

TR03 AD24 I Down

TR04 AC23 I Down

TR05 AH25 I Down

TR06 AC24 I Down

TR07 AE25 I Down

TX00 AE24 OZ Down

TX01 AD25 OZ Down

TX02 AJ24 OZ Down

TX03 AG24 OZ Down

TX04 AH24 OZ Down

TX05 AF24 OZ Down

TX06 AE23 OZ Down

TX07 AF23 OZ Down

Timer Inputs

Timer Outputs

TSIP

TSIP0

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-15 Terminal Functions — Signals and Control by Function (Part 12 of 13)

Signal Name Ball No. Type IPD/IPU Description

CLKA1 AJ23 I Down

CLKB1 AH23 I Down

FSA1 AG23 I Down

FSB1 AJ22 I Down

TR10 AE22 I Down

TR11 AD21 I Down

TR12 AC21 I Down

ADVANCE INFORMATION

TR13 AJ21 I Down

TR14 AH22 I Down

TR15 AJ20 I Down

TR16 AH21 I Down

TR17 AG21 I Down

TX10 AF21 OZ Down

TX11 AD22 OZ Down

TX12 AC22 OZ Down

TX13 AE21 OZ Down

TX14 AG20 OZ Down

TX15 AE20 OZ Down

TX16 AH20 OZ Down

TX17 AF20 OZ Down

UARTRXD AD1 I Down UART Serial Data In

UARTTXD AC1 OZ Down UART Serial Data Out

UARTCTS AB3 I Down UART Clear To Send

UARTRTS AB2 OZ Down UART Request To Send

RSV01 AH28 IOZ Down Reserved - leave unconnected

RSV02 N24 OZ Down Reserved - leave unconnected

RSV03 N23 OZ Down Reserved - leave unconnected

RSV04 AH2 O Reserved - leave unconnected

RSV05 AJ3 O Reserved - leave unconnected

RSV06 H28 O Reserved - leave unconnected

RSV07 G28 O Reserved - leave unconnected

RSV08 AH19 A Reserved - leave unconnected

RSV09 AF19 A Reserved - leave unconnected

RSV10 K22 A Reserved - leave unconnected

RSV11 J22 A Reserved - leave unconnected

RSV12 Y5 A Reserved - leave unconnected

RSV13 W5 A Reserved - leave unconnected

RSV14 W6 A Reserved - leave unconnected

RSV15 AE12 A Reserved - leave unconnected

RSV16 AC9 A Reserved - leave unconnected

RSV17 AD19 A Reserved - leave unconnected

RSV24 AH4 O Reserved - leave unconnected

TSIP1

www.ti.com

UART

Reserved

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 2-15 Terminal Functions — Signals and Control by Function (Part 13 of 13)

Signal Name Ball No. Type IPD/IPU Description

RSV25 AH3 O Reserved - leave unconnected

RSV20 AF3 OZ Down Reserved - leave unconnected

RSV21 G25 OZ Down Reserved - leave unconnected

RSV22 AF1 OZ Down Reserved - leave unconnected

End of Table 2-15

Table 2-16 Terminal Functions — Power and Ground

Supply Ball No. Volts Description

AVDDA1 H22 1.8 PLL Supply - CORE_PLL

AVDDA2 AC6 1.8 PLL Supply - DDR3_PLL

AVDDA3 AD5 1.8 PLL Supply - PASS_PLL

CVDD H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16,

L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12, AA14, AA16, AA18, AA22

CVDD1 J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16,

V13, V15, W12, W14, W16

DVDD15 A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28,

G2, G4, G8, G10, G12, G14, G16, G18, G20, G23

DVDD18 H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26,

AG22, AH1, AH29, AJ2, AJ28

VDDR1 V5 1.5 HyperLink SerDes regulator supply

VDDR2 AE10 1.5 PCIe SerDes regulator supply

VDDR3 AE16 1.5 SGMII SerDes regulator supply

VDDR4 AE14 1.5 SRIO SerDes regulator supply

VDDT1 M7, N6, P7, R6, T7, U6, V7 1.0 HyperLink SerDes termination

VDDT2 AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13,

AD15, AD17, AE18

VREFSSTL E14 0.75 DDR3 reference voltage

VSS A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1,

G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24, H1, H2, H3, H4, H5, H6, H8, H10, H12, H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6, K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2, M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17, N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13, R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11, U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9, W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15, AF18, AF22, AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10, AJ13, AJ16, AJ19, AJ29

End of Table 2-16

0.9 to

1.1

1.0 Fixed core supply voltage

1.5 DDR IO supply

1.8 IO supply

1.0 SGMII/SRIO/PCIe SerDes

GND Ground

SPRS708—November 2010

SmartReflex core supply voltage

supply

termination supply

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-17 Terminal Functions

— By Signal Name (Part 1 of 13)

Signal Name Ball Number

AVDDA1 H22

AVDDA2 AC6

AVDDA3 AD5

BOOTCOMPLETE AE2

BOOTMODE00 † J28

ADVANCE INFORMATION

BOOTMODE01† J29

BOOTMODE02 † J26

BOOTMODE03 † J25

BOOTMODE04 † J27

BOOTMODE05 † J24

BOOTMODE06 † K27

BOOTMODE07 † K28

BOOTMODE08 † K26

BOOTMODE09 † K29

BOOTMODE10 † L28

BOOTMODE11 † L29

BOOTMODE12 † K25

CLKA0 AF25

CLKA1 AJ23

CLKB0 AG25

CLKB1 AH23

CORECLKN AG4

CORECLKP AG3

CORESEL0 AF2

CORESEL1 AD4

CORESEL2 AE6

CORESEL3 AE5

CVDD H7, H9, H11, H13,

H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16, L18, M11, M13, M15, M17, M19, N8, N10, N12, N14,

CVDD N16, N18, P9, P11,

P13, P15, P17, P19, P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, V17, V19, V21, W8,

CVDD W10, W18, W20,

W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12, AA14, AA16, AA18, AA22

Table 2-17 Terminal Functions

Signal Name Ball Number

CVDD1 J8, J14, K7, K9, K13,

DDRA00 A14

DDRA01 B14

DDRA02 F14

DDRA03 F13

DDRA04 A15

DDRA05 C15

DDRA06 B15

DDRA07 D15

DDRA08 F15

DDRA09 E15

DDRA10 E16

DDRA11 D16

DDRA12 E17

DDRA13 C16

DDRA14 D17

DDRA15 C17

DDRBA0 A13

DDRBA1 B13

DDRBA2 C13

DDRCAS

DDRCB00 E19

DDRCB01 C20

DDRCB02 D19

DDRCB03 B20

DDRCB04 C19

DDRCB05 C18

DDRCB06 B18

DDRCB07 A18

DDRCE0

DDRCE1

DDRCKE0 D11

DDRCKE1 E18

DDRCLKN H29

DDRCLKOUTN0 B12

DDRCLKOUTN1 B16

DDRCLKOUTP0 A12

DDRCLKOUTP1 A16

DDRCLKP G29

— By Signal Name (Part 2 of 13)

K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16, V13, V15, W12, W14, W16

D12

C11

C12

www.ti.com

Table 2-17 Terminal Functions

—BySignalName (Part 3 of 13)

Signal Name Ball Number

DDRD00 E28

DDRD01 D29

DDRD02 E27

DDRD03 D28

DDRD04 D27

DDRD05 B28

DDRD06 E26

DDRD07 F25

DDRD08 F24

DDRD09 E24

DDRD10 E25

DDRD11 D25

DDRD12 D26

DDRD13 C26

DDRD14 B26

DDRD15 A26

DDRD16 F23

DDRD17 F22

DDRD18 D24

DDRD19 E23

DDRD20 A23

DDRD21 B23

DDRD22 C24

DDRD23 E22

DDRD24 D21

DDRD25 F20

DDRD26 E21

DDRD27 F21

DDRD28 D22

DDRD29 C21

DDRD30 B22

DDRD31 C22

DDRD32 E10

DDRD33 D10

DDRD34 B10

DDRD35 D9

DDRD36 E9

DDRD37 C9

DDRD38 B8

DDRD39 E8

DDRD40 A7

DDRD41 D7

www.ti.com

Table 2-17 Terminal Functions

— By Signal Name (Part 4 of 13)

Signal Name Ball Number

DDRD42 E7

DDRD43 C7

DDRD44 B7

DDRD45 E6

DDRD46 D6

DDRD47 C6

DDRD48 C5

DDRD49 A5

DDRD50 B4

DDRD51 A4

DDRD52 D4

DDRD53 E4

DDRD54 C4

DDRD55 C3

DDRD56 F4

DDRD57 D2

DDRD58 E2

DDRD59 C2

DDRD60 F2

DDRD61 F3

DDRD62 E1

DDRD63 F1

DDRDQM0 E29

DDRDQM1 C27

DDRDQM2 A25

DDRDQM3 A22

DDRDQM4 A10

DDRDQM5 A8

DDRDQM6 B5

DDRDQM7 B2

DDRDQM8 A20

DDRDQS0N C29

DDRDQS0P C28

DDRDQS1N B27

DDRDQS1P A27

DDRDQS2N B24

DDRDQS2P A24

DDRDQS3N B21

DDRDQS3P A21

DDRDQS4N B9

DDRDQS4P A9

DDRDQS5N A6

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-17 Terminal Functions

— By Signal Name (Part 5 of 13)

Signal Name Ball Number

DDRDQS5P B6

DDRDQS6N A3

DDRDQS6P B3

DDRDQS7N C1

DDRDQS7P D1

DDRDQS8N B19

DDRDQS8P A19

DDRODT0 D13

DDRODT1 E13

DDRRAS

DDRRESET

DDRSLRATE0 G27

DDRSLRATE1 H27

DDRWE

DVDD15 A2, A11, A17, A28,

DVDD18 H24, N28, P23, T23,

EMIFA00 T27

EMIFA01 T24

EMIFA02 U29

EMIFA03 T25

EMIFA04 U27

EMIFA05 U28

EMIFA06 U25

EMIFA07 U24

EMIFA08 V28

EMIFA09 V29

EMIFA10 V27

EMIFA11 V26

EMIFA12 V25

EMIFA13 V24

EMIFA14 W28

EMIFA15 W27

EMIFA16 W29

EMIFA17 W26

C10

E11

E12

B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28, G2, G4, G8, G10, G12, G14, G16, G18, G20, G23

U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26, AG22, AH1, AH29, AJ2, AJ28

Table 2-17 Terminal Functions

—BySignalName (Part 6 of 13)

Signal Name Ball Number

EMIFA18 W25

EMIFA19 W24

EMIFA20 W23

EMIFA21 Y29

EMIFA22 Y28

EMIFA23 U23

EMIFBE0

EMIFBE1

EMIFCE0

EMIFCE1

EMIFCE2

EMIFCE3

EMIFD00 Y27

EMIFD01 AB29

EMIFD02 AA29

EMIFD03 Y26

EMIFD04 AA27

EMIFD05 AB27

EMIFD06 AA26

EMIFD07 AA25

EMIFD08 Y25

EMIFD09 AB25

EMIFD10 AA24

EMIFD11 Y24

EMIFD12 AB23

EMIFD13 AB24

EMIFD14 AB26

EMIFD15 AC25

EMIFOE

EMIFRW

EMIFWAIT0 T29

EMIFWAIT1 T28

EMIFWE

EMU00 AC29

EMU01 AC28

EMU02 AC27

EMU03 AC26

EMU04 AD29

EMU05 AD28

EMU06 AD27

EMU07 AE29

EMU08 AE28

R24

R23

P25

R27

R28

R25

R26

P26

P24

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-17 Terminal Functions

— By Signal Name (Part 7 of 13)

Signal Name Ball Number

EMU09 AF29

EMU10 AE27

EMU11 AF28

EMU12 AG29

EMU13 AD26

ADVANCE INFORMATION

EMU14 AG28

EMU15 AG27

EMU16 AJ27

EMU17 AF27

EMU18 AH27

FSA0 AJ26

FSA1 AG23

FSB0 AG26

FSB1 AJ22

GPIO00 H25

GPIO01 J28

GPIO02 J29

GPIO03 J26

GPIO04 J25

GPIO05 J27

GPIO06 J24

GPIO07 K27

GPIO08 K28

GPIO09 K26

GPIO10 K29

GPIO11 L28

GPIO12 L29

GPIO13 K25

GPIO14 K24

GPIO15 L27

HOUT AD20

LENDIAN † H25

LRESETNMIEN

LRESET

MCMCLKN Y2

MCMCLKP W2

MCMREFCLKOUTN W1

MCMREFCLKOUTP Y1

MCMRXFLCLK W3

MCMRXFLDAT W4

MCMRXN0 U2

MCMRXN1 T1

M27

N26

Table 2-17 Terminal Functions

Signal Name Ball Number

MCMRXN2 M1

MCMRXN3 P2

MCMRXP0 T2

MCMRXP1 R1

MCMRXP2 N1

MCMRXP3 N2

MCMRXPMCLK Y3

MCMRXPMDAT Y4

MCMTXFLCLK AA1

MCMTXFLDAT AA3

MCMTXN0 M5

MCMTXN1 T4

MCMTXN2 R5

MCMTXN3 N4

MCMTXP0 N5

MCMTXP1 U4

MCMTXP2 T5

MCMTXP3 P4

MCMTXPMCLK AA2

MCMTXPMDAT AA4

MDCLK H26

MDIO G26

NMI

PACLKSEL AE4

PASSCLKN AJ4

PASSCLKP AJ5

PCIECLKN AH5

PCIECLKP AG5

PCIERXN0 AH7

PCIERXN1 AJ9

PCIERXP0 AH8

PCIERXP1 AJ8

PCIESSMODE0 † K24

PCIESSMODE1 † L27

PCIESSEN † L24

PCIETXN0 AF8

PCIETXN1 AG9

PCIETXP0 AF7

PCIETXP1 AG8

POR

PTV15 G22

RESETFULL

— By Signal Name (Part 8 of 13)

M25

AC20

N25

www.ti.com

Table 2-17 Terminal Functions

—BySignalName (Part 9 of 13)

Signal Name Ball Number

RESETSTAT N27

RESET

RIORXN0 AJ11

RIORXN1 AH10

RIORXN2 AH14

RIORXN3 AJ15

RIORXP0 AJ12

RIORXP1 AH11

RIORXP2 AH13

RIORXP3 AJ14

RIOTXN0 AF10

RIOTXN1 AG11

RIOTXN2 AG15

RIOTXN3 AF14

RIOTXP0 AF11

RIOTXP1 AG12

RIOTXP2 AG14

RIOTXP3 AF13

RSV01 AH28

RSV02 N24

RSV03 N23

RSV04 AH2

RSV05 AJ3

RSV06 H28

RSV07 G28

RSV08 AH19

RSV09 AF19

RSV0A AA21

RSV0B AA20

RSV10 K22

RSV11 J22

RSV12 Y5

RSV13 W5

RSV14 W6

RSV15 AE12

RSV16 AC9

RSV17 AD19

RSV20 AF3

RSV21 G25

RSV22 AF1

RSV24 AH4

RSV25 AH3

M29

www.ti.com

Table 2-17 Terminal Functions

— By Signal Name (Part 10 of 13)

Signal Name Ball Number

SCL AD3

SDA AC4

SGMII0RXN AJ18

SGMII0RXP AJ17

SGMII0TXN AG18

SGMII0TXP AG17

SGMII1RXN AH17

SGMII1RXP AH16

SGMII1TXN AF17

SGMII1TXP AF16

SPICLK AE1

SPIDIN AD2

SPIDOUT AB1

SPISCS0 AG1

SPISCS1 AG2

SRIOSGMIICLKN AJ6

SRIOSGMIICLKP AG6

SYSCLKOUT AE3

TCK N29

TDI P27

TDO R29

TIMI0 L24

TIMI1 L26

TIMO0 L25

TIMO1 M26

TMS P29

TR00 AH26

TR01 AJ25

TR02 AD23

TR03 AD24

TR04 AC23

TR05 AH25

TR06 AC24

TR07 AE25

TR10 AE22

TR11 AD21

TR12 AC21

TR13 AJ21

TR14 AH22

TR15 AJ20

TR16 AH21

TR17 AG21

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-17 Terminal Functions

— By Signal Name (Part 11 of 13)

Signal Name Ball Number

TRST P28

TX00 AE24

TX01 AD25

TX02 AJ24

TX03 AG24

TX04 AH24

TX05 AF24

TX06 AE23

TX07 AF23

TX10 AF21

TX11 AD22

TX12 AC22

TX13 AE21

TX14 AG20

TX15 AE20

TX16 AH20

TX17 AF20

UARTCTS AB3

UARTRTS AB2

UARTRXD AD1

UARTTXD AC1

VCL M24

VCNTL0 L23

VCNTL1 K23

VCNTL2 J23

VCNTL3 H23

VD M23

VDDR1 V5

VDDR2 AE10

VDDR3 AE16

VDDR4 AE14

VDDT1 M7, N6, P7, R6, T7,

U6, V7

VDDT2 AB9, AB11, AB13,

AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13, AD15, AD17, AE18

VREFSSTL E14

Table 2-17 Terminal Functions

—BySignalName (Part 12 of 13)

Signal Name Ball Number

VSS A1, A29, B11, B17,

B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1, G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24,

VSS H1, H2, H3, H4, H5,

H6, H8, H10, H12, H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6, K8, K10, K12, K14, K16,

VSS K18, K20, L1, L2, L3,

L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2, M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9,

VSS N11, N13, N15, N17,

N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13, R15, R17, R19, R21, T3, T6, T8, T10, T12,

VSS T14, T16, T18, T20,

T22, T26, U1, U3, U5, U7, U9, U11, U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9, W11,

VSS W13, W15, W17,

W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8,

VSS AB10, AB12, AB14,

AB16, AB18, AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AE7, AE8,

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-17 Terminal Functions

— By Signal Name (Part 13 of 13)

Signal Name Ball Number

VSS AE9, AE11, AE13,

ADVANCE INFORMATION

VSS AJ1, AJ7, AJ10,

End of Table 2-17

AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15, AF18, AF22AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18,

AJ13, AJ16, AJ19, AJ29

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 1 of 21)

Ball Number Signal Name

A1 VSS

A2 DVDD15

A3 DDRDQS6N

A4 DDRD51

A5 DDRD49

A6 DDRDQS5N

A7 DDRD40

A8 DDRDQM5

A9 DDRDQS4P

A10 DDRDQM4

A11 DVDD15

A12 DDRCLKOUTP0

A13 DDRBA0

A14 DDRA00

A15 DDRA04

A16 DDRCLKOUTP1

A17 DVDD15

A18 DDRCB07

A19 DDRDQS8P

A20 DDRDQM8

A21 DDRDQS3P

A22 DDRDQM3

A23 DDRD20

A24 DDRDQS2P

A25 DDRDQM2

A26 DDRD15

A27 DDRDQS1P

A28 DVDD15

A29 VSS

B1 DVDD15

B2 DDRDQM7

B3 DDRDQS6P

B4 DDRD50

B5 DDRDQM6

B6 DDRDQS5P

B7 DDRD44

B8 DDRD38

B9 DDRDQS4N

B10 DDRD34

B11 VSS

B12 DDRCLKOUTN0

B13 DDRBA1

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 2 of 21)

Ball Number Signal Name

B14 DDRA01

B15 DDRA06

B16 DDRCLKOUTN1

B17 VSS

B18 DDRCB06

B19 DDRDQS8N

B20 DDRCB03

B21 DDRDQS3N

B22 DDRD30

B23 DDRD21

B24 DDRDQS2N

B25 VSS

B26 DDRD14

B27 DDRDQS1N

B28 DDRD05

B29 DVDD15

C1 DDRDQS7N

C2 DDRD59

C3 DDRD55

C4 DDRD54

C5 DDRD48

C6 DDRD47

C7 DDRD43

C8 VSS

C9 DDRD37

C10 DDRRAS

C11 DDRCE0

C12 DDRCE1

C13 DDRBA2

C14 DVDD15

C15 DDRA05

C16 DDRA13

C17 DDRA15

C18 DDRCB05

C19 DDRCB04

C20 DDRCB01

C21 DDRD29

C22 DDRD31

C23 VSS

C24 DDRD22

C25 DVDD15

C26 DDRD13

Table 2-18 Terminal Functions

— By Ball Number (Part 3 of 21)

Ball Number Signal Name

C27 DDRDQM1

C28 DDRDQS0P

C29 DDRDQS0N

D1 DDRDQS7P

D2 DDRD57

D3 VSS

D4 DDRD52

D5 DVDD15

D6 DDRD46

D7 DDRD41

D8 DVDD15

D9 DDRD35

D10 DDRD33

D11 DDRCKE0

D12 DDRCAS

D13 DDRODT0

D14 VSS

D15 DDRA07

D16 DDRA11

D17 DDRA14

D18 VSS

D19 DDRCB02

D20 DVDD15

D21 DDRD24

D22 DDRD28

D23 DVDD15

D24 DDRD18

D25 DDRD11

D26 DDRD12

D27 DDRD04

D28 DDRD03

D29 DDRD01

E1 DDRD62

E2 DDRD58

E3 DVDD15

E4 DDRD53

E5 VSS

E6 DDRD45

E7 DDRD42

E8 DDRD39

E9 DDRD36

E10 DDRD32

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 4 of 21)

Ball Number Signal Name

E11 DDRRESET

E12 DDRWE

E13 DDRODT1

E14 VREFSSTL

E15 DDRA09

ADVANCE INFORMATION

E16 DDRA10

E17 DDRA12

E18 DDRCKE1

E19 DDRCB00

E20 VSS

E21 DDRD26

E22 DDRD23

E23 DDRD19

E24 DDRD09

E25 DDRD10

E26 DDRD06

E27 DDRD02

E28 DDRD00

E29 DDRDQM0

F1 DDRD63

F2 DDRD60

F3 DDRD61

F4 DDRD56

F5 DVDD15

F6 VSS

F7 DVDD15

F8 VSS

F9 DVDD15

F10 VSS

F11 DVDD15

F12 VSS

F13 DDRA03

F14 DDRA02

F15 DDRA08

F16 VSS

F17 DVDD15

F18 VSS

F19 DVDD15

F20 DDRD25

F21 DDRD27

F22 DDRD17

F23 DDRD16

Table 2-18 Terminal Functions

Ball Number Signal Name

F24 DDRD08

F25 DDRD07

F26 DVDD15

F27 VSS

F28 DVDD15

F29 VSS

G1 VSS

G2 DVDD15

G3 VSS

G4 DVDD15

G5 VSS

G6 VSS

G7 VSS

G8 DVDD15

G9 VSS

G10 DVDD15

G11 VSS

G12 DVDD15

G13 VSS

G14 DVDD15

G15 VSS

G16 DVDD15

G17 VSS

G18 DVDD15

G19 VSS

G20 DVDD15

G21 VSS

G22 PTV15

G23 DVDD15

G24 VSS

G25 RSV21

G26 MDIO

G27 DDRSLRATE0

G28 RSV07

G29 DDRCLKP

H1 VSS

H2 VSS

H3 VSS

H4 VSS

H5 VSS

H6 VSS

H7 CVDD

— By Ball Number (Part 5 of 21)

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 6 of 21)

Ball Number Signal Name

H8 VSS

H9 CVDD

H10 VSS

H11 CVDD

H12 VSS

H13 CVDD

H14 VSS

H15 CVDD

H16 VSS

H17 CVDD

H18 VSS

H19 CVDD

H20 VSS

H21 CVDD

H22 AVDDA1

H23 VCNTL3

H24 DVDD18

H25 GPIO00

H25 LENDIAN †

H26 MDCLK

H27 DDRSLRATE1

H28 RSV06

H29 DDRCLKN

J1 VSS

J2 VSS

J3 VSS

J4 VSS

J5 VSS

J6 VSS

J7 VSS

J8 CVDD1

J9 VSS

J10 CVDD

J11 VSS

J12 CVDD

J13 VSS

J14 CVDD1

J15 VSS

J16 CVDD

J17 VSS

J18 CVDD

J19 VSS

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 7 of 21)

Ball Number Signal Name

J20 CVDD

J21 VSS

J22 RSV11

J23 VCNTL2

J24 GPIO06

J24 BOOTMODE05 †

J25 GPIO04

J25 BOOTMODE03 †

J26 GPIO03

J26 BOOTMODE02 †

J27 GPIO05

J27 BOOTMODE04 †

J28 GPIO01

J28 BOOTMODE00 †

J29 GPIO02

J29 BOOTMODE01†

K1 VSS

K2 VSS

K3 VSS

K4 VSS

K5 VSS

K6 VSS

K7 CVDD1

K8 VSS

K9 CVDD1

K10 VSS

K11 CVDD

K12 VSS

K13 CVDD1

K14 VSS

K15 CVDD1

K16 VSS

K17 CVDD

K18 VSS

K19 CVDD

K20 VSS

K21 CVDD

K22 RSV10

K23 VCNTL1

K24 GPIO14

K24 PCIESSMODE0 †

K25 GPIO13

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 8 of 21)

Ball Number Signal Name

K25 BOOTMODE12 †

K26 GPIO09

K26 BOOTMODE08 †

K27 GPIO07

K27 BOOTMODE06 †

K28 GPIO08

K28 BOOTMODE07 †

K29 GPIO10

K29 BOOTMODE09 †

L1 VSS

L2 VSS

L3 VSS

L4 VSS

L5 VSS

L6 VSS

L7 VSS

L8 CVDD1

L9 VSS

L10 CVDD

L11 VSS

L12 CVDD

L13 VSS

L14 CVDD1

L15 VSS

L16 CVDD

L17 VSS

L18 CVDD

L19 VSS

L20 CVDD1

L21 VSS

L22 CVDD1

L23 VCNTL0

L24 TIMI0

L24 PCIESSEN †

L25 TIMO0

L26 TIMI1

L27 GPIO15

L27 PCIESSMODE1 †

L28 GPIO11

L28 BOOTMODE10 †

L29 GPIO12

L29 BOOTMODE11 †

Table 2-18 Terminal Functions

— By Ball Number (Part 9 of 21)

Ball Number Signal Name

M1 MCMRXN2

M2 VSS

M3 VSS

M4 VSS

M5 MCMTXN0

M6 VSS

M7 VDDT1

M8 VSS

M9 CVDD1

M10 VSS

M11 CVDD

M12 VSS

M13 CVDD

M14 VSS

M15 CVDD

M16 VSS

M17 CVDD

M18 VSS

M19 CVDD

M20 VSS

M21 CVDD1

M22 VSS

M23 VD

M24 VCL

M25 NMI

M26 TIMO1

M27 LRESETNMIEN

M28 VSS

M29 RESET

N1 MCMRXP2

N2 MCMRXP3

N3 VSS

N4 MCMTXN3

N5 MCMTXP0

N6 VDDT1

N7 VSS

N8 CVDD

N9 VSS

N10 CVDD

N11 VSS

N12 CVDD

N13 VSS

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 10 of 21)

Ball Number Signal Name

N14 CVDD

N15 VSS

N16 CVDD

N17 VSS

N18 CVDD

ADVANCE INFORMATION

N19 VSS

N20 CVDD1

N21 VSS

N22 CVDD1

N23 RSV03

N24 RSV02

N25 RESETFULL

N26 LRESET

N27 RESETSTAT

N28 DVDD18

N29 TCK

P1 VSS

P2 MCMRXN3

P3 VSS

P4 MCMTXP3

P5 VSS

P6 VSS

P7 VDDT1

P8 VSS

P9 CVDD

P10 VSS

P11 CVDD

P12 VSS

P13 CVDD

P14 VSS

P15 CVDD

P16 VSS

P17 CVDD

P18 VSS

P19 CVDD

P20 VSS

P21 CVDD

P22 VSS

P23 DVDD18

P24 EMIFWE

P25 EMIFCE0

P26 EMIFRW

Table 2-18 Terminal Functions

Ball Number Signal Name

P27 TDI

P28 TRST

P29 TMS

R1 MCMRXP1

R2 VSS

R3 VSS

R4 VSS

R5 MCMTXN2

R6 VDDT1

R7 VSS

R8 CVDD

R9 VSS

R10 CVDD

R11 VSS

R12 CVDD1

R13 VSS

R14 CVDD1

R15 VSS

R16 CVDD1

R17 VSS

R18 CVDD

R19 VSS

R20 CVDD

R21 VSS

R22 CVDD

R23 EMIFBE1

R24 EMIFBE0

R25 EMIFCE3

R26 EMIFOE

R27 EMIFCE1

R28 EMIFCE2

R29 TDO

T1 MCMRXN1

T2 MCMRXP0

T3 VSS

T4 MCMTXN1

T5 MCMTXP2

T6 VSS

T7 VDDT1

T8 VSS

T9 CVDD

T10 VSS

— By Ball Number (Part 11 of 21)

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 12 of 21)

Ball Number Signal Name

T11 CVDD

T12 VSS

T13 CVDD

T14 VSS

T15 CVDD

T16 VSS

T17 CVDD

T18 VSS

T19 CVDD

T20 VSS

T21 CVDD

T22 VSS

T23 DVDD18

T24 EMIFA01

T25 EMIFA03

T26 VSS

T27 EMIFA00

T28 EMIFWAIT1

T29 EMIFWAIT0

U1 VSS

U2 MCMRXN0

U3 VSS

U4 MCMTXP1

U5 VSS

U6 VDDT1

U7 VSS

U8 CVDD

U9 VSS

U10 CVDD

U11 VSS

U12 CVDD1

U13 VSS

U14 CVDD1

U15 VSS

U16 CVDD1

U17 VSS

U18 CVDD

U19 VSS

U20 CVDD

U21 VSS

U22 CVDD

U23 EMIFA23

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 13 of 21)

Ball Number Signal Name

U24 EMIFA07

U25 EMIFA06

U26 DVDD18

U27 EMIFA04

U28 EMIFA05

U29 EMIFA02

V1 VSS

V2 VSS

V3 VSS

V4 VSS

V5 VDDR1

V6 VSS

V7 VDDT1

V8 VSS

V9 CVDD

V10 VSS

V11 CVDD

V12 VSS

V13 CVDD1

V14 VSS

V15 CVDD1

V16 VSS

V17 CVDD

V18 VSS

V19 CVDD

V20 VSS

V21 CVDD

V22 VSS

V23 DVDD18

V24 EMIFA13

V25 EMIFA12

V26 EMIFA11

V27 EMIFA10

V28 EMIFA08

V29 EMIFA09

W1 MCMREFCLKOUTN

W2 MCMCLKP

W3 MCMRXFLCLK

W4 MCMRXFLDAT

W5 RSV13

W6 RSV14

W7 VSS

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 14 of 21)

Ball Number Signal Name

W8 CVDD

W9 VSS

W10 CVDD

W11 VSS

W12 CVDD1

W13 VSS

W14 CVDD1

W15 VSS

W16 CVDD1

W17 VSS

W18 CVDD

W19 VSS

W20 CVDD

W21 VSS

W22 CVDD

W23 EMIFA20

W24 EMIFA19

W25 EMIFA18

W26 EMIFA17

W27 EMIFA15

W28 EMIFA14

W29 EMIFA16

Y1 MCMREFCLKOUTP

Y2 MCMCLKN

Y3 MCMRXPMCLK

Y4 MCMRXPMDAT

Y5 RSV12

Y6 VSS

Y7 DVDD18

Y8 VSS

Y9 CVDD

Y10 VSS

Y11 CVDD

Y12 VSS

Y13 CVDD

Y14 VSS

Y15 CVDD

Y16 VSS

Y17 CVDD

Y18 VSS

Y19 CVDD

Y20 VSS

Table 2-18 Terminal Functions

— By Ball Number (Part 15 of 21)

Ball Number Signal Name

Y21 CVDD

Y22 VSS

Y23 DVDD18

Y24 EMIFD11

Y25 EMIFD08

Y26 EMIFD03

Y27 EMIFD00

Y28 EMIFA22

Y29 EMIFA21

AA1 MCMTXFLCLK

AA2 MCMTXPMCLK

AA3 MCMTXFLDAT

AA4 MCMTXPMDAT

AA5 VSS

AA6 DVDD18

AA7 VSS

AA8 CVDD

AA9 VSS

AA10 CVDD

AA11 VSS

AA12 CVDD

AA13 VSS

AA14 CVDD

AA15 VSS

AA16 CVDD

AA17 VSS

AA18 CVDD

AA19 VSS

AA20 RSV0B

AA21 RSV0A

AA22 CVDD

AA23 VSS

AA24 EMIFD10

AA25 EMIFD07

AA26 EMIFD06

AA27 EMIFD04

AA28 VSS

AA29 EMIFD02

AB1 SPIDOUT

AB2 UARTRTS

AB3 UARTCTS

AB4 VSS

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 16 of 21)

Ball Number Signal Name

AB5 DVDD18

AB6 VSS

AB7 DVDD18

AB8 VSS

AB9 VDDT2

ADVANCE INFORMATION

AB10 VSS

AB11 VDDT2

AB12 VSS

AB13 VDDT2

AB14 VSS

AB15 VDDT2

AB16 VSS

AB17 VDDT2

AB18 VSS

AB19 DVDD18

AB20 VSS

AB21 DVDD18

AB22 VSS

AB23 EMIFD12

AB24 EMIFD13

AB25 EMIFD09

AB26 EMIFD14

AB27 EMIFD05

AB28 DVDD18

AB29 EMIFD01

AC1 UARTTXD

AC2 VSS

AC3 DVDD18

AC4 SDA

AC5 VSS

AC6 AVDDA2

AC7 VSS

AC8 VDDT2

AC9 RSV16

AC10 VDDT2

AC11 VSS

AC12 VDDT2

AC13 VSS

AC14 VDDT2

AC15 VSS

AC16 VDDT2

AC17 VSS

Table 2-18 Terminal Functions

Ball Number Signal Name

AC18 VDDT2

AC19 VSS

AC20 POR

AC21 TR12

AC22 TX12

AC23 TR04

AC24 TR06

AC25 EMIFD15

AC26 EMU03

AC27 EMU02

AC28 EMU01

AC29 EMU00

AD1 UARTRXD

AD2 SPIDIN

AD3 SCL

AD4 CORESEL1

AD5 AVDDA3

AD6 VSS

AD7 VDDT2

AD8 VSS

AD9 VDDT2

AD10 VSS

AD11 VDDT2

AD12 VSS

AD13 VDDT2

AD14 VSS

AD15 VDDT2

AD16 VSS

AD17 VDDT2

AD18 VSS

AD19 RSV17

AD20 HOUT

AD21 TR11

AD22 TX11

AD23 TR02

AD24 TR03

AD25 TX01

AD26 EMU13

AD27 EMU06

AD28 EMU05

AD29 EMU04

AE1 SPICLK

— By Ball Number (Part 17 of 21)

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 18 of 21)

Ball Number Signal Name

AE2 BOOTCOMPLETE

AE3 SYSCLKOUT

AE4 PACLKSEL

AE5 CORESEL3

AE6 CORESEL2

AE7 VSS

AE8 VSS

AE9 VSS

AE10 VDDR2

AE11 VSS

AE12 RSV15

AE13 VSS

AE14 VDDR4

AE15 VSS

AE16 VDDR3

AE17 VSS

AE18 VDDT2

AE19 VSS

AE20 TX15

AE21 TX13

AE22 TR10

AE23 TX06

AE24 TX00

AE25 TR07

AE26 VSS

AE27 EMU10

AE28 EMU08

AE29 EMU07

AF1 RSV22

AF2 CORESEL0

AF3 RSV20

AF4 VSS

AF5 DVDD18

AF6 VSS

AF7 PCIETXP0

AF8 PCIETXN0

AF9 VSS

AF10 RIOTXN0

AF11 RIOTXP0

AF12 VSS

AF13 RIOTXP3

AF14 RIOTXN3

www.ti.com

Table 2-18 Terminal Functions

— By Ball Number (Part 19 of 21)

Ball Number Signal Name

AF15 VSS

AF16 SGMII1TXP

AF17 SGMII1TXN

AF18 VSS

AF19 RSV09

AF20 TX17

AF21 TX10

AF22 VSS

AF23 TX07

AF24 TX05

AF25 CLKA0

AF26 DVDD18

AF27 EMU17

AF28 EMU11

AF29 EMU09

AG1 SPISCS0

AG2 SPISCS1

AG3 CORECLKP

AG4 CORECLKN

AG5 PCIECLKP

AG6 SRIOSGMIICLKP

AG7 VSS

AG8 PCIETXP1

AG9 PCIETXN1

AG10 VSS

AG11 RIOTXN1

AG12 RIOTXP1

AG13 VSS

AG14 RIOTXP2

AG15 RIOTXN2

AG16 VSS

AG17 SGMII0TXP

AG18 SGMII0TXN

AG19 VSS

AG20 TX14

AG21 TR17

AG22 DVDD18

AG23 FSA1

AG24 TX03

AG25 CLKB0

AG26 FSB0

AG27 EMU15

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 2-18 Terminal Functions

— By Ball Number (Part 20 of 21)

Ball Number Signal Name

AG28 EMU14

AG29 EMU12

AH1 DVDD18

AH2 RSV04

AH3 RSV25

AH4 RSV24

AH5 PCIECLKN

AH6 VSS

AH7 PCIERXN0

AH8 PCIERXP0

AH9 VSS

AH10 RIORXN1

AH11 RIORXP1

AH12 VSS

AH13 RIORXP2

AH14 RIORXN2

AH15 VSS

AH16 SGMII1RXP

AH17 SGMII1RXN

AH18 VSS

AH19 RSV08

AH20 TX16

AH21 TR16

AH22 TR14

AH23 CLKB1

AH24 TX04

AH25 TR05

AH26 TR00

AH27 EMU18

AH28 RSV01

AH29 DVDD18

AJ1 VSS

AJ2 DVDD18

AJ3 RSV05

AJ4 PASSCLKN

AJ5 PASSCLKP

AJ6 SRIOSGMIICLKN

AJ7 VSS

AJ8 PCIERXP1

AJ9 PCIERXN1

AJ10 VSS

AJ11 RIORXN0

Table 2-18 Terminal Functions

— By Ball Number (Part 21 of 21)

Ball Number Signal Name

AJ12 RIORXP0

AJ13 VSS

AJ14 RIORXP3

AJ15 RIORXN3

AJ16 VSS

AJ17 SGMII0RXP

AJ18 SGMII0RXN

AJ19 VSS

AJ20 TR15

AJ21 TR13

AJ22 FSB1

AJ23 CLKA1

AJ24 TX02

AJ25 TR01

AJ26 FSA0

AJ27 EMU16

AJ28 DVDD18

AJ29 VSS

End of Table 2-18

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

2.9 Development

2.9.1 Development Support

In case the customer would like to develop their own features and software on the C6672 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

ADVANCE INFORMATION

• Software Development Tools: – Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools

– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software

needed to support any DSP application.

• Hardware Development Tools:

– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug) – EVM (Evaluation Module)

www.ti.com

2.9.2 Device Support

2.9.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications

• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification

• TMS: Fully qualified production device

Support tool development evolutionary flow:

• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification testing.

• TMDS: Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

3 Device Configuration

On the TMS320C6672 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.

3.1 Device Configuration at Device Reset

Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device

configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP.

Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal

pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.

Table 3-1 TMS320C6672 Device Configuration Pins

Configuration Pin Pin No. IPD/IPU

LENDIAN

BOOTMODE[12:0]

PCIESSMODE[1:0]

PCIESSEN

PACLKSEL

End of Table 3-1

1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on

2 These signal names are the secondary functions of these pins.

(1) (2)

(1)

pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.

H25 IPU Device endian mode (LENDIAN).

J28, J29, J26, J25, J27, J24, K27, K28, K26, K29, L28, L29,

K25

L27, K24 IPD PCIe Subsystem mode selection.

L24 IPD PCIe subsystem enable/disable.

AE4 IPD Packet accelerator subsystem clock select.

(1)

Functional Description

0 = Device operates in big endian mode 1 = Device operates in little endian mode

IPD Method of boot.

Some pins may not be used by bootloader and can be used as general purpose config pins. Refer to the Bootloader for the C66x DSP User Guide (literature number SPRUGY5) for how to determine the device enumeration ID value.

00 = PCIe in end point mode 01 = PCIe legacy end point (no support for MSI) 10 = PCIe in root complex mode 11 = Reserved

0 = PCIE Subsystem is disabled 1 = PCIE Subsystem is enabled

0 = SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS

PLL

1 = PASSCLK is used as the input to PASS PLL

ADVANCE INFORMATION

3.2 Peripheral Selection After Device Reset

Several of the peripherals on the TMS320C6672 are controlled by the Power Sleep Controller (PSC). By default, the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide (literature number SPRUGV4).

3.3 Device State Control Registers

The TMS320C6672 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-2.

ADVANCE INFORMATION

Table 3-2 Device State Control Registers (Part 1 of 3)

Address Start Address End Size Acronym Description

0x02620000 0x02620007 8B Reserved

0x02620008 0x02620017 16B Reserved

0x02620018 0x0262001B 4B JTAGID See section 3.3.3

0x0262001C 0x0262001F 4B Reserved

0x02620020 0x02620023 4B DEVSTAT See section 3.3.1

0x02620024 0x02620037 20B Reserved

0x02620038 0x0262003B 4B KICK0 See section 3.3.4

0x0262003C 0x0262003F 4B KICK1

0x02620040 0x02620043 4B DSP_BOOT_ADDR0 The boot address for C66x DSP CorePac 0

0x02620044 0x02620047 4B DSP_BOOT_ADDR1 The boot address for C66x DSP CorePac 1

0x02620048 0x0262004B 4B Reserved

0x0262004C 0x0262004F 4B Reserved

0x02620050 0x02620053 4B Reserved

0x02620054 0x02620057 4B Reserved

0x02620058 0x0262005B 4B Reserved

0x0262005C 0x0262005F 4B Reserved

0x02620060 0x026200DF 128B Reserved

0x026200E0 0x0262010F 48B Reserved

0x02620110 0x02620117 8B MACID See section 7.19 ‘‘Ethernet MAC (EMAC)’’ on page 190

0x02620118 0x0262012F 24B Reserved

0x02620130 0x02620133 4B LRSTNMIPIN See section 3.3.6

0x02620134 0x02620137 4B RESET_STAT_CLR See section 3.3.8

0x02620138 0x0262013B 4B Reserved

0x0262013C 0x0262013F 4B BOOTCOMPLETE See section 3.3.9

0x02620140 0x02620143 4B Reserved

0x02620144 0x02620147 4B RESET_STAT See section 3.3.7

0x02620148 0x0262014B 4B LRSTNMIPINSTAT See section 3.3.5

0x0262014C 0x0262014F 4B DEVCFG See section 3.3.2

0x02620150 0x02620153 4B PWRSTATECTL See section 3.3.10

0x02620154 0x0262017F 44B Reserved

0x02620180 0x02620183 4B Reserved

0x02620184 0x0262018F 12B Reserved

www.ti.com

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 3-2 Device State Control Registers (Part 2 of 3)

Address Start Address End Size Acronym Description

0x02620190 0x02620193 4B Reserved

0x02620194 0x02620197 4B Reserved

0x02620198 0x0262019B 4B Reserved

0x0262019C 0x0262019F 4B Reserved

0x026201A0 0x026201A3 4B Reserved

0x026201A4 0x026201A7 4B Reserved

0x026201A8 0x026201AB 4B Reserved

0x026201AC 0x026201AF 4B Reserved

0x026201B0 0x026201B3 4B Reserved

0x026201B4 0x026201B7 4B Reserved

0x026201B8 0x026201BB 4B Reserved

0x026201BC 0x026201BF 4B Reserved

0x026201C0 0x026201C3 4B Reserved

0x026201C4 0x026201C7 4B Reserved

0x026201C8 0x026201CB 4B Reserved

0x026201CC 0x026201CF 4B Reserved

0x026201D0 0x026201FF 48B Reserved

0x02620200 0x02620203 4B NMIGR0 See section 3.3.11

0x02620204 0x02620207 4B NMIGR1

0x02620208 0x0262020B 4B NMIGR2

0x0262020C 0x0262020F 4B NMIGR3

0x02620210 0x02620213 4B NMIGR4

0x02620214 0x02620217 4B NMIGR5

0x02620218 0x0262021B 4B NMIGR6

0x0262021C 0x0262021F 4B NMIGR7

0x02620220 0x0262023F 32B Reserved

0x02620240 0x02620243 4B IPCGR0 See section 3.3.12

0x02620244 0x02620247 4B IPCGR1

0x02620248 0x0262024B 4B IPCGR2

0x0262024C 0x0262024F 4B IPCGR3

0x02620250 0x02620253 4B IPCGR4

0x02620254 0x02620257 4B IPCGR5

0x02620258 0x0262025B 4B IPCGR6

0x0262025C 0x0262025F 4B IPCGR7

0x02620260 0x0262027B 28B Reserved

0x0262027C 0x0262027F 4B IPCGRH See section 3.3.14

0x02620280 0x02620283 4B IPCAR0 See section 3.3.13

0x02620284 0x02620287 4B IPCAR1

0x02620288 0x0262028B 4B IPCAR2

0x0262028C 0x0262028F 4B IPCAR3

0x02620290 0x02620293 4B IPCAR4

0x02620294 0x02620297 4B IPCAR5

0x02620298 0x0262029B 4B IPCAR6

0x0262029C 0x0262029F 4B IPCAR7

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 3-2 Device State Control Registers (Part 3 of 3)

Address Start Address End Size Acronym Description

0x026202A0 0x026202BB 28B Reserved

0x026202BC 0x026202BF 4B IPCARH See section 3.3.15

0x026202C0 0x026202FF 64B Reserved

0x02620300 0x02620303 4B TINPSEL See section 3.3.16

0x02620304 0x02620307 4B TOUTPSEL

0x02620308 0x0262030B 4B RSTMUX0 See section 3.3.18

0x0262030C 0x0262030F 4B RSTMUX1

ADVANCE INFORMATION

0x02620310 0x02620313 4B RSTMUX2

0x02620314 0x02620317 4B RSTMUX3

0x02620318 0x0262031B 4B RSTMUX4

0x0262031C 0x0262031F 4B RSTMUX5

0x02620320 0x02620323 4B RSTMUX6

0x02620324 0x02620327 4B RSTMUX7

0x02620328 0x0262032B 4B MAINPLLCTL0 See section 7.8 ‘‘Main PLL and PLL Controller’’ on page 207

0x0262032C 0x0262032F 4B Reserved

0x02620330 0x02620333 4B DDR3PLLCTL0 See section 7.9 ‘‘DD3 PLL’’ on page 220

0x02620334 0x02620337 4B Reserved

0x02620338 0x0262033B 4B PAPLLCTL0 See section 7.10 ‘‘PASS PLL’’ on page 222

0x0262033C 0x0262033F 4B Reserved

End of Table 3-2

www.ti.com

See section 3.3.17

3.3.1 Device Status Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR RESETFULL

pin. Once set, these bits will remain set until a power-on reset. The Device Status Register is shown in

Figure 3-1 and described in Table 3-3.

Figure 3-1 Device Status Register

31 18 17 16 15 14 13 1 0

Reserved PACLKSEL PCIESSEN PCIESSMODE[1:0 BOOTMODE[12:0] LENDIAN

R-0 R-x R/W-xx R/W-xxxxxxxxxxxx R-x

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 x indicates the bootstrap value latched via the external pin

Table 3-3 Device Status Register Field Descriptions (Part 1 of 2)

Bit Field Description

31-18 Reserved Reserved. Read only, writes have no effect.

17 PACLKSEL PA Clock select to select the reference clock for PA Sub-System PLL

0 = Selects PASSCLKP/N 1 = Selects output of Main PLL MUX (SYSCLK vs. ALTCORECLK - depending on CORECLKSEL pin)

16 PCIESSEN PCIe module enable

0 = PCIe module disabled 1 = PCIe module enabled

(1)

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 3-3 Device Status Register Field Descriptions (Part 2 of 2)

Bit Field Description

15-14 PCIESSMODE[1:0] PCIe Mode selection pins

00b = PCIe in End-point mode 01b = PCIe in Legacy End-point mode (no support for MSI) 10b = PCIe in Root complex mode 11b = Reserved

13-1 BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, refer to Section 2.5 ‘‘Boot

Modes Supported and PLL Settings’’ on page 27 and see the Bootloader for the C66x DSP User Guide (literature number SPRUGY5).

0 LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little

Endian mode (default).

0 = System is operating in Big Endian mode 1 = System is operating in Little Endian mode (default)

End of Table 3-3

3.3.2 Device Configuration Register

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in

Table 3-4.

SPRS708—November 2010

Figure 3-2 Device Configuration Register (DEVCFG)

31 10

Reserved SYSCLKOUTEN

R-0 R/W-1

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-4 Device Configuration Register Field Descriptions

Bit Field Description

31:1 Reserved Reserved. Read only, writes have no effect.

0 SYSCLKOUTEN SYSCLKOUT Enable

0 = No clock output 1 = Clock output enabled (default)

End of Table 3-4

3.3.3 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3 and described in Table 3-5.

Figure 3-3 JTAG ID (JTAGID) Register

31 28 27 12 11 1 0

VARIANT PART NUMBER MANUFACTURER LSB

R-0000 R-0000 0000 1001 1110b 0000 0010 111b R-1

Legend: RW = Read/Write; R = Read only; -n = value after reset

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 3-5 JTAG ID Register Field Descriptions

Bit Acronym Value Description

31-28 VARIANT 0000b Variant (4-Bit) value. The value of this field depends on the silicon revision being used.

27-12 PART NUMBER 0000 0000 1001 1110b Part Number for boundary scan

11-1 MANUFACTURER 0000 0010 111b Manufacturer

0 LSB 1b This bit is read as a 1 for TMS320C6672

End of Table 3-5

www.ti.com

ADVANCE INFORMATION

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on page 62 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable (the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg MMRs. In order to ensure protection to all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6.

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

31 18 17 16 15 2 1 0

Reserved NMI1 NMI0 Reserved LR1 LR0

R, +0000 0000 R-0 R-0 R, +0000 0000 R-0 R-0

Legend: R = Read only; -n = value after reset;

Table 3-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions

Bit Field Description

31-18 Reserved Reserved

17 NMI1 CorePac 1 in NMI

16 NMI0 CorePac 0 in NMI

15-2 Reserved Reserved

1 LR1 CorePac 1 in Local Reset

0 LR0 CorePac 0 in Local Reset

End of Table 3-6

and NMI based on

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

TMS320C6672

SPRS708—November 2010

The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET

and NMI based on CORESEL. The

LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

31 18 17 16 15 2 1 0

Reserved NMI1 NMI0 Reserved LR1 LR0

R, +0000 0000 WC,+0 WC,+0 R, +0000 0000 WC,+0 WC,+0

Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

Table 3-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions

Bit Field Description

31-18 Reserved Reserved

17 NMI1 CorePac 1 in NMI Clear

16 NMI0 CorePac 0 in NMI Clear

15-2 Reserved Reserved

1 LR1 CorePac 1 in Local Reset Clear

0 LR0 CorePac 0 in Local Reset Clear

End of Table 3-7

3.3.7 Reset Status (RESET_STAT) Register

The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives an local reset without receiving a global reset.

• In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

ADVANCE INFORMATION

The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.

Figure 3-6 Reset Status Register (RESET_STAT)

31 30 210

GR Reserved LR1 LR0

R, +1 R, + 000 0000 0000 0000 0000 0000 R,+0 R,+0

Legend: R = Read only; -n = value after reset

Table 3-8 Reset Status Register (RESET_STAT) Field Descriptions (Part 1 of 2)

Bit Field Description

31 GR Global reset status

0 = Device has not received a global reset. 1 = Device received a global reset.

30-2 Reserved Reserved.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 3-8 Reset Status Register (RESET_STAT) Field Descriptions (Part 2 of 2)

Bit Field Description

1 LR1 CorePac 1 reset status

0 = CorePac 1 has not received a local reset. 1 = CorePac 1 received a local reset.

0 LR0 CorePac 0 reset status

0 = CorePac 0 has not received a local reset. 1 = CorePac 0 received a local reset.

End of Table 3-8

www.ti.com

ADVANCE INFORMATION

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR)

31 30 210

GR Reserved LR1 LR0

RW, +0 R, + 000 0000 0000 0000 0000 0000 RW,+0 RW,+0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions

Bit Field Description

31 GR Global Reset Clear bit

30-2 Reserved Reserved.

1 LR1 CorePac 1 reset Clear bit

0 LR0 CorePac 0 reset Clear bit

End of Table 3-9

0 = Writing a 0 has no effect. 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.

0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

3.3.9 Boot Complete (BOOTCOMPLETE) Register

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-8 and described in

Table 3-10.

Figure 3-8 Boot Complete Register (BOOTCOMPLETE)

31 210

Reserved BC1 BC0

R, + 0000 0000 0000 0000 0000 0000 RW,+0 RW,+0

Legend: R = Read only; RW = Read/Write; -n = value after reset

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 3-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions

Bit Field Description

31-2 Reserved Reserved.

1 BC1 CorePac 1 boot status

0 = CorePac 1 boot NOT complete 1 = CorePac 1 boot complete

0 BC0 CorePac 0 boot status

0 = CorePac 0 boot NOT complete 1 = CorePac 0 boot complete

End of Table 3-10

The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before branching to the predefined location in memory.

3.3.10 Power State Control (PWRSTATECTL) Register

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from

Texas Instruments’’ on page 59 for more information. The Power State Control Register is shown in Figure 3-9 and

described in Table 3-11.

SPRS708—November 2010

Figure 3-9 Power State Control Register (PWRSTATECTL)

31 3 2 1 0

GENERAL_PURPOSE HIBERNATION_MODE HIBERNATION STANDBY

RW, +0000 0000 0000 0000 0000 0000 0000 0 RW,+0 RW,+0 RW,+0

Legend: RW = Read/Write; -n = value after reset

Table 3-11 Power State Control Register (PWRSTATECTL) Field Descriptions

Bit Field Description

31-3 GENERAL_PURPOSE Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User

Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

2 HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.

0 = Hibernation mode 1 1 = Hibernation mode 2

1 HIBERNATION Indicates whether the device is in hibernation mode or not.

0 = Not in hibernation mode 1 = Hibernation mode

0 STANDBY Indicates whether the device is in standby mode or not.

0 = Not in standby mode 1 = Standby mode

End of Table 3-11

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

3.3.11 NMI Even Generation to CorePac (NMIGRx) Register

NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6672 has two NMIGRx registers (NMIGR0 through NMIGR1). The NMIGR0 register generates an NMI event to CorePac0, the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI Even Generation to CorePac Register is shown in Figure 3-10 and described in Table 3-12.

Figure 3-10 NMI Generation Register (NMIGRx)

31 10

GENERAL_PURPOSE NMIG

ADVANCE INFORMATION

Legend: RW = Read/Write; -n = value after reset

Table 3-12 NMI Generation Register (NMIGRx) Field Descriptions

Bit Field Description

31-1 Reserved Reserved

0NMIG Reads return 0

Writes:

0 = No effect 1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.

End of Table 3-12

R, +0000 0000 0000 0000 0000 0000 0000 000 RW,+0

www.ti.com

3.3.12 IPC Generation (IPCGRx) Registers

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6672 has two IPCGRx registers (IPCGR0 through IPCGR1) registers. This can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an interrupt pulse to CorePacx (0 <= x <= 1).

These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Al location of sou rce bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.

Figure 3-11 IPC Generation Registers (IPCGRx)

31 30 29 28 27 8 7 6 5 4 3 1 0

SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 – SRCS4 SRCS3 SRCS2 RCS1 SRCS0 Reserved IPCG

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 3-13 IPC Generation Registers (IPCGRx) Field Descriptions

Bit Field Description

31-4 SRCSx Reads return current value of internal register bit.

Writes:

0 = No effect 1 = Sets both SRCSx and the corresponding SRCCx.

3-1 Reserved Reserved

0IPCG Reads return 0.

Writes:

0 = No effect 1 = Creates an Inter-DSP interrupt.

End of Table 3-13

3.3.13 IPC Acknowledgement (IPCARx) Registers

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

The C6672 has two IPCARx (IPCAR0 through IPCAR1) registers. These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in

Figure 3-12 and described in Table 3-14.

SPRS708—November 2010

Figure 3-12 IPC Acknowledgement Registers (IPCARx)

31 30 29 28 27 8 7 6 5 4 3 0

SRCC27 SRCC26 SRCC25 SRCC24 SRCC23 – SRCC4 SRCC3 SRCC2 RCC1 SRCC0 Reserved

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions

Bit Field Description

31-4 SRCCx Reads return current value of internal register bit.

Writes:

0 = No effect 1 = Clears both SRCCx and the corresponding SRCSx

3-0 Reserved Reserved

End of Table 3-14

3.3.14 IPC Generation Host (IPCGRH) Register

IPCGRH register is provided to facilitate host DSP interrupt. Operation and use of IPCGRH is the same as other IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event output (HOUT).

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (DSP/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 DSP/6 cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 DSP/6 cycle period. The IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.

Figure 3-13 IPC Generation Registers (IPCGRH)

31 30 29 28 27 8 7 6 5 4 3 1 0

SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 – SRCS4 SRCS3 SRCS2 RCS1 SRCS0 Reserved IPCG

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

ADVANCE INFORMATION

Table 3-15 IPC Generation Registers (IPCGRH) Field Descriptions

Bit Field Description

31-4 SRCSx Reads return current value of internal register bit.

Writes:

0 = No effect 1 = Sets both SRCSx and the corresponding SRCCx.

3-1 Reserved Reserved

0IPCG Reads return 0.

Writes:

0 = No effect 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

End of Table 3-15

www.ti.com

3.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in

Table 3-16.

Figure 3-14 IPC Acknowledgement Register (IPCARH)

31 30 29 28 27 8 7 6 5 4 3 0

SRCC27 SRCC26 SRCC25 SRCC24 SRCC23 – SRCC4 SRCC3 SRCC2 RCC1 SRCC0 Reserved

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-16 IPC Acknowledgement Register (IPCARH) Field Descriptions

Bit Field Description

31-4 SRCCx Reads return current value of internal register bit.

Writes:

0 = No effect 1 = Clears both SRCCx and the corresponding SRCSx

3-0 Reserved Reserved

End of Table 3-16

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

3.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown in Figure 3-15 and described in Table 3-17.

Figure 3-15 Timer Input Selection Register (TINPSEL)

31 876543210

Reserved TINPHSEL3 TINPLSEL3 TINPHSEL2 TINPLSEL2 TINPHSEL1 TINPLSEL1 TINPHSEL0 TINPLSEL0

RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +1 RW, +1 RW, +0

R = Read only; RW = Read/Write; -n = value after reset

Table 3-17 Timer Input Selection Field Description (TINPSEL)

Bit Field Description

31-8 Reserved Reserved

7 TINPHSEL3 Input select for TIMER3 high.

0 = TIMI0 1 = TIMI1

6 TINPLSEL3 Input select for TIMER3 low.

0 = TIMI0 1 = TIMI1

5 TINPHSEL2 Input select for TIMER2 high.

0 = TIMI0 1 = TIMI1

4 TINPLSEL2 Input select for TIMER2 low.

0 = TIMI0 1 = TIMI1

3 TINPHSEL1 Input select for TIMER1 high.

0 = TIMI0 1 = TIMI1

2 TINPLSEL1 Input select for TIMER1 low.

0 = TIMI0 1 = TIMI1

1 TINPHSEL0 Input select for TIMER0 high.

0 = TIMI0 1 = TIMI1

0 TINPLSEL0 Input select for TIMER0 low.

0 = TIMI0 1 = TIMI1

End of Table 3-17

SPRS708—November 2010

ADVANCE INFORMATION

3.3.17 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in Figure 3-16 and described in Table 3-18.

Figure 3-16 Timer Output Selection Register (TOUTPSEL)

31 109540

Reserved TOUTPSEL1 TOUTPSEL0

R,+000000000000000000000000 RW,+00001 RW,+00000

Legend: R = Read only; RW = Read/Write; -n = value after reset

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 3-18 Timer Output Selection Field Description (TOUTPSEL)

Bit Field Description

31-9 Reserved Reserved

9-5 TOUTPSEL1 Output select for TIMO1

00000: TOUTL0 00001: TOUTH0 00010: TOUTL1 00011: TOUTH1

4 Reserved Reserved

ADVANCE INFORMATION

4-0 TOUTPSEL0 Output select for TIMO0

00000: TOUTL0 00001: TOUTH0 00010: TOUTL1 00011: TOUTH1

End of Table 3-18

3.3.18 Reset Mux (RSTMUXx) Register

www.ti.com

00100: TOUTL2 00101: TOUTH2 00110: TOUTL3 00111: TOUTH3 01000 to 11111: Reserved

The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX1 for each of the two CorePacs on the C6672. These registers are located in Bootcfg memory space. The Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.

Figure 3-17 Reset Mux Register RSTMUXx

31 109 8754310

Reserved EVTSTATCLR Reserved DELAY EVTSTAT OMODE LOCK

R, +0000 0000 0000 0000 0000 00 RC, +0 R, +0 RW, +100 R, +0 RW, +000 RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset; RC

Table 3-19 Reset Mux Register Field Descriptions (Part 1 of 2)

Bit Field Description

31-10 Reserved Reserved

9 EVTSTATCLR 0 = Writing O had no effect

1 = Writing 1 to this bit clears the EVTSTAT bit

8 Reserved Reserved

7-5 DELAY 000b = 256 DSP/6 cycles delay between NMI & Local reset, when OMODE = 100b

001b = 512 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b 010b = 1024 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b 011b = 2048 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b 100b = 4096 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b (Default) 101b = 8192 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b 110b = 16384 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b 111b = 32768 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b

4 EVTSTAT 0 = No event received (Default)

1 = WD timer event received by Reset Mux block

= Read only and write 1 to clear

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 3-19 Reset Mux Register Field Descriptions (Part 2 of 2)

Bit Field Description

3-1 OMODE 000b = WD Timer Event input to the Reset Mux block does not cause any output event (Default)

001b = Reserved 010b = WD Timer Event input to the Reset Mux block causes local reset input to CorePac 011b = WD Timer Event input to the Reset Mux block causes NMI input to CorePac 100b = WD Timer Event input to the Reset Mux block causes NMI input followed by Local reset input to CorePac. Delay

between NMI and local reset is set in DELAY bit field. 101b = WD Timer Event input to the Reset Mux block causes Device Reset to C6672 110b = Reserved 111b = Reserved

0 LOCK 0 = Register fields are not locked (Default)

1 = Register fields are locked until the next timer reset

End of Table 3-19

TMS320C6672

SPRS708—November 2010

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

3.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

ADVANCE INFORMATION

For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V connected to the net. For a pullup resistor, this should be above the highest V A reasonable choice would be to target the V by definition, have margin to the V

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DV

and VIH levels.

www.ti.com

level of all inputs

level of all inputs on the net.

or VOH levels for the logic family of the limiting device; which,

rail.

For most systems:

•A 1-kΩ resistor can be used to op pose th e IPU /IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

), and the low-level/high-level input voltages (VIL and VIH) for

the TMS320C6672 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 91.

To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-15 ‘‘Terminal

Functions — Signals and Control by Function’’ on page 33.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

4 System Interconnect

On the TMS320C6672 device, the C66x CorePac, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.

4.1 Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer data. Similarly, the data bus can also be used to access the register space of a peripheral. For example, the DDR3 memory controller registers are accessed through their data bus interface.

The C66x CorePac, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves.

Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them. Examples of masters include the EDMA3 traffic controllers, SRIO, and EMAC. Examples of slaves include the SPI, UART, and I

The device contains two switch fabrics (the TeraNet) through which masters and slaves communicate. The data switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move data across the system (for more information, see Section 4.2 ‘‘Data Switch Fabric Connections’’). The data SCR is further divided into two smaller SCRs. One connects very high speed masters to slaves via 256-bit data buses running at a DSP/2 frequency. The other connects masters to slaves via 128-bit data buses running at a DSP/3 frequency. Peripherals that match the native bus width of the SCR it is connected to can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly used to access peripheral registers (for more information, see Section 4.3 ‘‘Configuration Switch Fabric’’). The configuration SCR connects the C66x CorePac and masters on the data switch fabric to slaves via 32-bit configuration buses running at a DSP/3 frequency. As with the data SCR, some peripherals require the use of a bridge to interface to the configuration SCR.

Bridges perform a variety of functions:

• Conversion between configuration bus and data bus.

• Width conversion between peripheral bus width and SCR bus width.

• Frequency conversion between peripheral bus frequency and SCR bus frequency.

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

4.2 Data Switch Fabric Connections

A detailed figure will be added here for a future release. Connection information is shown in the tables below.

Table 4-1 DSP/2 Data SCR Connection Matrix

Masters

TPCC0 TC0_RD Y Y Y N Y N N

TPCC0 TC0_WR Y Y Y N Y N N

ADVANCE INFORMATION

TPCC0 TC1_RD Y Y Y N N Y N

TPCC0 TC1_WR Y Y Y N N Y N

HyperLink_Master N Y Y YNNN

MSMC_master Y N N NNNY

From DSP/3 Data SCR Br_5 Y Y Y NNNN

From DSP/3 Data SCR Br_6 Y Y Y NNNN

From DSP/3 Data SCR Br_7 Y Y Y NNNN

From DSP/3 Data SCR Br_8 Y Y Y NNNN

From DSP/3 Data SCR Br_9 Y Y Y NNNN

From DSP/3 Data SCR Br_10 Y Y Y NNNN

End of Table 4-1

HyperLink_Slave MSMC_SMS MSMC_SES

www.ti.com

Slave

To DSP/3 Data SCR

Br_1 Br_2 Br_3 Br_4

Table 4-2 DSP/3 Data SCR Connection Matrix (Part 1 of 2)

Slaves

CorePac0_SDMA

CorePac1_SDMA

SRIO_Data_Slave

Boot ROM

SPI

PCIe Slave

QM Slave

HyperLink Slave

EMIF16

Br_5 (to DSP/2 Data SCR)

Br_6 (to DSP/2 Data SCR)

Br_7 (to DSP/2 Data SCR)

Br_8 (to DSP/2 Data SCR)

Br_9 (to DSP/2 Data SCR)

Br_10 (to DSP/2 Data SCR)

Br_12 (to Config SCR)

Masters

HyperLink Data YYYYYYYNYNNNNNNYNN

TPCC0_TC0_RD YYYYYYNYYNNNNNNYNN

TPCC0_TC0_WR Y YY NY Y NY Y NNNNNNY NN

TPCC0_TC1_RD YYYYYYNYYNNNNNNYNN

TPCC0_TC1_WR Y YY NY Y NY Y NNNNNNY NN

TPCC1_TC0_RD YYYYYYNYYYNNNNNYNN

TPCC1_TC0_WR Y YY NY Y NY Y Y NNNNNY NN

TPCC1_TC1_RD YYYYYYYYYNYNNNNNYN

TPCC1_TC1_WR YYYNYYYYYNYNNNNNYN

TPCC1_TC2_RD YYYYYYNYYNNYNNNNNY

TPCC1_TC2_WR Y YY NY Y NY Y NNY NNNNNY

TPCC1_TC3_RD YYYYYYNYYNNNYNNYNN

TPCC1_TC3_WR YYYNYYNYYNNNYNNYNN

TPCC2_TC0_RD YYYYYYNYYNNNNYNYNN

Br_13 (to Config SCR)

Br_14 (to Config SCR)

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 4-2 DSP/3 Data SCR Connection Matrix (Part 2 of 2)

Slaves

CorePac0_SDMA

CorePac1_SDMA

SRIO_Data_Slave

Boot ROM

SPI

PCIe Slave

QM Slave

HyperLink Slave

EMIF16

Br_5 (to DSP/2 Data SCR)

Br_6 (to DSP/2 Data SCR)

Masters

TPCC2_TC0_WR Y YY NY Y NY Y NNNNY NY NN

TPCC2_TC1_RD YYYYYYYYYNNNNNYNYN

TPCC2_TC1_WR YYYNYYYYYNNNNNYNYN

TPCC2_TC2_RD YYYYYYNYYYNNNNNYNN

TPCC2_TC2_WR Y YY NY Y NY Y Y NNNNNY NN

TPCC2_TC3_RD YYYYYYNYYNYNNNNNNY

TPCC2_TC3_WR YYYNYYNYYNYNNNNNNY

SRIO Messaging Y YNNNNY NYNNNNY NNNN

SRIO Data Master Y YNNY NYY YNNNNY NYNN

PCIe Master Y YNNY NYYY NNYNNNY NN

Packet Accelerator DataYY NNNNYNNNNNNNY NNN

MSMC Data (Br_4) YYYYYYYYYNNNNNNYNN

Queue Manager Y YNNNNY YNNNNY NNNNN

TSIP 0 Y YNNNNNNNY NNNNNNNN

TSIP 1 Y YNNNNNNNY NNNNNNNN

End of Table 4-2

Br_7 (to DSP/2 Data SCR)

SPRS708—November 2010

Br_8 (to DSP/2 Data SCR)

Br_9 (to DSP/2 Data SCR)

Br_10 (to DSP/2 Data SCR)

Br_12 (to Config SCR)

Br_13 (to Config SCR)

Br_14 (to Config SCR)

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

4.3 Configuration Switch Fabric

A detailed figure will be added here for a future release. All masters can talk to all slaves on the configuration switch fabric.

4.4 Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers will be present to allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority - PRI = 000b = urgent, PRI = 111b = low.

ADVANCE INFORMATION

All other masters provide their priority directly and do not need a default priority setting. Examples include the CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA based peripherals also have internal registers to define the priority level of their initiated transactions.

The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-1 and

Table 4-3.

Figure 4-1 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)

31 16 15 10 9 8 7 4 3 2 0

R/W-00000000000000000000001000011 RW-000

Legend: R = Read only; R/W = Read/Write; -n = value after reset

Table 4-3 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions

Bit Acronym Description

31-10 Reserved Reserved.

2-0 PKDTDMA_PRI Control the priority level for the transactions from Packet DMA Master port, which access the external linking

RAM.

End of Table 4-3

Reserved PKTDMA_PRI

For all other modules, see the respective User Guides in “Related Documentation from Texas Instruments” on

page 59 for programmable priority registers.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

5 C66x CorePac

The C66x CorePac consists of several components:

• The C66x DSP and associated C66x CorePac core

• Level-one and level-two memories (L1P, L1D, L2)

• Data Trace Formatter (DTF)

• Embedded Trace Buffer (ETB)

• Interrupt controller

• Power-down controller

• External memory controller

• Extended memory controller

• A dedicated power/sleep controller (LPSC)

The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.

Figure 5-1 C66x CorePac Block Diagram

32KB L1P

Boot

Controller

LPSCPLLC

GPSC

Program Memory Controller (PMC)With

Memory Protect/Bandwidth Mgmt

C66x DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control

In-Circuit Emulation

Instruction Decode

Data Path A

A Register File

A31-A16

A15-A0

.M1

.L1 .S1

xxxx.D1 .D2

Data Memory Controller (DMC)With

Memory Protect/Bandwidth Mgmt

Registers

Data Path B

B Register File

B31-B16

B15-B0

.M2

xxxx.S2 .L2

ller

ion Contro

d Except

Interrupt an

ller (UMC)

UnifiedMemory

Contro

ller (XMC)

ExtendedMemory

Contro

lMemory

ller (EMC)

Contro

Externa

L2 Cache/

SRAM

512KB

ADVANCE INFORMATION

MSM

SRAM

4096KB

DDR3

SRAM

DMASwitch

Fabric

CFG Switch

Fabric

32KB L1D

For more detailed information on the TMS320C66x CorePac on the C6672 device, see the C66x CorePac User Guide (literature number SPRUGW0).

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

5.1 Memory Architecture

Each C66x CorePac of the TMS320C6672 device contains a 512KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory (MSM). All memory on the C6672 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map

Summary for TMS320C6672’’ on page 19.

The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

ADVANCE INFORMATION

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader for the C66x DSP User Guide (literature number SPRUGY5).

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide (literature number

SPRUGY8).

5.1.1 L1P Memory

The L1P memory configuration for the C6672 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

Figure 5-2 shows the available SRAM/cache configurations for L1P.

Figure 5-2 TMS320C6672 L1P Memory Configurations

L1P mode bits

000 001 010 011 100

SRAM

3/4

SRAM

mapped

direct

mapped

cache

All

SRAM

7/8

SRAM

cache

1/2

direct

cache

direct

mapped

cache

L1P memory

16K bytes

8K bytes

4K bytes

Block base address

00E0 0000h

00E0 4000h

00E0 6000h

00E0 7000h

00E0 8000h

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

5.1.2 L1D Memory

The L1D memory configuration for the C6672 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1D.

Figure 5-3 TMS320C6672 L1D Memory Configurations

L1D mode bits

000 001 010 011 100

L1D memory

TMS320C6672

SPRS708—November 2010

Block base address

00F0 0000h

1/2

SRAM

3/4

SRAM

2-way cache

All

SRAM

7/8

SRAM

2-way

cache

5.1.3 L2 Memory

The L2 memory configuration for the C6672 device is as follows:

• Total memory size is 4096KB

• Each core contains 512KB of memory

• Local starting address for each core is 0080 0000h

16K bytes

00F0 4000h

8K bytes

00F0 6000h

4K bytes

00F0 7000h

4K bytes

00F0 8000h

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

Figure 5-4 TMS320C6672 L2 Memory Configurations

L2 Mode Bits

000 001 010 011 100

ADVANCE INFORMATION

101

L2 Memory

www.ti.com

Block Base Address

0080 0000h

ALL

SRAM

15/16

SRAM

4-Way

Cache

7/8

SRAM

4-Way Cache

3/4

SRAM

4-Way Cache

1/2

SRAM

4-Way Cache

ALL

Cache

4-Way

Cache

256Kbytes

128Kbytes

64Kbytes

32Kbytes

0084 0000h

0086 0000h

0087 0000h

0087 8000h

0087 FFFFh

Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.

For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000 and for C66x CorePac Core 1 this is equivalent to 0x11800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

5.1.4 MSMC SRAM

The MSMC SRAM configuration for the C6672 device is as follows:

• Memory size is 4096KB

• The MSMC SRAM can be configured as shared L2 and/or shared L3 memory

• Allows extension of external addresses from 2GB to up to 8GB

• Has built in memory protection features

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide (literature number SPRUGW7).

5.1.5 L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

SPRS708—November 2010

5.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 5-1.

Table 5-1 Available Memory Page Protection Schemes

AIDx Bit Local Bit Description

0 0 No access to memory page is permitted.

0 1 Only direct access by DSP is permitted.

1 0 Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).

1 1 All accesses permitted.

End of Table 5-1

Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

• Block the access — reads return zero, writes are ignored

• Capture the initiator in a status register — ID, address, and access type are stored

• Signal event to DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User Guide (literature number SPRUGW0).

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

5.3 Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware:

• Level 1 Program (L1P) SRAM/Cache

• Level 1 Data (L1D) SRAM/Cache

• Level 2 (L2) SRAM/Cache

• Memory-mapped registers configuration bus

ADVANCE INFORMATION

The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x CorePac. These operations are:

• DSP-initiated transfers

• User-programmed cache coherency operations

• IDMA-initiated transfers

The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC) System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities, see section 4.4 ‘‘Bus Priorities’’ on page 80 for more details.

More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac User Guide (literature number SPRUGW0.)

5.4 Power-Down Control

The C66x CorePac supports the ability to power-down various parts of the C66x CorePac. The power-down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power requirements.

Note—The C6672 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac Reference Guide (literature number SPRUGW0).

5.5 C66x CorePac Resets

Table 5-2 shows the reset types supported on the C6672 device and how they affect the resetting of the CorePac,

either both globally or just locally.

Table 5-2 C66x CorePac Reset (Global or Local)

Reset Type Global C66x CorePac Reset Local C66x CorePac Reset

Power-On Reset Y Y

Warm Reset Y Y

System Reset Y Y

DSP Reset N Y

End of Table 5-2

For more detailed information on the global and local C66x CorePac resets, see the C66x CorePac Reference Guide (literature number SPRUGW0). And for more detailed information on device resets, see section 7.7 ‘‘Reset

Controller’’ .

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

5.6 C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Table 5-3 and described in Table 5-4. The C66x CorePac revision is dependant on the silicon revision being used.

Table 5-3 CorePac Revision ID Register (MM_REVID)

Address - 0181 2000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Acronym

(1)

Reset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Acronym

(1)

Reset

1 R/W = Read/Write; R = Read only; -n = value after reset

Table 5-4 CorePac Revision ID Register (MM_REVID) Field Descriptions

Bit Acronym Value Description

31:16 VERSION - Version of the C66x CorePac implemented on the device.

15:0 REVISION - Revision of the C66x CorePac version implemented on the device.

End of Table 5-4

VERSION

R-h

REVISION

R-n

5.7 C66x CorePac Register Descriptions

See the C66x CorePac Reference Guide (literature number SPRUGW0) for register offsets and definitions.

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

ADVANCE INFORMATION

www.ti.com

6 Device Operating Conditions

6.1 Absolute Maximum Ratings

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

Table 6-1 Absolute Maximum Ratings

Over Operating Case Temperature Range (Unless Otherwise Noted)

) range:

(2)

(3)

: -65°C to 150°C

stg

Supply voltage range

Input voltage (V

Output voltage (V

Operating case temperature range, T

Overshoot/undershoot

Storage temperature range, T

End of Table 6-1

1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the

device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated

conditions for extended periods may affect device reliability. 2 All voltage values are with respect to VSS. 3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and

maximum undershoot value would be VSS - 0.20 × DVDD18

(1)

CVDD -0.3 V to TBD V

CVDD1 -0.3 V to TBD V

DVDD15 -0.3 V to TBD V

DVDD18 -0.3 V to TBD V

VREFSSTL 0.49 × DVDD15 to 0.51 × DV

VDDT1, VDDT2, VDDT3

VDDT4, VDDT5, VDDT6

VDDR1, VDDR2, VDDR3 -0.3 V to TBD V

AVDDA1, AVDDA2, AVDDA3

VSS Ground 0 V

LVCMOS (1.8V) -0.3 V to TBD V

DDR3 -0.3 V to TBD V

C -0.3 V to TBD V

LVDS -0.3 V to TBD V

LJCB -0.3 V to TBD V

SERDES -0.3 V to TBD V

LVCMOS (1.8V) -0.3 V to TBD V

DDR3 -0.3 V to TBD V

C -0.3 V to TBD V

SERDES -0.3 V to TBD V

Commercial 0°C to 85°C

Extended -40°C to 100°C

LVCMOS (1.8V)

DDR3

20% Overshoot/Undershoot for 20% of

Signal Duty Cycle

DD15

-0.3 V to TBD V

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

6.2 Recommended Operating Conditions

www.ti.com

Table 6-2 Recommended Operating Conditions

CVDD Core Supply

CVDD1 SR Core Supply 0.95 1 1.05 V

DVDD18 1.8-V supply I/O voltage 1.71 1.8 1.89 V

DVDD15 1.5-V supply I/O voltage 1.425 1.5 1.575 V

ADVANCE INFORMATION

VREFSSTL DDR3 reference voltage 0.49 × DVDD15 0.5 × DVDD15 0.51 × DVDD15 V

(3)

DDRx

DDAx

DDTx

Ground 0 0 0 V

Operating case temperature

End of Table 6-2

1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE

802.3ae-2002. 2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002. 3 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.

SerDes regulator supply 1.425 1.5 1.575 V

PLL analog supply 1.71 1.8 1.89 V

SerDes termination supply 0.95 1 1.05 V

LVCMOS (1.8 V) 0.65 × DVDD18 V

C 0.7 × DVDD18 V

High-level input voltage

Low-level input voltage

DDR3 EMIF VREFSSTL + 0.1 V

LVCMOS (1.8 V) 0.35 × DVDD18 V

DDR3 EMIF -0.3 VREFSSTL - 0.1 V

C 0.3 × DVDD18 V

Commercial

Extended -40 100 °C

(1) (2)

Min Nom Max Unit

DSP at 1 GHz 0.95 1 1.05

DSP at 800 MHz 0.855 0.9 0.945

085°C

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

6.3 Electrical Characteristics

Table 6-3 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Parameter Test Conditions

High-level output voltage

LVCMOS (1.8 V) I

2C (2)

LVCMOS (1.8 V) I

= IOH DV

= IOL 0.45

VOLLow-level output voltage

= 3 mA, pulled up to 1.8 V 0.4

No IPD/IPU -5 5 μA

(3)

Input current [DC]

LVCMOS (1.8 V)

Internal pullup 50 100 170

Internal pulldown -170 -100 -50

0.1 × DVDD18 V < V DVDD18 V

TBD TBD

High-level output current [DC]

TBD TBD

Low-level output current [DC]

TBD TBD

(4)

Off-state output current [DC] LVCMOS (1.8 V) -2 2 μA

(1)

< 0.9 ×

Min Typ Max Unit

- 0.45

DD18

- 0.4

DD15

-10 10 μA

VDDR3 DV

VDDR3 0.4

ADVANCE INFORMATION

End of Table 6-3

1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

2 I

C uses open collector IOs and does not have a V

3II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and

off-state (Hi-Z) output leakage current.

4IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

Minimum.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

ADVANCE INFORMATION

www.ti.com

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

SPRS708—November 2010

7 TMS320C6672 Peripheral Information and Electrical Specifications

This chapter covers the various peripherals on the TMS320C6672 DSP. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

7.1 Parameter Information

This section describes the conditions used to capture the electrical data seen in this chapter.

The data manual provides timing at the device pin. For output analysis, the transmission line and associated parasitics (vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design. For recommended transmission line lengths, see the appropriate application notes, user guides, and design guides. A transmission line delay of 2 ns was used for all output measurements, except the DDR3, which was evaluated using a 528-ps delay.

Figure 7-1 represents all device outputs, except differential or I

Figure 7-1 Test Load Circuit for AC Timing Measurements

Device

DDR3 Output Test Load

Transmission Line

Zo=50W

4pF

Data Manual Timing

Reference Point

(Device Terminal)

Device

Output Test Load Excluding DDR3

Transmission Line

Zo=50W

5pF

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

7.1.1 1.8-V Signal Transition Levels

All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.

Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements

ADVANCE INFORMATION

V = 0.9 V

ref

TMS320C6672

)

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels

7.1.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board

ADVANCE INFORMATION

design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number TBD). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 7-1 and Figure 7-4).

Table 7-1 Board-Level Timing Example

(see Figure 7-4)

No. Description

1 Clock route delay

2 Minimum DSP hold time

3 Minimum DSP setup time

4 External device hold time requirement

5 External device setup time requirement

6 Control signal route delay

7 External device hold time

8 External device access time

9 DSP hold time requirement

10 DSP setup time requirement

11 Data route delay

End of Table 7-1

V = V MIN (or V MIN

ref IH OH

www.ti.com

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Figure 7-4 shows a general transfer between the DSP and an external device. The figure also shows board route

delays and how they are perceived by the DSP and the external device

Figure 7-4 Board-Level Input/Output Timings

AECLKOUT

(Output from DSP)

AECLKOUT

(Input to External Device)

Control Signals

(Output from DSP)

Control Signals

(Input to External Device)

Data Signals

(Output from External Device)

Data Signals

(Input to DSP)

(A)

(B)

SPRS708—November 2010

(A) Control signals include data for writes. (B) Data signals are generated during reads from an external device.

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

7.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.

7.3 Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the C6672. The various power supply rails and their primary function is listed in Table 7-2 below.

Table 7-2 Power Supply Rails on TMS320C6672

ADVANCE INFORMATION

Name Primary Function Voltage Notes

CVDD SmartReflex core supply voltage 0.9 - 1.1 V Includes core voltage for DDR3 module

CVDD1 Core supply voltage for memory

array

VDDT1 HyperLink SerDes termination

supply

VDDT2 SGMII/SRIO/PCIE SerDes

termination supply

DVDD15 1.5-V DDR3 IO supply 1.5 V

VDDR1 HyperLink SerDes regulator supply 1.5 V Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

VDDR2 PCIE SerDes regulator supply 1.5 V Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE

VDDR3 SGMII SerDes regulator supply 1.5 V Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

VDDR4 SRIO SerDes regulator supply 1.5 V Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO

VDDR6

DVDD18 1.8-V IO supply 1.8V

AVDDA1 Main PLL supply 1.8 V Filtered version of DVDD18. Special considerations for noise.

AVDDA2 DDR3 PLL supply 1.8 V Filtered version of DVDD18. Special considerations for noise.

AVDDA3 PASS PLL supply 1.8 V Filtered version of DVDD18. Special considerations for noise.

VREFSSTL 0.75-V DDR3 reference voltage 0.75 V Should track the 1.5-V supply. Use 1.5 V as source.

VSS Ground GND

End of Table 7-2

1.0 V Fixed supply at 1.0 V

1.0 V Filtered version of CVDD1. Special considerations for noise. Filter is not needed if

www.ti.com

HyperLink is not in use.

SGMII/SRIO/PCIE is not in use.

HyperLink is not in use.

is not in use.

SGMII is not in use.

is not in use.

7.3.1 Power-Supply Sequencing

This section defines the requirements for a power up sequencing from a Power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.

1. CVDD

2. CVDD1, VDDT1-3

3. DVDD18, AVDD1, AVDD2 (HHV)

4. DVDD15, VDDR1-6

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

1. DVDD18, AVDD1, AVDD2 (HHV)

2. CVDD

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

3. CVDD1, VDDT1-3

4. DVDD15, VDDR1-6

The device initialization is broken into two phases. The first phase consists of the time period from the activation of the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR

must be held low for the entire

power stabilization phase.

SPRS708—November 2010

This is followed by the device initialization phase. Either POR

or RESETFULL may be used to trigger the end of the initialization phase, but both must be inactive for the initialization to complete. The differences between POR

-controlled initialization and RESETFULL initialization are described below. The following section has a mention of REFCLK in many places. REFCLK here refers to the clock input that has been selected as the source for the Main PLL. See Figure 7-23 for more details.

For more information on Power Supply sequencing see the Hardware Design Guide for KeyStone Devices (literature number SPRABI2).

7.3.1.1 POR-Controlled Device Initialization

The timing diagrams in the figures below show the power sequencing and reset control of the device when RESETFULL

is held high and POR is used to control the device initialization. In this mode, POR must be held low until the power has been stable for the required 100 μsec and the device initialization requirements have been met. On the rising edge of POR and pulls. The POR

, the HHV signal will go inactive allowing the core to control the state of the output buffers

must be held for the 100 μsec after the power has stabilized plus the time period between that100 μsec and when the clock is active in addition to the 16 μsec following the active clock. If the clock becomes active before the 100 μsec stabilization period has expired, only the additional 16 μsecs of POR

is required to complete

initialization.

Note—REFCLK must always be active before POR can be removed.

7.3.1.1.1 Core-Before-IO Power Sequencing

ADVANCE INFORMATION

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

The timing diagram for core-before-IO power sequencing is shown in Figure 7-5 and defined in Table 7-3.

Figure 7-5 POR-Controlled Power Sequencing — Core Before IO

Power Stabilization Phase C hip Initializ ation Phas e

PORz

RESETFULLz

ADVANCE INFORMATION

RESET z

C VDD(core AVS)

CVDD1 (core constant)

DVDD18 (1.8V)

DVDD15 (1 .5V)

t2b

t4b

t2a

t4a

t2c

www.ti.com

REFC LKP&N

DDRCLKP&N

RES ETSTA Tz

PORz Controlled Reset Sequencing – Core before IO

Table 7-3 POR-Controlled Power Sequencing — Core Before IO (Part 1 of 2)

Time System State

t1 Begin Power Stabilization Phase

• CVDD (core AVS) ramps up.

•POR

must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from

POR

) is put into the reset state.

t2a • CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is

t2b • Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be

t2c • The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR

t3 • DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).

t4a • DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the

permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD (core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.

driven with a valid clock or be held in a static state with one leg high and one leg low.

goes high

specified by t7.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.

voltage for DVDD15 must never exceed DVDD18.

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com

Table 7-3 POR-Controlled Power Sequencing — Core Before IO (Part 2 of 2)

Time System State

t4b • RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR controlled boot both RESETFULL and RESET

t5 • POR

must be high before POR

must continue to remain low for at least 100 μs after power has stabilized.

is driven high.

End Power Stabilization Phase

t6 • Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay

of an additional 16 μs is required before a rising edge of POR

t7 • The rising edge of POR

• Once device initialization and the efuse farm scan are complete, the RESETSTAT

will remove the reset to the efuse farm, allowing the scan to begin.

. The clock must be active during the entire 16 μs.

signal is driven high. This delay will be 10000 to 50000

clock cycles.

End Device Initialization Phase

End of Table 7-3

7.3.1.1.2 IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in Figure 7-6 and defined in Table 7-4.

Figure 7-6 POR-Controlled Power Sequencing — IO Before Core

SPRS708—November 2010

PORz

RESETF ULLz

RESETz

CVDD(core AVS)

CVDD1 ( core constant)

DVDD18 (1.8V)

DVDD15 (1.5V)

REFCLKP&N

DDRCLKP&N

RESETSTATz

Power Stabilization Phase C hip Initialization Phase

t2a

t3a

t2b

t3b

t3c

ADVANCE INFORMATION

PORz Controlled Reset Sequencing – IO before Core

TMS320C6672

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS708—November 2010

www.ti.com

Table 7-4 POR

Time System State

t1 Begin Power Stabilization Phase

• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).

•Since POR

• Filtered versions of 1.8V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before

t2a • RESETFULL

ADVANCE INFORMATION

t2b • CVDD (core AVS) ramps up.

t3a • CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD

t3b • Once CVDD is valid the clock drivers should be enabled. Although the clock inputs are not necessary at this time they should either be

t3c • The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR

t4 • DVDD15 (1.5 V) supply is ramped up following CVDD1.

t5 • POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

t6 Begin Device Initialization

• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay

•POR

t7 • The rising edge of the POR

• Once device initialization and the efuse farm scan are complete, the RESETSTAT

End Device Initialization Phase

End of Table 7-4

-Controlled Power Sequencing — IO Before Core

is low all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must

remain low through Power Stabilization Phase.

DVDD18 could cause damage to the device.

and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR-controlled boot both RESETFULL and RESET

must be high before POR

voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the specified draw of CVDD1.

driven with a valid clock or held is a static state with one leg high and one leg low.

specified by t7.

of an additional 16 μs is required before a rising edge of POR

must remain low.

clock cycles.

is driven high.

will remove the reset to the efuse farm allowing the scan to begin.

goes high

. The clock must be active during the entire 16 μs.

signal is driven high. This delay will be 10000 to 50000

7.3.1.2 RESETFULL-Controlled Device Initialization

The timing diagrams in the figures below show the power sequencing and reset control of the device when RESETFULL stable for the required 100 μsec, but RESETFULL been met. On the rising edge of POR

Note—REFCLK must always be active before POR can be removed.

7.3.1.2.1 Core-Before-IO Power Sequencing

is used to extend device initialization. In this mode, POR may be removed after the power has been

may be held low until the device initialization requirements have

, the HHV signal will go inactive.

Texas instruments TMS320C6672 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Data Manual

Release History

Contents

List of Figures

List of Tables

1Features

1.1 KeyStone Architecture

1.2 Device Description

1.3 Functional Block Diagram

2 Device Overview

2.1 Device Characteristics

2.2 DSP Core Description

2.3 Memory Map Summary

2.4 Boot Sequence

2.5 Boot Modes Supported and PLL Settings

2.5.1 Boot Device Field

2.5.2 Device Configuration Field

2.5.2.1 Sleep / EMIF16 Boot Device Configuration

2.5.2.2 Ethernet (SGMII) Boot Device Configuration

2.5.2.3 Serial Rapid I/O Boot Device Configuration

2.5.2.4 PCI Boot Device Configuration

2.5.2.5 I2C Boot Device Configuration

2.5.2.6 SPI Boot Device Configuration

2.5.2.7 HyperLink Boot Device Configuration

2.5.3 PLL Boot Configuration Settings

2.6 Second-Level Bootloaders

2.7 Terminals

2.8 Terminal Functions

2.9 Development

2.9.1 Development Support

2.9.2 Device Support

2.9.2.1 Device and Development-Support Tool Nomenclature

Related Documentation from Texas Instruments

3 Device Configuration

3.1 Device Configuration at Device Reset

3.2 Peripheral Selection After Device Reset

3.3 Device State Control Registers

3.3.1 Device Status Register

3.3.2 Device Configuration Register

3.3.3 JTAG ID (JTAGID) Register Description

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

3.3.7 Reset Status (RESET_STAT) Register

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register

3.3.9 Boot Complete (BOOTCOMPLETE) Register

3.3.10 Power State Control (PWRSTATECTL) Register

3.3.11 NMI Even Generation to CorePac (NMIGRx) Register

3.3.12 IPC Generation (IPCGRx) Registers

3.3.13 IPC Acknowledgement (IPCARx) Registers

3.3.14 IPC Generation Host (IPCGRH) Register

3.3.15 IPC Acknowledgement Host (IPCARH) Register

3.3.16 Timer Input Selection Register (TINPSEL)

3.3.17 Timer Output Selection Register (TOUTPSEL)

3.3.18 Reset Mux (RSTMUXx) Register

3.4 Pullup/Pulldown Resistors

4 System Interconnect

4.1 Internal Buses, Bridges, and Switch Fabrics

4.2 Data Switch Fabric Connections

4.3 Configuration Switch Fabric

4.4 Bus Priorities

5 C66x CorePac

5.1 Memory Architecture

5.1.1 L1P Memory

5.1.2 L1D Memory

5.1.3 L2 Memory

5.1.4 MSMC SRAM

5.1.5 L3 Memory

5.2 Memory Protection

5.3 Bandwidth Management

5.4 Power-Down Control

5.5 C66x CorePac Resets

5.6 C66x CorePac Revision

5.7 C66x CorePac Register Descriptions

6 Device Operating Conditions

6.1 Absolute Maximum Ratings