Texas instruments TMS320C6670 Data Manual

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

Data Manual

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

Literature Number: SPRS689

November 2010

TMS320C6670

Data Manual

SPRS689—November 2010

Release History

Release Date Chapter/Topic Description/Comments

1.0 November 2010 All Initial Release

www.ti.com

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

SPRS689—November 2010

1 TMS320C6670 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 KeyStone Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2 CPU (DSP Core) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.5 Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.5.3 PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

2.9 Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.3.2 Device Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.3.11 NMI Even Generation to CorePac (NMIGRx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.3.12 IPC Generation (IPCGRx) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4 System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.1 Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.2 Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.3 Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.4 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5 C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.5 CorePac Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.6 CorePac Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.7 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7 TMS320C6670 Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.1.2 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3.1 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.3.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.3.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.4 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.4.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.4.2 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.2 INTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.5.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.4 NMI

7.5.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.6 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

7.6.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.6.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.7 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.7.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.7.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.7.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.7.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.7.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.7.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.7.7 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.8 Main PLL and the PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

7.8.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

7.8.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.8.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

7.9 DDR3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

7.9.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

7.9.2 DDR3 PLL Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7.9.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7.10 PASS PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7.10.1 PASS PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.10.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.10.3 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.11 DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.11.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

7.12 I

7.12.1 I

7.12.2 I

and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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7.12.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.17 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.18 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

7.19 Ethernet MAC (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

7.20 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.21 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.21.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.21.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.22 Rake Search Accelerator (RSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.23 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.24 Third-Generation Turbo Decoder Coprocessor (TCP3d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.25 Turbo Encoder Coprocessor (TCP3e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.26 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.27 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.27.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.27.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.28 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.29 Antenna Interface Subsystem 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

7.30 FFTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.31 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.31.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.31.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.31.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

8 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

8.1 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

8.2 Package CYP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

SPRS689—November 2010

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

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List of Figures

Figure 1-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 2-1 TMS320C6670 CPU (DSP Core) Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 2-2 Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 2-3 Sleep Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-4 Ethernet (SGMII) Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-5 Serial Rapid I/O Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 2-6 PCI Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 2-7 I Figure 2-8 I

Figure 2-9 SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 2-10 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 2-11 CYP 841-PIN BGA Package Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 3-1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 3-2 Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 3-3 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 3-6 Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 3-8 Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 3-9 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 3-10 NMI Generation Register (NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 3-11 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 3-12 IPC Acknowledgement Registers (IPCARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 3-13 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 3-14 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 3-15 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 3-16 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 3-17 Reset Mux Register (RSTMUX0 through RSTMUX3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 4-1 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 5-1 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 5-2 TMS320C6670 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 5-3 TMS320C6670 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 5-4 TMS320C6670 L2 Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 7-1 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 7-4 Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 7-5 POR Figure 7-6 POR Figure 7-7 RESETFULL Figure 7-8 RESETFULL

Figure 7-9 SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Figure 7-10 SmartReflex I Figure 7-11 SmartReflex I

Figure 7-12 TMS320C6670 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Figure 7-13 NMI

Figure 7-14 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Figure 7-15 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Figure 7-16 Programmable Range n End Address Register (PROGn_MPEAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-17 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Figure 7-18 POR

C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

C Interface Receive Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

C Interface Transmit Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

and LRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

Figure 7-19 RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Figure 7-20 Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Figure 7-21 Soft-Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Figure 7-22 Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Figure 7-23 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Figure 7-24 PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Figure 7-25 PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Figure 7-26 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Figure 7-27 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Figure 7-28 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Figure 7-29 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Figure 7-30 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Figure 7-31 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Figure 7-32 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Figure 7-33 Main PLL Control Register (MAINPLLCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Figure 7-34 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 7-35 Main PLL Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 7-36 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Figure 7-37 DDR3 PLL Control Register (DDR3PLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Figure 7-38 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Figure 7-39 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Figure 7-40 PASS PLL Control Register (PASSPLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Figure 7-41 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Figure 7-42 I Figure 7-43 I Figure 7-44 I

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Figure 7-45 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 7-46 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 7-47 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 7-48 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 7-49 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 7-50 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Figure 7-51 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Figure 7-52 UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Figure 7-53 UART RTS (Request-to-Send Output) – Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Figure 7-54 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-55 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-56 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 7-57 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 7-58 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Figure 7-59 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Figure 7-60 AIF2 RP1 Frame Synchronization Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Figure 7-61 AIF2 RP1 Frame Synchronization Burst Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Figure 7-62 AIF2 Physical Layer Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Figure 7-63 AIF2 Radio Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Figure 7-64 AIF2 Timer External Frame Event Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Figure 7-65 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Figure 7-66 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Figure 8-1 CYP (S–PBGA–N841) Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

SPRS689—November 2010

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

www.ti.com

List of Tables

Table 2-1 Characteristics of the C6670 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 2-2 TMS320C6670 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 2-3 Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 2-4 Sleep Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 2-5 Ethernet (SGMII) Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 2-6 Serial Rapid I/O Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 2-7 PCI Device Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 2-8 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 2-9 I Table 2-10 I

Table 2-11 SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 2-12 HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-13 C66x CorePac System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-14 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 2-15 Terminal Functions — Signals and Control by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 2-16 Terminal Functions — Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 2-17 Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 2-18 Terminal Functions — By Ball Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 3-1 TMS320C6670 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-3 Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 3-4 Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 3-5 JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 3-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 3-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 3-8 Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 3-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 3-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 3-11 Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 3-12 NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 3-13 IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 3-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 3-15 IPC Generation Registers (IPCGRH) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-16 IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-17 Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 3-18 Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 3-19 Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 4-1 CPU/2 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 4-2 CPU/3 Data SCR Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 4-3 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 5-1 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 5-2 CorePac Reset (Global or Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 5-3 CorePac Revision ID Register (MM_REVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 5-4 CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 6-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 6-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 7-1 Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 7-2 Power Supply Rails on TMS320C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 7-3 POR Table 7-4 POR Table 7-5 RESETFULL

C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

Table 7-6 RESETFULL-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 7-7 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 7-8 SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Table 7-9 SmartReflex I Table 7-10 SmartReflex I

C Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

C Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 7-11 EDMA3 Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 7-12 TPCC0 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 7-13 TPCC1 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 7-14 TPCC2 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-15 TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 7-16 INTC0 Event Inputs — C66x CorePac Secondary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Table 7-17 INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 7-18 INTC2 Event Inputs (Secondary Events for TPCC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-19 INTC0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Table 7-20 INTC1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-21 INTC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-22 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-23 LRESET Table 7-24 NMI

and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

and LRESET Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-25 MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-26 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-27 Device Master Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-28 MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-29 MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-30 MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-31 MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Table 7-32 Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Table 7-33 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU0). . . . . . . . . . . . . . . . . . . . . . . .145

Table 7-34 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .145

Table 7-35 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU2) . . . . . . . . . . . . . . . . . . . . . . . .146

Table 7-36 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU3). . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-37 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU0). . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-38 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-39 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU2). . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-40 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU3) . . . . . . . . . . . . . . . . . . . . . . . .149

Table 7-41 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions. . . . . . . . . . . .150

Table 7-42 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .151

Table 7-43 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 7-44 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Table 7-45 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Table 7-46 Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 7-47 Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Table 7-48 PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Table 7-49 PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table 7-50 PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table 7-51 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Table 7-52 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Table 7-53 SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Table 7-54 Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Table 7-55 Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Table 7-56 Reset Configuration Register (RSTCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 7-57 Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-58 Main PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-59 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . .

SPRS689—November 2010

. . . . . . . . . . . . . . .170

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

Table 7-60 DDR3 PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-61 DDR3 PLL DDRREFCLK(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-62 PASS PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Table 7-63 PASS PLL Timing Requirments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Table 7-64 I Table 7-65 I Table 7-66 I

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Table 7-67 SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-68 SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-69 HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-70 HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-71 UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Table 7-72 UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-73 MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-74 MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-75 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-76 MDIO Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-77 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Table 7-78 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Table 7-79 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-80 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-81 AIF2 Timer Module Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Table 7-82 AIF2 Timer Module Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Table 7-83 Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Table 7-84 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Table 7-85 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

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1 TMS320C6670 Features

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

• Four TMS320C66x™ DSP Core Subsystems, Each With – 1.2 GHz C66x Fixed/Floating-Point DSP Core

› 32 GMacs/Core for Fixed Point @ 1.2 GHz › 16 GFlops/Core for Floating Point @ 1.2 GHz

–Memory

› 32K Byte L1P Per Core › 32K Byte L1D Per Core › 1024K Byte Local L2 Per Core

• Multicore Shared Memory Controller (MSMC) – 2048 KB MSM SRAM Memory Shared by Four DSP

Cores

– Memory Protection Unit for Both MSM SRAM and

DDR3_EMIF

• Hardware Coprocessors – Two Enhanced Coprocessors for Turbo Decoding

› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,

LTE, and WiMAX

› Supports up to 365 Mbps for LTE and up to

233 Mbps for WCDMA

› Low DSP Overhead – HW Interleaver Table

Generation and CRC Check

– One Enhanced Coprocessor for Turbo Encoding

› Supports up to 643 Mbps for LTE and up to 746

Mbps for WCDMA

– Four Viterbi Decoders

› Supports More Than 38 Mbps @ 40 bit Block Size

– Two Fast Fourier Transform Coprocessors

› 1365 pt FFT in 4.8 μs

• Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue

Manager

– Packet-Based DMA for Zero-Overhead Transfers

• Network Coprocessors – Packet Accelerator Enables Support for

› Transport Plane IPsec, GTP-U, SCTP, PDCP › L2 User Plane PDCP (RoHC, Air Ciphering) › 1 Gbps Wire Speed Throughput at 1.5M Packets

Per Second

– Security Accelerator Engine Enables Support for

› IPSec, SRTP, 3GPP and WiMAX Air Interface, and

SSL/TLS Security

› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,

CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5

› Up to 2.8 Gbps Encryption Speed

• Four Rake/Search Accelerators (RSA) for – Chip Rate Processing for WCDMA Rel'99, HSDPA,

and HSDPA+

– Reed-Muller Decoding

• Peripherals – Six Lane SerDes-Based Antenna Interface (AIF2)

› Operating at up to 6.144 Gbps › Compliant with OBSAI RP3 and CPRI Standards

for 3G / 4G (WCDMA, LTE TDD, LTE FDD, TD-SCDMA, and WiMAX)

– Four Lanes of SRIO 2.1

› 5 GBaud Operation Per Lane › Supports Direct I/O, Message Passing

– Two Lanes PCIe Gen2

› Supports Up To 5 GBaud

– Hyperlink

› Supports Connections to Other KeyStone

Architecture Devices Providing Resource Scalability

› Supports up to 50 Gbaud

– Ethernet MAC Subsystem (EMAC)

›Two SGMII Ports

› IEEE1588 Support –64-Bit DDR3 Interface –UART Interface

–I

C Interface –16 GPIO pins –SPI Interface – Semaphore Module –Eight 64-Bit Timers – Three On-Chip PLLs

• Commercial Temperature: – 0°C to 100°C

• Extended Temperature: – - 40°C to 105°C

ADVANCE INFORMATION

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

1.1 KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched

ADVANCE INFORMATION

central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

1.2 Device Description

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The TMS320C6670 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure applications. The C6670 provides a very high performance macro basestation platform for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. The C6670 also sets a new standard for clock speed with operating frequencies up to 1.2 GHz.

TI's SoC architecture provides a programmable platform integrating various subsystems (C66x cores, IP network, radio layers 1 and 2, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet Switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high speed IO, to each operate at maximum efficiency with no blocking or stalling.

TI's new C66x core launches a new era of DSP technology by combining fixed point and floating point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 32 GMACS/core and 16 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming.

The C6670 contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains numerous copies of key coprocessors such as the FFTC and TCP3d. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI's scalable multicore SoC architecture solutions provide developers with a range of software- and hardware-compatible devices to minimize development time and maximize reuse across all base station platforms from Femto to Macro.

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

The C6670 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

SPRS689—November 2010

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320C6670 device.

Figure 1-1 Functional Block Diagram

Memory Subsystem

64-Bit

DDR3 EMIF

Debug & Trace

Boot ROM

Semaphore

Power

Management

PLL

EDMA

HyperLink

´3

2MB

MSM

SRAM

MSMC

RSA RSA

C66x™

CorePac

32KB L1 P-Cache

1024KB L2 Cache

4 Cores @ 1.0 GHz / 1.2 GHz

TeraNet

32KB L1 D-Cache

´2

C6670

Coprocessors

VCP2

TCP3d

TCP3e

FFTC

Multicore Navigator

´4

´2

ADVANCE INFORMATION

Queue

Manager

Others

PCIe 2

UART

SPI

AIF2

Switch

SRIO 4

Ethernet

SGMII

Network Coprocessor

Switch

Packet

DMA

Security

Accelerator

Packet

Accelerator

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320C6670 DSP. The table shows significant features of the C6670 device,

including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.

2.2 CPU (DSP Core) Description

Table 2-1 Characteristics of the C6670 Processor (Part 1 of 2)

HARDWARE FEATURES TMS320C6670

ADVANCE INFORMATION

Peripherals

Encoder/Decoder Coprocessors

Accelerators

On-Chip Memory

C66x CorePac Revision ID

JTAG BSDL_ID JTAGID register (address location: 0x02620018)

Frequency MHz 1200 (1.2 GHz) [-1200]

Cycle Time ns 0.83 ns [-1200]

Voltage

BGA Package 24 mm × 24 mm 841-Pin Flip-Chip Plastic BGA (CYP)

DDR3 Memory Controller (64-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P)

EDMA3 (16 independent channels) [CPU/2 clock rate] 1

EDMA3 (64 independent channels) [CPU/3 clock rate] 2

High-speed 1×/2x/4× Serial RapidIO Port (4 lanes) 1

Second generation Antenna Interface (AIF2) 1

C 1

SPI 1

PCIe (2 lanes) 1

UART 1

10/100/1000 Ethernet MAC (EMAC) 2

Management Data Input/Output (MDIO) 1

64-Bit Timers (Configurable) (internal clock source = CPU/6 clock frequency)

General-Purpose Input/Output Port (GPIO) 16

VCP2 (clock source = CPU/3 clock frequency) 4

TCP3d (clock source = CPU/2 clock frequency) 2

TCP3e (clock source = CPU/3 clock frequency) 1

FFTC (clock source = CPU/3 clock frequency) 2

Rake/Search Accelerator 4

Packet Accelerator 1

Security Accelerator

Size (Bytes) 6528K

Organization

CorePac Revision ID Register (address location: 0181 2000h) See Section 5.6 ‘‘CorePac Revision’’ on page 88.

Core (V) SmartReflex variable supply

I/O (V) 1.0 V, 1.5 V, and 1.8 V

(1)

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Eight 64-bit or Sixteen 32-bit

128KB L1 Program Memory Controller [SRAM/Cache] 128KB L1 Data Memory Controller [SRAM/Cache] 4096KB L2 Unified Memory/Cache 2048KB MSM SRAM 128KB L3 ROM

See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register

Description’’ on page 65

1000 (1.0 GHz) [-1000]

1 ns [-1000]

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-1 Characteristics of the C6670 Processor (Part 2 of 2)

HARDWARE FEATURES TMS320C6670

Process Technology μm 0.040 μm

Product Status

End of Table 2-1

1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments. 2 ADVA NCE INFOR MATION co ncerns ne w product s in the sa mpling or preproduction phase of development. Characteristic data and other specifications are sub ject to change

without notice.

(2)

Product Preview (PP), Advance Information (AI), or Production Data (PD)

The C66x Central Processing Unit (CPU) extends the performance of the C64x+ and C674x CPUs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x CPUs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x CPU, the vector processing capability is improved by extending the width of the SIMD instructions. C66x CPUs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x CPU also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.

SPRS689—November 2010

The C66x CPU consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data. 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3 upper registers.

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions that multiply a complex number with a complex conjugate of another number with rounding capability. Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability. A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.

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Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x CPU. This includes one single-precision multiply each cycle and one double precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

C66x CPU improves the performance over the C674x double-precision multiplies by adding a instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one the following floating-point operations each clock cycle: one, two, or four single-precision multiplies or a complex single-precision multiply.

The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger

ADVANCE INFORMATION

operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number.

The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a CPU stall until the completion of all the CPU-triggered memory transactions, including:

• Cache line fills

• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints

• Victim write backs

• Block or global coherence operations

•Cache mode changes

• Outstanding XMC prefetch requests

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This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations.

For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following documents ( ‘‘Related Documentation from Texas Instruments’’ on page 59):

• C66x CPU and Instruction Set Reference Guide

• C66x DSP Cache User Guide

• C66x CorePac User Guide

Multicore Fixed and Floating-Point System-on-Chip

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Figure 2-1 shows the DSP core functional units and data paths.

Figure 2-1 TMS320C6670 CPU (DSP Core) Data Paths

TMS320C6670

SPRS689—November 2010

Note: Default bus width is 64 bits (i.e. a register pair)

Data Path A

ST1

LD1

DA1

DA2

LD2

src1

.L1

src2

dst

File A

(A0, A1, A2,

...A31)

src1

.S1

.M1

.D1

.D2

.M2

src2

dst

src1

src1_hi

src2

src2_hi

dst2

dst1

src1

dst

src2

src1

dst1

dst2

src2_hi

src2

src1_hi

src1

dst

File B

(B0, B1, B2,

...B31)

ADVANCE INFORMATION

Data Path B

dst

.S2

ST2

.L2

66xx

src2

src1

dst

src2

src1

Control

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the TMS320C6670 device.

Table 2-2 TMS320C6670 Memory Map Summary (Part 1 of 9)

Logical 32 bit Address Physical 36 bit Address

0000 0000 007F FFFF 0 0000 0000 0 007F FFFF 8M Reserved

0080 0000 008F FFFF 0 0080 0000 0 008F FFFF 1M L2 SRAM

0090 0000 00DF FFFF 0 0090 0000 0 00DF FFFF 5M Reserved

ADVANCE INFORMATION

00E00000 00E0 7FFF 0 00E00000 0 00E0 7FFF 32K L1P SRAM

00E08000 00EF FFFF 0 00E08000 0 00EF FFFF 1M-32K Reserved

00F00000 00F0 7FFF 0 00F00000 0 00F0 7FFF 32K L1D SRAM

00F08000 00FF FFFF 0 00F08000 0 00FF FFFF 1M-32K Reserved

0100 0000 01BF FFFF 0 0100 0000 0 01BF FFFF 12 M C66x CorePac Registers

01C0 0000 01CF FFFF 0 01C0 0000 0 01CF FFFF 1M Reserved

01D0 0000 01D0 007F 0 01D0 0000 0 01D0 007F 128 Tracer 0

01D0 0080 01D0 7FFF 0 01D0 0080 0 01D0 7FFF 32K-128 Reserved

01D0 8000 01D0 807F 0 01D0 8000 0 01D0 807F 128 Tracer 1

01D0 8080 01D0 FFFF 0 01D0 8080 0 01D0 FFFF 32K-128 Reserved

01D1 0000 01D1 007F 0 01D1 0000 0 01D1 007F 128 Tracer 2

01D1 0080 01D1 7FFF 0 01D1 0080 0 01D1 7FFF 32K-128 Reserved

01D1 8000 01D1 807F 0 01D1 8000 0 01D1 807F 128 Tracer 3

01D1 8080 01D1 FFFF 0 01D1 8080 0 01D1 FFFF 32K-128 Reserved

01D2 0000 01D2 007F 0 01D2 0000 0 01D2 007F 128 Tracer 4

01D2 0080 01D2 7FFF 0 01D2 0080 0 01D2 7FFF 32K-128 Reserved

01D2 8000 01D2 807F 0 01D2 8000 0 01D2 807F 128 Tracer 5

01D2 8080 01D2 FFFF 0 01D2 8080 0 01D2 FFFF 32K-128 Reserved

01D3 0000 01D3 007F 0 01D3 0000 0 01D3 007F 128 Tracer 6

01D3 0080 01D3 7FFF 0 01D3 0080 0 01D3 7FFF 32K-128 Reserved

01D3 8000 01D3 807F 0 01D3 8000 0 01D3 807F 128 Tracer 7

01D3 8080 01D3 FFFF 0 01D3 8080 0 01D3 FFFF 32K-128 Reserved

01D4 0000 01D4 007F 0 01D4 0000 0 01D4 007F 128 Tracer 8

01D4 0080 01D4 7FFF 0 01D4 0080 0 01D4 7FFF 32K-128 Reserved

01D4 8000 01D4 807F 0 01D4 8000 0 01D4 807F 128 Tracer 9

01D4 8080 01D4 FFFF 0 01D4 8080 0 01D4 FFFF 32K-128 Reserved

01D5 0000 01D5 007F 0 01D5 0000 0 01D5 007F 128 Tracer 10

01D5 0080 01D5 7FFF 0 01D5 0080 0 01D5 7FFF 32K-128 Reserved

01D5 8000 01D5 807F 0 01D5 8000 0 01D5 807F 128 Tracer 11

01D5 8080 01D5 FFFF 0 01D5 8080 0 01D5 FFFF 32K-128 Reserved

01D6 0000 01D6 007F 0 01D6 0000 0 01D6 007F 128 Tracer 12

01D6 0080 01D6 7FFF 0 01D6 0080 0 01D6 7FFF 32K-128 Reserved

01D6 8000 01D6 807F 0 01D6 8000 0 01D6 807F 128 Tracer 13

01D6 8080 01D6 FFFF 0 01D6 8080 0 01D6 FFFF 32K-128 Reserved

01D7 0000 01D7 007F 0 01D7 0000 0 01D7 007F 128 Tracer 14

01D7 0080 01D7 7FFF 0 01D7 0080 0 01D7 7FFF 32K-128 Reserved

01D7 8000 01D7 807F 0 01D7 8000 0 01D7 807F 128 Tracer 15

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Bytes DescriptionStart End Start End

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-2 TMS320C6670 Memory Map Summary (Part 2 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

01D7 8080 01D7 FFFF 0 01D7 8080 0 01D7 FFFF 32K-128 Reserved

01D8 0000 01D8 007F 0 01D8 0000 0 01D8 007F 128 Reserved

01D8 0080 01D8 7FFF 0 01D8 0080 0 01D8 7FFF 32K-128 Reserved

01D8 8000 01DF FFFF 0 01D8 8000 0 01DF FFFF 480K Reserved

01E0 0000 01E3 FFFF 0 01E0 0000 0 01E3 FFFF 256K Reserved

01E4 0000 01E7 FFFF 0 01E4 0000 0 01E7 FFFF 256K Reserved

01E8 0000 01EB FFFF 0 01E8 0000 0 01EB FFFF 256K Reserved

01EC 0000 01EF FFFF 0 01EC 0000 0 01EF FFFF 256K Reserved

01F0 0000 01F7 FFFF 0 01F0 0000 0 01F7 FFFF 512k AIF2 Control

01F80000 01F8FFFF 01F80000 01F8FFFF 64K Reserved

01F90000 01F9FFFF 01F90000 01F9FFFF 64K Reserved

01FA0000 01FBFFFF 01FA0000 01FBFFFF 128K Reserved

01FC0000 01FDFFFF 01FC0000 01FDFFFF 128K Reserved

01FE 0000 01FF FFFF 0 01FE 0000 0 01FF FFFF 128k Reserved

0200 0000 0208 FFFF 0 0200 0000 0 0208 FFFF 576K Packet Accelerator Configuration

0209 0000 020B FFFF 0 0209 0000 0 020B FFFF 192K Ethernet Switch Subsystem Configuration

020C 0000 020F FFFF 0 020C 0000 0 020F FFFF 256K Security Accelerator Subsystem Configuration

02100000 0210FFFF 02100000 0210FFFF 64K Reserved

02110000 0211FFFF 02110000 0211FFFF 64K Reserved

02120000 0213FFFF 02120000 0213FFFF 128K Reserved

02140000 0215FFFF 02140000 0215FFFF 128K Reserved

0216 0000 0217 FFFF 0 0216 0000 0 0217 FFFF 128K Reserved

02180000 02187FFF 02180000 02187FFF 32k Reserved

02188000 0218FFFF 02188000 0218FFFF 32k Reserved

02190000 0219FFFF 02190000 0219FFFF 64k Reserved

021A0000 021AFFFF 021A0000 021AFFFF 64K Reserved

021B 0000 021B FFFF 0 021B 0000 0 021B FFFF 64K Reserved

021C 0000 021C 03FF 0 021C 0000 0 021C 03FF 1K TCP3d-A

021C 0400 021C 7FFF 0 021C 0400 0 021C 7FFF 31K Reserved

021C 8000 021C 83FF 0 021C 8000 0 021C 83FF 1K TCP3d-B

021C 8400 021C FFFF 0 021C 8400 0 021C FFFF 31K Reserved

021D 0000 021D 00FF 0 021D 0000 0 021D 00FF 256 VCP2_A

021D 0100 021D 3FFF 0 021D 0100 0 021D 3FFF 16K Reserved

021D 4000 021D 40FF 0 021D 4000 0 021D 40FF 256 VCP2_B

021D 4100 021D 7FFF 0 021D 4100 0 021D 7FFF 16K Reserved

021D 8000 021D 80FF 0 021D 8000 0 021D 80FF 256 VCP2_C

021D 8100 021D BFFF 0 021D 8100 0 021D BFFF 16K Reserved

021D C000 021D C0FF 0 021D C000 0 021D C0FF 256 VCP2_D

021D C100 021D FFFF 0 021D C100 0 021D FFFF 16K Reserved

021E 0000 021E 0FFF 0 021E 0000 0 021E 0FFF 4K TCP3e

021E 1000 021E FFFF 0 021E 1000 0 021E FFFF 60k Reserved

021F 0000 021F 07FF 0 021F 0000 0 021F 07FF 2K FFTC-A Configuration

021F 0800 021F 3FFF 0 021F 0800 0 021F 3FFF 14K Reserved

SPRS689—November 2010

TMS320C6670

ADVANCE INFORMATION

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

Table 2-2 TMS320C6670 Memory Map Summary (Part 3 of 9)

Logical 32 bit Address Physical 36 bit Address

021F 4000 021F 47FF 0 021F 4000 0 021F 47FF 2K FFTC-B Configuration

021F 4800 021F FFFF 0 021F 4800 0 021F FFFF 46K Reserved

0220 0000 0220 007F 0 0220 0000 0 0220 007F 128 Timer0

0220 0080 0220 FFFF 0 0220 0080 0 0220 FFFF 64K-128 Reserved

0221 0000 0221 007F 0 0221 0000 0 0221 007F 128 Timer1

0221 0080 0221 FFFF 0 0221 0080 0 0221 FFFF 64K-128 Reserved

ADVANCE INFORMATION

0222 0000 0222 007F 0 0222 0000 0 0222 007F 128 Timer2

0222 0080 0222 FFFF 0 0222 0080 0 0222 FFFF 64K-128 Reserved

0223 0000 0223 007F 0 0223 0000 0 0223 007F 128 Timer3

0223 0080 0223 FFFF 0 0223 0080 0 0223 FFFF 64K-128 Reserved

0224 0000 0224 007F 0 0224 0000 0 0224 007F 128 Timer4

0224 0080 0224 FFFF 0 0224 0080 0 0224 FFFF 64K-128 Reserved

0225 0000 0225 007F 0 0225 0000 0 0225 007F 128 Timer5

0225 0080 0225 FFFF 0 0225 0080 0 0225 FFFF 64K-128 Reserved

0226 0000 0226 007F 0 0226 0000 0 0226 007F 128 Timer6

0226 0080 0226 FFFF 0 0226 0080 0 0226 FFFF 64K-128 Reserved

0227 0000 0227 007F 0 0227 0000 0 0227 007F 128 Timer7

0227 0080 0227 FFFF 0 0227 0080 0 0227 FFFF 64K-128 Reserved

0228 0000 0228 007F 0 0228 0000 0 0228 007F 128 Reserved

0228 0080 0228 FFFF 0 0228 0080 0 0228 FFFF 64K-128 Reserved

0229 0000 0229 007F 0 0229 0000 0 0229 007F 128 Reserved

0229 0080 0229 FFFF 0 0229 0080 0 0229 FFFF 64K-128 Reserved

022A 0000 022A 007F 0 022A 0000 0 022A 007F 128 Reserved

022A 0080 022A FFFF 0 022A 0080 0 022A FFFF 64K-128 Reserved

022B 0000 022B 007F 0 022B 0000 0 022B 007F 128 Reserved

022B 0080 022B FFFF 0 022B 0080 0 022B FFFF 64K-128 Reserved

022C 0000 022C 007F 0 022C 0000 0 022C 007F 128 Reserved

022C 0080 022C FFFF 0 022C 0080 0 022C FFFF 64K-128 Reserved

022D 0000 022D 007F 0 022D 0000 0 022D 007F 128 Reserved

022D 0080 022D FFFF 0 022D 0080 0 022D FFFF 64K-128 Reserved

022E 0000 022E 007F 0 022E 0000 0 022E 007F 128 Reserved

022E 0080 022E FFFF 0 022E 0080 0 022E FFFF 64K-128 Reserved

022F 0000 022F 007F 0 022F 0000 0 022F 007F 128 Reserved

022F 0080 022F FFFF 0 022F 0080 0 022F FFFF 64K-128 Reserved

0230 0000 0230 FFFF 0 0230 0000 0 0230 FFFF 64K Reserved

0231 0000 0231 01FF 0 0231 0000 0 0231 01FF 512 PLL Controller

0231 0200 0231 FFFF 0 0231 0200 0 0231 FFFF 64K-512 Reserved

0232 0000 0232 00FF 0 0232 0000 0 0232 00FF 256 GPIO

0232 0100 0232 FFFF 0 0232 0100 0 0232 FFFF 64K-256 Reserved

0233 0000 0233 03FF 0 0233 0000 0 0233 03FF 1K SmartReflex

0233 0400 0233 FFFF 0 0233 0400 0 0233 FFFF 63K Reserved

0234 0000 0234 FFFF 0 0234 0000 0 0234 FFFF 64K Reserved

0235 0000 0235 0FFF 0 0235 0000 0 0235 0FFF 4K Power Sleep Controller

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Bytes DescriptionStart End Start End

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-2 TMS320C6670 Memory Map Summary (Part 4 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

0235 1000 0235 FFFF 0 0235 1000 0 0235 FFFF 64K-4K Reserved

0236 0000 0236 03FF 0 0236 0000 0 0236 03FF 1K Memory Protection Unit (MPU) 0

0236 0400 0236 7FFF 0 0236 0400 0 0236 7FFF 31K Reserved

0236 8000 0236 83FF 0 0236 8000 0 0236 83FF 1K Memory Protection Unit (MPU) 1

0236 8400 0236 FFFF 0 0236 8400 0 0236 FFFF 31K Reserved

0237 0000 0237 03FF 0 0237 0000 0 0237 03FF 1K Memory Protection Unit (MPU) 2

0237 0400 0237 7FFF 0 0237 0400 0 0237 7FFF 31K Reserved

0237 8000 0237 83FF 0 0237 8000 0 0237 83FF 1K Memory Protection Unit (MPU) 3

0237 8400 0237 FFFF 0 0237 8400 0 0237 FFFF 31K Reserved

0238 0000 0238 03FF 0 0238 0000 0 0238 03FF 1K Reserved

0238 0400 023F FFFF 0 0238 0400 0 023F FFFF 511K Reserved

0240 0000 0243 FFFF 0 0240 0000 0 0243 FFFF 256K Reserved

0244 0000 0244 3FFF 0 0244 0000 0 0244 3FFF 16K DSP Trace Formatter 0

0244 4000 0244 FFFF 0 0244 4000 0 0244 FFFF 48K Reserved

0245 0000 0245 3FFF 0 0245 0000 0 0245 3FFF 16K DSP Trace Formatter 1

0245 4000 0245 FFFF 0 0245 4000 0 0245 FFFF 48K Reserved

0246 0000 0246 3FFF 0 0246 0000 0 0246 3FFF 16K DSP Trace Formatter 2

0246 4000 0246 FFFF 0 0246 4000 0 0246 FFFF 48K Reserved

0247 0000 0247 3FFF 0 0247 0000 0 0247 3FFF 16K DSP Trace Formatter 3

0247 4000 0247 FFFF 0 0247 4000 0 0247 FFFF 48K Reserved

0248 0000 0248 3FFF 0 0248 0000 0 0248 3FFF 16K Reserved

0248 4000 0248 FFFF 0 0248 4000 0 0248 FFFF 48K Reserved

0249 0000 0249 3FFF 0 0249 0000 0 0249 3FFF 16K Reserved

0249 4000 0249 FFFF 0 0249 4000 0 0249 FFFF 48K Reserved

024A 0000 024A 3FFF 0 024A 0000 0 024A 3FFF 16K Reserved

024A 4000 024A FFFF 0 024A 4000 0 024A FFFF 48K Reserved

024B 0000 024B 3FFF 0 024B 0000 0 024B 3FFF 16K Reserved

024B 4000 024B FFFF 0 024B 4000 0 024B FFFF 48K Reserved

024C 0000 024C 01FF 0 024C 0000 0 024C 01FF 512 Reserved

024C 0200 024C 03FF 0 024C 0200 0 024C 03FF 1K-512 Reserved

024C 0400 024C 07FF 0 024C 0400 0 024C 07FF 1K Reserved

024C 0800 024C FFFF 0 024C 0800 0 024C FFFF 62K Reserved

024D 0000 024F FFFF 0 024D 0000 0 024F FFFF 192K Reserved

0250 0000 0250 007F 0 0250 0000 0 0250 007F 128 Reserved

0250 0080 0250 7FFF 0 0250 0080 0 0250 7FFF 32K-128 Reserved

0250 8000 0250 FFFF 0 0250 8000 0 0250 FFFF 32K Reserved

0251 0000 0251 FFFF 0 0251 0000 0 0251 FFFF 64K Reserved

0252 0000 0252 03FF 0 0252 0000 0 0252 03FF 1K Reserved

0252 0400 0252 FFFF 0 0252 0400 0 0252 FFFF 64K-1K Reserved

0253 0000 0253 007F 0 0253 0000 0 0253 007F 128 I2C Data & Control

0253 0080 0253 FFFF 0 0253 0080 0 0253 FFFF 64K-128 Reserved

0254 0000 0254 003F 0 0254 0000 0 0254 003F 64 UART

02540 400 0254 FFFF 0 02540 400 0 0254 FFFF 64K-64 Reserved

TMS320C6670

SPRS689—November 2010

ADVANCE INFORMATION

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

Table 2-2 TMS320C6670 Memory Map Summary (Part 5 of 9)

Logical 32 bit Address Physical 36 bit Address

0255 0000 0257 FFFF 0 0255 0000 0 0257 FFFF 192K Reserved

0258 0000 025B FFFF 0 0258 0000 0 025B FFFF 256K Reserved

025C 0000 025F FFFF 0 025C 0000 0 025F FFFF 256K Reserved

0260 0000 0260 1FFF 0 0260 0000 0 0260 1FFF 8K Secondary Interrupt Contoller (INTC) 0

0260 2000 0260 3FFF 0 0260 2000 0 0260 3FFF 8K Reserved

0260 4000 0260 5FFF 0 0260 4000 0 0260 5FFF 8K Secondary Interrupt Contoller (INTC) 1

ADVANCE INFORMATION

0260 6000 0260 7FFF 0 0260 6000 0 0260 7FFF 8K Reserved

0260 8000 0260 9FFF 0 0260 8000 0 0260 9FFF 8K Secondary Interrupt Contoller (INTC) 2

0260 A000 0260 BFFF 0 0260 A000 0 0260 BFFF 8K Reserved

0260 C000 0260 DFFF 0 0260 C000 0 0260 DFFF 8K Reserved

0260 E000 0260 FFFF 0 0260 E000 0 0260 FFFF 8K Reserved

0261 0000 0261 FFFF 0 0261 0000 0 0261 FFFF 64K Reserved

0262 0000 0262 03FF 0 0262 0000 0 0262 03FF 1K Chip-Level Registers

0262 0400 0262 FFFF 0 0262 0400 0 0262 FFFF 63K Reserved

0263 0000 0263 FFFF 0 0263 0000 0 0263 FFFF 64K Reserved

0264 0000 0264 07FF 0 0264 0000 0 0264 07FF 2K Semaphore

0264 0800 0264 FFFF 0 0264 0800 0 0264 FFFF 64K-2K Reserved

0265 0000 026F FFFF 0 0265 0000 0 026F FFFF 704K Reserved

0270 0000 0270 7FFF 0 0270 0000 0 0270 7FFF 32K EDMA Channel Controller (TPCC) 0

0270 8000 0271 FFFF 0 0270 8000 0 0271 FFFF 96K Reserved

0272 0000 0272 7FFF 0 0272 0000 0 0272 7FFF 32K EDMA Channel Controller (TPCC) 1

0272 8000 0273 FFFF 0 0272 8000 0 0273 FFFF 96K Reserved

02740000 0274 7FFF 0 02740000 0 0274 7FFF 32K EDMA Channel Controller (TPCC) 2

0274 8000 0275 FFFF 0 0274 8000 0 0275 FFFF 96K Reserved

0276 0000 0276 03FF 0 0276 0000 0 0276 03FF 1K EDMA TPCC0 Transfer Controller (TPTC) 0

0276 0400 0276 7FFF 0 0276 0400 0 0276 7FFF 31K Reserved

0276 8000 0276 83FF 0 0276 8000 0 0276 83FF 1K EDMA TPCC0 Transfer Controller (TPTC) 1

0276 8400 0276 FFFF 0 0276 8400 0 0276 FFFF 31K Reserved

0277 0000 0277 03FF 0 0277 0000 0 0277 03FF 1K EDMA TPCC1 Transfer Controller (TPTC) 0

0277 0400 0277 7FFF 0 0277 0400 0 0277 7FFF 31K Reserved

0277 8000 0277 83FF 0 0277 8000 0 0277 83FF 1K EDMA TPCC1 Transfer Controller (TPTC) 1

0278 0400 0277 FFFF 0 0278 0400 0 0277 FFFF 31K Reserved

0278 0000 0278 03FF 0 0278 0000 0 0278 03FF 1K EDMA TPCC1 Transfer Controller (TPTC) 2

0278 0400 0278 7FFF 0 0278 0400 0 0278 7FFF 31K Reserved

0278 8000 0278 83FF 0 0278 8000 0 0278 83FF 1K EDMA TPCC1 Transfer Controller (TPTC) 3

0278 8400 0278 FFFF 0 0278 8400 0 0278 FFFF 31K Reserved

0279 0000 0279 03FF 0 0279 0000 0 0279 03FF 1K EDMA TPCC2 Transfer Controller (TPTC) 0

0279 0400 0279 7FFF 0 0279 0400 0 0279 7FFF 31K Reserved

0279 8000 0279 83FF 0 0279 8000 0 0279 83FF 1K EDMA TPCC2 Transfer Controller (TPTC) 1

0279 8400 0279 FFFF 0 0279 8400 0 0279 FFFF 31K Reserved

027A 0000 027A 03FF 0 027A 0000 0 027A 03FF 1K EDMA TPCC2 Transfer Controller (TPTC) 2

027A 0400 027A 7FFF 0 027A 0400 0 027A 7FFF 31K Reserved

027A 8000 027A 83FF 0 027A 8000 0 027A 83FF 1K EDMA TPCC2 Transfer Controller (TPTC) 3

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Bytes DescriptionStart End Start End

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-2 TMS320C6670 Memory Map Summary (Part 6 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

027A 8400 027A FFFF 0 027A 8400 0 027A FFFF 31K Reserved

027B 0000 027B FFFF 0 027B 0000 0 027B FFFF 64K Reserved

027C 0000 027C FFFF 0 027C 0000 0 027C FFFF 64k Reserved

027D 0000 027D 3FFF 0 027D 0000 0 027D 3FFF 16k TI Embedded Trace Buffer (TETB) - Core 0

027D 4000 027D FFFF 0 027D 4000 0 027D FFFF 48k Reserved

027E 0000 027E 3FFF 0 027E 0000 0 027E 3FFF 16k TI Embedded Trace Buffer (TETB) - Core 1

027E 4000 027E FFFF 0 027E 4000 0 027E FFFF 48k Reserved

027F 0000 027F 3FFF 0 027F 0000 0 027F 3FFF 16k TI Embedded Trace Buffer (TETB) - Core 2

027F 4000 027F FFFF 0 027F 4000 0 027F FFFF 48k Reserved

0280 0000 0280 3FFF 0 0280 0000 0 0280 3FFF 16k TI Embedded Trace Buffer (TETB) - Core 3

0280 4000 0280 FFFF 0 0280 4000 0 0280 FFFF 48k Reserved

0281 0000 0281 3FFF 0 0281 0000 0 0281 3FFF 16k Reserved

0281 4000 0281 FFFF 0 0281 4000 0 0281 FFFF 48k Reserved

0282 0000 0282 3FFF 0 0282 0000 0 0282 3FFF 16k Reserved

0282 4000 0282 FFFF 0 0282 4000 0 0282 FFFF 48k Reserved

0283 0000 0283 3FFF 0 0283 0000 0 0283 3FFF 16k Reserved

0283 4000 0283 FFFF 0 0283 4000 0 0283 FFFF 48k Reserved

0284 0000 0284 3FFF 0 0284 0000 0 0284 3FFF 16k Reserved

0284 4000 0284 FFFF 0 0284 4000 0 0284 FFFF 48k Reserved

0285 0000 0285 7FFF 0 0285 0000 0 0285 7FFF 32k TI Embedded Trace Buffer (TETB) - System

0285 8000 0285 FFFF 0 0285 8000 0 0285 FFFF 32k Reserved

0286 0000 028F FFFF 0 0286 0000 0 028F FFFF 640K Reserved

0290 0000 0290 7FFF 0 0290 0000 0 0290 7FFF 32K Serial RapidIO Configuration

0290 8000 029F FFFF 0 0290 8000 0 029F FFFF 1M-32k Reserved

02A0 0000 02AF FFFF 0 02A0 0000 0 02AF FFFF 1M Queue Manager Subsystem Configuration

02B0 0000 02BF FFFF 0 02B0 0000 0 02BF FFFF 1M Reserved

02C0 0000 02FF FFFF 0 02C0 0000 0 02FF FFFF 4M Reserved

03000 000 07FF FFFF 0 03000 000 0 07FF FFFF 80M Reserved

0800 0000 0800 FFFF 0 0800 0000 0 0800 FFFF 64k Extended Memory Controller (XMC) Configuration

0801 0000 0BBF FFFF 0 0801 0000 0 0BBF FFFF 60M-64k Reserved

0BC0 0000 0BCF FFFF 0 0BC0 0000 0 0BCF FFFF 1M Multicore Shared Memory Controller (MSMC) Config

0BD0 0000 0BFF FFFF 0 0BD0 0000 0 0BFF FFFF 3M Reserved

0C00 0000 0C1F FFFF 0 0C00 0000 0 0C1F FFFF 2M Multicore Shared Memory (MSM)

0C20 0000 0C3F FFFF 0 0C20 0000 0 0C3F FFFF 2M Reserved

0C40 0000 0FFF FFFF 0 0C40 0000 0 0FFF FFFF 60 M Reserved

1000 0000 107F FFFF 0 1000 0000 0 107F FFFF 8M Reserved

1080 0000 108F FFFF 0 1080 0000 0 108F FFFF 1M Core 0 L2 SRAM

1090 0000 10DF FFFF 0 1090 0000 0 10DF FFFF 5M Reserved

10E0 0000 10E0 7FFF 0 10E0 0000 0 10E0 7FFF 32k Core 0 L1P SRAM

10E0 8000 10EF FFFF 0 10E0 8000 0 10EF FFFF 1M-32K Reserved

10F0 0000 10F0 7FFF 0 10F0 0000 0 10F0 7FFF 32k Core 0 L1D SRAM

10F0 8000 117F FFFF 0 10F0 8000 0 117F FFFF 9M-32k Reserved

1180 0000 118F FFFF 0 1180 0000 0 118F FFFF 1M Core 1 L2 SRAM

SPRS689—November 2010

ADVANCE INFORMATION

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

Table 2-2 TMS320C6670 Memory Map Summary (Part 7 of 9)

Logical 32 bit Address Physical 36 bit Address

1190 0000 11DF FFFF 0 1190 0000 0 11DF FFFF 5M Reserved

11E0 0000 11E0 7FFF 0 11E0 0000 0 11E0 7FFF 32k Core 1 L1P SRAM

11E0 8000 11EF FFFF 0 11E0 8000 0 11EF FFFF 1M-32K Reserved

11F0 0000 11F0 7FFF 0 11F0 0000 0 11F0 7FFF 32k Core 1 L1D SRAM

11F0 8000 127F FFFF 0 11F0 8000 0 127F FFFF 9M-32k Reserved

1280 0000 128F FFFF 0 1280 0000 0 128F FFFF 1M Core 2 L2 SRAM

ADVANCE INFORMATION

1290 0000 12DF FFFF 0 1290 0000 0 12DF FFFF 5M Reserved

12E0 0000 12E0 7FFF 0 12E0 0000 0 12E0 7FFF 32k Core 2 L1P SRAM

12E0 8000 12EF FFFF 0 12E0 8000 0 12EF FFFF 1M-32K Reserved

12F0 0000 12F0 7FFF 0 12F0 0000 0 12F0 7FFF 32k Core 2 L1D SRAM

12F0 8000 137F FFFF 0 12F0 8000 0 137F FFFF 9M-32k Reserved

1380 0000 1388 FFFF 0 1380 0000 0 1388 FFFF 1M Core 3 L2 SRAM

1390 0000 13DF FFFF 0 1390 0000 0 13DF FFFF 5M Reserved

13E0 0000 13E0 7FFF 0 13E0 0000 0 13E0 7FFF 32k Core 3 L1P SRAM

13E0 8000 13EF FFFF 0 13E0 8000 0 13EF FFFF 1M-32K Reserved

13F0 0000 13F0 7FFF 0 13F0 0000 0 13F0 7FFF 32k Core 3 L1D SRAM

13F0 8000 147F FFFF 0 13F0 8000 0 147F FFFF 9M-32k Reserved

1480 0000 1487 FFFF 0 1480 0000 0 1487 FFFF 512K Reserved

1488 0000 148F FFFF 0 1488 0000 0 148F FFFF 512K Reserved

1490 0000 14DF FFFF 0 1490 0000 0 14DF FFFF 5M Reserved

14E0 0000 14E0 7FFF 0 14E0 0000 0 14E0 7FFF 32k Reserved

14E0 8000 14EF FFFF 0 14E0 8000 0 14EF FFFF 1M-32K Reserved

14F0 0000 14F0 7FFF 0 14F0 0000 0 14F0 7FFF 32k Reserved

14F0 8000 157F FFFF 0 14F0 8000 0 157F FFFF 9M-32k Reserved

1580 0000 1587 FFFF 0 1580 0000 0 1587 FFFF 512K Reserved

1588 0000 158F FFFF 0 1588 0000 0 158F FFFF 512K Reserved

1590 0000 15DF FFFF 0 1590 0000 0 15DF FFFF 5M Reserved

15E0 0000 15E0 7FFF 0 15E0 0000 0 15E0 7FFF 32k Reserved

15E0 8000 15EF FFFF 0 15E0 8000 0 15EF FFFF 1M-32K Reserved

15F0 0000 15F0 7FFF 0 15F0 0000 0 15F0 7FFF 32k Reserved

15F0 8000 167F FFFF 0 15F0 8000 0 167F FFFF 9M-32k Reserved

1680 0000 1687 FFFF 0 1680 0000 0 1687 FFFF 512K Reserved

1688 0000 168F FFFF 0 1688 0000 0 168F FFFF 512K Reserved

1690 0000 16DF FFFF 0 1690 0000 0 16DF FFFF 5M Reserved

16E0 0000 16E0 7FFF 0 16E0 0000 0 16E0 7FFF 32k Reserved

16E0 8000 16EF FFFF 0 16E0 8000 0 16EF FFFF 1M-32K Reserved

16F0 0000 16F0 7FFF 0 16F0 0000 0 16F0 7FFF 32k Reserved

16F0 8000 177F FFFF 0 16F0 8000 0 177F FFFF 9M-32k Reserved

1780 0000 1787 FFFF 0 1780 0000 0 1787 FFFF 512K Reserved

1788 0000 178F FFFF 0 1788 0000 0 178F FFFF 512K Reserved

1790 0000 17DF FFFF 0 1790 0000 0 17DF FFFF 5M Reserved

17E0 0000 17E0 7FFF 0 17E0 0000 0 17E0 7FFF 32k Reserved

17E0 8000 17EF FFFF 0 17E0 8000 0 17EF FFFF 1M-32K Reserved

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Bytes DescriptionStart End Start End

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-2 TMS320C6670 Memory Map Summary (Part 8 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

17F0 0000 17F0 7FFF 0 17F0 0000 0 17F0 7FFF 32k Reserved

17F0 8000 1FFF FFFF 0 17F0 8000 0 1FFF FFFF 129M-32k Reserved

2000 0000 200F FFFF 0 2000 0000 0 200F FFFF 1M System Trace Manager (STM) Configuration

2010 0000 201F FFFF 0 2010 0000 0 201F FFFF 1M Reserved

20200000 205FFFFF 20200000 205FFFFF 4M Reserved

2060 0000 206F FFFF 0 2060 0000 0 206F FFFF 1M TCP3d-B Data

2070 0000 207F FFFF 0 2070 0000 0 207F FFFF 1M Reserved

2080 0000 208F FFFF 0 2080 0000 0 208F FFFF 1M TCP3d-A Data

2090 0000 2090 1FFF 0 2090 0000 0 2090 1FFF 8K TCP3e Data Write Port

2090 2000 2090 3FFF 0 2090 2000 0 2090 3FFF 8K TCP3e Data Read Port

2090 4000 209F FFFF 0 2090 4000 0 209F FFFF 1M-16K Reserved

20A0 0000 20A3 FFFF 0 20A0 0000 0 20A3 FFFF 256K Reserved

20A4 0000 20A4 FFFF 0 20A4 0000 0 20A4 FFFF 64K Reserved

20A5 0000 20AF FFFF 0 20A5 0000 0 20AF FFFF 704k Reserved

20B0 0000 20B1 FFFF 0 20B0 0000 0 20B1 FFFF 128k Boot ROM

20B2 0000 20BE FFFF 0 20B2 0000 0 20BE FFFF 832k Reserved

20BF 0000 20BF 03FF 0 20BF 0000 0 20BF 03FF 1k SPI

20BF 0400 20BF FFFF 0 20BF 0400 0 20BF FFFF 63k Reserved

20C0 0000 20C0 00FF 0 20C0 0000 0 20C0 00FF 256 Reserved

20C0 0100 20FF FFFF 0 20C0 0100 0 20FF FFFF 4M-256 Reserved

2100 0000 2100 00FF 0 2100 0000 0 2100 00FF 256 DDR3 EMIF Configuration

2100 0100 213F FFFF 0 2100 0100 0 213F FFFF 4M-256 Reserved

2140 0000 2140 03FF 0 2140 0000 0 2140 03FF 1K HyperLink Config

2140 0400 217F FFFF 0 2140 0400 0 217F FFFF 4M-1K Reserved

2180 0000 2180 7FFF 0 2180 0000 0 2180 7FFF 32K PCIe Config

2180 8000 21BF FFFF 0 2180 8000 0 21BF FFFF 4M-32K Reserved

21C0 0000 21FF FFFF 0 21C0 0000 0 21FF FFFF 4M Reserved

2200 0000 229F FFFF 0 2200 0000 0 229F FFFF 10M Reserved

22A0 0000 22A0 FFFF 0 22A0 0000 0 22A0 FFFF 64K VCP2_A

22A1 0000 22AF FFFF 0 22A1 0000 0 22AF FFFF 1M-64K Reserved

22B0 0000 22B0 FFFF 0 22B0 0000 0 22B0 FFFF 64K VCP2_B

22B1 0000 22BF FFFF 0 22B1 0000 0 22BF FFFF 1M-64K Reserved

22C0 0000 22C0 FFFF 0 22C0 0000 0 22C0 FFFF 64K VCP2_C

22C1 0000 22CF FFFF 0 22C1 0000 0 22CF FFFF 1M-64K Reserved

22D0 0000 22D0 FFFF 0 22D0 0000 0 22D0 FFFF 64K VCP2_D

22D1 0000 22DF FFFF 0 22D1 0000 0 22DF FFFF 1M-64K Reserved

22E0 0000 23FF FFFF 0 22E0 0000 0 23FF FFFF 18M Reserved

2400 0000 2FFF FFFF 0 2400 0000 0 2FFF FFFF 192M Reserved

3000 0000 331F FFFF 0 3000 0000 0 331F FFFF 50M Reserved

33200000 335FFFFF 33200000 335FFFFF 4M Reserved

3360 0000 33FF FFFF 0 3360 0000 0 33FF FFFF 10M Reserved

3400 0000 341F FFFF 0 3400 0000 0 341F FFFF 2M Queue Manager Subsystem Data

3420 0000 342F FFFF 0 3420 0000 0 342F FFFF 1M Reserved

SPRS689—November 2010

TMS320C6670

ADVANCE INFORMATION

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689—November 2010

Table 2-2 TMS320C6670 Memory Map Summary (Part 9 of 9)

Logical 32 bit Address Physical 36 bit Address

3430 0000 3439 FFFF 0 3430 0000 0 3439 FFFF 640K Reserved

343A 0000 343F FFFF 0 343A 0000 0 343F FFFF 384K Reserved

3440 0000 347F FFFF 0 3440 0000 0 347F FFFF 4M Reserved

3480 0000 34BF FFFF 0 3480 0000 0 34BF FFFF 4M Reserved

34C00000 34C2FFFF 34C00000 34C2FFFF 192K Reserved

34C3 0000 34FF FFFF 0 34C3 0000 0 34FF FFFF 4M-192K Reserved

ADVANCE INFORMATION

3500 0000 37FF FFFF 0 3500 0000 0 37FF FFFF 48M Reserved

3800 0000 3FFF FFFF 0 3800 0000 0 3FFF FFFF 128M Reserved

4000 0000 4FFF FFFF 0 4000 0000 0 4FFF FFFF 256M HyperLink Data

5000 0000 5FFF FFFF 0 5000 0000 0 5FFF FFFF 256M Reserved

6000 0000 6FFF FFFF 0 6000 0000 0 6FFF FFFF 256M PCIe Data

7000 0000 73FF FFFF 0 7000 0000 0 73FF FFFF 64M Reserved

7400 0000 77FF FFFF 0 7400 0000 0 77FF FFFF 64M Reserved

7800 0000 7BFF FFFF 0 7800 0000 0 7BFF FFFF 64M Reserved

7C00 0000 7FFF FFFF 0 7C00 0000 0 7FFF FFFF 64M Reserved

8000 0000 FFFF FFFF 8 8000 0000 8 FFFF FFFF 2G DDR3 EMIF Data

End of Table 2-2

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Bytes DescriptionStart End Start End

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

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SPRS689—November 2010

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset. A Hard reset, Soft reset or Local reset to an individual C66x CorePac should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section

7.7 ‘‘Reset Controller’’ on page 153.

The C6670 supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 59.

2.5 Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

• Public ROM Boot - C66x CorePac is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I execution from the L2 RAM base address.

• Secure ROM Boot - On secure devices, the C66x CorePac is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C66x CorePac initiates the boot process. The C66x CorePac performs any authentication and decryption required on the bootloaded image prior to beginning execution.

C ROM, Ethernet, or RapidIO), the C66x CorePac then begins

The boot process performed by the C66x CorePac in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac reads this value, and then executes the associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0]. The PLL settings is shown at the end of this section, and the PLL setup details can be found in Section 7.8 ‘‘Main PLL and the PLL

Controller’’ on page 160

Figure 2-2 Boot Mode Pin Decoding

Boot Mode Pins

12 11 10 9 8 7 6 5 4 3 2 1 0

PLL Mult I

C /SPI Ext Dev Cfg Device Configuration Reserved Boot Device

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2.5.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 ‘‘Boot Mode Pins: Boot

Device Values’’ shows the supported boot modes.

Table 2-3 Boot Mode Pins: Boot Device Values

Bit Field Value Description

2-0 Boot Device 0 No boot

1Serial Rapid I/O

2 Ethernet (SGMII) (PA driven from core clk)

ADVANCE INFORMATION

2.5.2 Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode

3 Ethernet (SGMII) (PA driver from PA clk)

4PCI

6SPI

7HyperLink

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2.5.2.1 No Boot Device Configuration

Figure 2-3 Sleep Configuration Bit Fields

9 8 7 6 5 4 3

Reserved Wait Enable Sub-Mode Reserved

Table 2-4 Sleep Configuration Bit Field Descriptions

Bit Field Value Description

9-8 Reserved Reserved

7 Wait Enable 0

6-5 Sub-Mode 0

1-3

4-3 Reserved Reserved

Wait enable disabled

Wait enable enabled

No Boot

Reserved

2.5.2.2 Ethernet (SGMII) Boot Device Configuration

Figure 2-4 Ethernet (SGMII) Device Configuration Bit Fields

9 8 7 6 5 4 3

SerDes Clock Mult Ext connection Dev ID

Multicore Fixed and Floating-Point System-on-Chip

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Table 2-5 Ethernet (SGMII) Configuration Bit Field Descriptions

Bit Field Value Description

9-8 SerDes clock mult

7-6 Ext connection 0

5-3 Device ID 0-7 This value is used in the device ID field of the Ethernet-ready frame.

The output frequency of the PLL must be 1.25 GBs.

×8 for input clock of 156.25 MHz

×5 for input clock of 250 MHz

×4 for input clock of 312.5 MHz

Reserved

Mac to Mac connection, master with auto negotiation

Mac to Mac connection, slave, and Mac to Phy

Mac to Mac, forced link

Mac to fiber connection

TMS320C6670

SPRS689—November 2010

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2.5.2.3 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-5 Serial Rapid I/O Device Configuration Bit Fields

9 8 7 6 5 4 3

Lane Setup Data Rate Ref Clock Reserved

Table 2-6 Serial Rapid I/O Configuration Bit Field Descriptions

Bit Field Value Description

ADVANCE INFORMATION

9Lane Setup 01Port Configured as 4 ports each 1 lane wide (4 -1× ports)

Port Configured as 2 ports 2 lanes wide (2 – 2× ports)

8-7 Data Rate 0

6-5 Ref Clock 0

4-3 Reserved 0-3 Reserved

Data Rate = 1.25 GBs

Data Rate = 2.5 GBs

Data Rate = 3.125 GBs

Data Rate = 5.0 GBs

Reference Clock = 156.25 MHz

Reference Clock = 250 MHz

Reference Clock = 312.5 MHz

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In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.

2.5.2.4 PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.

Figure 2-6 PCI Device Configuration Bit Fields

9 8 7 6 5 4 3

Reserved BAR Config Reserved

Table 2-7 PCI Device Configuration Bit Field Descriptions

Bit Field Value Description

9 Reserved Reserved

8-5 Bar Config 0-0xf See Table 2-8.

4-3 Reserved 0-3 Reserved

+ 176 hidden pages

Texas instruments TMS320C6670 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Release History

Contents

List of Figures

List of Tables

1 TMS320C6670 Features

1.1 KeyStone Architecture

1.2 Device Description

1.3 Functional Block Diagram

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

2.3 Memory Map Summary

2.4 Boot Sequence

2.5 Boot Modes Supported and PLL Settings

2.5.1 Boot Device Field

2.5.2 Device Configuration Field

2.5.2.1 No Boot Device Configuration

2.5.2.2 Ethernet (SGMII) Boot Device Configuration

2.5.2.3 Serial Rapid I/O Boot Device Configuration

2.5.2.4 PCI Boot Device Configuration