Texas instruments TMS320C6457 Data Manual

TMS320C6457

Communications Infrastructure Digital Signal Processor

Data Manual

PRODUCT ION DATA infor mation is current as of p ublication dat e.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS582B

July 2010

TMS320C6457

Data Manual

SPRS582B—July 2010

Release History

Additions/Modifications/Deletions

SPRS582B • Added 850 mHz clock speed.

• Added content to the Warm Reset section describing how to preserve contents of DDR2 SDRAM through a Warm Reset
cycle with Self-Refresh mode enabled on the SDRAM.

• Corrected typo in the Reset Timing Requirements table, parameter number 2: changed RESET

• Corrected 1.2-V to 1.1-V in last item of Features bullet list.

SPRS582A • Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times

• Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK

• Corrected PLL2 block diagram to include correct reference to PLLV

• Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table

• Removed PLLOUT term from the PLL2 Clock Frequency ranges table

• Clarified wording in the introduction of the PLL2 section and on the effective x5 multiplier that generates
DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) from DDRREFCLK(P|N) or ALTDDRCLK

• Added Table 7-4 Power Supply to Peripheral I/O Mapping to clarify the exact I/O and reference clock buffers each power
supply provides power for

• Added Overshoot/Undershoot definition to Table 6-1 Absolute Maximum Ratings

• Fixed typo in Table 2-1 under the 1.2 GHz space, “1.2 V, 1.8 V, and 3.3 V” now correctly reads “1.1 V, 1.8 V, and 3.3 V”

• Fixed typo for the McBSP timing parameters. “P = 1/CORECLK” now correctly reads “P = 1/SYSREFCLK”

• Fixed typo in 7.3.1 Power-Supply Sequencing - The SPRAAG5 reference now correctly references SPRAAV7

SPRS582 • Initial version

voltage net

2

x to RESET and POR to POR.

www.ti.com

2 Release History 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

Contents

1 TMS320C6457 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 TMS320C6457CMH/GMH BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2 CPU (DSP Core) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.5 Boot Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.5.1 Second-Level Bootloaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.6.1 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.7 Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.9 Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.4 Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.5 JTAG ID (JTAGID) Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.6 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4 System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.1 Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.2 Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.3 Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.4 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5 C64x+ Megamodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

5.1.4 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.5 Megamodule Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.6 Megamodule Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.7 C64x+ Megamodule Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

7 C64x+ Peripheral Information and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1.2 3.3-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.1.3 3.3-V Signal Transition Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.1.4 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.3.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

2009 Texas Instruments Incorporated Contents 3

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

7.3.2 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.3.3 Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.4 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

7.4.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.4.2 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.4.3 EDMA3 Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

7.5.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

7.5.2 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.6 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.6.1 Power-on Reset (POR

7.6.2 Warm Reset (RESET Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.6.3 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.6.4 CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.7 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.7 PLL1 and PLL1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.7.1 PLL1 Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.7.2 PLL1 Controller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

7.7.3 PLL1 Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.7.4 PLL1 Controller Input and Output Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.8 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.8.1 PLL2 Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.8.2 PLL2 Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.9 DDR2 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.9.1 DDR2 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.9.2 DDR2 Memory Controller Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.9.3 DDR2 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10 External Memory Interface A (EMIFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10.1 EMIFA Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10.2 EMIFA Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.10.3 EMIFA Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

2

7.11 I

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.11.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.11.2 I

2

C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.11.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.12 Host-Port Interface (HPI) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.1 HPI Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.2 HPI Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.3 HPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.13 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.13.1 McBSP Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.13.2 McBSP Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

7.14 Ethernet MAC (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.14.1 EMAC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.14.2 EMAC Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.14.3 EMAC Electrical Data/Timing (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15.1 MDIO Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15.2 MDIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.16 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.16.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.16.2 Timers Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.16.3 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.17 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.17.1 VCP2 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.17.2 VCP2 Peripheral Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.18 Enhanced Turbo Decoder Coprocessor (TCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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4Contents 2009 Texas Instruments Incorporated

TMS320C6457

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7.18.1 TCP2 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.19 UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.1 UTOPIA Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.2 UTOPIA Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.3 UTOPIA Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.20 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.20.1 Serial RapidIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.20.2 Serial RapidIO Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

7.20.3 Serial RapidIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.2 GPIO Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.3 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.22.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.3 Package CMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

8.4 Package GMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

SPRS582B—July 2010

2009 Texas Instruments Incorporated Contents 5

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

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List of Figures

Figure 1-1 CMH/GMH 688-Pin Ball Grid Array (BGA) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 1-2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 2-1 TMS320C64x+ CPU (DSP Core) Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 2-2 TMS320C6457 Pin Map (Bottom View) [Quadrant A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 2-3 TMS320C6457 Pin Map (Bottom View) [Quadrant B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 2-4 TMS320C6457 Pin Map (Bottom View) [Quadrant C] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 2-5 TMS320C6457 Pin Map (Bottom View) [Quadrant D] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 2-6 CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 2-7 Timers/GPIO/RapidIO Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-8 EMIFA and DDR2 Memory Controller Peripheral Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 2-9 HPI/McBSP/I

Figure 2-10 EMAC/MDIO (SGMII) Peripheral Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-11 UTOPIA Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 2-12 TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6457 DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 4-1 Data Switched Central Resource Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 4-2 Configuration Switched Central Resource (SCR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 5-1 64x+ Megamodule Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 5-2 TMS320C6457 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 5-3 TMS320C6457 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 5-4 TMS320C6457 L2 Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 7-1 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-2 Input and Output Voltage Reference Levels for 1.8-V AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-4 Input and Output Voltage Reference Levels for 3.3-V AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 7-5 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 7-6 Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 7-7 Power-Supply Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 7-8 NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Figure 7-9 Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Figure 7-10 Warm Reset Timing — RESETSTAT
Figure 7-11 Warm Reset Timing — Setup Time Between POR

Figure 7-12 PLL1 and PLL1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Figure 7-13 CORECLK(N|P) and ALTCORECLK Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-14 PLL2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-15 DDRREFCLK(N|P) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 7-16 EMIFA AECLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-17 EMIFA AECLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-18 EMIFA Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Figure 7-19 EMIFA Asynchronous Memory Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 7-20 EMIFA EM_Wait Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 7-21 EMIFA EM_Wait Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Figure 7-22 EMIFA Programmable Synchronous Interface Read Timing (With Read Latency = 2)
Figure 7-23 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 0)
Figure 7-24 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 1)
Figure 7-25 I
Figure 7-26 I
Figure 7-27 I

2

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

2

C Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

2

C Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Figure 7-28 HPI16 Read Timing (HAS
Figure 7-29 HPI16 Read Timing (HAS
Figure 7-30 HPI16 Write Timing (HAS
Figure 7-31 HPI16 Write Timing (HAS
Figure 7-32 HPI32 Read Timing (HAS

2

C Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Relative to RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

De-Asserted and RESET Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Used). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

6List of Figures 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Figure 7-33 HPI32 Read Timing (HAS Used). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Figure 7-34 HPI32 Write Timing (HAS
Figure 7-35 HPI32 Write Timing (HAS

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Figure 7-36 McBSP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 7-37 FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 7-38 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 7-39 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Figure 7-40 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Figure 7-41 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Figure 7-42 EMAC, MDIO, and EMAC Control Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Figure 7-43 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Figure 7-44 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Figure 7-45 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 7-46 UXCLK Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-47 URCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-48 UTOPIA Slave Transmit Timing
Figure 7-49 UTOPIA Slave Receive Timing

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 7-50 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-51 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-52 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-53 HS-RTDX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Figure 8-1 CMH (S–PBGA–N688) Pb-Free Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 8-2 GMH (S–PBGA–N688) Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

SPRS582B—July 2010

2009 Texas Instruments Incorporated List of Figures 7

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

www.ti.com

List of Tables

Table 2-1 Characteristics of the C6457 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 2-2 TMS320C6457 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 2-3 TMS320C6457 Supported Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 2-4 Serial RapidIO (SRIO) Supported Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 2-5 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-7 Relevant Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 3-1 TMS320C6457 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 3-3 Device Configuration Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-4 Device Configuration Status Register (DEVSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-5 Device Configuration Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-6 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 3-7 JTAG ID (JTAGID) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 4-1 SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-2 TMS320C6457 Default Bus Master Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-3 Priority Allocation Register (PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-4 Priority Allocation Register (PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 5-1 Available Memory Page Protection Scheme With Privilege ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 5-2 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 5-3 Megamodule Reset (Global or Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-4 Megamodule Revision ID Register (MM_REVID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-5 Megamodule Revision ID Register (MM_REVID) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-6 Megamodule Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-7 Megamodule Powerdown Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-8 Megamodule Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-9 Megamodule IDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-10 Megamodule Cache Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-11 Megamodule Error Detection Correct Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 5-12 Megamodule L1/L2 Memory Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 5-13 CPU Megamodule Bandwidth Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 6-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 6-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 6-4 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 7-1 Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 7-2 Timing Requirements for Power-Supply Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 7-3 C6457 EDMA3 Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 7-4 EDMA3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Table 7-5 EDMA3 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-6 EDMA3 Transfer Controller 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-7 EDMA3 Transfer Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7-8 EDMA3 Transfer Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table 7-9 EDMA3 Transfer Controller 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 7-10 EDMA3 Transfer Controller 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 7-11 EDMA3 Transfer Controller 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Table 7-12 TMS320C6457 System Event Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Table 7-13 Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 7-14 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 7-15 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-16 Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-17 Software Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

8List of Tables 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 7-18 Software Reset Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-19 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-20 Reset Configuration Register (RSTCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-21 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-22 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-23 Warm Reset Switching Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-24 Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-25 PLL1 Stabilization, Lock, and Reset Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-26 PLL1 Controller Registers (Including Reset Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Table 7-27 PLL1 Control Register (PLLCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-28 PLL1 Control Register (PLLCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-29 PLL Multiplier Control Register (PLLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-30 PLL Multiplier Control Register (PLLM) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-31 PLL Post-Divider Control Register (POSTDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-32 PLL Post-Divider Control Register (POSTDIV) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-33 PLL Controller Divider 3 Register (PLLDIV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-34 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-35 PLL Controller Divider 6 Register (PLLDIV6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-36 PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-37 PLL Controller Divider 7 Register (PLLDIV7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-38 PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-39 PLL Controller Divider 8 Register (PLLDIV8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-40 PLL Controller Divider 8 Register (PLLDIV8) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-41 PLL Controller Command Register (PLLCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-42 PLL Controller Command Register (PLLCMD) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-43 PLL Controller Status Register (PLLSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-44 PLL Controller Status Register (PLLSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-45 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-46 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-47 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-48 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-49 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-50 SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-51 CORECLK(N|P) and ALTCORECLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-52 PLL2 Clock Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-53 Timing Requirements for DDRREFCLK(N|P) and ALTDDRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-54 DDR2 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Table 7-55 EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Table 7-56 EMIFA AECLKIN Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-57 EMIFA AECLKOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-58 EMIFA Asynchronous Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-59 EMIFA Asynchronous Memory Read Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-60 EMIFA Asynchronous Memory Write Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 7-61 EMIFA EM_Wait Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-62 EMIFA EM_Wait Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-63 EMIFA EM_Wait Write Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-64 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-65 Switching Characteristics for Programmable Synchronous Interface Cycles for EMIFA Module. . . . . . . . . . . . . . . . . . . . . .152

Table 7-66 I
Table 7-67 I
Table 7-68 I

2

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

2

C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

2

C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Table 7-69 HPIWIDTH Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 7-70 HPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 7-71 Host-Port Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

SPRS582B—July 2010

2009 Texas Instruments Incorporated List of Tables 9

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 7-72 Host-Port Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 7-73 McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 7-74 McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-75 McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-76 Switching Characteristics for McBSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 7-77 Timing Requirements for FSR When GSYNC = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Table 7-78 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Table 7-79 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Table 7-80 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-81 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-82 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-83 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-84 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-85 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Table 7-86 Ethernet MAC (EMAC) Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Table 7-87 EMAC Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 7-88 EMAC Descriptor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-89 SGMII Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-90 EMIC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-91 MDIO Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Table 7-92 MDIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-93 MDIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-94 Timer1 Watchdog Reset Selection Register (WDRSTSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-95 Timer1 Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-96 Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-97 Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-98 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-99 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-100 VCP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Table 7-101 TCP2_A Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-102 TCP2_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-103 UTOPIA Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-104 UTOPIA Data Queues (Receive and Transmit) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-105 UXCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-106 URCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-107 UTOPIA Slave Transmit Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-108 UTOPIA Slave Transmit Cycles Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-109 UTOPIA Slave Receive Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-110 Switching Characteristics for UTOPIA Slave Receive Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-111 RapidIO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Table 7-112 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Table 7-113 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-114 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-115 Switching Characteristics for Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Table 7-116 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-117 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-118 Timing Requirements for HS-RTDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-119 Switching Characteristics for HS-RTDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 8-1 Thermal Resistance Characteristics (PBGA Package) [CMH/GMH] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

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10 List of Tables 2009 Texas Instruments Incorporated

www.ti.com

1 TMS320C6457 Features

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

• High-Performance Fixed-Point DSP (C6457)
– 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time
– 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 8000 and 9600 MIPS/MMACS (16-Bits)
– Case Temperature

›Commercial:

» 0ºC to 100ºC (850 MHz)
» 0ºC to 100ºC (1 GHz)
» 0ºC to 95ºC (1.2 GHz)

› Extended:

» -40ºC to 100ºC (1 GHz)
» -40ºC to 95ºC (1.2 GHz)

• TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling

• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:

– 256K-Bit (32K-Byte) L1P Program Cache [Direct

Mapped]

– 256K-Bit (32K-Byte) L1D Data Cache [2-Way

Set-Associative]

– 16M-Bit (2048K-Byte) L2 Unified Mapped

Ram/Cache [Flexible Allocation]

› Configurable up to 1MB of L2 Cache
– 512K-Bit (64K-Byte) L3 ROM
– Time Stamp Counter

•Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters

• Two Enhanced Turbo Decoder Coprocessors
(TCP2_A and TCP2_B)

– Each TCP2 Supports up to Eight 2-Mbps 3GPP

(6 Iterations)

– Programmable Turbo Code and Decoding

Parameters

• Endianess: Little Endian, Big Endian

• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous Memories

(SRAM, Flash, and EEPROM) and Synchronous
Memories (SBSRAM, ZBT SRAM)

– Supports Interface to Standard Sync Devices and

Custom Logic (FPGA, CPLD, ASICs, etc.)

– 32M-Byte Total Addressable External Memory

Space

• 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)

• Four 1× Serial RapidIO® Links (or One 4×), v1.3
Compliant

– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing, DirectIO Support, Error Mgmt

Extensions, Congestion Control

– IEEE 1149.6 Compliant I/Os

• EDMA3 Controller (64 Independent Channels)

•32-/16-Bit Host-Port Interface (HPI)

• Two 1.8-V McBSPs

• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
–Supports SGMII, v1.8 Compliant
– 8 Independent Transmit (TX) and 8 Independent

Receive (RX) Channels

• Two 64-Bit General-Purpose Timers
– Configurable as Four 32-Bit Timers
– Configurable in a Watchdog Timer Mode

•UTOPIA
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up to

50 MHz per Direction

– User-Defined Cell Format up to 64 Bytes

• One 1.8-V Inter-Integrated Circuit (I2C) Bus

• 16 General-Purpose I/O (GPIO) Pins

• System PLL and PLL Controller

• DDR PLL, Dedicated to DDR2 Memory Controller

• Advanced Event Triggering (AET) Compatible

• Trace-Enabled Device

• Supports IP Security

• IEEE-1149.1 and IEEE-1149.6 (JTAG™)
Boundary-Scan-Compatible

• 688-Pin Ball Grid Array (BGA) Package (CMH or GMH
Suffix), 0.8-mm Ball Pitch

• 0.065-μm/7-Level Cu Metal Process (CMOS)

• 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal

PRODUCT PREVIEW

2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

1.1 TMS320C6457CMH/GMH BGA Package (Bottom View)

Figure 1-1 CMH/GMH 688-Pin Ball Grid Array (BGA) Package

AH

AF

AD

AB

Y

V

T

PRODUCT PREVIEW

P

M

K

H

F

D

B

CMH/GMH 688-PIN BALL GRID ARRAY (BGA) PACKAGE

AG

AE

AC

AA

W

U

R

N

L

J

G

E

C

A

1345678910111213141516171819202122232425

2

(BOTTOM VIEW)

26

27

28

www.ti.com

(A) The CMH mechanical package designator represents the version of the GMH package with lead-free balls. For more detailed information, see ‘‘Mechanical Data’’ on

page 209 of this document.

1.2 Description

The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP
generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSPs an excellent choice for applications including video and telecom
infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible
from previous devices that are part of the C6000™ DSP platform.

Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or
9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to
high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed
controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000
devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply
throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock
cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this
means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one
32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.

The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system
performance and reduces system cost for applications that include multiple DSPs on a board, such as video and
telecom infrastructures and medical/imaging.

12 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1
(L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped
RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped
cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program
and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some
combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral
configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control,
interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

2

The peripheral set includes: an inter-integrated circuit bus module (I
(McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave
[UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a
user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port
(GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller
(EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a
management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO
addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA),
which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.

The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor
(VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps
adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and
9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions.
Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels
(assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all
polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully
programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and
stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out
through the EDMA3 controller.

C); two multichannel buffered serial ports

SPRS582B—July 2010

PRODUCT PREVIEW

The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code
execution.

2009 Texas Instruments Incorporated 13

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

1.3 Functional Block Diagram

Figure 1-2 Shows the functional block diagram of the TMS320C6457 device.

Figure 1-2 Functional Block Diagram

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DDR2 SDRAM

I/O Devices

32

64

DDR2

Mem Ctlr

PLL2

EMIFA

TCP2_A

PRODUCT PREVIEW

TCP2_B

VCP2

McBSP0

McBSP1

Serial Rapid

I/O

HPI (32/16)

UTOPIA

EMAC

10/100/1000

SGMII

MDIO

Primary Switched Central Resource

L2

Cache

Memory

2048K

Bytes

L1P SRAM/Cache Direct-Mapped

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

Instruction Fetch

16-/32-bit

Instruction Dispatch

Instruction
M
e
g
a
m
o
d
u

l

e

Decode

Data Path A

A Register File

A31−A16

A15−A0

.L1 .S1

.M1

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

C64x+ DSP Core

.D1 .D2

xx
xx

32K Bytes

Control Registers

SPLOOP Buffer

In-Circuit Emulation

Data Path B

B Register File

B31−B16

B15−B0

.M2

xx
xx

.S2 .L2

C6457

Power Control

System

Interrupt and Exception Controller

(Memory Protect/

Bandwidth Mgmt)

L2 Memory Controller

(IDMA)

Internal DMA

16

GPIO16

I2C

Timer1

HI

LO

Timer0

HI

LO

L1D SRAM/Cache

2-Way

Set-Associative

(A)

EDMA 3.0

L3 ROM

(A)

Secondary

Switched Central

Resource

32K Bytes Total

PLL1 and

PLL1

Controller

Boot Configuration

Device

Configuration

Logic

(A) Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either one 64-bit general-purpose timer or two 32-bit general-purpose timers or a watchdog timer.

14 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320C6457 DSP. The table shows significant features of the C6457 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package and pin count.

2.2 CPU (DSP Core) Description

Table 2-1 Characteristics of the C6457 Processor (Part 1 of 2)

HARDWARE FEATURES TMS320C6457

EMIFA (64-bit bus width) (clock source = AECLKIN or SYSCLK7) 1

DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock source = DDRREFCLKN|P)

EDMA3 (64 independent channels) [CPU/3 clock rate] 1

High-speed 1×/4× Serial RapidIO Port (4 lanes) 1

2

C 1

I

Peripherals

Decoder
Coprocessors

On-Chip Memory

C64x+ Megamodule
Revision ID

JTAG BSDL_ID JTAGID register (address location: 0288 0818h)

Frequency MHz 850, 1000 (1 GHz), and 1200 (1.2 GHz)

Cycle Time ns 1.18 ns, 1 ns, and 0.83 ns (0.85, 1.0, & 1.2-GHz CPU)

Voltage

PLL1 and PLL1
Controller Options

PLL2 DDR2 Clock ×10

BGA Package 23 mm × 23 mm 688-Pin Flip-Chip Plastic BGA (CMH/GMH)

Process Technology μm 0.065 μm

HPI (32-or 16-bit user selectable) 1 (HPI16 or HPI32)

McBSPs (internal or external clock source up to 100 Mbps) 2

UTOPIA (8-bit mode, 50-MHz, slave-only) 1

10/100/1000 Ethernet MAC (EMAC) 1

Management Data Input/Output (MDIO) 1

64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) 2 64-bit or 4 32-bit

General-Purpose Input/Output Port (GPIO) 16

VCP2 (clock source = CPU/3 clock frequency) 1

TCP2 (clock source = CPU/3 clock frequency) 2

Size (Bytes) 2176K

Organization

Megamodule Revision ID Register (address location: 0181 2000h)

850-MHz CPU 1.1 V

Core (V)

I/O (V)

CLKIN1 frequency multiplier Bypass (×1), (×4 to ×32)

1-GHz CPU 1.1 V

1.2-GHz CPU 1.2 V

850-MHz CPU 1.1 V, 1.8 V, and 3.3 V

1-GHz CPU 1.1 V, 1.8 V, and 3.3 V

1.2-GHz CPU 1.1 V, 1.8 V, and 3.3 V

1

32KB L1 Program Memory Controller [SRAM/Cache]
32KB L1 Data Memory Controller [SRAM/Cache]
2048KB L2 Unified Memory/Cache 64KB L3 ROM

See Section 5.6 ‘‘Megamodule Revision’’ on
page 77

See Section 3.5 ‘‘JTAG ID (JTAGID) Register

Description’’ on page 62

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 15

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-1 Characteristics of the C6457 Processor (Part 2 of 2)

HARDWARE FEATURES TMS320C6457

Product Status Production Data (PD) PD

Device Part
Numbers

End of Table 2-1

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths
as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total
of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types
supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than
32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an

PRODUCT PREVIEW

even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

(For more details on the C64x+™ DSP part numbering, see Figure 2-12)

www.ti.com

TMS320C6457CMH/GMH

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 × 32 bit multiply, two 16 × 16 bit
multiplies, two 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four
16 × 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois
field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit
real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one
32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 × 32 bit multiply instructions
provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and
unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of
common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual
16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances
the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the
.L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that
do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained
high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for
parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP — A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with
software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions — The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can
restrict the code to use certain registers in the register file. This compression is performed by the code
generation tools.

• Instruction Set Enhancements — As noted above, there are new instructions such as 32-bit multiplications,
complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

16 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

• Exception Handling — Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect
and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system
events (such as a watchdog time expiration).

• Privilege — Defines user and supervisor modes of operation, allowing the operating system to give a basic level
of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and
execute permissions.

• Time-Stamp Counter — Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU, which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)

• TMS320C64x+ Megamodule Reference Guide (literature number SPRU871)

• TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84)

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 17

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-1 shows the DSP core functional units and data paths.

Figure 2-1 TMS320C64x+ CPU (DSP Core) Data Paths

www.ti.com

PRODUCT PREVIEW

Data path A

ST1b

ST1a

LD1b

LD1a

LD2a
LD2b

32 MSB

32 LSB

32 MSB

32 LSB

DA1

DA2

32 LSB

32 MSB

.L1

.S1

.M1

.D1

.D2

.M2

src1

src2

odd dst

even dst

long src

long src

even dst

odd dst

src1

src2

dst2
dst1
src1

src2

src1

src2

src2

src1

src2

src1
dst2

dst1

dst

dst

Odd

register

file A

(A1, A3,

A5...A31)

(D)

8

8

(D)

32

32

32

32

(A)
(B)

(C)

2x

1x

(C)

(B)

(A)

Odd

register

file B

(B1, B3,

B5...B31)

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

src2

src1

.S2

.L2

odd dst

even dst

long src

long src

even dst

odd dst

src2

src1

8

8

Data path B

32 MSB

ST2a

32 LSB

ST2b

(A) On .M unit, dst2 is 32 MSB. ____(B) On .M unit, dst1 is 32 LSB. ____(C) On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.

(D) On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

(D)

(D)

Control Register

18 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the TMS320C6457 device. The external memory configuration

register address ranges in the C6457 device begin at the hex address location 0x7000 0000 for EMIFA and hex
address location 0x7800 0000 for DDR2 Memory Controller.

Table 2-2 TMS320C6457 Memory Map Summary (Part 1 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 8M 0000 0000 - 007F FFFF

L2 SRAM 2M 0080 0000 - 009F FFFF

Reserved 4M 00A0 0000 - 00DF FFFF

L1P SRAM 32K 00E0 0000 - 00E0 7FFF

Reserved 1M - 32K 00E0 8000 - 00EF FFFF

L1D SRAM 32K 00F0 0000 - 00F0 7FFF

Reserved 1M -32K 00F0 8000 - 00FF FFFF

Reserved 8M 0100 0000 - 017F FFFF

C64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFF

Reserved 12.5M 01C0 0000 - 0287 FFFF

HPI Control Registers 256 0288 0000 - 0288 00FF

Reserved 2K - 256 0288 0100 - 0288 07FF

Chip-Level Registers 1K 0288 0800 - 0288 0BFF

Reserved 253K 0288 0C00 - 028B FFFF

McBSP 0 Registers 256 028C 0000 - 028C 00FF

Reserved 256K - 256 028C 0100 - 028F FFFF

McBSP 1 Registers 256 0290 0000 - 0290 00FF

Reserved 256K - 256 0290 0100 - 0293 FFFF

Timer 0 Registers 128 0294 0000 - 0294 007F

Reserved 256K - 128 0294 0080 - 0297 FFFF

Timer 1 Registers 128 0298 0000 - 0298 007F

Reserved 128K - 128 0298 0080 - 0299 FFFF

PLL Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FF

Reserved 384K - 512 029A 0200 - 029F FFFF

EDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFF

Reserved 96K 02A0 8000 - 02A1 FFFF

EDMA3 Transfer Controller 0 Registers 1K 02A2 0000 - 02A2 03FF

Reserved 31K 02A2 0400 - 02A2 7FFF

EDMA3 Transfer Controller 1 Registers 1K 02A2 8000 - 02A2 83FF

Reserved 31K 02A2 8400 - 02A2 FFFF

EDMA3 Transfer Controller 2 Registers 1K 02A3 0000 - 02A3 03FF

Reserved 31K 02A3 0400 - 02A3 7FFF

EDMA3 Transfer Controller 3 Registers 1K 02A3 8000 - 02A3 83FF

Reserved 31K 02A3 8400 - 02A3 FFFF

EDMA3 Transfer Controller 4 Registers 1K 02A4 0000 - 02A4 03FF

Reserved 31K 02A4 0400 - 02A4 7FFF

EDMA3 Transfer Controller 5 Registers 1K 02A4 8000 - 02A4 83FF

Reserved 479K 02A4 8400 - 02AB FFFF

Power / Sleep Controller (PSC) 4K 02AC 0000 - 02AC 0FFF

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 19

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-2 TMS320C6457 Memory Map Summary (Part 2 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 60K 02AC 1000 - 02AC FFFF

Embedded Trace Buffer (ETB) 8K 02AD 0000 - 02AD 1FFF

Reserved 184K 02AD 2000 - 02AF FFFF

GPIO Registers 256 02B0 0000 - 02B0 00FF

Reserved 16K - 256 02B0 0100 - 02B0 3FFF

I2C Data and Control Registers 128 02B0 4000 - 02B0 407F

Reserved 240K - 128 02B0 4080 - 02B3 FFFF

UTOPIA Control Registers 512 02B4 0000 - 02B4 01FF

Reserved 256K - 512 02B4 0200 - 02B7 FFFF

PRODUCT PREVIEW

VCP2 Control Registers 256 02B8 0000 - 02B8 00FF

Reserved 128K - 256 02B8 0100 - 02B9 FFFF

TCP2_A Control Registers 256 02BA 0000 - 02BA 00FF

TCP2_B Control Registers 256 02BA 0100 - 02BA 01FF

Reserved 640K - 512 02BA 0200 - 02C3 FFFF

SGMII Control 256 02C4 0000 - 02C4 00FF

Reserved 256K - 256 02C4 0100 - 02C7 FFFF

EMAC Control 2K 02C8 0000 - 02C8 07FF

Reserved 2K 02C8 0800 - 02C8 0FFF

EMAC Interrupt Controller 256 02C8 1000 - 02C8 10FF

Reserved 2K - 256 02C8 1100 - 02C8 17FF

MDIO Control Registers 256 02C8 1800 - 02C8 18FF

Reserved 2K - 256 02C8 1900 - 02C8 1FFF

EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF

Reserved 496K 02C8 4000 - 02CF FFFF

RapidIO Control Registers 132K 02D0 0000 - 02D2 0FFF

Reserved 892K 02D2 1000 - 02DF FFFF

RapidIO Descriptor Memory 16K 02E0 0000 - 02E0 3FFF

Reserved 1M - 16K 02E0 4000 - 02EF FFFF

Reserved 1M 02F0 0000 - 02FF FFFF

Reserved 208M 0300 0000 - 0FFF FFFF

Reserved 512M 1000 0000 - 2FFF FFFF

McBSP 0 Data 256 3000 0000 - 3000 00FF

Reserved 64M - 256 3000 0100 - 33FF FFFF

McBSP 1 Data 256 3400 0000 - 3400 00FF

Reserved 128M - 256 3400 0100 - 3BFF FFFF

L3 ROM 64K 3C00 0000 - 3C00 FFFF

Reserved 16M - 64K 3C01 0000 - 3CFF FFFF

UTOPIA Receive (RX) Data 128 3D00 0000 - 3D00 007F

Reserved 896 3D00 0080 - 3D00 03FF

UTOPIA Transmit (TX) Data 128 3D00 0400 - 3D00 047F

Reserved 304M - 1152 3D00 0480 - 4FFF FFFF

TCP2_A Data 1M 5000 0000 - 500F FFFF

TCP2_B Data 1M 5010 0000 - 501F FFFF

Reserved 126M 5020 0000 - 57FF FFFF

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20 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-2 TMS320C6457 Memory Map Summary (Part 3 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

VCP2 Data 64K 5800 0000 - 5800 FFFF

Reserved 384M - 64K 5801 0000 - 6FFF FFFF

EMIFA (EMIF64) Configuration Registers 256 7000 0000 - 7000 00FF

Reserved 128M - 256 7000 0100 - 77FF FFFF

DDR2 EMIF Configuration Registers 256 7800 0000 - 7800 00FF

Reserved 128M - 256 7800 0100 - 7FFF FFFF

Reserved 512M 8000 0000 - 9FFF FFFF

EMIFA CE2 Data -SBSRAM/Async 8M A000 0000 - A07F FFFF

Reserved 256M - 8M A080 0000 - AFFF FFFF

EMIFA CE3 Data -SBSRAM/Async 8M B000 0000 - B07F FFFF

Reserved 256M - 8M B080 0000 - BFFF FFFF

EMIFA CE4 Data -SBSRAM/Async 8M C000 0000 - C07F FFFF

Reserved 256M - 8M C080 0000 - CFFF FFFF

EMIFA CE5 Data -SBSRAM/Async 8M D000 0000 - D07F FFFF

Reserved 256M - 8M D080 0000 - DFFF FFFF

DDR2 EMIF CE0 Data 512M E000 0000 - FFFF FFFF

End of Table 2-2

TMS320C6457

SPRS582B—July 2010

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset, warm reset, and system reset. A local reset to an individual C64x+ Megamodule should
not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see
Section 7.6 ‘‘Reset Controller’’ on page 123.

The C6457 supports several boot processes begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software driven; using the
BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed.

2.5 Boot Modes Supported

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:

• Public ROM Boot - C64x+ Megamodule is released from reset and begins executing from the L3 ROM base
address. After performing the boot process (e.g., from I
Megamodule then begins execution from the L2 RAM base address.

• Secure ROM Boot - On secure devices, the C64x+ Megamodule is released from reset and begin executing
from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C64x+
Megamodule initiates the boot process. The C64x+ Megamodule performs any authentication and decryption
required on the bootloaded image prior to beginning execution.

2

C ROM, Ethernet, or RapidIO), the C64x+

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 21

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

The boot process performed by the C64x+ Megamodule in public ROM boot and secure ROM boot are determined
by the BOOTMODE[3:0] value in the DEVSTAT register. The C64x+ Megamodule reads this value, and then
executes the associated boot process in software. Table 2-3 shows the supported boot modes.

Table 2-3 TMS320C6457 Supported Boot Modes

Mode Name Bootmode[3:0] Description

No Boot 0000b No Boot

2

C Master Boot A 0001b Slave I2C address is 0x50. The C64x+ Megamodule configures I2C, acts as a master to the I2C bus and

I

2

I

C Master Boot B 0010b Similar to I2C boot A except the slave I2C address is 0x51.

2

C Slave Boot 0011b The C64x+ Megamodule configures I2C and acts as a slave and will accept data and code section

I

PRODUCT PREVIEW

HPI Boot 0100b Host boot.

EMIFA Boot 0101b External memory boot from ACE3 space (0xB0000000 address).

EMAC Master Boot 0110b

EMAC Slave Boot 0111b

EMAC Forced-Mode Boot 1000b

Reserved 1001b Reserved

RapidIO Boot (Config 0) 1010b

RapidIO Boot (Config 1) 1011b

RapidIO Boot (Config 2) 1100b

RapidIO Boot (Config 3) 1101b

End of Table 2-3

www.ti.com

copies data from an I
table format. The destination address and length are contained within the boot table.

packets through the I2C interface. It is required that an I

TI Ethernet Boot. The C64x+ Megamodule configures EMAC and EDMA, if required, and brings the
code image into the internal on-chip memory via the protocol defined by the boot method (EMAC
bootloader).

The C64x+ Megamodule configures the SRIO and an external host loads the application via SRIO
peripheral, using directIO protocol. A doorbell interrupt is used to indicate that the code has been
loaded. For more details on the RapidIO configurations, see Table 2-4.

2

C EEPROM or a device acting as an I2C slave to the DSP using a predefined boot

2

C master is present in the system.

The C64x+ Megamodule configures Serial RapidIO, EMAC, and EDMA, if required, and brings the code image into
the internal on-chip memory via the protocol defined by the boot method (SRIO EMAC bootloader).

Table 2-4 Serial RapidIO (SRIO) Supported Boot Modes

SRIO Boot Mode SerDes Clock Link Rate SRIO Boot Configuration

Bootmode 10 - Config 0 125 MHz 1.25 Gbps Four 1× SRIO links

Bootmode 11 - Config 1 125 MHz 3.125 Gbps One 4× SRIO link

Bootmode 12 - Config 2 156.25 MHz 1.25 Gbps One 4× SRIO link

Bootmode 13 - Config 3 156.25 MHz 3.125 Gbps One 4× SRIO link

End of Table 2-4

All the other BOOTMODE[3:0] modes are reserved.

2.5.1 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.

22 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

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2.6 Pin Assignments

2.6.1 Pin Map

Figure 2-2 through Figure 2-5 show the C6457 pin assignments in four quadrants (A, B, C, and D).

Figure 2-2 TMS320C6457 Pin Map (Bottom View) [Quadrant A]

1

432

65

10987

1211

13

TMS320C6457

SPRS582B—July 2010

14

V

AH CORECLKP

DDS18_1

V

AG

TDO

AF

EMU12

AE

EMU15

AD

EMU14 EMU18 RSV01

AC

TDI

AB

EMU17

AA

Y

CLKS1

HD11 DR1

W

SS

V

SS

EMU7

EMU11

TRST

V

SS

V

RSV02

V

SS

TMS CLKR1DX1

HD00

EMU8

EMU13

EMU10

EMU16

DDS18_1

CLKX0

CLKX1

EMU4

EMU5

EMU6

EMU3

EMU9

RSV03

CLKS0

FSX0

EMU2

V

DDS18_1

V

EMU1

EMU0

V

DDA18V1

RSV12

RSV13

CLKR0

FSX1

SS

RIOSGMII

CLKN

ALTCORE

CLK

CORE

CLKSEL

RSV24

RSV20 RSV21

V

SS

V

DDS18_1

DR0

DX0

CORECLKN RIOTXN1

RIOSGMII

CLKP

RSV09

RSV08

SYSCLK

OUT

V

DDS18_1

V

V

DDS18_1

V

V

SS

RIORXN0

RIOTXP0

SS

SS

V

DDS18_1

RIORXP0

V

V

DDT

SS

RIOTXN0

V

V

V

DDT

SS

V

SS

V

SS

SS

RIOTXP1

V

SS

RIORXP1

V

DDR4

V

SS

V

DDA

V

SS

V

SS

V

SS

V

DDT

RIORXN1

V

SS

V

DDT

V

SS

V

SS

V

DDD

RIORXN1TCLK

RSV16

RIORXP1

V

RIOTXN3

SS

RIOTXN2

SGMIITXP

RIOTXP314AG

RIOTXP2

RIORXN3RIORXP3

V

V

V

V

SS

DDA

SS

DDT

V

SS

V

SS

AH

AF

V

AE

SS

V

AD

SS

V

AC

DDA

V

AB

SS

AA

PRODUCT PREVIEW

Y

V

V

SS

V

DDD

W

SS

HD22

V

U

HD21 HD27 HD23

HD19 HD15

T

HD17

R R

HD25

HD13

V

DDS33

V

FSR0

HD05

SS

HD09

V

V

SS

DDS33

FSR1

HD29HD03

HD10HD07

V

DDS18_1

HD06

HD04

V

SS

V

DDS33

V

SS

V

DDS33

V

V

RSV23

RSV23

V

DD

SS

V

SS

V

V

V

V

DD

V

SS

V

DD

V

V

DDD

SS

DD

SS

SS

V

DDD

V

SS

V

DD

V

DDD

V

U

SS

V

T

DD

V

SS

13121110987654321

2009 Texas Instruments Incorporated Device Overview 23

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-3 TMS320C6457 Pin Map (Bottom View) [Quadrant B]

15

181716

19

20

2221

www.ti.com

23

24

25

26

27

28

SGMIITXN

AH TINP0L

V

AG

V

AF

V

AE

PRODUCT PREVIEW

V

AD

V

AC

V

AB

V

V

SS

RSV17

SS

SGMIIRXN

DDT

V

SS

DDR3

V

DDT

SS

SS

SS

V

DDA

V

SS

DDT

V

SS

SGMIIRXP

V

SS

V

DDT

V

SS

V

SS

AA

Y

V

W

V

DDD

V

SS

DD

MDCLK

V

V

DDS18_2

V

V

DDS18_2

V

V

DDS18_2

V

MDIO

NMI

V

SS

DDS18_2

V

SS

V

DD

TOUT0LTINP1L

RSV14

RSV06

RSV04

V

SS

TOUT1L

SS

V

SS

SS

V

SS

DDS18_2

RSV18

RSV19

RSV07

RSV05

V

RSV15

DDS18_2

V

SS

RSV29

POR

RSV27

RSV26

V

DDS18_2

V

V

DDS33_1

V

V

DDS33_1

V

SS

SS

SS

RESET

RSV28

RESETSTAT

RSV22

V

SS

V

DDS33_1

V

SS

DDS33_1

V

SS

V

DDS33_1

V

AED03 AED16

V

AED00

AED24 AED28

ASDWE

ABE01

ARNW ACE2

AED05

DDS33_1

V

AED14

SS

AED09

AOEAED01

AED07

DDS33_1

AED11

AED26 V

AED23V

ABE00 AED27AED31

ACE3

V

AED06

AED02

AED20

AED18

AED15AED10

AED12 AED17

AED08

AED25

AED04

AED13

AED22

V

SS

DDS33_1

V

SS

AED30

AED19

AED21

V

DDS33_1

SS

AED29

ABE03

ABE02

ABE07

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

V

V

U

V

T

V

R R

V

SS

V

DD

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

V

DD

V

SS

V

DD

V

DD

SS

DD

SS

V

SS

DDMON

V

SS

V

DD

V

DDS33_1

V

DD33MON

V

DDS33_1

V

V

ABA1

SS

V

SS

V

AEA14

SS

V

SS

DDS33_1

AEA08

ABA0 ACE5

V

AEA00

SS

AEA01

AEA11 AEA02 AEA03 AEA06

AADS

AEA13

VSSAECLKOUT

ACE4

AEA04

AEA05

AHOLD

27262524232221201918171615

28

V

U

T

24 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Figure 2-4 TMS320C6457 Pin Map (Bottom View) [Quadrant C]

TMS320C6457

SPRS582B—July 2010

15

V

P

V

N

V

M

V

L

V

K

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

181716

V

SS

V

DD

V

SS

V

DD

V

SS

19

V

DD

V

SS

V

DD

V

SS

V

DD

20

SS

DD

SS

DD

SS

J

H

V

V

G

DDS18

V

F

V

V

DDS18

SS

DDS18

SS

DDRA00

V

V

DDS18

V

DDS18

SS

DDRRCVEN

V

SS

OUT1

V

V

DDS18

SS

V

2221

V

DDS33_1

V

V

DDS33_1

V

V

DDS33_1

V

V

DDS33_1

V

V

SS

23

V

V

DDS33_1

SS

V

V

DDS33_1

SS

V

V

DDS33_1

SS

V

V

SS

DD18MON

GP15

SS

24

AEA19

SS

AEA10

AEA17 AEA09

SS

AED33

SS

AED47

AED55 AED43

SS

AED63

SCL

25

AEA16

26

AEA15

AHOLDA

AEA18

ABUSREQ0

ABE06

AED46AED38 AED34AED32

AED45

AED44

AED54 V

AED36

V

SS

27

V

DDS33_1

AEA12AEA07

V

DDS33_1

ABE04

AED42

DDS33_1

AED48AED50

AED52AED56

28

V

SS

AECLKIN

V

SS

ABE05

AARDY

AED40

V

SS

AED35

AED37

P

N

M

L

K

J

H

G

F

PRODUCT PREVIEW

DDRODT

E

DDRA08

D

DDRA09

C

DDRA10 DDRA07 DDRD16

B

A

DDRA11

DDRA04

DDRA05

DDRA06

DDRA01

DDRA02

DDRA03

DDRCLK

OUT_N1

DDRCLK

OUT_P1

V

SS

DDRD19

DDRD18

DDRD17

DDRDQS2P

DDRDQS2N

DDRDQM2

V

DDS18

V

SS

DDRRCVEN

IN1

DDRD23

DDRD21

V

DDS18

DDRD27

DDRD26DDRD22

DDRD25

DDRD24DDRD20PTV18

DDRDQS3P

DDRDQS3N

DDRDQM3

V

DDS18

V

SS

V

DDS18

SDA

GP14 GP12

GP13

GP09

DDRD29 DDRD31

DDRD28 DDRD30

V

DDS33_1

AED57 AED53

AED59

V

DDS33_1

AED58 AED39

GP11 AED61 AED60 AED41

GP08

GP10 AED62 DDRSLRATE

AED49 AED51

V

DDS33_1

27262524232221201918171615

V

E

SS

D

C

V

B

SS

A

28

2009 Texas Instruments Incorporated Device Overview 25

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-5 TMS320C6457 Pin Map (Bottom View) [Quadrant D]

www.ti.com

HD14

HAS

432

HCNTL1

1

V

P

N

HD24

M

HD18

DDS33

HD20 HD12

V

SS

HD31

HD16HD26

HCS

PRODUCT PREVIEW

V

L

DDS33

URADDR4 URADDR3

K

URADDR2

J

V

H

DDS33

URDATA7

G

URDATA5

F

URADDR0 UXADDR0

URSOC

HHWIL

HDS1

UXADDR2 HD01

V

URADDR1

SS

HINT

URENB

UXADDR4 UXADDR1

UXDATA3 UXADDR3

UXDATA2

UXDATA7URDATA6

UXSOC

UXDATA1

HDS2

HR/W

RSV25

5

HD02

6

HD28

HD30HD08

HRDY

HCNTL0

RSV11

RSV10

DDRCLKSEL

GP05GP07

V

V

V

V

V

DDA18V2

V

DDS33

V

DDS33

V

DDS18

V

DDS18

87

SS

SS

SS

9

10

V

V

V

V

V

11

V

DD

V

SS

V

DD

V

SS

V

DD

12

V

SS

V

DD

V

SS

V

DD

V

SS

13

V

DD

V

SS

V

DD

V

SS

V

DD

14

V

SS

DD

SS

DD

SS

DD

P

V

N

SS

V

M

DD

V

L

SS

V

K

DD

J

V

V

DDS18

H

G

SS

F

SS

V

SS

DDRD11

V

DDS18

V

V

SS

V

SS

DDS18

V

DDS18

V

V

V

SS

DDS18

V

SS

DDS18

V

SS

E

D

C

B

URDATA3

URDATA1

URCLK

V

SS

V

DDS33

URDATA4

UXDATA0

URDATA2

URDATA0

URCLAV GP03

V

UXDATA4

SS

V

DDS33

UXCLAV

UXENB

UXDATA6

V

UXDATA5

UXCLK GP00

DDRREF

GP01

GP02

SS

GP06

ALTDDRCLK

GP04

DDRDQS1P

CLKN

DDRREF

DDRDQS1N

CLKP

DDRDQM1

DDRD14 DDRD12

DDRD10

DDRD09

DDRD08

V

DDRD13DDRD15

DDS18

V

SS

V

DDS18

DDRD07

DDRD06

DDRRCVEN

OUT0

DDRRCVEN

IN0

DDRDQS0P

DDRDQS0N

DDRDQM0

DDRD05

DDRD04

V

DDS18

DDRD03

DDRD02

V

DDS18

V

SS

DDRCAS

DDRRAS

DDRWE

DDRD01

DDRD00

DDRBA2

DDRCE

DDRCKE DDRBA1

V

DDRBA0

REFSSTL

DDRCLK

OUT_N0

DDRCLK

OUT_P0

DDRA13

DDRA12A

13121110987654321

14

E

D

C

B

A

26 Device Overview 2009 Texas Instruments Incorporated

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2.7 Signal Groups Description

Figure 2-6 shows the CPU and core peripheral signal groups.

Figure 2-6 CPU and Peripheral Signals

CORECLKP

CORECLKN

ALTCORECLK

CORECLKSEL

SYSCLKOUT

AV

DD118

DDRREFCLKP

DDRREFCLKN

ALTDDRCLK
DDRCLKSEL

AV

DD218

TMS
TDO

TDI

TCK

TRST

EMU0

EMU1

•

•

•

EMU14
EMU15
EMU16
EMU17
EMU18

Clock/PLL1

and

PLL Controller

Clock/PLL2

IEEE Standard

1149.1

(JTAG)

Emulation

Reset and
Interrupts

Reserved

Peripheral

Enable/Disable

TMS320C6457

SPRS582B—July 2010

RESETSTAT
RESET
NMI
POR

RSV

PRODUCT PREVIEW

Control/Status

2009 Texas Instruments Incorporated Device Overview 27

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-7 shows the timer peripheral I/O, the general purpose I/O, the Serial RapidIO, and the general purpose I/O

reference clock, transmit, and receive signals.

Figure 2-7 Timers/GPIO/RapidIO Peripheral Signals

www.ti.com

TINPL1

TOUTL1

PRODUCT PREVIEW

GP[15]
GP[14]
GP[13]
GP[12]
GP[11]
GP[10]

GP[9]
GP[8]

RIOTXN0
RIOTXP0

RIOTXN1

RIOTXP1
RIOTXN2
RIOTXP2
RIOTXN3
RIOTXP3

RIORXN0
RIORXP0

RIORXN1
RIORXP1

RIORXN2
RIORXP2
RIORXN3
RIORXP3

Timer 1

GPIO

General-Purpose Input/Output (GPIO) Port

Transmit

Receive

RapidIO

Timer 0

Timers (64-Bit)

Clock

GP[7]
GP[6]
GP[5]
GP[4]

GP[3]
GP[2]
GP[1]
GP[0]

RIOSGMIICLKN

RIOSGMIICLKP

TOUTL0

TINPL0

(A)

(A)

(A) Reference clock to drive RapidIO and SGMII.

28 Device Overview 2009 Texas Instruments Incorporated

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Figure 2-8 shows the EMIFA and DDR2 peripheral interfaces.

Figure 2-8 EMIFA and DDR2 Memory Controller Peripheral Signals

TMS320C6457

SPRS582B—July 2010

AED[63:0]

ACE5
ACE4
ACE3

ACE2

AEA[19:0]

ABE7
ABE6

ABE5

ABE4

ABE3
ABE2

ABE1
ABE0

ABA[1:0]

64

(A)

(A)

(A)

(A)

20

Data

Memory Map

Space Select

Address

Byte Enables

Bank Address

External

Memory I/F

Control

Bus

Arbitration

EMIFA (64-bit Data Bus)

AECLKIN

AECLKOUT

ASWE AAWE/
AARDY

AR/W

AAOE ASOE/
ASADS/ASRE

AHOLD

AHOLDA
ABUSREQ

PRODUCT PREVIEW

DDRD[31:0]

DDRCE

DDRA[13:0]

DDRDQM0

DDRDQM1
DDRDQM2

DDRDQM3

(A) The EMIFA ACE0 and ACE1 are not functionally supported on C6457 devices.

32

14

Data

Memory Map

Address

Byte Enables

DDR2 Memory Controller (32-bit Data Bus)

External

Memory

Controller

Bank Address

DDRCLKOUTP[1:0]
DDRCLKOUTN[1:0]

DDRCKE

DDRCAS
DDRRAS

DDRWE

DDRDQSP[3:0]
DDRDQSN[3:0]

DDRRCVENIN[2:0]
DDRRCVENOUT[2:0]
DDRODT
DDRSLRATE
V

REFSSTL

DDRBA0
DDRBA1
DDRBA2

2009 Texas Instruments Incorporated Device Overview 29

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Figure 2-9 shows the HPI, McBSP, and I2C peripheral signals.

Figure 2-9 HPI/McBSP/I2C Peripheral Signals

HD[15:0]

HD[31:16]

HCNTL0

HCNTL1

HHWIL

(HPI16 ONLY)

32

PRODUCT PREVIEW

Data

Register Select

Half-Word

Select

(A)

HPI

(Host-Port Interface)

Control

www.ti.com

HAS

HR/W
HCS

HDS1
HDS2
HRDY

HINT

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

McBSP1

Transmit

Receive

Clock

McBSPs

(Multichannel Buffered Serial Ports)

I2C

McBSP0

Transmit

Receive

Clock

CLKX0

FSX0
DX0

CLKR0
FSR0
DR0

CLKS0

SCL

SDA

(A) When the HPI is enabled, the number of HPI pins used depends on the HPI configuration (HPI16 or HPI32).

30 Device Overview 2009 Texas Instruments Incorporated

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Figure 2-10 shows the EMAC/MDIO (SGMII) peripheral signals.

Figure 2-10 EMAC/MDIO (SGMII) Peripheral Signals

Ethernet MAC

(EMAC)

TMS320C6457

SPRS582B—July 2010

SGMIITXN

SGMIITXP

SGMIIRXN

SGMIIRXP

RIOSGMIICLKN

RIOSGMIICLKP

(A) Reference clock to drive RapidIO and SGMII.

(A)

(A)

SGMII

Transmit

SGMII

Receive

SGMII

Clock

Ethernet MAC (EMAC) and MDIO

MDIO

MDIO

MDCLK

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 31

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Figure 2-11 shows the UTOPIA peripheral signals.

Figure 2-11 UTOPIA Peripheral Signals

UTOPIA (SL AVE)

www.ti.com

URDATA7
URDATA6
URDATA5
URDATA4
URDATA3
URDATA2
URDATA1

PRODUCT PREVIEW

URDATA0

URENB

URADDR4
URADDR3
URADDR2
URADDR1
URADDR0

URCLAV

URSOC

URCLK

Receive

Control/Status

Clock

Transmit

Control/Status

Clock

UXDATA7
UXDATA6
UXDATA5
UXDATA4
UXDATA3
UXDATA2
UXDATA1
UXDATA0

UXENB
UXADDR4
UXADDR3
UXADDR2
UXADDR1
UXADDR0
UXCLAV
UXSOC

UXCLK

32 Device Overview 2009 Texas Instruments Incorporated

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SPRS582B—July 2010

2.8 Terminal Functions

The terminal functions table Table 2-6 identifies the external signal names, the associated pin (ball) numbers along
with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors, and a functional pin description. For more detailed information on device configuration,
peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see Section 3 ‘‘Device

Configuration’’ on page 59.

Use the symbol definitions in Table 2-5 when reading Table 2-6.

Table 2-5 I/O Functional Symbol Definitions

Functional

Symbol

Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can

IPD or IPU

AAnalog signal Type

GND Ground Type

IInput terminal Type

OOutput terminal Type

S Supply voltage Type

Z Three-state terminal or high impedance Type

End of Table 2-5

be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see Section 3.6 ‘‘Pullup/Pulldown

Resistors’’ on page 63.

Definition

Table 2-6

Column Heading

IPD/IPU

Table 2-6 Terminal Functions (Part 1 of 22)

Signal Name Ball No. Type IPD/IPU Description

CLOCK/PLL CONFIGURATIONS

CORECLKN AH7 I Clock Input for PLL1 (differential).

CORECLKP AH6 I Clock Input for PLL1 (differential).

ALTCORECLK AF6 Alternate Core Clock (single-ended) input to main PLL [vs. CORECLK(N|P)].

Core Clock Select. Selects between CORECLK(N|P) and ALTCORECLK to the Main PLL.

CORECLKSEL AE6

SYSCLKOUT AD7 O/Z IPD SYSCLKOUT is the clock output at 1/10 (default rate) of the device speed.

DDRREFCLKN E6 I DDR Reference Clock Input to DDR PLL (differential).

DDRREFCLKP D6 I DDR Reference Clock Input to DDR PLL (differential).

ALTDDRCLK C6 I Alternate DDR Clock (single-ended) input to DDR PLL [vs. DDRREFCLK(N|P)].

DDRCLKSEL G6 I

RIOSGMIICLKN AG6 RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes (differential).

RIOSGMIICLKP AG7 RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes (differential).

• When CORECLKSEL = 0, it selects the differential clock [CORECLK(N|P)].

• When CORECLKSEL = 1, it selects the single-ended clock [ALTCORECLK].

DDR Clock Select. Selects between DDRREFCLK(N|P) and ALTDDRCLK to the DDR PLL.

• When DDRCLKSEL = 0, it selects the differential clock [DDRREFCLK(N|P)].

• When DDRCLKSEL = 1, it selects the single-ended clock [ALTDDRCLK].

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 33

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Table 2-6 Terminal Functions (Part 2 of 22)

Signal Name Ball No. Type IPD/IPU Description

TMS Y2 I IPU JTAG test-port mode select

TDO AF1 O/Z JTAG test-port data out

TDI AB1 I IPU JTAG test-port data in

TCK AH3 I IPU JTAG test-port clock

AE2 I IPD

TRST

EMU0(3) AD5

EMU1(3) AE5 Emulation pin 1

PRODUCT PREVIEW

EMU2 AH5 Emulation pin 2

EMU3 AE4 Emulation pin 3

EMU4 AH4 Emulation pin 4

EMU5 AG4 Emulation pin 5

EMU6 AF4 Emulation pin 6

EMU7 AG2 Emulation pin 7

EMU8 AG3 Emulation pin 8

EMU9 AD4 Emulation pin 9

EMU10 AE3 Emulation pin 10

EMU11 AF2 Emulation pin 11

EMU12 AE1 Emulation pin 12

EMU13 AF3 Emulation pin 13

EMU14 AC1 Emulation pin 14

EMU15 AD1 Emulation pin 15

EMU16 AD3 Emulation pin 16

EMU17 AA1 Emulation pin 17

EMU18 AC2 Emulation pin 18

AH23 I Device reset

RESET

NMI AE19 I IPD

RESETSTAT

POR

AF23 O Reset Status pin. The RESETSTAT pin indicates when the device is in reset

AG22 I Power on reset.

I/O/Z IPU

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

www.ti.com

JTAG EMULATION

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see 7.22.3.1 ‘‘IEEE 1149.1 JTAG

Compatibility Statement’’ on page 206.

Emulation pin 0

Nonmaskable interrupt, edge-driven (rising edge).

NOTE: Any noise on the NMI pin may trigger an NMI interrupt. Therefore, if the NMI pin is not
used, it is recommended that the NMI pin be grounded instead of relying on the IPD.

34 Device Overview 2009 Texas Instruments Incorporated

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Table 2-6 Terminal Functions (Part 3 of 22)

Signal Name Ball No. Type IPD/IPU Description

GP15 F23

GP14 D23

GP13 C23

GP12 D24

GP11 C25

GP10 A25

GP09 C24

GP08 B25

GP07 F5

GP06 C5

GP05 F6

GP04 B5

GP03 B4

GP02 D5

GP01 E5

GP00 A5

HINT

HCNTL1 M5 I/O/Z Host control -selects between control, address, or data registers (I) [default]

HCNTL0 L6 I/O/Z Host control -selects between control, address, or data registers (I) [default]

HHWIL L3 I/O/Z

K5 I/O/Z Host read or write select (I) [default]

HR/W

M4 I/O/Z Host address strobe (I) [default]

HAS

HCS

L2 I/O/Z Host data strobe 1 (I) [default]

HDS1

L5 I/O/Z Host data strobe 2 (I) [default]

HDS2

HRDY

M3 I/O/Z Host chip select (I) [default]

M6 I/O/Z Host ready from DSP to host (O/Z) [default]

I/O/Z IPD

L4 I/O/Z Host interrupt from DSP to host (O/Z)

General-purpose input/output (GPIO) pins (I/O/Z). GPIO[15:0] pins are multiplexed at power-on
reset for configuration latching:

• GPIO[0] is mapped to LENDIAN

• GPIO[4:1] are mapped to BOOTMODE[3:0] (see Section 2.5 ‘‘Boot Modes Supported’’ on
page 21)

• GPIO[8:5] are mapped to DEVNUM[3:0]

• GPIO[13:9] are mapped to CFGGP[4:0]

• GPIO[14] is mapped to HPIWIDTH

• GPIO[15] is mapped to ECLKINSEL

HOST PORT INTERFACE (HPI)

Host half-word select — first or second half-word (not necessarily high or low order).
For HPI16 bus width selection only] (I) [default]

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 35

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Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 4 of 22)

Signal Name Ball No. Type IPD/IPU Description

HD31 P3

HD30 N6

HD29 T5

HD28 P6

HD27 U5

HD26 N1

HD25 V2

HD24 M1

HD23 U6

PRODUCT PREVIEW

HD22 V1

HD21 U1

HD20 N2

HD19 T1

HD18 P2

HD17 R1

HD16 N3

HD15 T2

HD14 P4

HD13 U2

HD12 N4

HD11 W1

HD10 R5

HD09 T3

HD08 N5

HD07 R4

HD06 T6

HD05 U4

HD04 R6

HD03 T4

HD02 P5

HD01 K6

HD00 W2

I/O/Z

I/O/Z Host-port data [15:0] pin (I/O/Z) [default]

www.ti.com

Host-port data [31:16] pin (I/O/Z) [default]

36 Device Overview 2009 Texas Instruments Incorporated

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Communications Infrastructure Digital Signal Processor

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Table 2-6 Terminal Functions (Part 5 of 22)

Signal Name Ball No. Type IPD/IPU Description

EMIFA (64-BIT) — CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

ABA1 V24 O/Z IPD EMIFA bank address control (ABA[1:0]). Active-low bank selects for the 64-bit EMIFA.

ABA0 V25 O/Z IPD

ACE5

V26

U27

ACE4

W25

ACE3

ACE2

ABE07

ABE06

ABE05

ABE04

ABE03

ABE02

ABE01

ABE00

AHOLDA

AHOLD

ABUSREQ L26 O IPU EMIFA bus request output

AECLKIN N28 I IPD

AECLKOUT V28 O/Z IPD EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK7) frequency]

/ASWE AA24 O/Z IPU Asynchronous memory write-enable/Programmable synchronous interface write-enable

AAWE

AARDY K28 I IPU Asynchronous memory ready input

W24 O/Z IPU Asynchronous memory read/write

AR/W

/ASOE AE25 O/Z IPU Asynchronous/Programmable synchronous memory output-enable

AAOE

ASADS

/ASRE R25 O/Z IPU

W26

W28

L25

L28

L27

Y28

W27

Y24

Y25

N25 O IPU EMIFA hold-request-acknowledge to the host

R28 I IPU EMIFA hold request from the host

O/Z IPU

O/Z IPU

EMIFA (64-BIT) — ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

• When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the byte address.

• For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address.

EMIFA memory space enables.

• Enabled by bits 28 through 31 of the word address

• Only one pin is asserted during any external data access

NOTE: The C6457 device does not have ACE0 and ACE1 pins.

EMIFA byte-enable control.

• Decoded from the low-order address bits. The number of address bits or byte enables used
depends on the width of external memory.

• Byte-write enables for most types of memory.

EMIFA (64-BIT) — BUS ARBITRATION

EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK7 clock) is selected at
reset via the pullup/pulldown resistor on the GPIO[15] pin.

NOTE: AECLKIN is the default for the EMIFA input clock.

Programmable synchronous address strobe or read-enable

• For programmable synchronous interface, the R_ENABLE field in the Chip Select x
Configuration Register selects between ASADS and ASRE:

– If R_ENABLE = 0, then the ASADS/ASRE signal functions as the ASADS signal.
– If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal.

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 37

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Table 2-6 Terminal Functions (Part 6 of 22)

Signal Name Ball No. Type IPD/IPU Description

AEA19 P24

AEA18 M25

AEA17 M24

AEA16 P25

AEA15 P26

AEA14 T24

AEA13 R26 O/Z IPU

AEA12 N27

PRODUCT PREVIEW

AEA11 T25

AEA10 N24

AEA09 M26

AEA08 R24

AEA07 N26

AEA06 T28

AEA05 U28

AEA04 R27

AEA03 T27

AEA02 T26

AEA01 U26

AEA00 U25

O/Z IPD

O/Z IPD

O/Z IPD

www.ti.com

EMIFA (64-BIT) — ADDRESS

EMIFA external address (word address) (O/Z)

38 Device Overview 2009 Texas Instruments Incorporated

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Table 2-6 Terminal Functions (Part 7 of 22)

Signal Name Ball No. Type IPD/IPU Description

AED63 G24

AED62 A26

AED61 C26

AED60 C27

AED59 E26

AED58 D27

AED57 D25

AED56 F26

AED55 H24

AED54 H25

AED53 D26

AED52 F27

AED51 B27

AED50 G26

AED49 B26

AED48 G27

AED47 J24

AED46 K25

AED45 J25

AED44 J26

AED43 H26

AED42 J27

AED41 C28

AED40 J28

AED39 D28

AED38 K24

AED37 F28

AED36 G25

AED35 G28

AED34 K27

AED33 L24

AED32 K26

AED31 Y26

AED30 AF28

AED29 AA28

AED28 AB26

AED27 Y27

AED26 AB25

I/O/Z IPU EMIFA external data

TMS320C6457

SPRS582B—July 2010

EMIFA (64-BIT) — DATA

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 39

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Table 2-6 Terminal Functions (Part 8 of 22)

Signal Name Ball No. Type IPD/IPU Description

AED25 AA26

AED24 AB24

AED23 AA25

AED22 AA27

AED21 AC28

AED20 AG27

AED19 AE28

AED18 AF27

AED17 AD28

PRODUCT PREVIEW

AED16 AF26

AED15 AE27

AED14 AG25

AED13 AC27

AED12 AD26

AED11 AC25

AED10 AE26

AED09 AF25

AED08 AC26

AED07 AD25

AED06 AH26

AED05 AH25

AED04 AD27

AED03 AF24

AED02 AG26

AED01 AE24

AED00 AC24

I/O/Z IPU EMIFA external data

www.ti.com

40 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 9 of 22)

Signal Name Ball No. Type IPD/IPU Description

DDR2 MEMORY CONTROLLER

DDRDQM0 C10

DDRDQM1 C7

DDRDQM2 C19

DDRDQM3 C22

DDRBA0 C14

DDRBA2 E14

DDRA00 F17

DDRA01 E17

DDRA02 D17

DDRA03 C17

DDRA04 E16

DDRA05 D16

DDRA06 C16

DDRA07 B16

DDRA08 D15

DDRA09 C15

DDRA10 B15

DDRA11 A15

DDRA12 A14

DDRA13 B14

DDRCLKOUTP0 A13

DDRCLKOUTN0 B13

DDRCLKOUTP1 A17

DDRCLKOUTN1 B17

O/Z DDR2 EMIF Data Masks

O/Z DDR Bank Address DDRBA1 D14

O/Z DDR2 EMIF Address Bus

O/Z DDR2 EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 41

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 10 of 22)

Signal Name Ball No. Type IPD/IPU Description

DDRD00 A12

DDRD01 B12

DDRD02 C11

DDRD03 D11

DDRD04 A10

DDRD05 B10

DDRD06 C9

DDRD07 D9

DDRD08 C8

PRODUCT PREVIEW

DDRD09 D8

DDRD10 E8

DDRD11 F8

DDRD12 B7

DDRD13 A7

DDRD14 B6

DDRD15 A6

DDRD16 B18

DDRD17 A18

DDRD18 C18

DDRD19 D18

DDRD20 A20

DDRD21 B20

DDRD22 C20

DDRD23 D20

DDRD24 A21

DDRD25 B21

DDRD26 C21

DDRD27 D21

DDRD28 A23

DDRD29 B23

DDRD30 A24

DDRD31 B24

DDRCAS

DDRRAS

E13 O/Z DDR2 EMIF Chip Enable

DDRCE

DDRWE

DDRCKE D13 O/Z DDR2 EMIF Clock Enable

E12 O/Z DDR2 EMIF Column Address Strobe

D12 O/Z DDR2 EMIF Row Address Strobe

C12 O/Z DDR2 EMIF Write Enable

O/Z DDR2 EMIF Data Bus

www.ti.com

42 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 11 of 22)

Signal Name Ball No. Type IPD/IPU Description

DDRDQS0P E10

DDRDQS0N D10

DDRDQS1P E7

DDRDQS1N D7

DDRDQS2P E19

DDRDQS2N D19

DDRDQS3P E22

DDRDQS3N D22

DDRRCVENIN0 A9 I

DDRRCVENOUT0 B9 O/Z

DDRRCVENIN1 E20 I

DDRRCVENOUT1 F20 O/Z

DDRODT E15 O/Z DDR2 EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDRSLRATE A27 I DDR2 Slew rate control

C13 A Reference Voltage Input for SSTL18 buffers used by DDR2 EMIF (V

V

REFSSTL

TOUT1L AF19 O/Z IPD Timer 1 output pin for lower 32-bit counter

TINP1L AG19 I IPD Timer 1 input pin for lower 32-bit counter

TOUT0L AG20 O/Z IPD Timer 0 output pin for lower 32-bit counter

TINP0L AH20 I IPD Timer 0 input pin for lower 32-bit counter

SCL F24 I/O/Z I

SDA E24 I/O/Z I

CLKS0 AA4 I IPD McBSP0 Module Clock

CLKR0 Y5 I/O/Z IPD McBSP0 Receive Clock

CLKX0 AB3 I/O/Z IPD McBSP0 Transmit Clock

DR0 Y6 I IPD McBSP0 Receive Data

DX0 W6 O/Z IPD McBSP0 Transmit Data

FSR0 V4 I/O/Z IPD McBSP0 Receive Frame Sync

FSX0 W4 I/O/Z IPD McBSP0 Transmit Frame Sync

CLKS1 Y1 I IPD McBSP1 Module Clock

CLKR1 Y4 I/O/Z IPD McBSP1 Receive Clock

CLKX1 AA3 I/O/Z IPD McBSP1 Transmit Clock

DR1 W3 I IPD McBSP1 Receive Data

DX1 Y3 O/Z IPD McBSP1 Transmit Data

FSR1 V5 I/O/Z IPD McBSP1 Receive Frame Sync

FSX1 W5 I/O/Z IPD McBSP1 Transmit Frame Sync

I/O/Z DDR2 EMIF Data Strobe

DDR2 EMIF Data Strobe Gate Input/Outputs to help meet DDR Timing

TIMER 1

TIMER 0

INTER-INTEGRATED CIRCUIT (I

2

C clock. When the I2C module is used, use an external pullup resistor.

2

C data. When I2C is used, ensure there is an external pullup resistor.

MULTICHANNEL BUFFERED SERIAL PORT (McBSP)

2

C)

SPRS582B—July 2010

)

DDS18_2

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 43

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Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 12 of 22)

Signal Name Ball No. Type IPD/IPU Description

UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]

UTOPIA SLAVE (ATM CONTROLLER) — TRANSMIT INTERFACE

UXCLK A4 I Source clock for UTOPIA transmit driven by Master ATM Controller.

UXCLAV C3 O/Z

UXENB

B3 I

UXSOC G4 O/Z

PRODUCT PREVIEW

UXADDR4 J4

UXADDR3 H5

UXADDR2 K3

UXADDR1 J5

UXADDR0 H4

UXDATA7 F3

UXDATA6 E4

UXDATA5 C4

UXDATA4 A3

UXDATA3 H3

UXDATA2 G3

UXDATA1 F4

UXDATA0 E3

URCLK C1 I Source clock for UTOPIA receive driven by Master ATM Controller.

URCLAV B2 O/Z

K4 I

URENB

URSOC G2 I

URADDR4 K1

URADDR3 K2

URADDR2 J1

URADDR1 J3

URADDR0 H2

I

O/Z

UTOPIA SLAVE (ATM CONTROLLER) — RECEIVE INTERFACE

I

www.ti.com

Transmit cell available status output signal from UTOPIA Slave.

•0 indicates a complete cell is NOT available for transmit

• 1 indicates a complete cell is available for transmit

UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate
that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and
the UXSOC signal in the next clock cycle.

Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the
UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus
(UXDATA[7:0]).

UTOPIA transmit address pins (UXADDR[4:0]) (I) 5-bit Slave transmit address input pins driven by
the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in
the ATM System.

UTOPIA 8-bit transmit data bus (I/O/Z) Using the Transmit Data Bus, the UTOPIA Slave (on the
rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.

Receive cell available status output signal from UTOPIA Slave.

• 0 indicates NO space is available to receive a cell from Master ATM Controller.

• 1 indicates space is available to receive a cell from Master ATM Controller.

UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indicate
to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal in the next
clock cycle or thereafter.

Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to the
UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive Data
Bus (URDATA[7:0]).

UTOPIA receive address pins [URADDR[4:0] (I)]: 5-bit Slave receive address input pins driven by
the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in
the ATM System.

44 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 13 of 22)

Signal Name Ball No. Type IPD/IPU Description

URDATA7 G1

URDATA6 F2

URDATA5 F1

URDATA4 E2

URDATA3 E1

URDATA2 D2

URDATA1 D1

URDATA0 C2

RIORXN0 AG8

RIORXP0 AG9

RIORXN1 AF11

RIORXP1 AF10

RIORXN2 AH13

RIORXP2 AH12

RIORXN3 AE13

RIORXP3 AE12

RIOTXN0 AE9

RIOTXP0 AE8

RIOTXN1 AH9

RIOTXP1 AH10

RIOTXN2 AF13

RIOTXP2 AF14

RIOTXN3 AG13

RIOTXP3 AG14

SGMIIRXN AF16

SGMIIRXP AF17

SGMIITXN AH15

SGMIITXP AH14

MDIO AH19 I/O/Z IPU MDIO Data

MDCLK AH18 O IPD MDIO Clock

PTV18 A16 A PTV Compensation NMOS Reference Input. Install with 47-Ω, 5% resistor to GND

U19 A 1.1-V CVDD Supply Monitor

CV

DDMON

DV

DV

U22 A 3.3-V DV

DD33MON

G23 A 1.8-V DVDD Supply Monitor

DD18MON

I

I

O

I Ethernet MAC SGMII Receive Data

O Ethernet MAC SGMII Transmit Data

UTOPIA 8-bit Receive Data Bus (I/O/Z). Using the Receive Data Bus, the UTOPIA Slave (on the
rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.

SERIAL RAPIDIO (SRIO)

Serial RapidIO Receive Data (4 links)

Serial RapidIO Transmit data (4 links)

ETHERNET MAC (EMAC) AND SGMII

MANAGEMENT DATA INPUT/OUTPUT (MDIO)

VOLTAGE CONTROL TERMINALS

SUPPLY VOLTAGE MONITOR TERMINALS

Supply Monitor

DD

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 45

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 14 of 22)

Signal Name Ball No. Type IPD/IPU Description

V

DDR18

V

DDA11

PRODUCT PREVIEW

V

DDD11

V

DDT11

DV

DD18

AE10

AE16

AC10

AC12

AC14

AC16

U13

V12

V14

W11

W13

W15

AD9

AD11

AD13

AD15

AD17

AF9

AF15

AG11

AH17

AA6

AB18

AB20

AB7

AC19

AC21

AC3

AC8

AD18

AD22

AF18

AG5

AH1

B11

B19

B22

B8

S 1.8-V I/O supply voltage (SRIO/SGMII SerDes regulator supply).

S

S

S

S 1.8-V I/O supply voltage

www.ti.com

SUPPLY VOLTAGE TERMINALS

SRIO/SGMII analog supply:

1.1-V I/O supply voltage

Do not use core supply.

SRIO/SGMII SerDes digital supply:

1.1-V I/O supply voltage

Do not use core supply.

SRIO/SGMII SerDes termination supply:

1.1-V I/O supply voltage

Do not use core supply.

46 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 15 of 22)

Signal Name Ball No. Type IPD/IPU Description

E11

E21

E23

E9

F10

F12

F14

F16

F18

DV

DD18

G11

G13

G15

G17

G19

G21

G7

G9

J7

V6

Y7

S 1.8-V I/O supply voltage

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 47

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SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 16 of 22)

Signal Name Ball No. Type IPD/IPU Description

A1

A28

AA23

AB22

AB28

AC23

AD24

AH24

AH28

PRODUCT PREVIEW

DV

DD33

D3

E25

E27

H1

H22

H27

J23

K22

L1

L23

L7

M22

M27

N23

N7

P1

P22

P27

R23

R3

R7

T22

U7

V22

V3

W23

Y22

S 3.3-V I/O supply voltage

www.ti.com

48 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 17 of 22)

Signal Name Ball No. Type IPD/IPU Description

K10

K12

K14

K16

K18

L11

L13

L15

L17

CVDD

CV

DD

AC5 S 1.8-V PLL Supply

PLLV

1

PLLV

2

L19

M10

M12

M14

M16

M18

N11

N13

N15

N17

N19

P10

P12

P14

P16

P18

R11

R13

R15

R17

R19

T12

T14

T16

T18

U11

U15

U17

V10

V16

V18

W17

W19

F7 S 1.8-V PLL Supply

S 1.1-V core supply voltage

S 1.1-V core supply voltage

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 49

TMS320C6457

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SPRS582B—July 2010

Table 2-6 Terminal Functions (Part 18 of 22)

Signal Name Ball No. Type IPD/IPU Description

A11

A19

A2

A22

A8

AA2

AA22

AA7

PRODUCT PREVIEW

VSS

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB19

AB21

AB23

AB27

AB6

AB8

AB9

AC11

AC13

AC15

AC17

AC18

AC20

AC22

AC9

AD10

AD12

AD14

AD16

AD19

AD2

GND Ground pins

www.ti.com

GROUND PINS

50 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 19 of 22)

Signal Name Ball No. Type IPD/IPU Description

AD23

AD8

AE11

AE14

AE15

AE17

AE18

AF5

AF8

AG1

AG10

AG12

AG15

AG17

AG18

AG24

AG28

AH11

VSS

AH16

AH2

AH27

AH8

B1

B28

D4

E18

E28

F11

F13

F15

F19

F21

F22

F25

F9

G10

G12

G14

GND Ground pins

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 51

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Table 2-6 Terminal Functions (Part 20 of 22)

Signal Name Ball No. Type IPD/IPU Description

G16

G18

G20

G22

G8

H23

H28

H7

J2

PRODUCT PREVIEW

VSS

J22

K11

K13

K15

K17

K19

K23

K7

L10

L12

L14

L16

L18

L22

M11

M13

M15

M17

M19

M2

M23

M28

M7

N10

N12

N14

N16

N18

N22

GND Ground pins

www.ti.com

52 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-6 Terminal Functions (Part 21 of 22)

Signal Name Ball No. Type IPD/IPU Description

P11

P13

P15

P17

P19

P23

P28

P7

R12

R14

R16

R18

R2

R22

T11

T13

T15

T17

T19

T23

VSS

U10

U12

U14

U16

U18

U23

U24

U3

V11

V13

V15

V17

V19

V23

V27

V7

W10

W12

W14

W16

GND Ground pins

T7

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 53

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Table 2-6 Terminal Functions (Part 22 of 22)

Signal Name Ball No. Type IPD/IPU Description

W18

VSS

RSV01 AC4 I/O/Z IPU Reserved - Unconnected

RSV02 AB2 I/O/Z IPU Reserved - Unconnected

RSV03 AB4 I/O/Z IPU Reserved - Unconnected

RSV04 AD20 O/Z IPD Reserved - Unconnected

PRODUCT PREVIEW

RSV05 AD21 O/Z IPD Reserved - Unconnected

RSV06 AE20 A Reserved - Unconnected

RSV07 AE21 A Reserved - Unconnected

RSV08 AE7 O Reserved - Unconnected

RSV09 AF7 O Reserved - Unconnected

RSV10 H6 O Reserved - Unconnected

RSV11 J6 O Reserved - Unconnected

RSV12 AB5 A Reserved - Connect to GND

RSV13 AA5 A Reserved - Unconnected

RSV14 AF20 I/O/Z IPU Reserved - Unconnected

RSV15 AF21 I/O/Z IPU Reserved - Unconnected

RSV16 AF12 A Reserved - Unconnected

RSV17 AG16 A Reserved - Unconnected

RSV18 AH21 A Reserved - Unconnected

RSV19 AG21 A Reserved - Unconnected

RSV20 AC6 A Reserved - Unconnected

RSV21 AC7 A Reserved - Unconnected

RSV22 AE23 I IPU Reserved - Pullup to DV

RSV23 R10 S Reserved - Connected to CV

RSV23 T10 S Reserved - Connected to CV

RSV24 AD6 O/Z IPD Reserved - Unconnected

RSV25 G5 O/Z IPD Reserved - Unconnected

RSV26 AE22 Reserved - Unconnected

RSV27 AF22 Reserved - Unconnected

RSV28 AG23 Reserved - Unconnected

RSV29 AH22 Reserved - Unconnected

End of Table 2-6

W22

W7

Y23

GND Ground pins

RESERVED PINS

DD18

www.ti.com

with 10-kΩ resistor.

DD

DD

54 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

2.9 Development

2.9.1 Development Support

In case the customer would like to develop their own features and software on the C6457 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

• Software Development Tools:
– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools

– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software

needed to support any DSP application.

• Hardware Development Tools:

– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
– EVM (Evaluation Module)

2.9.2 Device Support

2.9.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,
TMX320C6457CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications

• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification

• TMS: Fully qualified production device

Support tool development evolutionary flow:

• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.

• TMDS: Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.

PRODUCT PREVIEW

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for
example, CMH), the temperature range (for example, blank is the default case temperature range), and the device
speed range, in megahertz (for example, blank is 1000 MHz [1 GHz]).

2009 Texas Instruments Incorporated Device Overview 55

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SPRS582B—July 2010

provides a legend for reading the complete device name for any TMS320C64x+™ DSP generation member.

For device part numbers and further ordering information for TMS320C6457 in the CMH package type, see the TI
website www.ti.com or contact your TI sales representative.

Figure 2-12 TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6457 DSP)

TMX 320 C6457

PREFIX

TMX = Experimental device
TMS = Qualified device

DEVICE FAMILY

320 = TMS320 DSP family

PRODUCT PREVIEW

DEVICE

C64x+ DSP: C6457

SILICON REVISION

Blank = Initial Silicon 1.1

A = Silicon Rev 1.2
B = Silicon Rev 1.3

C = Silicon Rev 1.4

()

CMH

()

()

850 MHz

1 GHz

1.2 GHz

www.ti.com

DEVICE SPEED RANGE

Blank=1GHz

2 = 1.2 GHz
8 = 850 MHz

TEMPERATURE RANGE

Blank = 0°C to +100°C (default case temperature)
Blank = 0°C to +100°C (default case temperature)

A = -40°C to +100°C

Blank = 0°C to +95°C (default case temperature)

A = -40°C to +95°C

PACKAGE TYPE

CMH = 688-pin plastic BGA, with Pb-Free solder balls
GMH = 688-pin plastic BGA, with Pb-ed solder balls

(A)

(A) BGA = Ball Grid Array

2.9.2.2 Documentation Support

The documents shown in Table 2-7 describe the TMS320C6457 Communications Infrastructure Digital Signal
Processor. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number
in the search box provided at www.ti.com.

The current documentation that describes the TMS320C6457, related peripherals, and other technical collateral, is
available in the C6000 DSP product folder at: www.ti.com/c6000.

Table 2-7 Relevant Documents (Part 1 of 2)

TI Literature No. Description

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set,

SPRU871 TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule.

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital

SPRU889 High-Speed DSP Systems Design Reference Guide. Provides recommendations for meeting the many challenges of

SPRUGK5 TMS320C6457 DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in

SPRUGK6 TMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide. This document describes the Enhanced DMA (EDMA3)

SPRUGK2 TMS320C6457 DSP External Memory Interface (EMIF) User's Guide. This document describes the operation of the external

and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family.
The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.

Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down
controller, memory protection, bandwidth management, and the memory and cache.

signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the
two cores. Functionality in the devices that is identical is not included.

high-speed DSP system design. These recommendations include information about DSP audio, video, and
communications systems for the C5000 and C6000 DSP platforms.

the TMS320C6457 digital-signal processors (DSPs).

Controller on the TMS320C6457 device.

memory interface (EMIF) in the digital signal processors (DSPs) of the TMS320C6457 DSP family.

56 Device Overview 2009 Texas Instruments Incorporated

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Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-7 Relevant Documents (Part 2 of 2)

TI Literature No. Description

SPRUGL2 TMS320C6457 DSP General-Purpose Input/Output (GPIO) User's Guide. This document describes the general-purpose

SPRUGK7 TMS320C6457 DSP Host Port Interface (HPI) User's Guide. This guide describes the host port interface (HPI) on the

SPRUGK3 TMS320C6457 DSP Inter-Integrated Circuit (I

SPRUGK4 TMS320C6457 Serial RapidIO (SRIO) User's Guide. This document describes the Serial RapidIO (SRIO) on the TMS320C6457

SPRUGL3 TMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG. This document describes the operation

SPRUGL0 TMS320C6457 DSP 64-Bit Timer User's Guide. This document provides an overview of the 64-bit timer in the TMS320C6457

SPRUGK1 TMS320C6457 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide. Channel decoding of high bit-rate data channels

SPRUGL1 TMS320C6457 DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) User's Guide. This document describes the

SPRUGK0 TMS320C6457 DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide. Channel decoding of voice and low bit-rate data

SPRUGK9 TMS320C6457 DSP Ethernet Media Access Controller (EMAC) / Management Data Input Output (MDIO) User’s Guide. This

SPRUGK8 TMS320C6457 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide. This document describes the operation of the

SPRUGL4 TMS320C6457 DSP Power/Sle ep Controller (PSC) User’s Guide. This document covers the usage of the Power/Sleep Controller

SPRUGL5 TMS320C6457 DSP Bootloader User’s Guide. This document describes the features of the on-chip bootloader provided with

End of Table 2-7

input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C6457 DSP family. The GPIO peripheral
provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input,
you can detect the state of the input by reading the state of an internal register. When configured as an output, you can
write to an internal register to control the state driven on the output pin.

TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access DSP
resources (including internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface.

2

(I

C) module in the TMS320C6457 Digital Signal Processor (DSP). The I2C provides an interface between the TMS320C6457
device and other devices compliant with Philips Semiconductors Inter-IC bus (I
connected by way of an I

devices.

of the software-programmable phase-locked loop (PLL) controller in the TMS320C6457 digital signal processors (DSPs).
The PLL controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify
the input signal internally. The resulting clock outputs are passed to the TMS320C6457 DSP core, peripherals, and other
modules inside the TMS320C6457 DSP.

DSP. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog
timer. When configured as a dual 32-bit timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

found in third generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder
coprocessor (TCP) in some of the digital signal processor (DSPs) of the TMS320C6000™ DSP family has been designed to
perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming
of the TCP.

universal test and operations PHY interface for asynchronous transfer mode (ATM) 2 (UTOPIA2) in the TMS320C6457
digital signal processors (DSPs) of the TMS320C6000™ DSP family.

channels found in third generation (3G) cellular standards requires decoding of convolutional encoded data. The
Viterbi-decoder coprocessor 2 (VCP2) provided in TMS320C6457 devices has been designed to perform Viterbi-Decoding
for IS2000 and 3GPP wireless standards. The VCP2 coprocessor has been designed to perform forward error correction for
2G and 3G wireless systems. The VCP2 coprocessor offers a very cost effective and synergistic solution when combined
with Texas Instruments (TI) DSPs. The VCP2 can support 1941 12.2 Kbps class A 3G voice channels running at 333 MHz. This
document describes the operation and programming of the VCP2.

document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY)
device Management Data Input/Output (MDIO) module integrated with TMS320C6457 devices. Included are the features
of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the
outside world, and the registers description for each module.

multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000™ DSP family.

(PSC) in the TMS320C6457 device.

the TMS320C6457 Digital Signal Processor (DSP).

2

C-bus. This document assumes the reader is familiar with the I2C-bus specification.

2

C) Module User's Guide. This document describes the inter-integrated circuit

2

C-bus) specification version 2.1 and

SPRS582B—July 2010

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3 Device Configuration

On the TMS320C6457 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By
default, the peripherals on the C6457 device are disabled and need to be enabled by software before being used.

3.1 Device Configuration at Device Reset

Table 3-1 describes the C6457 device configuration pins. The logic level is latched at power-on reset to determine

the device configuration. The logic level on the device configuration pins can be set by using external
pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins.
When using a control device, care should be taken to ensure there is no contention on the lines when the device is
out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is
removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP.

Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the

internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an
external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and
situations in which external pullup/pulldown resistors are required, see Section 3.6 ‘‘Pullup/Pulldown

Resistors’’ on page 63.

Table 3-1 TMS320C6457 Device Configuration Pins

Configuration Pin No. IPD/IPU

GPIO[0]

A5 IPU

GPIO[4:1]

GPIO[8:5] [B25,

GPIO[13:9] [C23,

GPIO[14]

GPIO[15]

CORECLKSEL

DDRCLKSEL

End of Table 3-1

1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on

pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.6 ‘‘Pullup/Pulldown Resistors’’ on page 63.

[B5,

B4, D5,

E5]

F5, C5,

F6]

D24,
C25,
A25,
C24]

D23 IPD

F23 IPD

AE6

G6

(1)

Functional Description

Device Endian mode (LENDIAN)

0 = Device operates in Big Endian mode.
1 = Device operates in Little Endian mode (default).

IPD

IPD Device Number (DEVNUM[3:0])

IPD

Boot Mode Selection (BOOTMODE [3:0])

These pins select the boot mode for the device. For more information on the boot modes, see Section

2.4 ‘‘Boot Sequence’’ on page 21.

Configuration General-Purpose Inputs (CFGGP[4:0])

The value of these pins is latched to the Device Status Register following power-on reset and is used by

the software.

HPI peripheral bus width select (HPIWIDTH)

0 = HPI operates in HPI16 mode (default).

HPI bus is 16 bits wide; HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in
the Hi-Z state.

1 = HPI operates in HPI32 mode.

HPI bus is 32 bits wide; HD[31:0] pins are used.

EMIFA input clock source select (ECLKINSEL).

0 = ECLKIN (default mode)
1 = SYSCLK7 (CPU/x) Clock Rate.

The SYSCLK7 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK7 is
selected as CPU ÷ 10 clock rate.

Core Clock Select

0 = CORECLK(N|P) is the input to main PLL.
1 = ALTCORECLK is used as the input to main PLL.

DDR Clock Select

0 = DDRREFCLK(N|P) is the input to DDR PLL.
1 = ALTDDRCLK is used as the input to DDR PLL.

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3.2 Peripheral Selection After Device Reset

Several of the peripherals on the TMS320C6457 are controlled by the Power Sleep Controller (PSC). By default, the
SRIO, TCP2_A, TCP2_B, and VCP are held in reset and clock-gated. The memories in these modules are also in a
low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules
(turns on clocks and de-asserts reset) before these modules can be used.

In addition, the EMIFA, HPI, and UTOPIA come up clock-gated and held in reset. Memories in these modules are
already enabled. Software is required to enable these modules before they are used as well.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.

PRODUCT PREVIEW

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the TMS320C6457 DSP Power/Sleep Controller PSC User's Guide (literature
number SPRUGL4).

3.3 Device State Control Registers

The C6457 device has a set of registers that are used to control the status of its peripherals. These registers are shown
in Table 3-2 and described in the next sections.

Table 3-2 Device State Control Registers

Hex Address Range Acronym Description

0288 0818 JTAGID

0288 081C - Reserved

0288 0820 DEVSTAT Stores parameters latched from configuration pins

0288 0824 - 0288 0837 - Reserved

0288 0838 KICK0

0288 083C KICK1

0288 0840 DSP_BOOT_ADDR DSP boot address

0288 0844 - 0288 090F - Reserved

0288 0910 DEVCFG Parameters set through software for device configuration

0288 0914 MACID1 EFUSE derived MAC address for C6457

0288 0918 MACID2 EFUSE derived MAC address for C6457

0288 0922 - 0288 091B - Reserved

0288 091C PRI_ALLOC Sets priority for Master peripherals

0288 0920 WDRSTSEL Reset select for Watchdog (Timer1)

End of Table 3-2

1 Writes are conditional based on valid keys written to both the KICK0 and KICK1 registers.

(1)

Parameters for DSP device ID. Also referred to as JTAG or BSDL ID. These are readable by the
configuration bus and can be accessed via the JTAG and the CPU.

Two successive key writes are required to get write access to any of the device state control
register s. KICK0 is th e first key re gister. The written data must be 0x83E70B13 to unlock it and it must
be written before the KICK1 register. Writing any other value will lock the device state control
registers.

KICK1 is the second key register to be unlocked in order to get write access to any of the device state
control registers. The written data must be 0x95A4F1E0 to unlock it and it must be written after the
KICK0 register. Writing any other value will lock the device state control registers.

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3.4 Device Status Register Description

The device status register depicts the device configuration selected upon power-on reset. Once set, these bits will
remain set until a power-on reset. For the actual register bit names and their associated bit field descriptions, see

Table 3-4 and Table 3-5.

Table 3-3 shows the parameters that are set through software to configure different components on the device. The

configuration is done through the device configuration DEVCFG register, which is one-time writeable through
software. The register is reset on all hard resets and is locked after the first write.

Table 3-3 Device Configuration Register Fields

Field Reset Description Settings

Device Configuration 1 Register Fields

CLKS0 0b McBSP0 CLKS Select 0 = CLKS0 device pin

1 = chip_clks from Main.PLL

CLKS1 0b McBSP1 CLKS Select 0 = CLKS1 device pin

1 = chip_clks from Main.PLL

SYSCLKOUTEN 1b SYSCLKOUT Enable 0 = No clock output

1 = Clock output enabled

End of Table 3-3

Table 3-4 Device Configuration Status Register (DEVSTAT)

HEX ADDRESS - 0288 0820h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Acronym Reserved

(1)

Reset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Acronym ECLKINSEL HPIWIDTH CFGGP DEVNUM BOOTMODE LENDIAN

(1)

Reset

1 R/W = Read/Write; R = Read only; -n = value after reset

0 0 R-n R R R-1

R-0

Table 3-5 Device Configuration Status Register Field Descriptions (Part 1 of 2)

Bit Acronym Description

31:16 Reserved Reserved. Read only, writes have no effect.

15 ECLKINSEL EMIFA input clock select — shows the status of what clock mode is enabled or disabled for EMIFA.

14 HPIWIDTH HPI bus width control bit — shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode.

13:9 CFGGP[4:0] Used as general-purpose inputs for configuration purposes. These pins are latched at power-on reset. These values can be

8:5 DEVNUM[3:0] Device number.

0 = ECLKIN (default mode)
1 = SYSCLK7 (CPU ÷ x) Clock Rate. The SYSCLK7 clock rate is software selectable via the PLL1 Controller. By default,

SYSCLK7 is selected as CPU ÷ 10 clock rate.

0 = HPI operates in 16-bit mode. (default)
1 = HPI operates in 32-bit mode

used by software routines for boot operations.

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Table 3-5 Device Configuration Status Register Field Descriptions (Part 2 of 2)

Bit Acronym Description

4:1 BOOTMODE[3:0] Determines the boot method for the device. For more information on bootmode, see Section 2.4 ‘‘Boot Sequence’’ on

PRODUCT PREVIEW

0 LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little Endian

End of Table 3-5

page 21.

0000 = No Boot

2

0001 = I
0010 = I
0011 = I
0100 = HPI Boot
0101 = EMIFA Boot
0110 = EMAC Master Boot
0111 = EMAC Slave Boot
1000 = EMAC Forced Mode Boot
1001 = Reserved
1010 = RapidIO Boot (Configuration 0)
1011 = RapidIO Boot (Configuration 1)
1100 = RapidIO Boot (Configuration 2)
1101 = RapidIO Boot (Configuration 3)
111x = Reserved

mode (default).

0 = System is operating in Big Endian mode

1 = System is operating in Little Endian mode (default)

C Master Boot (Slave Address 0x50)

2

C Master Boot (Slave Address 0x51)

2

C Slave Boot

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3.5 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the C6457
device, the JTAG ID register resides at address location 0x0288 0818. For the actual register bit names and their
associated bit field descriptions, see Table 3-6 and Table 3-7.

Table 3-6 JTAG ID (JTAGID) Register

HEX ADDRESS - 0288 0818h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Acronym VARIANT PART NUMBER (16-bit)

(1)

Reset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Acronym PART NUMBER (Continued) MANUFACTURER LSB

(1)

Reset

1 R/W = Read/Write; R = Read only; -n = value after reset

Table 3-7 JTAG ID (JTAGID) Register Field Descriptions

Bit Acronym Value Description

31:28 VARIANT 0000 Variant (4-Bit) value. The value of this field depends on the silicon revision being used.

27:12 PART NUMBER 0000 0000 1001 0110b Part Number for boundary scan

11:1 MANUFACTURER 0000 0010 111b Manufacturer

0 LSB 1b This bit is read as a 1 for TMS320C6457

End of Table 3-7

R-0000 R-0000 0000 1001 0110b

0000 0010 111b R-1

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3.6 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the C6457 device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The C6457 device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V
connected to the net. For a pullup resistor, this should be above the highest V
A reasonable choice would be to target the V
by definition, have margin to the V

and VIH levels.

IL

or VOH levels for the logic family of the limiting device; which,

OL

level of all inputs on the net.

IH

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DV

DD

rail.

level of all inputs

IL

PRODUCT PREVIEW

For most systems:

•A 1-kΩ resi stor can b e used to op pos e the IPU/I PD wh ile meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.

• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

), and the low-level/high-level input voltages (VIL and VIH) for

I

the TMS320C6457 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 89.

To determine which pins on the C6457 device include internal pullup/pulldown resistors, see Table 2-6 ‘‘Terminal

Functions’’ on page 33.

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64 Device Configuration 2009 Texas Instruments Incorporated

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4 System Interconnect

On the TMS320C6457 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals
are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers
between master peripherals and slave peripherals; for example, through a switch fabric the CPU can send data to the
Viterbi co-processor (VCP2) without affecting a data transfer between the HPI and the DDR2 memory controller.
The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.

4.1 Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the C6457 device: data buses and configuration buses. Some C6457 peripherals have both
a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus
interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the
register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the
configuration bus is also used to transfer data. For example, data is transferred to the VCP2 and TCP2 via their
configuration bus. Similarly, the data bus can also be used to access the register space of a peripheral. For example,
the EMIFA and DDR2 memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be classified into
two categories: masters and slaves.

Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data
transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them. Examples of masters
include the EDMA3 traffic controllers, SRIO, EMAC, and HPI. Examples of slaves include the McBSP, UTOPIA,

2

C.

and I

The C6457 device contains two switch fabrics through which masters and slaves communicate. The data switch
fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move
data across the system (for more information, see Section 4.2 ‘‘Data Switch Fabric Connections’’). The data SCR
connects masters to slaves via 128-bit data buses running at a SYSCLK4 frequency (SYSCLK4 is generated from PLL
controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to the data
SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly used by
the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3 ‘‘Configuration Switch

Fabric’’). The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a

SYSCLK4 frequency (SYSCLK4 is generated from PLL controller). As with the data SCR, some peripherals require
the use of a bridge to interface to the configuration SCR. Note that the data SCR also connects to the configuration
SCR.

Bridges perform a variety of functions:

• Conversion between configuration bus and data bus.

• Width conversion between peripheral bus width and SCR bus width.

• Frequency conversion between peripheral bus frequency and SCR bus frequency.

For example, the EMIFA requires a bridge to convert its 64-bit data bus interface into a 128-bit interface so that it
can connect to the data SCR. In the case of the TCP2 and VCP2, a bridge is required to connect the data SCR to the
64-bit configuration bus interface.

Note that some peripherals can be accessed through the data SCR and also through the configuration SCR.

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4.2 Data Switch Fabric Connections

Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR).

Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-bit data buses
running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the
CPU frequency divided by 3.

Figure 4-1 Data Switched Central Resource Block Diagram

EDMA3 Channel

Controller

PRODUCT PREVIEW

MASTER

128

M0

128

M1

128

EDMA3

Transfer

Controllers

EMAC

M2

M3

M4

M5

M

128

128

128

32

Bridge

128

Events

Data SCR

S0

S1

S2

S3

S4

S5

S

128-bit

M

M

M

M

Data Bus

128

Bridge

128

Bridge

128

32

32

Bridge

SLAVE

Configuration Bus

32

32

32

32128

32

32

S TCP2_A

VCP2S

S

TCP2_B

McBSP0S

McBSP1S

CFG
SCR

SBridge

HPI

Serial RapidIO

(Descriptor)

Serial

RapidIO

(Data)

32

128

128

128

128

M

S

S

S

M

M EMIFASBridge

128

128 64

128

Bridge

32128

32

M

32

M

M

MMegamodule

Bridge

Bridge

S

SS

SS

SM

L3 ROM

UTOPIA

DDR2

Memory

Controller

Megamodule

66 System Interconnect 2009 Texas Instruments Incorporated

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Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-bit data buses
running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the
CPU frequency divided by 3.

Some peripherals and the C64x+ Megamodule have both slave and master ports. Note that each EDMA3 transfer
controller has an independent connection to the data SCR.

The Serial RapidIO (SRIO) peripheral has two connections to the data SCR. The first connection is used when
descriptors are being fetched from system memory. The other connection is used for all other data transfers.

Note that masters can access the configuration SCR through the data SCR. The configuration SCR is described in
Section 4.3 ‘‘Configuration Switch Fabric’’.

Not all masters on the C6457 DSP may connect to all slaves. Allowed connections are summarized in Table 4-1.

Table 4-1 SCR Connection Matrix

Configuration

VCP2 TCP2_A TCP2_B McBSPs L3 ROM UTOPIA

TC0 Y Y Y N N N N Y Y Y

TC1 N N Y Y Y N N Y Y Y

TC2 N N N Y Y Y Y Y Y Y

TC3 N N N N N Y Y Y Y Y

TC4 N N N N N N Y Y Y Y

TC5 N N N N N N Y Y Y Y

EMAC N N N N N N N Y Y Y

HPI N N N N N N Y Y Y Y

(1)

SRIO

Megamodule Y Y Y Y Y Y N Y Y N

End of Table 4-1

1 Applies to both descriptor and data accesses by the SRIO peripheral.

N N N N N N Y Y Y Y

SCR

DDR2 Memory

Controller

SPRS582B—July 2010

EMIFA Megamodule

PRODUCT PREVIEW

4.3 Configuration Switch Fabric

Figure 4-2 shows the connection between the C64x+ Megamodule and the configuration switched central resource

(SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral registers. The data
SCR also has a connection to the configuration SCR which allows masters to access most peripheral registers. The
only registers not accessible by the data SCR through the configuration SCR are the device configuration registers
and the PLL controller registers; these can only be accessed by the C64x+ Megamodule.

The configuration SCR uses 32-bit configuration buses running at SYSCLK4 frequency. SYSCLK4 is supplied by the
PLL controller and is fixed at a frequency equal to the CPU frequency divided by 3.

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Figure 4-2 Configuration Switched Central Resource (SCR) Block Diagram

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Configuration Bus

Data Bus

PRODUCT PREVIEW

Megamodule

M

MData SCR

MUX

3232

3232

32

32

32

32

32

MUX

32

32

32

MUX

32

32

TCP2_A

S

TCP2_B

S

S

VCP2

S

ETB

S

McBSPs (x2)

S

GPIO

S

GPSC

S

S

Timers (x2)

EMAC

S MDIO

S CP-GMAC

Ethernet

S

CPPI

S CP-SGMII

S SERDES

Device

S

Configuration

Registers

32

S

UTOPIA

32

SS

I2C

32

S

HPI

32

(A)

S

PLL

Controller

(A)

CFG SCR

32

M

M

M

M

Bridge

32-bit

M

Bridge

32

32

S

S

32

S

Serial RapidIO

(Data)

S

Serial RapidIO

(Descriptor)

SS

EDMA3 CC

S

EDMA3 TC1

S

EDMA3 TC3

S

EDMA3 TC5

32

32

32

S

S

EDMA3 TC0

S EDMA3 TC2

S EDMA3 TC4

Note A: Only accessible by

the C64x+ Megamodule

32

M

M

Bridge

MUX

32

32

32

3232

MUX

32

32

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4.4 Bus Priorities

On the TMS320C6457 device, bus priority is programmable for each master. The register bit fields and default
priority levels for C6457 bus masters are shown in Table 4-2.

Table 4-2 TMS320C6457 Default Bus Master Priorities

Bus Master Default Priority Level Priority Control

EDMA3TC0 0 QUEPRI.PRIQ0 (EDMA3 register)

EDMA3TC1 0 QUEPRI.PRIQ1 (EDMA3 register)

EDMA3TC2 0 QUEPRI.PRIQ2 (EDMA3 register)

EDMA3TC3 0 QUEPRI.PRIQ3 (EDMA3 register)

EDMA3TC4 0 QUEPRI.PRIQ4 (EDMA3 register)

EDMA3TC5 0 QUEPRI.PRIQ5 (EDMA3 register)

EMAC 1 PRI_ALLOC.EMAC

SRIO (Data Access) 0 PER_SET_CNTL.CBA_TRANS_PRI (SRIO register)

SRIO (Descriptor Access) 1 PRI_ALLOC.SRIO_CPPI

HPI 2 PRI_ALLOC.HOST

C64x+ Megamodule (MDMA port) 7 MDMAARBE.PRI (C64x+ Megamodule Register)

End of Table 4-2

The priority levels should be tuned to obtain the best system performance for a particular application. Lower values
indicate higher priorities. For some masters, the priority values are programmed at the system level by configuring
the PRI_ALLOC register. Details on the PRI_ALLOC register are shown in Table 4-3 and Table 4-4. The C64x+
megamodule, SRIO, and EDMA masters contain registers that control their own priority values.

Table 4-3 Priority Allocation Register (PRI_ALLOC)

0x0288 091C

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Acronym

(1)

Reset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Acronym

(1)

Reset

1 R/W = Read/Write; R = Read only; -n = value after reset

Reserved HPI SRIO_CPPI EMAC

R-0000 000 R/W-010 R/W-001 R/W-001

Table 4-4 Priority Allocation Register (PRI_ALLOC) Field Descriptions

Bit Acronym Value Description

31:16 Reserved 0000 0000 0000 0000 Reserved.

15:9 Reserved 0000 000 Reserved.

8:6 HOST 010 Priority of the HPI peripheral.

5:3 SRIO_CPPI 001 Priority of the Serial RapidIO when accessing descriptors from system memory. This priority is set

2:0 EMAC 001 Priority of the EMAC peripheral.

End of Table 4-4

in the peripheral, itself.

Reserved

R-0000 0000 0000 0000

PRODUCT PREVIEW

The priority is enforced when several masters in the system are vying for the same endpoint. Note that the
configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when
multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when
a master (through the data SCR) tries to access the same endpoint as the C64x+ megamodule.

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In the PRI_ALLOC register, the HOST field applies to the priority of the HPI peripheral. The EMAC fields specify
the priority of the EMAC peripheral. The SRIO_CPPI field is used to specify the priority of the Serial RapidIO when
accessing descriptors from system memory. The priority for Serial RapidIO data accesses is set in the peripheral
itself.

PRODUCT PREVIEW

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5 C64x+ Megamodule

The C64x+ Megamodule consists of several components:

• The C64x+ CPU and associated C64x+ Megamodule core

• Level-one and level-two memories (L1P, L1D, L2)

• Interrupt controller

• Power-down controller

• External memory controller

• A dedicated power/sleep controller (LPSC)

The C64x+ Megamodule also provides support for memory protection and bandwidth management (for resources
local to the C64x+ Megamodule). Figure 5-1 shows a block diagram of the C64x+ Megamodule.

Figure 5-1 64x+ Megamodule Block Diagram

32KB L1P

Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

Boot

Controller

LPSCPLLC

GPSC

C64x+ DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A

A Register File

A31-A16

A15-A0

.M1

.L1 .S1

xxxx.D1 .D2

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

B Register File

32KB L1D

Data Path B

B31-B16

B15-B0

.M2

xxxx.S2 .L2

Interrupt and Exception Controller

Unified Memory

Controller (UMC)

Controller (EMC)

External Memory

L2 Cache/

SRAM

2048KB

PRODUCT PREVIEW

DMA Switch
Fabric

CFG Switch
Fabric

For more detailed information on the TMS320C64x+ megamodule on the C6457 device, see the TMS320C64x+
Megamodule Reference Guide (literature number SPRU871).

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5.1 Memory Architecture

The TMS320C6457 device contains a 2048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a
32KB level-1 data memory (L1D). All memory on the C6457 has a unique location in the memory map (see
Table 2-2 ‘‘TMS320C6457 Memory Map Summary’’ on page 19).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the
L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. L1D is a two-way
set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the
TMS320C6457 Bootloader User's Guide (literature number SPRUGL5).

PRODUCT PREVIEW

For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (literature
number SPRU862).

5.1.1 L1P Memory

The L1P memory configuration for the C6457 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

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Figure 5-2 shows the available SRAM/cache configurations for L1P.

Figure 5-2 TMS320C6457 L1P Memory Configurations

mode bits

000 001 010 011 100

1/2

SRAM

3/4

SRAM

direct

mapped

cache

direct

mapped

cache

direct

mapped

cache

All

SRAM

7/8

SRAM

dm

cache

L1P memory

16K bytes

8K bytes

4K bytes

4K bytes

Block base
address

00E0 0000h

00E0 4000h

00E0 6000h

00E0 7000h

00E0 8000h

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5.1.2 L1D Memory

The L1D memory configuration for the C6457 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1D.

Figure 5-3 TMS320C6457 L1D Memory Configurations

L1D mode bits

000 001 010 011 100

L1D memory

TMS320C6457

SPRS582B—July 2010

Block base
address

00F0 0000h

All

SRAM

7/8

SRAM

2-way

cache

3/4

SRAM

2-way
cache

1/2

SRAM

2-way
cache

2-way
cache

16K bytes

8K bytes

4K bytes

4K bytes

00F0 4000h

00F0 6000h

00F0 7000h

00F0 8000h

PRODUCT PREVIEW

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5.1.3 L2 Memory

The L2 memory configuration for the C6457 device is as follows:

• Memory size is 2048KB

• Starting address is 0080 0000h

L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is
configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+
Megamodule. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all
SRAM after device reset.

Figure 5-4 TMS320C6457 L2 Memory Configurations

L2 mode bits

PRODUCT PREVIEW

000 001 010 011 100

101 110

SRAM

12

/

L2 memory

1024K bytes

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Block base
address

0080 0000h

ALL

SRAM

63 64

/

SRAM

4-way
cache

31 32

/

SRAM

4-way
cache

15 16

/

SRAM

4-way
cache

78

/

SRAM

4-way
cache

34

/

SRAM

4-way
cache

4-way
cache

512K bytes

256K bytes

128K bytes

64K bytes

32K bytes
32K bytes

0090 0000h

0098 0000h

009C 0000h

009E 0000h

009F 0000h
009F 8000h

009F FFFFh

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5.1.4 L3 Memory

The L3 ROM on the device is 64KB. The contents of the ROM are divided into two partitions. The first is the ROM
bootloader with the primary purpose of containing software to boot the device. There is no requirement to block
accesses from this portion to the ROM. The second partition is the secure portion of ROM, which has a secure kernel
that is necessary for support of security features on the device. The secure portion of ROM cannot be accessed both
on secure, and non-secure parts. Only secure supervisors should have access.

Emulation accesses follows the same rules of the secure portion of the ROM. Emulation can access the non-secure
portion of the ROM, but cannot read the secure portion of the ROM.

SPRS582B—July 2010

5.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 64 pages of L2 (32KB each). The L1D, L1P, and L2 memory controllers in
the C64x+ Megamodule are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the CPU count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The CPU and each of the system masters on the device are all assigned a privilege ID (see Table 5-1). It is only
possible to specify whether memory pages are locally or globally accessible.

Table 5-1 Available Memory Page Protection Scheme With Privilege ID

Privid Module Description

0 C64x+ Megamodule

1 Reserved

2 Reserved

3 EMAC

4 RapidIO and RapidIO CPPI

5 HPI

End of Table 5-1

The AID0 and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-2.

Table 5-2 Available Memory Page Protection Schemes

AID0 Bit Local Bit Description

0 0 No access to memory page is permitted.

0 1 Only direct access by CPU is permitted.

1 0 Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the CPU).

1 1 All accesses permitted

PRODUCT PREVIEW

Faults are handled by software in an interrupt (or an exception, programmable within the C64x+ megamodule
interrupt controller) service routine. A CPU or DMA access to a page without the proper permissions will:

• Block the access — reads return zero, writes are ignored

• Capture the initiator in a status register — ID, address, and access type are stored

• Signal event to CPU interrupt controller

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The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+
Megamodule Reference Guide (literature number SPRU871).

5.3 Bandwidth Management

When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is resolved by granting
access to the highest priority requestor. The following four resources are managed by the Bandwidth Management
control hardware:

• Level 1 Program (L1P) SRAM/Cache

• Level 1 Data (L1D) SRAM/Cache

• Level 2 (L2) SRAM/Cache

PRODUCT PREVIEW

• Memory-mapped registers configuration bus

The priority level for operations initiated within the C64x+ Megamodule are declared through registers in the C64x+
Megamodule. These operations are:

• CPU-initiated transfers

• User-programmed cache coherency operations

• IDMA-initiated transfers

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The priority level for operations initiated outside the C64x+ Megamodule by system peripherals is declared through
the Priority Allocation Register (PRI_ALLOC), see Section 4.4 ‘‘Bus Priorities’’ on page 69. System peripherals with
no fields in PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C64x+ Megamodule can be found in the
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871.)

5.4 Power-Down Control

The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The
power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache control
hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used to design systems
for lower overall system power requirements.

Note—The C6457 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C64x+ Megamodule can be found in the TMS320C64x+
Megamodule Reference Guide (literature number SPRU871).

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5.5 Megamodule Resets

Table 5-3 shows the reset types supported on the C6457 device and they affect the resetting of the Megamodule,

either both globally or just locally.

Table 5-3 Megamodule Reset (Global or Local)

Reset Type Global Megamodule Reset Local Megamodule Reset

Power-On Reset Y Y

Warm Reset Y Y

System Reset Y Y

CPU Reset N Y

End of Table 5-3

For more detailed information on the global and local Megamodule resets, see the TMS320C64x+ Megamodule
Reference Guide (literature number SPRU871). And for more detailed information on device resets, see Section

7.6 ‘‘Reset Controller’’ on page 123.

5.6 Megamodule Revision

The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register
(MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Table 5-4 and described in

Table 5-5. The C64x+ Megamodule revision is dependant on the silicon revision being used.

Table 5-4 Megamodule Revision ID Register (MM_REVID)

Address - 0181 2000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Acronym

(1)

Reset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Acronym

(1)

Reset

1 R/W = Read/Write; R = Read only; -n = value after reset

Table 5-5 Megamodule Revision ID Register (MM_REVID) Field Descriptions

Bit Acronym Value Description

31:16 VERSION 5h Version of the C64x+ Megamodule implemented on the device. This field is always read as 5h.

15:0 REVISION - Revision of the C64x+ Megamodule version implemented on the device.

End of Table 5-5

VERSION

R-5h

REVISION

R-n

5.7 C64x+ Megamodule Register Descriptions

Table 5-6 Megamodule Interrupt Registers (Part 1 of 2)

Hex Address Range Acronym Register Name

0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0])

0180 0004 EVTFLAG1 Event Flag Register 1

0180 0008 EVTFLAG2 Event Flag Register 2

0180 000C EVTFLAG3 Event Flag Register 3

0180 0010 - 0180 001C - Reserved

0180 0020 EVTSET0 Event Set Register 0 (Events [31:0])

0180 0024 EVTSET1 Event Set Register 1

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Table 5-6 Megamodule Interrupt Registers (Part 2 of 2)

Hex Address Range Acronym Register Name

0180 0028 EVTSET2 Event Set Register 2

0180 002C EVTSET3 Event Set Register 3

0180 0030 - 0180 003C - Reserved

0180 0040 EVTCLR0 Event Clear Register 0 (Events [31:0])

0180 0044 EVTCLR1 Event Clear Register 1

0180 0048 EVTCLR2 Event Clear Register 2

0180 004C EVTCLR3 Event Clear Register 3

0180 0050 - 0180 007C - Reserved

0180 0080 EVTMASK0 Event Mask Register 0 (Events [31:0])

PRODUCT PREVIEW

End of Table 5-6

0180 0084 EVTMASK1 Event Mask Register 1

0180 0088 EVTMASK2 Event Mask Register 2

0180 008C EVTMASK3 Event Mask Register 3

0180 0090 - 0180 009C - Reserved

0180 00A0 MEVTFLAG0 Masked Event Flag Status Register 0 (Events [31:0])

0180 00A4 MEVTFLAG1 Masked Event Flag Status Register 1

0180 00A8 MEVTFLAG2 Masked Event Flag Status Register 2

0180 00AC MEVTFLAG3 Masked Event Flag Status Register 3

0180 00B0 - 0180 00BC - Reserved

0180 00C0 EXPMASK0 Exception Mask Register 0 (Events [31:0])

0180 00C4 EXPMASK1 Exception Mask Register 1

0180 00C8 EXPMASK2 Exception Mask Register 2

0180 00CC EXPMASK3 Exception Mask Register 3

0180 00D0 - 0180 00DC - Reserved

0180 00E0 MEXPFLAG0 Masked Exception Flag Register 0

0180 00E4 MEXPFLAG1 Masked Exception Flag Register 1

0180 00E8 MEXPFLAG2 Masked Exception Flag Register 2

0180 00EC MEXPFLAG3 Masked Exception Flag Register 3

0180 00F0 - 0180 00FC - Reserved

0180 0100 - Reserved

0180 0104 INTMUX1 Interrupt Multiplexor Register 1

0180 0108 INTMUX2 Interrupt Multiplexor Register 2

0180 010C INTMUX3 Interrupt Multiplexor Register 3

0180 0110 - 0180 013C - Reserved

0180 0140 AEGMUX0 Advanced Event Generator Mux Register 0

0180 0144 AEGMUX1 Advanced Event Generator Mux Register 1

0180 0148 - 0180 017C - Reserved

0180 0180 INTXSTAT Interrupt Exception Status Register

0180 0184 INTXCLR Interrupt Exception Clear Register

0180 0188 INTDMASK Dropped Interrupt Mask Register

0180 0188 - 0180 01BC - Reserved

0180 01C0 EVTASRT Event Asserting Register

0180 01C4 - 0180 FFFF - Reserved

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Table 5-7 Megamodule Powerdown Control Registers

Hex Address Range Acronym Register Name

0181 0000 PDCCMD Power-down controller command register

0181 0004 - 0181 1FFF - Reserved

End of Table 5-7

Table 5-8 Megamodule Revision Register

Hex Address Range Acronym Register Name

0181 2000 MM_REVID Megamodule Revision ID Register

0181 2004 - 0181 2FFF - Reserved

End of Table 5-8

Table 5-9 Megamodule IDMA Registers

Hex Address Range Acronym Register Name

0182 0000 IDMA0STAT IDMA Channel 0 Status Register

0182 0004 IDMA0MASK IDMA Channel 0 Mask Register

0182 0008 IMDA0SRC IDMA Channel 0 Source Address Register

0182 000C IDMA0DST IDMA Channel 0 Destination Address Register

0182 0010 IDMA0CNT IDMA Channel 0 Count Register

0182 0014 - 0182 00FC - Reserved

0182 0100 IDMA1STAT IDMA Channel 1 Status Register

0182 0104 - Reserved

0182 0108 IMDA1SRC IDMA Channel 1 Source Address Register

0182 010C IDMA1DST IDMA Channel 1 Destination Address Register

0182 0110 IDMA1CNT IDMA Channel 1 Count Register

0182 0114 - 0182 017C - Reserved

0182 0180 - Reserved

0182 0184 - 0182 01FF - Reserved

End of Table 5-9

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

Table 5-10 Megamodule Cache Configuration Registers (Part 1 of 4)

Hex Address Range Acronym Register Name

0184 0000 L2CFG L2 Cache Configuration Register

0184 0004 - 0184 001F - Reserved

0184 0020 L1PCFG L1P Configuration Register

0184 0024 L1PCC L1P Cache Control Register

0184 0028 - 0184 003F - Reserved

0184 0040 L1DCFG L1D Configuration Register

0184 0044 L1DCC L1D Cache Control Register

0184 0048 - 0184 0FFF - Reserved

0184 1000 - 0184 104F - See Table 5-13 ‘‘CPU Megamodule Bandwidth Management Registers’’

0184 1050 - 0184 3FFF - Reserved

0184 4000 L2WBAR L2 Writeback Base Address Register — for Block Writebacks

0184 4004 L2WWC L2 Writeback Word Count Register

0184 4008 - 0184 400C - Reserved

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Table 5-10 Megamodule Cache Configuration Registers (Part 2 of 4)

Hex Address Range Acronym Register Name

0184 4010 L2WIBAR L2 Writeback and Invalidate Base Address Register — for Block Writebacks

0184 4014 L2WIWC L2 Writeback and Invalidate word count register

0184 4018 L2IBAR L2 Invalidate Base Address Register

0184 401C L2IWC L2 Invalidate Word Count Register

0184 4020 L1PIBAR L1P Invalidate Base Address Register

0184 4024 L1PIWC L1P Invalidate Word Count Register

0184 4030 L1DWIBAR L1D Writeback and Invalidate Base Address Register

0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register

0184 4038 - Reserved

PRODUCT PREVIEW

0184 4040 L1DWBAR L1D Writeback Base Address Register — for Block Writebacks

0184 4044 L1DWWC L1D Writeback Word Count Register

0184 4048 L1DIBAR L1D Invalidate Base Address Register

0184 404C L1DIWC L1D Invalidate Word Count Register

0184 4050 - 0184 4FFF - Reserved

0184 5000 L2WB L2 Global Writeback Register

0184 5004 L2WBINV L2 Global Writeback and Invalidate Register

0184 5008 L2INV L2 Global Invalidate Register

0184 500C - 0184 5024 - Reserved

0184 5028 L1PINV L1P Global Invalidate Register

0184 502C - 0184 503C - Reserved

0184 5040 L1DWB L1D Global Writeback Register

0184 5044 L1DWBINV L1D Global Writeback and Invalidate Register

0184 5048 L1DINV L1D Global Invalidate Register

0184 504C - 0184 5FFF - Reserved

0184 6000 - 0184 640F - See Table 5-11 ‘‘Megamodule Error Detection Correct Registers’’

0184 6410 - 0184 7FFF - Reserved

0184 8000 - 0184 81FC MAR0 to MAR127 Reserved

0184 8200 - 0184 823C MAR128 to MAR143 Reserved

0184 8240 - 0184 827C MAR144 to MAR159 Reserved

0184 8280 MAR160 Controls EMIFA CE2 Range A000 0000 - A0FF FFFF

0184 8284 MAR161 Controls EMIFA CE2 Range A100 0000 - A1FF FFFF

0184 8288 MAR162 Controls EMIFA CE2 Range A200 0000 - A2FF FFFF

0184 828C MAR163 Controls EMIFA CE2 Range A300 0000 - A3FF FFFF

0184 8290 MAR164 Controls EMIFA CE2 Range A400 0000 - A4FF FFFF

0184 8294 MAR165 Controls EMIFA CE2 Range A500 0000 - A5FF FFFF

0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 - A6FF FFFF

0184 829C MAR167 Controls EMIFA CE2 Range A700 0000 - A7FF FFFF

0184 82A0 MAR168 Controls EMIFA CE2 Range A800 0000 - A8FF FFFF

0184 82A4 MAR169 Controls EMIFA CE2 Range A900 0000 - A9FF FFFF

0184 82A8 MAR170 Controls EMIFA CE2 Range AA00 0000 - AAFF FFFF

0184 82AC MAR171 Controls EMIFA CE2 Range AB00 0000 - ABFF FFFF

0184 82B0 MAR172 Controls EMIFA CE2 Range AC00 0000 - ACFF FFFF

0184 82B4 MAR173 Controls EMIFA CE2 Range AD00 0000 - ADFF FFFF

0184 82B8 MAR174 Controls EMIFA CE2 Range AE00 0000 - AEFF FFFF

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Table 5-10 Megamodule Cache Configuration Registers (Part 3 of 4)

Hex Address Range Acronym Register Name

0184 82BC MAR175 Controls EMIFA CE2 Range AF00 0000 - AFFF FFFF

0184 82C0 MAR176 Controls EMIFA CE3 Range B000 0000 - B0FF FFFF

0184 82C4 MAR177 Controls EMIFA CE3 Range B100 0000 - B1FF FFFF

0184 82C8 MAR178 Controls EMIFA CE3 Range B200 0000 - B2FF FFFF

0184 82CC MAR179 Controls EMIFA CE3 Range B300 0000 - B3FF FFFF

0184 82D0 MAR180 Controls EMIFA CE3 Range B400 0000 - B4FF FFFF

0184 82D4 MAR181 Controls EMIFA CE3 Range B500 0000 - B5FF FFFF

0184 82D8 MAR182 Controls EMIFA CE3 Range B600 0000 - B6FF FFFF

0184 82DC MAR183 Controls EMIFA CE3 Range B700 0000 - B7FF FFFF

0184 82E0 MAR184 Controls EMIFA CE3 Range B800 0000 - B8FF FFFF

0184 82E4 MAR185 Controls EMIFA CE3 Range B900 0000 - B9FF FFFF

0184 82E8 MAR186 Controls EMIFA CE3 Range BA00 0000 - BAFF FFFF

0184 82EC MAR187 Controls EMIFA CE3 Range BB00 0000 - BBFF FFFF

0184 82F0 MAR188 Controls EMIFA CE3 Range BC00 0000 - BCFF FFFF

0184 82F4 MAR189 Controls EMIFA CE3 Range BD00 0000 - BDFF FFFF

0184 82F8 MAR190 Controls EMIFA CE3 Range BE00 0000 - BEFF FFFF

0184 82FC MAR191 Controls EMIFA CE3 Range BF00 0000 - BFFF FFFF

0184 8300 MAR192 Controls EMIFA CE4 Range C000 0000 - C0FF FFFF

0184 8304 MAR193 Controls EMIFA CE4 Range C100 0000 - C1FF FFFF

0184 8308 MAR194 Controls EMIFA CE4 Range C200 0000 - C2FF FFFF

0184 830C MAR195 Controls EMIFA CE4 Range C300 0000 - C3FF FFFF

0184 8310 MAR196 Controls EMIFA CE4 Range C400 0000 - C4FF FFFF

0184 8314 MAR197 Controls EMIFA CE4 Range C500 0000 - C5FF FFFF

0184 8318 MAR198 Controls EMIFA CE4 Range C600 0000 - C6FF FFFF

0184 831C MAR199 Controls EMIFA CE4 Range C700 0000 - C7FF FFFF

0184 8320 MAR200 Controls EMIFA CE4 Range C800 0000 - C8FF FFFF

0184 8324 MAR201 Controls EMIFA CE4 Range C900 0000 - C9FF FFFF

0184 8328 MAR202 Controls EMIFA CE4 Range CA00 0000 - CAFF FFFF

0184 832C MAR203 Controls EMIFA CE4 Range CB00 0000 - CBFF FFFF

0184 8330 MAR204 Controls EMIFA CE4 Range CC00 0000 - CCFF FFFF

0184 8334 MAR205 Controls EMIFA CE4 Range CD00 0000 - CDFF FFFF

0184 8338 MAR206 Controls EMIFA CE4 Range CE00 0000 - CEFF FFFF

0184 833C MAR207 Controls EMIFA CE4 Range CF00 0000 - CFFF FFFF

0184 8340 MAR208 Controls EMIFA CE5 Range D000 0000 - D0FF FFFF

0184 8344 MAR209 Controls EMIFA CE5 Range D100 0000 - D1FF FFFF

0184 8348 MAR210 Controls EMIFA CE5 Range D200 0000 - D2FF FFFF

0184 834C MAR211 Controls EMIFA CE5 Range D300 0000 - D3FF FFFF

0184 8350 MAR212 Controls EMIFA CE5 Range D400 0000 - D4FF FFFF

0184 8354 MAR213 Controls EMIFA CE5 Range D500 0000 - D5FF FFFF

0184 8358 MAR214 Controls EMIFA CE5 Range D600 0000 - D6FF FFFF

0184 835C MAR215 Controls EMIFA CE5 Range D700 0000 - D7FF FFFF

0184 8360 MAR216 Controls EMIFA CE5 Range D800 0000 - D8FF FFFF

0184 8364 MAR217 Controls EMIFA CE5 Range D900 0000 - D9FF FFFF

0184 8368 MAR218 Controls EMIFA CE5 Range DA00 0000 - DAFF FFFF

TMS320C6457

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Table 5-10 Megamodule Cache Configuration Registers (Part 4 of 4)

Hex Address Range Acronym Register Name

0184 836C MAR219 Controls EMIFA CE5 Range DB00 0000 - DBFF FFFF

0184 8370 MAR220 Controls EMIFA CE5 Range DC00 0000 - DCFF FFFF

0184 8374 MAR221 Controls EMIFA CE5 Range DD00 0000 - DDFF FFFF

0184 8378 MAR222 Controls EMIFA CE5 Range DE00 0000 - DEFF FFFF

0184 837C MAR223 Controls EMIFA CE5 Range DF00 0000 - DFFF FFFF

0184 8380 MAR224 Controls DDR2 CE0 Range E000 0000 - E0FF FFFF

0184 8384 MAR225 Controls DDR2 CE0 Range E100 0000 - E1FF FFFF

0184 8388 MAR226 Controls DDR2 CE0 Range E200 0000 - E2FF FFFF

0184 838C MAR227 Controls DDR2 CE0 Range E300 0000 - E3FF FFFF

PRODUCT PREVIEW

End of Table 5-10

0184 8390 MAR228 Controls DDR2 CE0 Range E400 0000 - E4FF FFFF

0184 8394 MAR229 Controls DDR2 CE0 Range E500 0000 - E5FF FFFF

0184 8398 MAR230 Controls DDR2 CE0 Range E600 0000 - E6FF FFFF

0184 839C MAR231 Controls DDR2 CE0 Range E700 0000 - E7FF FFFF

0184 83A0 MAR232 Controls DDR2 CE0 Range E800 0000 - E8FF FFFF

0184 83A4 MAR233 Controls DDR2 CE0 Range E900 0000 - E9FF FFFF

0184 83A8 MAR234 Controls DDR2 CE0 Range EA00 0000 - EAFF FFFF

0184 83AC MAR235 Controls DDR2 CE0 Range EB00 0000 - EBFF FFFF

0184 83B0 MAR236 Controls DDR2 CE0 Range EC00 0000 - ECFF FFFF

0184 83B4 MAR237 Controls DDR2 CE0 Range ED00 0000 - EDFF FFFF

0184 83B8 MAR238 Controls DDR2 CE0 Range EE00 0000 - EEFF FFFF

0184 83BC MAR239 Controls DDR2 CE0 Range EF00 0000 - EFFF FFFF

0184 83C0 - 0184 83FC MAR240 to MAR255 Reserved

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Table 5-11 Megamodule Error Detection Correct Registers

Hex Address Range Acronym Register Name

0184 6000 - Reserved

0184 6004 L2EDSTAT L2 Error Detection Status Register

0184 6008 L2EDCMD L2 Error Detection Command Register

0184 600C L2EDADDR L2 Error Detection Address Register

0184 6010 L2EDEN0 L2 Error Detection Enable Map 0 Register

0184 6014 L2EDEN1 L2 Error Detection Enable Map 1 Register

0184 6018 L2EDCPEC L2 Error Detection — Correctable Parity Error Count Register

0184 601C L2EDNPEC L2 Error Detection — Non-Correctable Parity Error Count Register

0184 6020 - 0184 6400 - Reserved

0184 6404 L1PEDSTAT L1P Error Detection Status Register

0184 6408 L1PEDCMD L1P Error Detection Command Register

0184 640C L1PEDADDR L1P Error Detection Address Register

End of Table 5-11

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Table 5-12 Megamodule L1/L2 Memory Protection Registers (Part 1 of 3)

Hex Address Range Acronym Register Name

0184 A000 L2MPFAR L2 memory protection fault address register

0184 A004 L2MPFSR L2 memory protection fault status register

0184 A008 L2MPFCR L2 memory protection fault command register

0184 A00C - 0184 A0FF - Reserved

0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]

0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]

0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]

0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]

0184 A110 L2MPLKCMD L2 memory protection lock key command register

0184 A114 L2MPLKSTAT L2 memory protection lock key status register

0184 A118 - 0184 A1FF - Reserved

0184 A200 L2MPPA0 L2 memory protection page attribute register 0

0184 A204 L2MPPA1 L2 memory protection page attribute register 1

0184 A208 L2MPPA2 L2 memory protection page attribute register 2

0184 A20C L2MPPA3 L2 memory protection page attribute register 3

0184 A210 L2MPPA4 L2 memory protection page attribute register 4

0184 A214 L2MPPA5 L2 memory protection page attribute register 5

0184 A218 L2MPPA6 L2 memory protection page attribute register 6

0184 A21C L2MPPA7 L2 memory protection page attribute register 7

0184 A220 L2MPPA8 L2 memory protection page attribute register 8

0184 A224 L2MPPA9 L2 memory protection page attribute register 9

0184 A228 L2MPPA10 L2 memory protection page attribute register 10

0184 A22C L2MPPA11 L2 memory protection page attribute register 11

0184 A230 L2MPPA12 L2 memory protection page attribute register 12

0184 A234 L2MPPA13 L2 memory protection page attribute register 13

0184 A238 L2MPPA14 L2 memory protection page attribute register 14

0184 A23C L2MPPA15 L2 memory protection page attribute register 15

0184 A240 L2MPPA16 L2 memory protection page attribute register 16

0184 A244 L2MPPA17 L2 memory protection page attribute register 17

0184 A248 L2MPPA18 L2 memory protection page attribute register 18

0184 A24C L2MPPA19 L2 memory protection page attribute register 19

0184 A250 L2MPPA20 L2 memory protection page attribute register 20

0184 A254 L2MPPA21 L2 memory protection page attribute register 21

0184 A258 L2MPPA22 L2 memory protection page attribute register 22

0184 A25C L2MPPA23 L2 memory protection page attribute register 23

0184 A260 L2MPPA24 L2 memory protection page attribute register 24

0184 A264 L2MPPA25 L2 memory protection page attribute register 25

0184 A268 L2MPPA26 L2 memory protection page attribute register 26

0184 A26C L2MPPA27 L2 memory protection page attribute register 27

0184 A270 L2MPPA28 L2 memory protection page attribute register 28

0184 A274 L2MPPA29 L2 memory protection page attribute register 29

0184 A278 L2MPPA30 L2 memory protection page attribute register 30

0184 A27C L2MPPA31 L2 memory protection page attribute register 31

0184 A280 - 0184 A2FC

(1)

- Reserved

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Table 5-12 Megamodule L1/L2 Memory Protection Registers (Part 2 of 3)

Hex Address Range Acronym Register Name

0184 0300 - 0184 A3FF - Reserved

0184 A400 L1PMPFAR L1 program (L1P) memory protection fault address register

0184 A404 L1PMPFSR L1P memory protection fault status register

0184 A408 L1PMPFCR L1P memory protection fault command register

0184 A40C - 0184 A4FF - Reserved

0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]

0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]

0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]

0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]

PRODUCT PREVIEW

0184 A510 L1PMPLKCMD L1P memory protection lock key command register

0184 A514 L1PMPLKSTAT L1P memory protection lock key status register

0184 A518 - 0184 A5FF - Reserved

0184 A600 - 0184 A63C

0184 A640 L1PMPPA16 L1P memory protection page attribute register 16

0184 A644 L1PMPPA17 L1P memory protection page attribute register 17

0184 A648 L1PMPPA18 L1P memory protection page attribute register 18

0184 A64C L1PMPPA19 L1P memory protection page attribute register 19

0184 A650 L1PMPPA20 L1P memory protection page attribute register 20

0184 A654 L1PMPPA21 L1P memory protection page attribute register 21

0184 A658 L1PMPPA22 L1P memory protection page attribute register 22

0184 A65C L1PMPPA23 L1P memory protection page attribute register 23

0184 A660 L1PMPPA24 L1P memory protection page attribute register 24

0184 A664 L1PMPPA25 L1P memory protection page attribute register 25

0184 A668 L1PMPPA26 L1P memory protection page attribute register 26

0184 A66C L1PMPPA27 L1P memory protection page attribute register 27

0184 A670 L1PMPPA28 L1P memory protection page attribute register 28

0184 A674 L1PMPPA29 L1P memory protection page attribute register 29

0184 A678 L1PMPPA30 L1P memory protection page attribute register 30

0184 A67C L1PMPPA31 L1P memory protection page attribute register 31

0184 A680 - 0184 ABFF - Reserved

0184 AC00 L1DMPFAR L1 data (L1D) memory protection fault address register

0184 AC04 L1DMPFSR L1D memory protection fault status register

0184 AC08 L1DMPFCR L1D memory protection fault command register

0184 AC0C - 0184 ACFF - Reserved

0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]

0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]

0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]

0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]

0184 AD10 L1DMPLKCMD L1D memory protection lock key command register

0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register

0184 AD18 - 0184 ADFF - Reserved

0184 AE00 - 0184 AE3C

0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16

0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17

(2)

(3)

- Reserved

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- Reserved

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Table 5-12 Megamodule L1/L2 Memory Protection Registers (Part 3 of 3)

Hex Address Range Acronym Register Name

0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18

0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19

0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20

0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21

0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22

0184 AE5C L1DMPPA23 L1D memory protection page attribute register 23

0184 AE60 L1DMPPA24 L1D memory protection page attribute register 24

0184 AE64 L1DMPPA25 L1D memory protection page attribute register 25

0184 AE68 L1DMPPA26 L1D memory protection page attribute register 26

0184 AE6C L1DMPPA27 L1D memory protection page attribute register 27

0184 AE70 L1DMPPA28 L1D memory protection page attribute register 28

0184 AE74 L1DMPPA29 L1D memory protection page attribute register 29

0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30

0184 AE7C L1DMPPA31 L1D memory protection page attribute register 31

0184 AE80 - 0185 FFFF - Reserved

End of Table 5-12

1 These addresses correspond to the L2 memory protection page attribute registers 32-63 (L2MPPA32 - L2MPPA63) of the C64x+ Megamodule. These registers are not

supported for the C6457 device.

2 These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0 - L1PMPPA15) of the C64x+ Megamodule. These registers are not

supported for the C6457 device.

3 These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0 - L1DMPPA15) of the C64x+ Megamodule. These registers are not

supported for the C6457 device.

SPRS582B—July 2010

Table 5-13 CPU Megamodule Bandwidth Management Registers

Hex Address Range Acronym Register Name

0182 0200 EMCCPUARBE EMC CPU Arbitration Control Register

0182 0204 EMCIDMAARBE EMC IDMA Arbitration Control Register

0182 0208 EMCSDMAARBE EMC Slave DMA Arbitration Control Register

0182 020C EMCMDMAARBE EMC Master DMA Arbitration Control Register

0182 0210 - 0182 02FF - Reserved

0184 1000 L2DCPUARBU L2D CPU Arbitration Control Register

0184 1004 L2DIDMAARBU L2D IDMA Arbitration Control Register

0184 1008 L2DSDMAARBU L2D Slave DMA Arbitration Control Register

0184 100C L2DUCARBU L2D User Coherence Arbitration Control Register

0184 1010 - 0184 103F - Reserved

0184 1040 L1DCPUARBD L1D CPU Arbitration Control Register

0184 1044 L1DIDMAARBD L1D IDMA Arbitration Control Register

0184 1048 L1DSDMAARBD L1D Slave DMA Arbitration Control Register

0184 104C L1DUCARBD L1D User Coherence Arbitration Control Register

End of Table 5-13

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6 Device Operating Conditions

Based on JESD22-C101C (Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components), the TMS320C6457 device’s
charged-device model (CDM) sensitivity classification is Class II (200 V to < 500 V). Specifically, DDR memory
interface and SerDes pins conform to ±200-V level. All other pins conform to ±500 V.

6.1 Absolute Maximum Ratings

Table 6-1 Absolute Maximum Ratings

(1)

Over Operating Case Temperature Range (Unless Otherwise Noted)

CVDD -0.3 V to 1.35 V

-0.3 V to 2.45 V

DV

DD18

-0.3 V to 3.60V

DV

DD33

Supply voltage range

0.49 × DV

V

(2)

:

REFSSTL

V

, V

, V

DD11

DDD11

-0.3 V to 2.45 V

V

DDR18

, AV

AV

DD118

DD218

Ground 0 V

V

SS

-0.3 V to 1.35 V

DDT11

LVCMOS (1.8V) -0.3 V to DV

LVCMOS (3.3V) -0.3 V to DV

to 0.51 × DV

DD18

DD18

-0.3 V to 2.45 V

+ 0.3 V

DD18

+ 0.3 V

DD33

DDR2 -0.3 V to 2.45 V

Input voltage (V

) range:

I

2

C -0.3 V to 2.45 V

I

LVDS -0.3 V to D

VDD18

+ 0.3 V

LJCB -0.3 V to 1.35 V

VDD11

DD18

DD33

DD11

+ 0.3 V

+ 0.3 V

+ 0.3 V

+ 0.3 V

Output voltage (V

) range:

O

SerDes -0.3 V to D

LVCMOS (1.8V) -0.3 V to DV

LVCMOS (3.3V) -0.3 V to DV

DDR2 -0.3 V to 2.45 V

2

C -0.3 V to 2.45 V

I

SerDes -0.3 V to DV

850 MHz CPU 0°C to 100°C

Operating case temperature range, T

Commercial

:

C

Extended

1-GHz CPU 0°C to 100°C

1.2-GHz CPU 0°C to 95°C

1-GHz CPU -40°C to 100°C

1.2-GHz CPU -40°C to 95°C

LVCMOS (1.8V)

(3)

Overshoot/undershoot

Storage temperature range, T

LVCMOS (3.3V)

DDR2

2

I

C

: -65°C to 150°C

stg

20% Overshoot/Undershoot for 20% of

Signal Duty Cycle

End of Table 6-1

1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the

device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated

conditions for extended periods may affect device reliability.
2 All voltage values are with respect to VSS.
3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DV

maximum undershoot value would be V

- 0.20 × DV

SS

DD18

+ 0.20 × DV

DD18

DD18

and

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6.2 Recommended Operating Conditions

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Table 6-2 Recommended Operating Conditions

Supply core voltage

CV

DD

1.8-V supply I/O voltage 1.71 1.8 1.89 V

DV

DD18

3.3-V supply I/O voltage 3.135 3.3 3.465 V

DV

DD33

DDR2 reference voltage 0.49 × DV

V

REFSSTL

V

DDR18

V

PRODUCT PREVIEW

DDA11

V

DDD11

V

DDT11

PLLV

PLLV

Ground 0 0 0 V

V

SS

V

IH

V

IL

Operating case temperature

T

C

End of Table 6-2

1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE

802.3ae-2002.

2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

SRIO/SGMII SerDes regulator supply 1.71 1.8 1.89 V

SRIO/SGMII SerDes analog supply 1.045 1.1 1.155 V

SRIO/SGMII SerDes digital supply 1.045 1.1 1.155 V

SRIO/SGMII SerDes termination supply 1.045 1.1 1.155 V

PLL1 analog supply 1.71 1.8 1.89 V

1

PLL2 analog supply 1.71 1.8 1.89 V

2

High-level input voltage

Low-level input voltage

(1) (2)

Min Nom Max Unit

850-MHz CPU 1.067 1.1 1.133

1.2-GHz CPU 1.164 1.2 1.236

LVCMOS (1.8 V) 0.65 × DV

DD18

DD18

0.5 × DV

DD18

0.51 × DV

DD18

LVCMOS (3.3 V) 2.0 V

2

C0.7 × DV

I

DDR2 EMIF V

REFSSTL

LVCMOS (1.8 V) 0.35 × DV

DD18

+ 0.125 DV

+ 0.3 V

DD18

DD18

LVCMOS (3.3 V) 0.8 V

DDR2 EMIF -0.3 V

2

C 0.3 × DV

I

REFSSTL

- 0.1 V

DD18

850 MHz CPU 0 100

Commercial

1.2-GHz CPU 0 95

Extended

1-GHz CPU -40 100

1.2-GHz CPU -40 95

V1-GHz CPU 1.067 1.1 1.133

V

V

V

V

V

°C 1-GHz CPU 0 100

°C

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6.3 Electrical Characteristics

Table 6-3 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Parameter Test Conditions

High-level output voltage

V

OH

VOLLow-level output voltage

LVCMOS (1.8 V) I

LVCMOS (3.3 V) I

DDR2 1.4

2

C 0.1 × DV

I

LVCMOS (1.8 V) I

LVCMOS (3.3 V) I

DDR2 0.4

2

CI

I

= IOH DV

O

= -2 mA 2.4

O

= IOL 0.45

O

= 2 mA 0.4

O

= 3 mA, pulled up to 1.8 V 0.4

O

No IPD/IPU -5 5

LVCMOS (1.8 V)

Internal pulldown -170 -100 -50

(2)

I

Input current [DC]

I

LVCMOS (3.3 V)

No IPD/IPU -1 1

Internal pulldown -270 -150 -70

2

C

I

0.1 × DV
DV

DD18

DD18

V

EMU[18:00], GPIO[15:0], TIMO[1:0] -8

SYSCLKOUT, TDO, CLKR0, CLKX0,
DX0, FSR0, FSX0, CLKR1, CLKX1,

High-level output current [DC]

I

OH

DX1, FSR1, FSX1, AECLKOUT

RESETSTAT

, MDIO, MDCLK -4

DDR2 4

LVCMOS (3.3 V), except AECLKOUT -4

EMU[18:00], GPIO[15:0], TIM[1:0] 8

SYSCLKOUT, TDO, CLKR0, CLKX0,
DX0, FSR0, FSX0, CLKR1, CLKX1,

Low-level output current [DC]

I

OL

DX1, FSR1, FSX1, AECLKOUT

RESETSTAT

, MDIO, MDCLK 4

DDR2 -4

LVCMOS (3.3 V), except AECLKOUT 4

(3)

Off-state output current [DC]

I

OZ

LVCMOS (1.8 V) -20 20

LVCMOS (3.3 V) -20 20

End of Table 6-3

1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
2II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and

off-state (Hi-Z) output leakage current.
3IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

(1)

V < VI < 0.9 ×

Min Typ Max Unit

- 0.45

DD18

DD18

-20 20 μA

-6

6

V

V

μAInternal pullup 50 100 170

μAInternal pullup 70 150 270

mA

mA

μA

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Table 6-4 Power Supply to Peripheral I/O Mapping

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)2

Power Supply I/O Buffer Type Associated Peripheral

Supply core voltage LJCB

CV

DD

DV

1.8-V supply I/O voltage

PRODUCT PREVIEW

DD18

3.3-V supply I/O voltage LVCMOS (3.3 V)

DV

DD33

SRIO/SGMII SerDes analog supply CML SRIO/SGMII SerDes CML I/O buffer

V

DDA11

End of Table 6-4

1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and

clock input buffers.
2 Please see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7) for more information about individual peripheral I/O.

(1) (2)

CORECLK(P|N) PLL input buffers

DDRREFCLK(N|P) PLL input buffers

RIOSGMIICLK(N|P) SerDes PLL input buffers

ALTCORECLK PLL input buffer

ALTDDRCLK PLL input buffer

POR/RESET input buffers

LVCMOS (1.8 V)

DDR2 (1.8V) All DDR2 memory controller peripheral I/O buffer

Open-drain (1.8 V) All I

All GPIO peripheral I/O buffer

All McBSP0/McBSP1 peripheral I/O buffer

All MDIO peripheral I/O buffer

All Timer0/Timer1 peripheral I/O buffer

NMI input buffers

2

C peripheral I/O buffer

All EMIFA peripheral I/O buffer

ALL HPI peripheral I/O buffer

ALL UTOPIA peripheral I/O buffer

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SPRS582B—July 2010

7 C64x+ Peripheral Information and Electrical Specifications

This chapter describes the various peripherals on the TMS320C6457 DSP. Peripheral specific information, timing
diagrams, electrical specifications and register memory maps are described in this chapter.

7.1 Parameter Information

This section describes the conditions used to capture the electrical data seen in this chapter.

Figure 7-1 Test Load Circuit for AC Timing Measurements

Tester Terminal Electronics

42 W

4.0 pF 1.85 pF

(A) The data manual provides timing at the device terminal. For output timing analysis, the tester terminal electronics and its transmission line effects must be taken into

account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not
necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

(B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device terminal.

3.5 nH

Transmission Line

Zo=50W

(see Note A)

Data Manual Timing Reference Point

Output Under Test

Device Terminal

(see Note B)

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load
capacitance value does not indicate the maximum load the device is capable of driving.

7.1.1 1.8-V Signal Transition Levels

All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.

Figure 7-2 Input and Output Voltage Reference Levels for 1.8-V AC Timing Measurements

V = 0.9 V

ref

PRODUCT PREVIEW

All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels

V = V MIN (or V MIN)

ref IH OH

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7.1.2 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.

Figure 7-4 Input and Output Voltage Reference Levels for 3.3-V AC Timing Measurements

V = 1.5 V

ref

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All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, V
and V

Figure 7-5 Rise and Fall Transition Time Voltage Reference Levels

MIN for output clocks.

OH

PRODUCT PREVIEW

7.1.3 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

7.1.4 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board
design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS)
models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis
for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839).
If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 7-1 and Figure 7-6).

V = V MIN (or V MIN)

ref IH OH

OL

MAX

Table 7-1 Board-Level Timing Example

(see Figure 7-6)

No. Description

1 Clock route delay

2 Minimum DSP hold time

3 Minimum DSP setup time

4 External device hold time requirement

5 External device setup time requirement

6 Control signal route delay

7 External device hold time

8 External device access time

9 DSP hold time requirement

10 DSP setup time requirement

11 Data route delay

End of Table 7-1

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Figure 7-6 shows a general transfer between the DSP and an external device. The figure also shows board route

delays and how they are perceived by the DSP and the external device

Figure 7-6 Board-Level Input/Output Timings

AECLKOUT

(Output from DSP)

AECLKOUT

(Input to External Device)

Control Signals

(Output from DSP)

Control Signals

(Input to External Device)

Data Signals

(Output from External Device)

Data Signals

(Input to DSP)

(A)

(B)

(B)

3

6

1

2

4

5

7

8

9

11

10

SPRS582B—July 2010

(A) Control signals include data for writes.
(B) Data signals are generated during reads from an external device.

7.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.

7.3 Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the
C6457 DSP. This section also describes proper power-supply decoupling methods.

PRODUCT PREVIEW

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7.3.1 Power-Supply Sequencing

TI recommends the power-supply sequence shown in Figure 7-7 and described in Table 7-2. The figure shows that
the 1.8-V I/O supply should be ramped first. This is followed by the scaled core supply and the fixed 1.1-V supplies
which must ramp within 5 ms of each other. The 3.3-V I/O supply should ramp up last. Some TI power-supply
devices include features that facilitate power sequencing; for example, Auto-Track or Slow-Start/Enable features.
For more information, visit www.ti.com/dsppower. See the TMS320TCI6468 and TMS329C6457 DSPs Hardware
Design Guide (SPRAAV7) for further details on proper power-supply sequencing.

Figure 7-7 Power-Supply Sequence

DV

DD18

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PRODUCT PREVIEW

V (DDR2)

REFSSTL

CV

DD11

DV

DD11

DV

DD33

POR

Table 7-2 Timing Requirements for Power-Supply Sequence

No. Min Max Unit

1t

su(DVDD18-DVDD11)

2t

su(DVDD11-DVDD33)

3t

h(DVDD33-POR)

End of Table 7-2

Setup Time, DV

Setup Time, DV

Hold time, POR low after DV

DD18

DD11

7.3.2 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close
to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective.
Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view.
Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors
should be used while maintaining the largest available capacitance value. As with the selection of any component,
verification of capacitor availability over the product's production lifetime should be considered.

and V

and CV

1

2

3

supplies stable before DV

REFSSTL

supplies stable before DV

DD11

supplies stable 100 μs

DD33

and CV

DD11

supply stable 0.5 200 ms

DD33

supplies stable 0.5 200 ms

DD11

7.3.3 Power-Down Operation

One of the power goals for the C6457 is to reduce power dissipation due to unused peripherals. There are different
ways to power down peripherals on the device.

After device reset, all peripherals on the C6457 device are in a disabled state and must be enabled by software before
being used. It is possible to enable only the peripherals needed by the application while keeping the rest disabled.
Note that peripherals in a disabled state are held in reset with their clocks gated. For more information on how to
enable peripherals, see Section 3.2 ‘‘Peripheral Selection After Device Reset’’ on page 60

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Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is possible to
disable peripherals used for booting after the boot process is complete. This, too, results in gating of the clock(s) to
the powered-down peripheral. Once a peripheral is powered-down, it must remain powered down until the next
device reset.

The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+
megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or the entire
C64x+ megamodule through the power-down controller based on its own execution thread or in response to an
external stimulus from a host or global controller. More information on the power-down features of the C64x+
Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).

SPRS582B—July 2010

7.4 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event-driven peripherals such as a McBSP or the UTOPIA port, and offloads data transfers from the device CPU.

The EDMA3 includes the following features:

• Fully orthogonal transfer description

– 3 transfer dimensions:

› Array (multiple bytes)
› Frame (multiple arrays)

› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination

• Flexible transfer definition:

– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous

transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event

• 256 PaRAM entries

– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

• 64 DMA channels
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain

triggered (completion of one transfer triggers another)

•8 Quick DMA (QDMA) channels

– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry

• 6 transfer controllers and 6 event queues with programmable system-level priority

• Interrupt generation for transfer completion and error conditions

• Debug visibility

– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug

PRODUCT PREVIEW

Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 4-1 ‘‘SCR

Connection Matrix’’ on page 67 lists the peripherals that can be accessed by the transfer controllers.

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7.4.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used.
On the C6457 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP2) and the Enhanced Turbo Decoder Coprocessor (TCP2). Constant addressing mode is not
supported by any other peripheral or internal memory in the C6457 DSP. Note that increment mode is supported
by all C6457 peripherals, including VCP2 and TCP2. For more information on these two addressing modes, see the
TMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRUGK6).

A DSP interrupt must be generated at the end of an HPI boot operation to begin execution of the loaded application.
Because the DSP interrupt generated by the HPI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will
get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering

PRODUCT PREVIEW

transfers on DMA channel 0. The EDMA3 on the C6457 DSP supports active memory protection, but it does not
support proxied memory protection.

7.4.2 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data
between system memories. DMA channels can be triggered by synchronization events generated by system
peripherals. Table 7-3 lists the source of the synchronization event associated with each of the DMA channels. On
the C6457, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

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For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the TMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's
Guide (literature number SPRUGK6).

Table 7-3 C6457 EDMA3 Channel Synchronization Events

EDMA Channel Event Name Event Description

(2)

DSP_EVT HPI-to-DSP event

0

1 TEVTLO0 Timer 0 Lower Counter Event

2 TEVTHI0 Timer 0 High Counter Event

3 - 8 - None

9 ETBHFULLINT Embedded Trace Buffer (ETB) is half full

10 ETBFULLINT Embedded Trace Buffer (ETB) is full

11 ETBACQINT Embedded Trace Buffer (ETB) acquisition is complete

12 XEVT0 McBSP0 Transmit Event

13 REVT0 McBSP0 Receive Event

14 XEVT1 McBSP1 Transmit Event

15 REVT1 McBSP1 Receive Event

16 TEVTLO1 Timer 1 Lower Counter Event

17 TEVTHI1 Timer 1 High Counter Event

18 - None

19 INTDST0 RapidIO Interrupt 0

20 INTDST1 RapidIO Interrupt 1

21 INTDST2 RapidIO Interrupt 2

22 INTDST3 RapidIO Interrupt 3

23 INTDST4 RapidIO Interrupt 4

24 INTDST5 RapidIO Interrupt 5

25 INTDST6 RapidIO Interrupt 6

26 - 27 - None

(1)

(Part 1 of 2)

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Table 7-3 C6457 EDMA3 Channel Synchronization Events

EDMA Channel Event Name Event Description

28 VCP2REVT VCP2 Receive Event

29 VCP2XEVT VCP2 Transmit Event

30 TCP2AREVT TCP2_A Receive Event

31 TCP2AXEVT TCP2_A Transmit Event

32 UREVT UTOPIA Receive Event

33 TCP2BREVT TCP2_B Receive Event

34 TCP2BXEVT TCP2_B Transmit Event

35 - 39 - None

40 UXEVT UTOPIA Transmit Event

41 - 43 - None

2

44 ICREVT I

45 ICXEVT I

46 - 47 - None

48 GPINT0 GPIO event 0

49 GPINT1 GPIO event 1

50 GPINT2 GPIO event 2

51 GPINT3 GPIO event 3

52 GPINT4 GPIO event 4

53 GPINT5 GPIO event 5

54 GPINT6 GPIO event 6

55 GPINT7 GPIO event 7

56 GPINT8 GPIO event 8

57 GPINT9 GPIO event 9

58 GPINT10 GPIO event 10

59 GPINT11 GPIO event 11

60 GPINT12 GPIO event 12

61 GPINT13 GPIO event 13

62 GPINT14 GPIO event 14

63 GPINT15 GPIO event 15

End of Table 7-3

1 In addition to the ev ents shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more

detailed information on EDMA event-transfer chaining, see the TMS320C6457 DSP Enhanced DM A (EDMA3) Controller User's Guide (literature number SPRUGK6).

2 HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (E R). T his eve nt m ust b e cl ear ed b y sof twa re b efo re

triggering transfers on DMA channel 0.

C Receive Event

2

C Transmit Event

(1)

(Part 2 of 2)

SPRS582B—July 2010

PRODUCT PREVIEW

7.4.3 EDMA3 Peripheral Register Description(s)

Table 7-4 EDMA3 Registers (Part 1 of 15)

Hex Address Acronym Register Name

02A0 0000 PID Peripheral ID Register

02A0 0004 CCCFG EDMA3CC Configuration Register

02A0 0008 - 02A0 00FC - Reserved

02A0 0100 DCHMAP0 DMA Channel 0 Mapping Register

02A0 0104 DCHMAP1 DMA Channel 1 Mapping Register

02A0 0108 DCHMAP2 DMA Channel 2 Mapping Register

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Table 7-4 EDMA3 Registers (Part 2 of 15)

Hex Address Acronym Register Name

02A0 010C DCHMAP3 DMA Channel 3 Mapping Register

02A0 0110 DCHMAP4 DMA Channel 4 Mapping Register

02A0 0114 DCHMAP5 DMA Channel 5 Mapping Register

02A0 0118 DCHMAP6 DMA Channel 6 Mapping Register

02A0 011C DCHMAP7 DMA Channel 7 Mapping Register

02A0 0120 DCHMAP8 DMA Channel 8 Mapping Register

02A0 0124 DCHMAP9 DMA Channel 9 Mapping Register

02A0 0128 DCHMAP10 DMA Channel 10 Mapping Register

02A0 012C DCHMAP11 DMA Channel 11 Mapping Register

PRODUCT PREVIEW

02A0 0130 DCHMAP12 DMA Channel 12 Mapping Register

02A0 0134 DCHMAP13 DMA Channel 13 Mapping Register

02A0 0138 DCHMAP14 DMA Channel 14 Mapping Register

02A0 013C DCHMAP15 DMA Channel 15 Mapping Register

02A0 0140 DCHMAP16 DMA Channel 16 Mapping Register

02A0 0144 DCHMAP17 DMA Channel 17 Mapping Register

02A0 0148 DCHMAP18 DMA Channel 18 Mapping Register

02A0 014C DCHMAP19 DMA Channel 19 Mapping Register

02A0 0150 DCHMAP20 DMA Channel 20 Mapping Register

02A0 0154 DCHMAP21 DMA Channel 21 Mapping Register

02A0 0158 DCHMAP22 DMA Channel 22 Mapping Register

02A0 015C DCHMAP23 DMA Channel 23 Mapping Register

02A0 0160 DCHMAP24 DMA Channel 24 Mapping Register

02A0 0164 DCHMAP25 DMA Channel 25 Mapping Register

02A0 0168 DCHMAP26 DMA Channel 26 Mapping Register

02A0 016C DCHMAP27 DMA Channel 27 Mapping Register

02A0 0170 DCHMAP28 DMA Channel 28 Mapping Register

02A0 0174 DCHMAP29 DMA Channel 29 Mapping Register

02A0 0178 DCHMAP30 DMA Channel 30 Mapping Register

02A0 017C DCHMAP31 DMA Channel 31 Mapping Register

02A0 0180 DCHMAP32 DMA Channel 32 Mapping Register

02A0 0184 DCHMAP33 DMA Channel 33 Mapping Register

02A0 0188 DCHMAP34 DMA Channel 34 Mapping Register

02A0 018C DCHMAP35 DMA Channel 35 Mapping Register

02A0 0190 DCHMAP36 DMA Channel 36 Mapping Register

02A0 0194 DCHMAP37 DMA Channel 37 Mapping Register

02A0 0198 DCHMAP38 DMA Channel 38 Mapping Register

02A0 019C DCHMAP39 DMA Channel 39 Mapping Register

02A0 01A0 DCHMAP40 DMA Channel 40 Mapping Register

02A0 01A4 DCHMAP41 DMA Channel 41 Mapping Register

02A0 01A8 DCHMAP42 DMA Channel 42 Mapping Register

02A0 01AC DCHMAP43 DMA Channel 43 Mapping Register

02A0 01B0 DCHMAP44 DMA Channel 44 Mapping Register

02A0 01B4 DCHMAP45 DMA Channel 45 Mapping Register

02A0 01B8 DCHMAP46 DMA Channel 46 Mapping Register

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Table 7-4 EDMA3 Registers (Part 3 of 15)

Hex Address Acronym Register Name

02A0 01BC DCHMAP47 DMA Channel 47 Mapping Register

02A0 01C0 DCHMAP48 DMA Channel 48 Mapping Register

02A0 01C4 DCHMAP49 DMA Channel 49 Mapping Register

02A0 01C8 DCHMAP50 DMA Channel 50 Mapping Register

02A0 01CC DCHMAP51 DMA Channel 51 Mapping Register

02A0 01D0 DCHMAP52 DMA Channel 52 Mapping Register

02A0 01D4 DCHMAP53 DMA Channel 53 Mapping Register

02A0 01D8 DCHMAP54 DMA Channel 54 Mapping Register

02A0 01DC DCHMAP55 DMA Channel 55 Mapping Register

02A0 01E0 DCHMAP56 DMA Channel 56 Mapping Register

02A0 01E4 DCHMAP57 DMA Channel 57 Mapping Register

02A0 01E8 DCHMAP58 DMA Channel 58 Mapping Register

02A0 01EC DCHMAP59 DMA Channel 59 Mapping Register

02A0 01F0 DCHMAP60 DMA Channel 60 Mapping Register

02A0 01F4 DCHMAP61 DMA Channel 61 Mapping Register

02A0 01F8 DCHMAP62 DMA Channel 62 Mapping Register

02A0 01FC DCHMAP63 DMA Channel 63 Mapping Register

02A0 0200 QCHMAP0 QDMA Channel 0 Mapping Register

02A0 0204 QCHMAP1 QDMA Channel 1 Mapping Register

02A0 0208 QCHMAP2 QDMA Channel 2 Mapping Register

02A0 020C QCHMAP3 QDMA Channel 3 Mapping Register

02A0 0210 QCHMAP4 QDMA Channel 4 Mapping Register

02A0 0214 QCHMAP5 QDMA Channel 5 Mapping Register

02A0 0218 QCHMAP6 QDMA Channel 6 Mapping Register

02A0 021C QCHMAP7 QDMA Channel 7 Mapping Register

02A0 0220 - 02A0 023C - Reserved

02A0 0240 DMAQNUM0 DMA Queue Number Register 0

02A0 0244 DMAQNUM1 DMA Queue Number Register 1

02A0 0248 DMAQNUM2 DMA Queue Number Register 2

02A0 024C DMAQNUM3 DMA Queue Number Register 3

02A0 0250 DMAQNUM4 DMA Queue Number Register 4

02A0 0254 DMAQNUM5 DMA Queue Number Register 5

02A0 0258 DMAQNUM6 DMA Queue Number Register 6

02A0 025C DMAQNUM7 DMA Queue Number Register 7

02A0 0260 QDMAQNUM QDMA Queue Number Register

02A0 0264 - 02A0 027C - Reserved

02A0 0280 QUETCMAP Queue to TC Mapping Register

02A0 0284 QUEPRI Queue Priority Register

02A0 0288 - 02A0 02FC - Reserved

02A0 0300 EMR Event Missed Register

02A0 0304 EMRH Event Missed Register High

02A0 0308 EMCR Event Missed Clear Register

02A0 030C EMCRH Event Missed Clear Register High

02A0 0310 QEMR QDMA Event Missed Register

TMS320C6457

SPRS582B—July 2010

PRODUCT PREVIEW

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Table 7-4 EDMA3 Registers (Part 4 of 15)

Hex Address Acronym Register Name

02A0 0314 QEMCR QDMA Event Missed Clear Register

02A0 0318 CCERR EDMA3CC Error Register

02A0 031C CCERRCLR EDMA3CC Error Clear Register

02A0 0320 EEVAL Error Evaluate Register

02A0 0324 - 02A0 033C - Reserved

02A0 0340 DRAE0 DMA Region Access Enable Register for Region 0

02A0 0344 DRAEH0 DMA Region Access Enable Register High for Region 0

02A0 0348 DRAE1 DMA Region Access Enable Register for Region 1

02A0 034C DRAEH1 DMA Region Access Enable Register High for Region 1

PRODUCT PREVIEW

02A0 0350 DRAE2 DMA Region Access Enable Register for Region 2

02A0 0354 DRAEH2 DMA Region Access Enable Register High for Region 2

02A0 0358 DRAE3 DMA Region Access Enable Register for Region 3

02A0 035C DRAEH3 DMA Region Access Enable Register High for Region 3

02A0 0360 DRAE4 DMA Region Access Enable Register for Region 4

02A0 0364 DRAEH4 DMA Region Access Enable Register High for Region 4

02A0 0368 DRAE5 DMA Region Access Enable Register for Region 5

02A0 036C DRAEH5 DMA Region Access Enable Register High for Region 5

02A0 0370 DRAE6 DMA Region Access Enable Register for Region 6

02A0 0374 DRAEH6 DMA Region Access Enable Register High for Region 6

02A0 0378 DRAE7 DMA Region Access Enable Register for Region 7

02A0 037C DRAEH7 DMA Region Access Enable Register High for Region 7

02A0 0380 QRAE0 QDMA Region Access Enable Register for Region 0

02A0 0384 QRAE1 QDMA Region Access Enable Register for Region 1

02A0 0388 QRAE2 QDMA Region Access Enable Register for Region 2

02A0 038C QRAE3 QDMA Region Access Enable Register for Region 3

02A0 0390 QRAE4 QDMA Region Access Enable Register for Region 4

02A0 0394 QRAE5 QDMA Region Access Enable Register for Region 5

02A0 0398 QRAE6 QDMA Region Access Enable Register for Region 6

02A0 039C QRAE7 QDMA Region Access Enable Register for Region 7

02A0 0400 Q0E0 Event Queue 0 Entry Register 0

02A0 0404 Q0E1 Event Queue 0 Entry Register 1

02A0 0408 Q0E2 Event Queue 0 Entry Register 2

02A0 040C Q0E3 Event Queue 0 Entry Register 3

02A0 0410 Q0E4 Event Queue 0 Entry Register 4

02A0 0414 Q0E5 Event Queue 0 Entry Register 5

02A0 0418 Q0E6 Event Queue 0 Entry Register 6

02A0 041C Q0E7 Event Queue 0 Entry Register 7

02A0 0420 Q0E8 Event Queue 0 Entry Register 8

02A0 0424 Q0E9 Event Queue 0 Entry Register 9

02A0 0428 Q0E10 Event Queue 0 Entry Register 10

02A0 042C Q0E11 Event Queue 0 Entry Register 11

02A0 0430 Q0E12 Event Queue 0 Entry Register 12

02A0 0434 Q0E13 Event Queue 0 Entry Register 13

02A0 0438 Q0E14 Event Queue 0 Entry Register 14

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