Texas instruments TMS320C6457 Data Manual

TMS320C6457

Communications Infrastructure Digital Signal Processor

Data Manual

PRODUCT ION DATA infor mation is current as of p ublication dat e.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS582B

July 2010

TMS320C6457

Data Manual

SPRS582B—July 2010

Release History

Additions/Modifications/Deletions

SPRS582B • Added 850 mHz clock speed.

• Added content to the Warm Reset section describing how to preserve contents of DDR2 SDRAM through a Warm Reset
cycle with Self-Refresh mode enabled on the SDRAM.

• Corrected typo in the Reset Timing Requirements table, parameter number 2: changed RESET

• Corrected 1.2-V to 1.1-V in last item of Features bullet list.

SPRS582A • Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times

• Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK

• Corrected PLL2 block diagram to include correct reference to PLLV

• Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table

• Removed PLLOUT term from the PLL2 Clock Frequency ranges table

• Clarified wording in the introduction of the PLL2 section and on the effective x5 multiplier that generates
DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) from DDRREFCLK(P|N) or ALTDDRCLK

• Added Table 7-4 Power Supply to Peripheral I/O Mapping to clarify the exact I/O and reference clock buffers each power
supply provides power for

• Added Overshoot/Undershoot definition to Table 6-1 Absolute Maximum Ratings

• Fixed typo in Table 2-1 under the 1.2 GHz space, “1.2 V, 1.8 V, and 3.3 V” now correctly reads “1.1 V, 1.8 V, and 3.3 V”

• Fixed typo for the McBSP timing parameters. “P = 1/CORECLK” now correctly reads “P = 1/SYSREFCLK”

• Fixed typo in 7.3.1 Power-Supply Sequencing - The SPRAAG5 reference now correctly references SPRAAV7

SPRS582 • Initial version

voltage net

2

x to RESET and POR to POR.

www.ti.com

2 Release History 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

Contents

1 TMS320C6457 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 TMS320C6457CMH/GMH BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2 CPU (DSP Core) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.5 Boot Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.5.1 Second-Level Bootloaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.6.1 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.7 Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.9 Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.4 Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.5 JTAG ID (JTAGID) Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.6 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4 System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.1 Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.2 Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.3 Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.4 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5 C64x+ Megamodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

5.1.4 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.5 Megamodule Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.6 Megamodule Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.7 C64x+ Megamodule Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

7 C64x+ Peripheral Information and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.1.2 3.3-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.1.3 3.3-V Signal Transition Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.1.4 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.3.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

2009 Texas Instruments Incorporated Contents 3

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

7.3.2 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.3.3 Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.4 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

7.4.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.4.2 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.4.3 EDMA3 Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

7.5.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

7.5.2 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.6 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.6.1 Power-on Reset (POR

7.6.2 Warm Reset (RESET Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.6.3 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.6.4 CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.7 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.7 PLL1 and PLL1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.7.1 PLL1 Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.7.2 PLL1 Controller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

7.7.3 PLL1 Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.7.4 PLL1 Controller Input and Output Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.8 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.8.1 PLL2 Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.8.2 PLL2 Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.9 DDR2 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.9.1 DDR2 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.9.2 DDR2 Memory Controller Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.9.3 DDR2 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10 External Memory Interface A (EMIFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10.1 EMIFA Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.10.2 EMIFA Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.10.3 EMIFA Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

2

7.11 I

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.11.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.11.2 I

2

C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.11.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.12 Host-Port Interface (HPI) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.1 HPI Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.2 HPI Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.12.3 HPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.13 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.13.1 McBSP Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.13.2 McBSP Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

7.14 Ethernet MAC (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.14.1 EMAC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.14.2 EMAC Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.14.3 EMAC Electrical Data/Timing (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15.1 MDIO Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.15.2 MDIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.16 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.16.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.16.2 Timers Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.16.3 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.17 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.17.1 VCP2 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.17.2 VCP2 Peripheral Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.18 Enhanced Turbo Decoder Coprocessor (TCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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4Contents 2009 Texas Instruments Incorporated

TMS320C6457

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7.18.1 TCP2 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.19 UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.1 UTOPIA Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.2 UTOPIA Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.19.3 UTOPIA Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.20 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.20.1 Serial RapidIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.20.2 Serial RapidIO Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

7.20.3 Serial RapidIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.2 GPIO Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.21.3 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.22.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.22.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.3 Package CMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

8.4 Package GMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

SPRS582B—July 2010

2009 Texas Instruments Incorporated Contents 5

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

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List of Figures

Figure 1-1 CMH/GMH 688-Pin Ball Grid Array (BGA) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 1-2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 2-1 TMS320C64x+ CPU (DSP Core) Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 2-2 TMS320C6457 Pin Map (Bottom View) [Quadrant A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 2-3 TMS320C6457 Pin Map (Bottom View) [Quadrant B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 2-4 TMS320C6457 Pin Map (Bottom View) [Quadrant C] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 2-5 TMS320C6457 Pin Map (Bottom View) [Quadrant D] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 2-6 CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 2-7 Timers/GPIO/RapidIO Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 2-8 EMIFA and DDR2 Memory Controller Peripheral Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 2-9 HPI/McBSP/I

Figure 2-10 EMAC/MDIO (SGMII) Peripheral Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-11 UTOPIA Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 2-12 TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6457 DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 4-1 Data Switched Central Resource Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 4-2 Configuration Switched Central Resource (SCR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 5-1 64x+ Megamodule Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 5-2 TMS320C6457 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 5-3 TMS320C6457 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 5-4 TMS320C6457 L2 Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 7-1 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-2 Input and Output Voltage Reference Levels for 1.8-V AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 7-4 Input and Output Voltage Reference Levels for 3.3-V AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 7-5 Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 7-6 Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 7-7 Power-Supply Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 7-8 NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Figure 7-9 Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Figure 7-10 Warm Reset Timing — RESETSTAT
Figure 7-11 Warm Reset Timing — Setup Time Between POR

Figure 7-12 PLL1 and PLL1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Figure 7-13 CORECLK(N|P) and ALTCORECLK Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-14 PLL2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-15 DDRREFCLK(N|P) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 7-16 EMIFA AECLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-17 EMIFA AECLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-18 EMIFA Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Figure 7-19 EMIFA Asynchronous Memory Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 7-20 EMIFA EM_Wait Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 7-21 EMIFA EM_Wait Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Figure 7-22 EMIFA Programmable Synchronous Interface Read Timing (With Read Latency = 2)
Figure 7-23 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 0)
Figure 7-24 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 1)
Figure 7-25 I
Figure 7-26 I
Figure 7-27 I

2

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

2

C Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

2

C Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Figure 7-28 HPI16 Read Timing (HAS
Figure 7-29 HPI16 Read Timing (HAS
Figure 7-30 HPI16 Write Timing (HAS
Figure 7-31 HPI16 Write Timing (HAS
Figure 7-32 HPI32 Read Timing (HAS

2

C Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Relative to RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

De-Asserted and RESET Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Used). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

6List of Figures 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Figure 7-33 HPI32 Read Timing (HAS Used). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Figure 7-34 HPI32 Write Timing (HAS
Figure 7-35 HPI32 Write Timing (HAS

Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Figure 7-36 McBSP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 7-37 FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 7-38 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 7-39 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Figure 7-40 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Figure 7-41 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Figure 7-42 EMAC, MDIO, and EMAC Control Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Figure 7-43 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Figure 7-44 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Figure 7-45 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 7-46 UXCLK Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-47 URCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-48 UTOPIA Slave Transmit Timing
Figure 7-49 UTOPIA Slave Receive Timing

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

(A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 7-50 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-51 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-52 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-53 HS-RTDX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Figure 8-1 CMH (S–PBGA–N688) Pb-Free Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 8-2 GMH (S–PBGA–N688) Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

SPRS582B—July 2010

2009 Texas Instruments Incorporated List of Figures 7

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

www.ti.com

List of Tables

Table 2-1 Characteristics of the C6457 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 2-2 TMS320C6457 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 2-3 TMS320C6457 Supported Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 2-4 Serial RapidIO (SRIO) Supported Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 2-5 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-7 Relevant Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 3-1 TMS320C6457 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 3-3 Device Configuration Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-4 Device Configuration Status Register (DEVSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-5 Device Configuration Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 3-6 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 3-7 JTAG ID (JTAGID) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 4-1 SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-2 TMS320C6457 Default Bus Master Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-3 Priority Allocation Register (PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-4 Priority Allocation Register (PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 5-1 Available Memory Page Protection Scheme With Privilege ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 5-2 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 5-3 Megamodule Reset (Global or Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-4 Megamodule Revision ID Register (MM_REVID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-5 Megamodule Revision ID Register (MM_REVID) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-6 Megamodule Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-7 Megamodule Powerdown Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-8 Megamodule Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-9 Megamodule IDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-10 Megamodule Cache Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-11 Megamodule Error Detection Correct Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 5-12 Megamodule L1/L2 Memory Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 5-13 CPU Megamodule Bandwidth Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 6-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 6-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 6-4 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 7-1 Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 7-2 Timing Requirements for Power-Supply Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 7-3 C6457 EDMA3 Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 7-4 EDMA3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Table 7-5 EDMA3 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-6 EDMA3 Transfer Controller 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-7 EDMA3 Transfer Controller 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7-8 EDMA3 Transfer Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table 7-9 EDMA3 Transfer Controller 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 7-10 EDMA3 Transfer Controller 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 7-11 EDMA3 Transfer Controller 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Table 7-12 TMS320C6457 System Event Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Table 7-13 Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 7-14 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 7-15 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-16 Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-17 Software Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

8List of Tables 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 7-18 Software Reset Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-19 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-20 Reset Configuration Register (RSTCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-21 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-22 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-23 Warm Reset Switching Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 7-24 Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-25 PLL1 Stabilization, Lock, and Reset Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-26 PLL1 Controller Registers (Including Reset Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Table 7-27 PLL1 Control Register (PLLCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-28 PLL1 Control Register (PLLCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-29 PLL Multiplier Control Register (PLLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-30 PLL Multiplier Control Register (PLLM) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-31 PLL Post-Divider Control Register (POSTDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-32 PLL Post-Divider Control Register (POSTDIV) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-33 PLL Controller Divider 3 Register (PLLDIV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-34 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-35 PLL Controller Divider 6 Register (PLLDIV6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-36 PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-37 PLL Controller Divider 7 Register (PLLDIV7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-38 PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-39 PLL Controller Divider 8 Register (PLLDIV8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-40 PLL Controller Divider 8 Register (PLLDIV8) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-41 PLL Controller Command Register (PLLCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-42 PLL Controller Command Register (PLLCMD) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-43 PLL Controller Status Register (PLLSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-44 PLL Controller Status Register (PLLSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-45 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-46 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-47 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-48 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 7-49 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-50 SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-51 CORECLK(N|P) and ALTCORECLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 7-52 PLL2 Clock Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-53 Timing Requirements for DDRREFCLK(N|P) and ALTDDRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-54 DDR2 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Table 7-55 EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Table 7-56 EMIFA AECLKIN Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-57 EMIFA AECLKOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-58 EMIFA Asynchronous Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-59 EMIFA Asynchronous Memory Read Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 7-60 EMIFA Asynchronous Memory Write Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 7-61 EMIFA EM_Wait Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-62 EMIFA EM_Wait Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-63 EMIFA EM_Wait Write Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-64 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-65 Switching Characteristics for Programmable Synchronous Interface Cycles for EMIFA Module. . . . . . . . . . . . . . . . . . . . . .152

Table 7-66 I
Table 7-67 I
Table 7-68 I

2

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

2

C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

2

C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Table 7-69 HPIWIDTH Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 7-70 HPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 7-71 Host-Port Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

SPRS582B—July 2010

2009 Texas Instruments Incorporated List of Tables 9

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 7-72 Host-Port Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 7-73 McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 7-74 McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-75 McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-76 Switching Characteristics for McBSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 7-77 Timing Requirements for FSR When GSYNC = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Table 7-78 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Table 7-79 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Table 7-80 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-81 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-82 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-83 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-84 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 7-85 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Table 7-86 Ethernet MAC (EMAC) Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Table 7-87 EMAC Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 7-88 EMAC Descriptor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-89 SGMII Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-90 EMIC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Table 7-91 MDIO Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Table 7-92 MDIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-93 MDIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-94 Timer1 Watchdog Reset Selection Register (WDRSTSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-95 Timer1 Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-96 Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Table 7-97 Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-98 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-99 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-100 VCP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Table 7-101 TCP2_A Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-102 TCP2_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-103 UTOPIA Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-104 UTOPIA Data Queues (Receive and Transmit) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-105 UXCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-106 URCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-107 UTOPIA Slave Transmit Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-108 UTOPIA Slave Transmit Cycles Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-109 UTOPIA Slave Receive Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-110 Switching Characteristics for UTOPIA Slave Receive Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-111 RapidIO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Table 7-112 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Table 7-113 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-114 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-115 Switching Characteristics for Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Table 7-116 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-117 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-118 Timing Requirements for HS-RTDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-119 Switching Characteristics for HS-RTDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 8-1 Thermal Resistance Characteristics (PBGA Package) [CMH/GMH] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

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10 List of Tables 2009 Texas Instruments Incorporated

www.ti.com

1 TMS320C6457 Features

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

• High-Performance Fixed-Point DSP (C6457)
– 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time
– 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 8000 and 9600 MIPS/MMACS (16-Bits)
– Case Temperature

›Commercial:

» 0ºC to 100ºC (850 MHz)
» 0ºC to 100ºC (1 GHz)
» 0ºC to 95ºC (1.2 GHz)

› Extended:

» -40ºC to 100ºC (1 GHz)
» -40ºC to 95ºC (1.2 GHz)

• TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling

• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:

– 256K-Bit (32K-Byte) L1P Program Cache [Direct

Mapped]

– 256K-Bit (32K-Byte) L1D Data Cache [2-Way

Set-Associative]

– 16M-Bit (2048K-Byte) L2 Unified Mapped

Ram/Cache [Flexible Allocation]

› Configurable up to 1MB of L2 Cache
– 512K-Bit (64K-Byte) L3 ROM
– Time Stamp Counter

•Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters

• Two Enhanced Turbo Decoder Coprocessors
(TCP2_A and TCP2_B)

– Each TCP2 Supports up to Eight 2-Mbps 3GPP

(6 Iterations)

– Programmable Turbo Code and Decoding

Parameters

• Endianess: Little Endian, Big Endian

• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous Memories

(SRAM, Flash, and EEPROM) and Synchronous
Memories (SBSRAM, ZBT SRAM)

– Supports Interface to Standard Sync Devices and

Custom Logic (FPGA, CPLD, ASICs, etc.)

– 32M-Byte Total Addressable External Memory

Space

• 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)

• Four 1× Serial RapidIO® Links (or One 4×), v1.3
Compliant

– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing, DirectIO Support, Error Mgmt

Extensions, Congestion Control

– IEEE 1149.6 Compliant I/Os

• EDMA3 Controller (64 Independent Channels)

•32-/16-Bit Host-Port Interface (HPI)

• Two 1.8-V McBSPs

• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
–Supports SGMII, v1.8 Compliant
– 8 Independent Transmit (TX) and 8 Independent

Receive (RX) Channels

• Two 64-Bit General-Purpose Timers
– Configurable as Four 32-Bit Timers
– Configurable in a Watchdog Timer Mode

•UTOPIA
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up to

50 MHz per Direction

– User-Defined Cell Format up to 64 Bytes

• One 1.8-V Inter-Integrated Circuit (I2C) Bus

• 16 General-Purpose I/O (GPIO) Pins

• System PLL and PLL Controller

• DDR PLL, Dedicated to DDR2 Memory Controller

• Advanced Event Triggering (AET) Compatible

• Trace-Enabled Device

• Supports IP Security

• IEEE-1149.1 and IEEE-1149.6 (JTAG™)
Boundary-Scan-Compatible

• 688-Pin Ball Grid Array (BGA) Package (CMH or GMH
Suffix), 0.8-mm Ball Pitch

• 0.065-μm/7-Level Cu Metal Process (CMOS)

• 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal

PRODUCT PREVIEW

2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

1.1 TMS320C6457CMH/GMH BGA Package (Bottom View)

Figure 1-1 CMH/GMH 688-Pin Ball Grid Array (BGA) Package

AH

AF

AD

AB

Y

V

T

PRODUCT PREVIEW

P

M

K

H

F

D

B

CMH/GMH 688-PIN BALL GRID ARRAY (BGA) PACKAGE

AG

AE

AC

AA

W

U

R

N

L

J

G

E

C

A

1345678910111213141516171819202122232425

2

(BOTTOM VIEW)

26

27

28

www.ti.com

(A) The CMH mechanical package designator represents the version of the GMH package with lead-free balls. For more detailed information, see ‘‘Mechanical Data’’ on

page 209 of this document.

1.2 Description

The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP
generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSPs an excellent choice for applications including video and telecom
infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible
from previous devices that are part of the C6000™ DSP platform.

Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or
9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to
high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed
controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000
devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply
throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock
cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this
means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one
32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.

The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system
performance and reduces system cost for applications that include multiple DSPs on a board, such as video and
telecom infrastructures and medical/imaging.

12 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1
(L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped
RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped
cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program
and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some
combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral
configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control,
interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

2

The peripheral set includes: an inter-integrated circuit bus module (I
(McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave
[UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a
user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port
(GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller
(EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a
management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO
addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA),
which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.

The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor
(VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps
adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and
9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions.
Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels
(assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all
polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully
programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and
stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out
through the EDMA3 controller.

C); two multichannel buffered serial ports

SPRS582B—July 2010

PRODUCT PREVIEW

The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code
execution.

2009 Texas Instruments Incorporated 13

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

1.3 Functional Block Diagram

Figure 1-2 Shows the functional block diagram of the TMS320C6457 device.

Figure 1-2 Functional Block Diagram

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DDR2 SDRAM

I/O Devices

32

64

DDR2

Mem Ctlr

PLL2

EMIFA

TCP2_A

PRODUCT PREVIEW

TCP2_B

VCP2

McBSP0

McBSP1

Serial Rapid

I/O

HPI (32/16)

UTOPIA

EMAC

10/100/1000

SGMII

MDIO

Primary Switched Central Resource

L2

Cache

Memory

2048K

Bytes

L1P SRAM/Cache Direct-Mapped

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

Instruction Fetch

16-/32-bit

Instruction Dispatch

Instruction
M
e
g
a
m
o
d
u

l

e

Decode

Data Path A

A Register File

A31−A16

A15−A0

.L1 .S1

.M1

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

C64x+ DSP Core

.D1 .D2

xx
xx

32K Bytes

Control Registers

SPLOOP Buffer

In-Circuit Emulation

Data Path B

B Register File

B31−B16

B15−B0

.M2

xx
xx

.S2 .L2

C6457

Power Control

System

Interrupt and Exception Controller

(Memory Protect/

Bandwidth Mgmt)

L2 Memory Controller

(IDMA)

Internal DMA

16

GPIO16

I2C

Timer1

HI

LO

Timer0

HI

LO

L1D SRAM/Cache

2-Way

Set-Associative

(A)

EDMA 3.0

L3 ROM

(A)

Secondary

Switched Central

Resource

32K Bytes Total

PLL1 and

PLL1

Controller

Boot Configuration

Device

Configuration

Logic

(A) Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either one 64-bit general-purpose timer or two 32-bit general-purpose timers or a watchdog timer.

14 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320C6457 DSP. The table shows significant features of the C6457 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package and pin count.

2.2 CPU (DSP Core) Description

Table 2-1 Characteristics of the C6457 Processor (Part 1 of 2)

HARDWARE FEATURES TMS320C6457

EMIFA (64-bit bus width) (clock source = AECLKIN or SYSCLK7) 1

DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock source = DDRREFCLKN|P)

EDMA3 (64 independent channels) [CPU/3 clock rate] 1

High-speed 1×/4× Serial RapidIO Port (4 lanes) 1

2

C 1

I

Peripherals

Decoder
Coprocessors

On-Chip Memory

C64x+ Megamodule
Revision ID

JTAG BSDL_ID JTAGID register (address location: 0288 0818h)

Frequency MHz 850, 1000 (1 GHz), and 1200 (1.2 GHz)

Cycle Time ns 1.18 ns, 1 ns, and 0.83 ns (0.85, 1.0, & 1.2-GHz CPU)

Voltage

PLL1 and PLL1
Controller Options

PLL2 DDR2 Clock ×10

BGA Package 23 mm × 23 mm 688-Pin Flip-Chip Plastic BGA (CMH/GMH)

Process Technology μm 0.065 μm

HPI (32-or 16-bit user selectable) 1 (HPI16 or HPI32)

McBSPs (internal or external clock source up to 100 Mbps) 2

UTOPIA (8-bit mode, 50-MHz, slave-only) 1

10/100/1000 Ethernet MAC (EMAC) 1

Management Data Input/Output (MDIO) 1

64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) 2 64-bit or 4 32-bit

General-Purpose Input/Output Port (GPIO) 16

VCP2 (clock source = CPU/3 clock frequency) 1

TCP2 (clock source = CPU/3 clock frequency) 2

Size (Bytes) 2176K

Organization

Megamodule Revision ID Register (address location: 0181 2000h)

850-MHz CPU 1.1 V

Core (V)

I/O (V)

CLKIN1 frequency multiplier Bypass (×1), (×4 to ×32)

1-GHz CPU 1.1 V

1.2-GHz CPU 1.2 V

850-MHz CPU 1.1 V, 1.8 V, and 3.3 V

1-GHz CPU 1.1 V, 1.8 V, and 3.3 V

1.2-GHz CPU 1.1 V, 1.8 V, and 3.3 V

1

32KB L1 Program Memory Controller [SRAM/Cache]
32KB L1 Data Memory Controller [SRAM/Cache]
2048KB L2 Unified Memory/Cache 64KB L3 ROM

See Section 5.6 ‘‘Megamodule Revision’’ on
page 77

See Section 3.5 ‘‘JTAG ID (JTAGID) Register

Description’’ on page 62

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 15

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-1 Characteristics of the C6457 Processor (Part 2 of 2)

HARDWARE FEATURES TMS320C6457

Product Status Production Data (PD) PD

Device Part
Numbers

End of Table 2-1

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths
as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total
of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types
supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than
32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an

PRODUCT PREVIEW

even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

(For more details on the C64x+™ DSP part numbering, see Figure 2-12)

www.ti.com

TMS320C6457CMH/GMH

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 × 32 bit multiply, two 16 × 16 bit
multiplies, two 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four
16 × 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois
field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit
real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one
32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 × 32 bit multiply instructions
provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and
unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of
common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual
16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances
the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the
.L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that
do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained
high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for
parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP — A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with
software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions — The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can
restrict the code to use certain registers in the register file. This compression is performed by the code
generation tools.

• Instruction Set Enhancements — As noted above, there are new instructions such as 32-bit multiplications,
complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

16 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

• Exception Handling — Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect
and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system
events (such as a watchdog time expiration).

• Privilege — Defines user and supervisor modes of operation, allowing the operating system to give a basic level
of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and
execute permissions.

• Time-Stamp Counter — Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU, which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)

• TMS320C64x+ Megamodule Reference Guide (literature number SPRU871)

• TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84)

SPRS582B—July 2010

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 17

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-1 shows the DSP core functional units and data paths.

Figure 2-1 TMS320C64x+ CPU (DSP Core) Data Paths

www.ti.com

PRODUCT PREVIEW

Data path A

ST1b

ST1a

LD1b

LD1a

LD2a
LD2b

32 MSB

32 LSB

32 MSB

32 LSB

DA1

DA2

32 LSB

32 MSB

.L1

.S1

.M1

.D1

.D2

.M2

src1

src2

odd dst

even dst

long src

long src

even dst

odd dst

src1

src2

dst2
dst1
src1

src2

src1

src2

src2

src1

src2

src1
dst2

dst1

dst

dst

Odd

register

file A

(A1, A3,

A5...A31)

(D)

8

8

(D)

32

32

32

32

(A)
(B)

(C)

2x

1x

(C)

(B)

(A)

Odd

register

file B

(B1, B3,

B5...B31)

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

src2

src1

.S2

.L2

odd dst

even dst

long src

long src

even dst

odd dst

src2

src1

8

8

Data path B

32 MSB

ST2a

32 LSB

ST2b

(A) On .M unit, dst2 is 32 MSB. ____(B) On .M unit, dst1 is 32 LSB. ____(C) On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.

(D) On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

(D)

(D)

Control Register

18 Device Overview 2009 Texas Instruments Incorporated

TMS320C6457

Communications Infrastructure Digital Signal Processor

www.ti.com

SPRS582B—July 2010

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the TMS320C6457 device. The external memory configuration

register address ranges in the C6457 device begin at the hex address location 0x7000 0000 for EMIFA and hex
address location 0x7800 0000 for DDR2 Memory Controller.

Table 2-2 TMS320C6457 Memory Map Summary (Part 1 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 8M 0000 0000 - 007F FFFF

L2 SRAM 2M 0080 0000 - 009F FFFF

Reserved 4M 00A0 0000 - 00DF FFFF

L1P SRAM 32K 00E0 0000 - 00E0 7FFF

Reserved 1M - 32K 00E0 8000 - 00EF FFFF

L1D SRAM 32K 00F0 0000 - 00F0 7FFF

Reserved 1M -32K 00F0 8000 - 00FF FFFF

Reserved 8M 0100 0000 - 017F FFFF

C64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFF

Reserved 12.5M 01C0 0000 - 0287 FFFF

HPI Control Registers 256 0288 0000 - 0288 00FF

Reserved 2K - 256 0288 0100 - 0288 07FF

Chip-Level Registers 1K 0288 0800 - 0288 0BFF

Reserved 253K 0288 0C00 - 028B FFFF

McBSP 0 Registers 256 028C 0000 - 028C 00FF

Reserved 256K - 256 028C 0100 - 028F FFFF

McBSP 1 Registers 256 0290 0000 - 0290 00FF

Reserved 256K - 256 0290 0100 - 0293 FFFF

Timer 0 Registers 128 0294 0000 - 0294 007F

Reserved 256K - 128 0294 0080 - 0297 FFFF

Timer 1 Registers 128 0298 0000 - 0298 007F

Reserved 128K - 128 0298 0080 - 0299 FFFF

PLL Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FF

Reserved 384K - 512 029A 0200 - 029F FFFF

EDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFF

Reserved 96K 02A0 8000 - 02A1 FFFF

EDMA3 Transfer Controller 0 Registers 1K 02A2 0000 - 02A2 03FF

Reserved 31K 02A2 0400 - 02A2 7FFF

EDMA3 Transfer Controller 1 Registers 1K 02A2 8000 - 02A2 83FF

Reserved 31K 02A2 8400 - 02A2 FFFF

EDMA3 Transfer Controller 2 Registers 1K 02A3 0000 - 02A3 03FF

Reserved 31K 02A3 0400 - 02A3 7FFF

EDMA3 Transfer Controller 3 Registers 1K 02A3 8000 - 02A3 83FF

Reserved 31K 02A3 8400 - 02A3 FFFF

EDMA3 Transfer Controller 4 Registers 1K 02A4 0000 - 02A4 03FF

Reserved 31K 02A4 0400 - 02A4 7FFF

EDMA3 Transfer Controller 5 Registers 1K 02A4 8000 - 02A4 83FF

Reserved 479K 02A4 8400 - 02AB FFFF

Power / Sleep Controller (PSC) 4K 02AC 0000 - 02AC 0FFF

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 19

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Table 2-2 TMS320C6457 Memory Map Summary (Part 2 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 60K 02AC 1000 - 02AC FFFF

Embedded Trace Buffer (ETB) 8K 02AD 0000 - 02AD 1FFF

Reserved 184K 02AD 2000 - 02AF FFFF

GPIO Registers 256 02B0 0000 - 02B0 00FF

Reserved 16K - 256 02B0 0100 - 02B0 3FFF

I2C Data and Control Registers 128 02B0 4000 - 02B0 407F

Reserved 240K - 128 02B0 4080 - 02B3 FFFF

UTOPIA Control Registers 512 02B4 0000 - 02B4 01FF

Reserved 256K - 512 02B4 0200 - 02B7 FFFF

PRODUCT PREVIEW

VCP2 Control Registers 256 02B8 0000 - 02B8 00FF

Reserved 128K - 256 02B8 0100 - 02B9 FFFF

TCP2_A Control Registers 256 02BA 0000 - 02BA 00FF

TCP2_B Control Registers 256 02BA 0100 - 02BA 01FF

Reserved 640K - 512 02BA 0200 - 02C3 FFFF

SGMII Control 256 02C4 0000 - 02C4 00FF

Reserved 256K - 256 02C4 0100 - 02C7 FFFF

EMAC Control 2K 02C8 0000 - 02C8 07FF

Reserved 2K 02C8 0800 - 02C8 0FFF

EMAC Interrupt Controller 256 02C8 1000 - 02C8 10FF

Reserved 2K - 256 02C8 1100 - 02C8 17FF

MDIO Control Registers 256 02C8 1800 - 02C8 18FF

Reserved 2K - 256 02C8 1900 - 02C8 1FFF

EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF

Reserved 496K 02C8 4000 - 02CF FFFF

RapidIO Control Registers 132K 02D0 0000 - 02D2 0FFF

Reserved 892K 02D2 1000 - 02DF FFFF

RapidIO Descriptor Memory 16K 02E0 0000 - 02E0 3FFF

Reserved 1M - 16K 02E0 4000 - 02EF FFFF

Reserved 1M 02F0 0000 - 02FF FFFF

Reserved 208M 0300 0000 - 0FFF FFFF

Reserved 512M 1000 0000 - 2FFF FFFF

McBSP 0 Data 256 3000 0000 - 3000 00FF

Reserved 64M - 256 3000 0100 - 33FF FFFF

McBSP 1 Data 256 3400 0000 - 3400 00FF

Reserved 128M - 256 3400 0100 - 3BFF FFFF

L3 ROM 64K 3C00 0000 - 3C00 FFFF

Reserved 16M - 64K 3C01 0000 - 3CFF FFFF

UTOPIA Receive (RX) Data 128 3D00 0000 - 3D00 007F

Reserved 896 3D00 0080 - 3D00 03FF

UTOPIA Transmit (TX) Data 128 3D00 0400 - 3D00 047F

Reserved 304M - 1152 3D00 0480 - 4FFF FFFF

TCP2_A Data 1M 5000 0000 - 500F FFFF

TCP2_B Data 1M 5010 0000 - 501F FFFF

Reserved 126M 5020 0000 - 57FF FFFF

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20 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Table 2-2 TMS320C6457 Memory Map Summary (Part 3 of 3)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

VCP2 Data 64K 5800 0000 - 5800 FFFF

Reserved 384M - 64K 5801 0000 - 6FFF FFFF

EMIFA (EMIF64) Configuration Registers 256 7000 0000 - 7000 00FF

Reserved 128M - 256 7000 0100 - 77FF FFFF

DDR2 EMIF Configuration Registers 256 7800 0000 - 7800 00FF

Reserved 128M - 256 7800 0100 - 7FFF FFFF

Reserved 512M 8000 0000 - 9FFF FFFF

EMIFA CE2 Data -SBSRAM/Async 8M A000 0000 - A07F FFFF

Reserved 256M - 8M A080 0000 - AFFF FFFF

EMIFA CE3 Data -SBSRAM/Async 8M B000 0000 - B07F FFFF

Reserved 256M - 8M B080 0000 - BFFF FFFF

EMIFA CE4 Data -SBSRAM/Async 8M C000 0000 - C07F FFFF

Reserved 256M - 8M C080 0000 - CFFF FFFF

EMIFA CE5 Data -SBSRAM/Async 8M D000 0000 - D07F FFFF

Reserved 256M - 8M D080 0000 - DFFF FFFF

DDR2 EMIF CE0 Data 512M E000 0000 - FFFF FFFF

End of Table 2-2

TMS320C6457

SPRS582B—July 2010

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset, warm reset, and system reset. A local reset to an individual C64x+ Megamodule should
not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see
Section 7.6 ‘‘Reset Controller’’ on page 123.

The C6457 supports several boot processes begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software driven; using the
BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed.

2.5 Boot Modes Supported

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:

• Public ROM Boot - C64x+ Megamodule is released from reset and begins executing from the L3 ROM base
address. After performing the boot process (e.g., from I
Megamodule then begins execution from the L2 RAM base address.

• Secure ROM Boot - On secure devices, the C64x+ Megamodule is released from reset and begin executing
from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C64x+
Megamodule initiates the boot process. The C64x+ Megamodule performs any authentication and decryption
required on the bootloaded image prior to beginning execution.

2

C ROM, Ethernet, or RapidIO), the C64x+

PRODUCT PREVIEW

2009 Texas Instruments Incorporated Device Overview 21

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

The boot process performed by the C64x+ Megamodule in public ROM boot and secure ROM boot are determined
by the BOOTMODE[3:0] value in the DEVSTAT register. The C64x+ Megamodule reads this value, and then
executes the associated boot process in software. Table 2-3 shows the supported boot modes.

Table 2-3 TMS320C6457 Supported Boot Modes

Mode Name Bootmode[3:0] Description

No Boot 0000b No Boot

2

C Master Boot A 0001b Slave I2C address is 0x50. The C64x+ Megamodule configures I2C, acts as a master to the I2C bus and

I

2

I

C Master Boot B 0010b Similar to I2C boot A except the slave I2C address is 0x51.

2

C Slave Boot 0011b The C64x+ Megamodule configures I2C and acts as a slave and will accept data and code section

I

PRODUCT PREVIEW

HPI Boot 0100b Host boot.

EMIFA Boot 0101b External memory boot from ACE3 space (0xB0000000 address).

EMAC Master Boot 0110b

EMAC Slave Boot 0111b

EMAC Forced-Mode Boot 1000b

Reserved 1001b Reserved

RapidIO Boot (Config 0) 1010b

RapidIO Boot (Config 1) 1011b

RapidIO Boot (Config 2) 1100b

RapidIO Boot (Config 3) 1101b

End of Table 2-3

www.ti.com

copies data from an I
table format. The destination address and length are contained within the boot table.

packets through the I2C interface. It is required that an I

TI Ethernet Boot. The C64x+ Megamodule configures EMAC and EDMA, if required, and brings the
code image into the internal on-chip memory via the protocol defined by the boot method (EMAC
bootloader).

The C64x+ Megamodule configures the SRIO and an external host loads the application via SRIO
peripheral, using directIO protocol. A doorbell interrupt is used to indicate that the code has been
loaded. For more details on the RapidIO configurations, see Table 2-4.

2

C EEPROM or a device acting as an I2C slave to the DSP using a predefined boot

2

C master is present in the system.

The C64x+ Megamodule configures Serial RapidIO, EMAC, and EDMA, if required, and brings the code image into
the internal on-chip memory via the protocol defined by the boot method (SRIO EMAC bootloader).

Table 2-4 Serial RapidIO (SRIO) Supported Boot Modes

SRIO Boot Mode SerDes Clock Link Rate SRIO Boot Configuration

Bootmode 10 - Config 0 125 MHz 1.25 Gbps Four 1× SRIO links

Bootmode 11 - Config 1 125 MHz 3.125 Gbps One 4× SRIO link

Bootmode 12 - Config 2 156.25 MHz 1.25 Gbps One 4× SRIO link

Bootmode 13 - Config 3 156.25 MHz 3.125 Gbps One 4× SRIO link

End of Table 2-4

All the other BOOTMODE[3:0] modes are reserved.

2.5.1 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.

22 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

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2.6 Pin Assignments

2.6.1 Pin Map

Figure 2-2 through Figure 2-5 show the C6457 pin assignments in four quadrants (A, B, C, and D).

Figure 2-2 TMS320C6457 Pin Map (Bottom View) [Quadrant A]

1

432

65

10987

1211

13

TMS320C6457

SPRS582B—July 2010

14

V

AH CORECLKP

DDS18_1

V

AG

TDO

AF

EMU12

AE

EMU15

AD

EMU14 EMU18 RSV01

AC

TDI

AB

EMU17

AA

Y

CLKS1

HD11 DR1

W

SS

V

SS

EMU7

EMU11

TRST

V

SS

V

RSV02

V

SS

TMS CLKR1DX1

HD00

EMU8

EMU13

EMU10

EMU16

DDS18_1

CLKX0

CLKX1

EMU4

EMU5

EMU6

EMU3

EMU9

RSV03

CLKS0

FSX0

EMU2

V

DDS18_1

V

EMU1

EMU0

V

DDA18V1

RSV12

RSV13

CLKR0

FSX1

SS

RIOSGMII

CLKN

ALTCORE

CLK

CORE

CLKSEL

RSV24

RSV20 RSV21

V

SS

V

DDS18_1

DR0

DX0

CORECLKN RIOTXN1

RIOSGMII

CLKP

RSV09

RSV08

SYSCLK

OUT

V

DDS18_1

V

V

DDS18_1

V

V

SS

RIORXN0

RIOTXP0

SS

SS

V

DDS18_1

RIORXP0

V

V

DDT

SS

RIOTXN0

V

V

V

DDT

SS

V

SS

V

SS

SS

RIOTXP1

V

SS

RIORXP1

V

DDR4

V

SS

V

DDA

V

SS

V

SS

V

SS

V

DDT

RIORXN1

V

SS

V

DDT

V

SS

V

SS

V

DDD

RIORXN1TCLK

RSV16

RIORXP1

V

RIOTXN3

SS

RIOTXN2

SGMIITXP

RIOTXP314AG

RIOTXP2

RIORXN3RIORXP3

V

V

V

V

SS

DDA

SS

DDT

V

SS

V

SS

AH

AF

V

AE

SS

V

AD

SS

V

AC

DDA

V

AB

SS

AA

PRODUCT PREVIEW

Y

V

V

SS

V

DDD

W

SS

HD22

V

U

HD21 HD27 HD23

HD19 HD15

T

HD17

R R

HD25

HD13

V

DDS33

V

FSR0

HD05

SS

HD09

V

V

SS

DDS33

FSR1

HD29HD03

HD10HD07

V

DDS18_1

HD06

HD04

V

SS

V

DDS33

V

SS

V

DDS33

V

V

RSV23

RSV23

V

DD

SS

V

SS

V

V

V

V

DD

V

SS

V

DD

V

V

DDD

SS

DD

SS

SS

V

DDD

V

SS

V

DD

V

DDD

V

U

SS

V

T

DD

V

SS

13121110987654321

2009 Texas Instruments Incorporated Device Overview 23

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-3 TMS320C6457 Pin Map (Bottom View) [Quadrant B]

15

181716

19

20

2221

www.ti.com

23

24

25

26

27

28

SGMIITXN

AH TINP0L

V

AG

V

AF

V

AE

PRODUCT PREVIEW

V

AD

V

AC

V

AB

V

V

SS

RSV17

SS

SGMIIRXN

DDT

V

SS

DDR3

V

DDT

SS

SS

SS

V

DDA

V

SS

DDT

V

SS

SGMIIRXP

V

SS

V

DDT

V

SS

V

SS

AA

Y

V

W

V

DDD

V

SS

DD

MDCLK

V

V

DDS18_2

V

V

DDS18_2

V

V

DDS18_2

V

MDIO

NMI

V

SS

DDS18_2

V

SS

V

DD

TOUT0LTINP1L

RSV14

RSV06

RSV04

V

SS

TOUT1L

SS

V

SS

SS

V

SS

DDS18_2

RSV18

RSV19

RSV07

RSV05

V

RSV15

DDS18_2

V

SS

RSV29

POR

RSV27

RSV26

V

DDS18_2

V

V

DDS33_1

V

V

DDS33_1

V

SS

SS

SS

RESET

RSV28

RESETSTAT

RSV22

V

SS

V

DDS33_1

V

SS

DDS33_1

V

SS

V

DDS33_1

V

AED03 AED16

V

AED00

AED24 AED28

ASDWE

ABE01

ARNW ACE2

AED05

DDS33_1

V

AED14

SS

AED09

AOEAED01

AED07

DDS33_1

AED11

AED26 V

AED23V

ABE00 AED27AED31

ACE3

V

AED06

AED02

AED20

AED18

AED15AED10

AED12 AED17

AED08

AED25

AED04

AED13

AED22

V

SS

DDS33_1

V

SS

AED30

AED19

AED21

V

DDS33_1

SS

AED29

ABE03

ABE02

ABE07

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

V

V

U

V

T

V

R R

V

SS

V

DD

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

V

DD

V

SS

V

DD

V

DD

SS

DD

SS

V

SS

DDMON

V

SS

V

DD

V

DDS33_1

V

DD33MON

V

DDS33_1

V

V

ABA1

SS

V

SS

V

AEA14

SS

V

SS

DDS33_1

AEA08

ABA0 ACE5

V

AEA00

SS

AEA01

AEA11 AEA02 AEA03 AEA06

AADS

AEA13

VSSAECLKOUT

ACE4

AEA04

AEA05

AHOLD

27262524232221201918171615

28

V

U

T

24 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Figure 2-4 TMS320C6457 Pin Map (Bottom View) [Quadrant C]

TMS320C6457

SPRS582B—July 2010

15

V

P

V

N

V

M

V

L

V

K

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

181716

V

SS

V

DD

V

SS

V

DD

V

SS

19

V

DD

V

SS

V

DD

V

SS

V

DD

20

SS

DD

SS

DD

SS

J

H

V

V

G

DDS18

V

F

V

V

DDS18

SS

DDS18

SS

DDRA00

V

V

DDS18

V

DDS18

SS

DDRRCVEN

V

SS

OUT1

V

V

DDS18

SS

V

2221

V

DDS33_1

V

V

DDS33_1

V

V

DDS33_1

V

V

DDS33_1

V

V

SS

23

V

V

DDS33_1

SS

V

V

DDS33_1

SS

V

V

DDS33_1

SS

V

V

SS

DD18MON

GP15

SS

24

AEA19

SS

AEA10

AEA17 AEA09

SS

AED33

SS

AED47

AED55 AED43

SS

AED63

SCL

25

AEA16

26

AEA15

AHOLDA

AEA18

ABUSREQ0

ABE06

AED46AED38 AED34AED32

AED45

AED44

AED54 V

AED36

V

SS

27

V

DDS33_1

AEA12AEA07

V

DDS33_1

ABE04

AED42

DDS33_1

AED48AED50

AED52AED56

28

V

SS

AECLKIN

V

SS

ABE05

AARDY

AED40

V

SS

AED35

AED37

P

N

M

L

K

J

H

G

F

PRODUCT PREVIEW

DDRODT

E

DDRA08

D

DDRA09

C

DDRA10 DDRA07 DDRD16

B

A

DDRA11

DDRA04

DDRA05

DDRA06

DDRA01

DDRA02

DDRA03

DDRCLK

OUT_N1

DDRCLK

OUT_P1

V

SS

DDRD19

DDRD18

DDRD17

DDRDQS2P

DDRDQS2N

DDRDQM2

V

DDS18

V

SS

DDRRCVEN

IN1

DDRD23

DDRD21

V

DDS18

DDRD27

DDRD26DDRD22

DDRD25

DDRD24DDRD20PTV18

DDRDQS3P

DDRDQS3N

DDRDQM3

V

DDS18

V

SS

V

DDS18

SDA

GP14 GP12

GP13

GP09

DDRD29 DDRD31

DDRD28 DDRD30

V

DDS33_1

AED57 AED53

AED59

V

DDS33_1

AED58 AED39

GP11 AED61 AED60 AED41

GP08

GP10 AED62 DDRSLRATE

AED49 AED51

V

DDS33_1

27262524232221201918171615

V

E

SS

D

C

V

B

SS

A

28

2009 Texas Instruments Incorporated Device Overview 25

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-5 TMS320C6457 Pin Map (Bottom View) [Quadrant D]

www.ti.com

HD14

HAS

432

HCNTL1

1

V

P

N

HD24

M

HD18

DDS33

HD20 HD12

V

SS

HD31

HD16HD26

HCS

PRODUCT PREVIEW

V

L

DDS33

URADDR4 URADDR3

K

URADDR2

J

V

H

DDS33

URDATA7

G

URDATA5

F

URADDR0 UXADDR0

URSOC

HHWIL

HDS1

UXADDR2 HD01

V

URADDR1

SS

HINT

URENB

UXADDR4 UXADDR1

UXDATA3 UXADDR3

UXDATA2

UXDATA7URDATA6

UXSOC

UXDATA1

HDS2

HR/W

RSV25

5

HD02

6

HD28

HD30HD08

HRDY

HCNTL0

RSV11

RSV10

DDRCLKSEL

GP05GP07

V

V

V

V

V

DDA18V2

V

DDS33

V

DDS33

V

DDS18

V

DDS18

87

SS

SS

SS

9

10

V

V

V

V

V

11

V

DD

V

SS

V

DD

V

SS

V

DD

12

V

SS

V

DD

V

SS

V

DD

V

SS

13

V

DD

V

SS

V

DD

V

SS

V

DD

14

V

SS

DD

SS

DD

SS

DD

P

V

N

SS

V

M

DD

V

L

SS

V

K

DD

J

V

V

DDS18

H

G

SS

F

SS

V

SS

DDRD11

V

DDS18

V

V

SS

V

SS

DDS18

V

DDS18

V

V

V

SS

DDS18

V

SS

DDS18

V

SS

E

D

C

B

URDATA3

URDATA1

URCLK

V

SS

V

DDS33

URDATA4

UXDATA0

URDATA2

URDATA0

URCLAV GP03

V

UXDATA4

SS

V

DDS33

UXCLAV

UXENB

UXDATA6

V

UXDATA5

UXCLK GP00

DDRREF

GP01

GP02

SS

GP06

ALTDDRCLK

GP04

DDRDQS1P

CLKN

DDRREF

DDRDQS1N

CLKP

DDRDQM1

DDRD14 DDRD12

DDRD10

DDRD09

DDRD08

V

DDRD13DDRD15

DDS18

V

SS

V

DDS18

DDRD07

DDRD06

DDRRCVEN

OUT0

DDRRCVEN

IN0

DDRDQS0P

DDRDQS0N

DDRDQM0

DDRD05

DDRD04

V

DDS18

DDRD03

DDRD02

V

DDS18

V

SS

DDRCAS

DDRRAS

DDRWE

DDRD01

DDRD00

DDRBA2

DDRCE

DDRCKE DDRBA1

V

DDRBA0

REFSSTL

DDRCLK

OUT_N0

DDRCLK

OUT_P0

DDRA13

DDRA12A

13121110987654321

14

E

D

C

B

A

26 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

2.7 Signal Groups Description

Figure 2-6 shows the CPU and core peripheral signal groups.

Figure 2-6 CPU and Peripheral Signals

CORECLKP

CORECLKN

ALTCORECLK

CORECLKSEL

SYSCLKOUT

AV

DD118

DDRREFCLKP

DDRREFCLKN

ALTDDRCLK
DDRCLKSEL

AV

DD218

TMS
TDO

TDI

TCK

TRST

EMU0

EMU1

•

•

•

EMU14
EMU15
EMU16
EMU17
EMU18

Clock/PLL1

and

PLL Controller

Clock/PLL2

IEEE Standard

1149.1

(JTAG)

Emulation

Reset and
Interrupts

Reserved

Peripheral

Enable/Disable

TMS320C6457

SPRS582B—July 2010

RESETSTAT
RESET
NMI
POR

RSV

PRODUCT PREVIEW

Control/Status

2009 Texas Instruments Incorporated Device Overview 27

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-7 shows the timer peripheral I/O, the general purpose I/O, the Serial RapidIO, and the general purpose I/O

reference clock, transmit, and receive signals.

Figure 2-7 Timers/GPIO/RapidIO Peripheral Signals

www.ti.com

TINPL1

TOUTL1

PRODUCT PREVIEW

GP[15]
GP[14]
GP[13]
GP[12]
GP[11]
GP[10]

GP[9]
GP[8]

RIOTXN0
RIOTXP0

RIOTXN1

RIOTXP1
RIOTXN2
RIOTXP2
RIOTXN3
RIOTXP3

RIORXN0
RIORXP0

RIORXN1
RIORXP1

RIORXN2
RIORXP2
RIORXN3
RIORXP3

Timer 1

GPIO

General-Purpose Input/Output (GPIO) Port

Transmit

Receive

RapidIO

Timer 0

Timers (64-Bit)

Clock

GP[7]
GP[6]
GP[5]
GP[4]

GP[3]
GP[2]
GP[1]
GP[0]

RIOSGMIICLKN

RIOSGMIICLKP

TOUTL0

TINPL0

(A)

(A)

(A) Reference clock to drive RapidIO and SGMII.

28 Device Overview 2009 Texas Instruments Incorporated

Communications Infrastructure Digital Signal Processor

www.ti.com

Figure 2-8 shows the EMIFA and DDR2 peripheral interfaces.

Figure 2-8 EMIFA and DDR2 Memory Controller Peripheral Signals

TMS320C6457

SPRS582B—July 2010

AED[63:0]

ACE5
ACE4
ACE3

ACE2

AEA[19:0]

ABE7
ABE6

ABE5

ABE4

ABE3
ABE2

ABE1
ABE0

ABA[1:0]

64

(A)

(A)

(A)

(A)

20

Data

Memory Map

Space Select

Address

Byte Enables

Bank Address

External

Memory I/F

Control

Bus

Arbitration

EMIFA (64-bit Data Bus)

AECLKIN

AECLKOUT

ASWE AAWE/
AARDY

AR/W

AAOE ASOE/
ASADS/ASRE

AHOLD

AHOLDA
ABUSREQ

PRODUCT PREVIEW

DDRD[31:0]

DDRCE

DDRA[13:0]

DDRDQM0

DDRDQM1
DDRDQM2

DDRDQM3

(A) The EMIFA ACE0 and ACE1 are not functionally supported on C6457 devices.

32

14

Data

Memory Map

Address

Byte Enables

DDR2 Memory Controller (32-bit Data Bus)

External

Memory

Controller

Bank Address

DDRCLKOUTP[1:0]
DDRCLKOUTN[1:0]

DDRCKE

DDRCAS
DDRRAS

DDRWE

DDRDQSP[3:0]
DDRDQSN[3:0]

DDRRCVENIN[2:0]
DDRRCVENOUT[2:0]
DDRODT
DDRSLRATE
V

REFSSTL

DDRBA0
DDRBA1
DDRBA2

2009 Texas Instruments Incorporated Device Overview 29

TMS320C6457

Communications Infrastructure Digital Signal Processor

SPRS582B—July 2010

Figure 2-9 shows the HPI, McBSP, and I2C peripheral signals.

Figure 2-9 HPI/McBSP/I2C Peripheral Signals

HD[15:0]

HD[31:16]

HCNTL0

HCNTL1

HHWIL

(HPI16 ONLY)

32

PRODUCT PREVIEW

Data

Register Select

Half-Word

Select

(A)

HPI

(Host-Port Interface)

Control

www.ti.com

HAS

HR/W
HCS

HDS1
HDS2
HRDY

HINT

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

McBSP1

Transmit

Receive

Clock

McBSPs

(Multichannel Buffered Serial Ports)

I2C

McBSP0

Transmit

Receive

Clock

CLKX0

FSX0
DX0

CLKR0
FSR0
DR0

CLKS0

SCL

SDA

(A) When the HPI is enabled, the number of HPI pins used depends on the HPI configuration (HPI16 or HPI32).

30 Device Overview 2009 Texas Instruments Incorporated