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Texas Instruments TMS320C6455 User Manual

TMS320C6455/C6454 DSP DDR2 Memory Controller

User's Guide
Literature Number: SPRU970G
December 2005–Revised June 2011
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SPRU970G–December 2005–Revised June 2011
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Contents
Preface ....................................................................................................................................... 7
1 Introduction ........................................................................................................................ 9
1.1 Purpose of the Peripheral .............................................................................................. 9
1.2 Features .................................................................................................................. 9
1.3 Functional Block Diagram .............................................................................................. 9
1.4 Industry Standard(s) Compliance Statement ....................................................................... 10
2 Peripheral Architecture ...................................................................................................... 11
2.1 Clock Control ........................................................................................................... 11
2.2 Memory Map ............................................................................................................ 11
2.3 Signal Descriptions .................................................................................................... 11
2.4 Protocol Description(s) ................................................................................................ 13
2.5 Memory Width, Byte Alignment, and Endianness ................................................................. 20
2.6 Address Mapping ...................................................................................................... 21
2.7 DDR2 Memory Controller Interface .................................................................................. 24
2.8 Refresh Scheduling .................................................................................................... 27
2.9 Self-Refresh Mode ..................................................................................................... 28
2.10 Reset Considerations .................................................................................................. 28
2.11 DDR2 SDRAM Memory Initialization ................................................................................ 28
2.12 Interrupt Support ....................................................................................................... 30
2.13 EDMA Event Support .................................................................................................. 30
2.14 Emulation Considerations ............................................................................................. 30
3 Using the DDR2 Memory Controller ..................................................................................... 31
3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM .................................................... 31
3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications .................... 35
4 DDR2 Memory Controller Registers ..................................................................................... 38
4.1 Module ID and Revision Register (MIDR) .......................................................................... 39
4.2 DDR2 Memory Controller Status Register (DMCSTAT) .......................................................... 40
4.3 SDRAM Configuration Register (SDCFG) .......................................................................... 41
4.4 SDRAM Refresh Control Register (SDRFC) ....................................................................... 43
4.5 SDRAM Timing 1 Register (SDTIM1) ............................................................................... 44
4.6 SDRAM Timing 2 Register (SDTIM2) ............................................................................... 46
4.7 Burst Priority Register (BPRIO) ...................................................................................... 47
4.8 DDR2 Memory Controller Control Register (DMCCTL) ........................................................... 48
Revision History ......................................................................................................................... 49

SPRU970G–December 2005–Revised June 2011 Table of Contents

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List of Figures
1 Device Block Diagram .................................................................................................... 10
2 DDR2 Memory Controller Signals....................................................................................... 12
3 DDR2 MRS and EMRS Command...................................................................................... 14
4 Refresh Command ........................................................................................................ 15
5 ACTV Command........................................................................................................... 16
6 DCAB Command .......................................................................................................... 17
7 DEAC Command .......................................................................................................... 18
8 DDR2 READ Command.................................................................................................. 19
9 DDR2 WRT Command ................................................................................................... 20
10 Byte Alignment............................................................................................................. 21
11 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM............................................... 22
12 Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM............................................... 22
13 Logical Address-to-DDR2 SDRAM Address Map..................................................................... 23
14 DDR2 SDRAM Column, Row, and Bank Access ..................................................................... 24
15 DDR2 Memory Controller FIFO Block Diagram ....................................................................... 25
16 Connecting to Two 16-Bit DDR2 SDRAM Devices ................................................................... 32
17 Connecting to a Single 16-Bit DDR2 SDRAM Device................................................................ 33
18 Connecting to Two 8-Bit DDR2 SDRAM Devices..................................................................... 34
19 Module ID and Revision Register (MIDR).............................................................................. 39
20 DDR2 Memory Controller Status Register (DMCSTAT).............................................................. 40
21 SDRAM Configuration Register (SDCFG) ............................................................................. 41
22 SDRAM Refresh Control Register (SDRFC)........................................................................... 43
23 SDRAM Timing 1 Register (SDTIM1)................................................................................... 44
24 SDRAM Timing 2 Register (SDTIM2)................................................................................... 46
25 Burst Priority Register (BPRIO).......................................................................................... 47
26 DDR2 Memory Controller Control Register (DMCCTL) .............................................................. 48
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List of Figures SPRU970G–December 2005–Revised June 2011
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1 DDR2 Memory Controller Signal Descriptions......................................................................... 12
2 DDR2 SDRAM Commands .............................................................................................. 13
3 Truth Table for DDR2 SDRAM Commands............................................................................ 13
4 Addressable Memory Ranges ........................................................................................... 20
5 Bank Configuration Register Fields for Address Mapping ........................................................... 21
6 DDR2 Memory Controller FIFO Description ........................................................................... 24
7 Refresh Urgency Levels.................................................................................................. 27
8 Device and DDR2 Memory Controller Reset Relationship........................................................... 28
9 DDR2 SDRAM Mode Register Configuration.......................................................................... 29
10 DDR2 SDRAM Extended Mode Register 1 Configuration ........................................................... 29
11 SDCFG Configuration..................................................................................................... 35
12 DDR2 Memory Refresh Specification .................................................................................. 36
13 SDRFC Configuration..................................................................................................... 36
14 SDTIM1 Configuration .................................................................................................... 36
15 SDTIM2 Configuration .................................................................................................... 37
16 DMCCTL Configuration................................................................................................... 37
17 DDR2 Memory Controller Registers .................................................................................... 38
18 Module ID and Revision Register (MIDR) Field Descriptions ....................................................... 39
19 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ....................................... 40
20 SDRAM Configuration Register (SDCFG) Field Descriptions ....................................................... 41
21 SDRAM Refresh Control Register (SDRFC) Field Descriptions .................................................... 43
22 SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................ 44
23 SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................ 46
24 Burst Priority Register (BPRIO) Field Descriptions ................................................................... 47
25 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions........................................ 48
List of Tables
SPRU970G–December 2005–Revised June 2011 List of Tables
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List of Tables SPRU970G–December 2005–Revised June 2011
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About This Manual
This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal processors (DSPs).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments

Preface

SPRU970G–December 2005–Revised June 2011
Read This First
The following documents describe the C6000™ devices and related support tools. Copies of these documents are available on the Internet. Tip: Enter the literature number in the search box provided at
www.ti.com. SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors (DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
SPRU970G–December 2005–Revised June 2011 Preface
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1 Introduction

1.1 Purpose of the Peripheral

The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage.

1.2 Features

The DDR2 memory controller supports the following features:
• JESD79-2B standard compliant DDR2 SDRAM
• 512M byte memory space
• Data bus width of 32 or 16 bits
• CAS latencies: 2, 3, 4, and 5
• Internal banks: 1, 2, 4, and 8
• Burst length: 8
• Burst type: sequential
• 1 CE signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM autoinitialization
• Self-refresh mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little endian and big endian transfers
User's Guide
SPRU970G–December 2005–Revised June 2011
C6455/C6454 DDR2 Memory Controller

1.3 Functional Block Diagram

The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1). Master peripherals, such as the EDMA controller and the CPU can access the DDR2 memory controller through the switched central resource (SCR). The DDR2 memory controller performs all memory-related background tasks such as opening and closing banks, refreshes, and command arbitration.
SPRU970G–December 2005–Revised June 2011 C6455/C6454 DDR2 Memory Controller
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L1 S1 M1 D1
Data path A
Register file A
Register file B
D2
Data path B
S2M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32−bit instruction dispatch
Instruction fetch SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller
Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
Switched central resource
PLL2
L2 memory
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection
Introduction
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Figure 1. Device Block Diagram

1.4 Industry Standard(s) Compliance Statement

The DDR2 memory controller is compliant with the JESD79-2B DDR2 SDRAM.
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C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
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2 Peripheral Architecture

The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform read and write operations to DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device.

2.1 Clock Control

The DDR2 memory controller is clocked directly from the output of the second phase-locked loop (PLL2) of C6455/C6454 devices. The PLL2 multiplies its input clock by 20. This clock is divided by 2 to generate DDR2CLKOUT. The frequency of DDR2CLKOUT can be determined by using the following formula:
DDR2CLKOUT frequency = (PLL2 input clock frequency × 20)/2 = PLL2 input clock frequency×10
The second output clock of the DDR2 memory controller, DDR2CLKOUT, is the inverse of DDR2CLKOUT. For more information on the PLL2, see the device-specific data manual.

2.2 Memory Map

For information describing the device memory map, see the device-specific data manual.
Peripheral Architecture

2.3 Signal Descriptions

The DDR2 memory controller signals are shown in Figure 2 and described in Table 1. The following features are included:
• The maximum width for the data bus (DED[31:0]) is 32-bits.
• The address bus (DEA[13:0]) is 14-bits wide with an additional 3 bank address pins (DBA[2:0]).
• Two differential output clocks (DDR2CLKOUT and DDR2CLKOUT) driven by internal clock sources.
• Command signals: Row and column address strobe (DSDRAS and DSDCAS), write enable strobe
(DSDWE), data strobe (DSDDQS[3:0] and DSDDQS[3:0]), and data mask (DSDDQM[3:0]).
• One chip select signal (DCE0).
• One clock enable signal (DSDCKE).
• Two on-die termination output signals (DEODT[1:0]). (These pins are reserved for future use.)
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DED[31:0]
DDR2 Memory Controller
DDR2CLKOUT
DDR2CLKOUT
DCE0
DSDCKE
DSDRAS
DSDWE
DSDDQM[3:0]
DSDCAS
DBA[2:0]
DSDDQS[3:0]
DEA[13:0]
V
REFSSTL
DSDDQGATE[3:0]
DSDDQS[3:0]
DEODT[1:0]
DDRSLRATE
Peripheral Architecture
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Figure 2. DDR2 Memory Controller Signals
Table 1. DDR2 Memory Controller Signal Descriptions
Pin Description
DED[31:0] Bidirectional data bus. Input for data reads and output for data writes. DEA[13:0] External address output. DCE0 Active-low chip enable for memory space CE0. DCE0 is used to enable the DDR2 SDRAM memory
DSDDQM[3:0] Active-low output data mask. DDR2CLKOUT Differential clock outputs.
DDR2CLKOUT DSDCKE Clock enable (used for self-refresh mode). DSDCAS Active-low column address strobe. DSDRAS Active-low row address strobe. DSDWE Active-low write enable. DSDDQS[3:0]/ Differential data strobe bidirectional signals.
DSDDQS[3:0] DEODT[1:0] On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and
DBA[2:0] Bank-address control outputs. DSDDQGATE[3:0] Data strobe gate pins. These pins are used as a timing reference during memory reads. The
V
REFSSTL
DDRSLRATE Pulling the DDRSLRATE input pin low selects the normal slew rate. If pulled high, the slew rate is
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C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
device during external memory accesses. The DCE0 pin stays low throughout the operation of the DDR2 memory controller; it never goes high. Note that this behavior does not affect the ability of the DDR2 memory controller to access DDR2 SDRAM memory devices.
should not be connected to the DDR2 SDRAM.
DSDDQGATE0 and DSDDQGATE2 pins should be routed out and connected to the DSDDQGATE1 and DSDDQGATE3 pins, respectively. For more routing requirements on these pins, see the device-specific data manual.
DDR2 Memory Controller reference voltage. This voltage must be supplied externally. For more details, see the device-specific data manual.
reduced by 33%. For normal full-speed operation, the DDRSLRATE should be pulled low.This pin needs to be pulled low or high at all times (it is not latched).
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2.4 Protocol Description(s)

The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands.
Command Function
ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set. Allows altering the contents of the mode register. MRS Mode register set. Allows altering the contents of the mode register. NOP No operation. Power Down Power down mode. READ Inputs the starting column address and begins the read operation. READ with Inputs the starting column address and begins the read operation. The read operation is followed by a
autoprecharge precharge. REFR Autorefresh cycle. SLFREFR Self-refresh mode. WRT Inputs the starting column address and begins the write operation. WRT with Inputs the starting column address and begins the write operation. The write operation is followed by a
autoprecharge precharge.
Peripheral Architecture
Table 2. DDR2 SDRAM Commands
Table 3. Truth Table for DDR2 SDRAM Commands
DDR2 SDRAM Signals CKE CS RAS CAS WE BA[2:0] A[13:11, 9:0] A10
DSDCKE
DDR2 Memory Previous Controller Signals Cycles Current Cycle DCE0 DSDRAS DSDCAS DSDWE DBA[2:0] DEA[13:11, 9:0] DEA[10]
ACTV H DCAB H H L L H L X X H DEAC H H L L H L Bank X L MRS H H L L L L BA EMRS H H L L L L BA OP Code READ H H L H L H BA Column Address L READ with H H L H L H BA Column Address H
precharge WRT H H L H L L BA Column Address L WRT with precharge H H L H L L BA Column Address L REFR H H L L L H X X X SLFREFR H L L L L H X X X
entry SLFREFR L H H X X X X X X
exit
NOP H X L H H H X X X DESEL H X H X X X X X X Power-down H L H X X X X X X
entry
Power-down L H H X X X X X X exit
(1)
LEGEND: H = logic high; L = logic low; X = don't care (either H or L).
(2)
BA refers to the bank address pins (BA[2:0]).
(1)
H L L H H Bank Row Address
(2)
L H H H X X X
L H H H X X X
L H H H X X X
OP Code
SPRU970G–December 2005–Revised June 2011 C6455/C6454 DDR2 Memory Controller
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COL
MRS/EMRS
BANK
DDR2CLKOUT
DDR2CLKOUT
DCE0
DSDCKE
DSDRAS
DSDWE
DSDCAS
DBA[2:0]
DEA[13:0]
Peripheral Architecture
2.4.1 Mode Register Set (MRS and EMRS)
DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DBA[1:0] selects the mode register to be written and the data on DEA[12:0] is loaded into the register.
Figure 3 shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence. For more information, see Section 2.11.
Figure 3. DDR2 MRS and EMRS Command
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C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
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REFR
DDR2CLKOUT DDR2CLKOUT
DCE0
DSDCKE
DSDRAS
DSDWE
DSDDQM[3:0]
DSDCAS
DBA[2:0]
DEA[13:0]
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2.4.2 Refresh Mode
The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC). Page information is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the DDR2 memory controller. See Section 2.8 for more details on REFR command scheduling.
Peripheral Architecture
Figure 4. Refresh Command
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