Texas instruments TMS320C6454 DATASHEET

TMS320C6454

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Fixed-Point Digital Signal Processor

Check for Samples: TMS320C6454

1 Features

12

• High-Performance Fixed-Point DSP (C6454)
– 1.39-, 1.17-, and 1-ns Instruction Cycle Time
– 720-MHz, 850-MHz, and 1-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 8000 MIPS/MMACS (16-Bits)
– Commercial Temperature [0°C to 90°C]
– Extended Temperature [-40°C to 105°C]

• TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling

• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:

– 256K-Bit (32K-Byte) L1P Program Cache

[Direct Mapped]

– 256K-Bit (32K-Byte) L1D Data Cache

[2-Way Set-Associative]

– 8M-Bit (1048K-Byte) L2 Unified Mapped

RAM/Cache [Flexible Allocation]
– 256K-Bit (32K-Byte) L2 ROM
– Time Stamp Counter

• Endianess: Little Endian, Big Endian

• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous

Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
SRAM)

– Supports Interface to Standard Sync

Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)

– 32M-Byte Total Addressable External

Memory Space

• DDR2 Memory Controller
– Interfaces to DDR2-533 SDRAM
– 32-Bit/16-Bit, 533-MHz (data rate) Bus
– 512M-Byte Total Addressable External

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

TMS320C6454

Memory Space

• EDMA3 Controller (64 Independent Channels)

• 32-/16-Bit Host-Port Interface (HPI)

• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Local Bus Specification (v2.3)

• One Inter-Integrated Circuit (I2C) Bus

• Two McBSPs

• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports Multiple Media Independent

Interfaces (MII, GMII, RMII, and RGMII)

– 8 Independent Transmit (TX) and

8 Independent Receive (RX) Channels

• Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers

• 16 General-Purpose I/O (GPIO) Pins

• System PLL and PLL Controller

• Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller

• Advanced Event Triggering (AET) Compatible

• Trace-Enabled Device

• IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible

• 697-Pin Ball Grid Array (BGA) Package
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch

• 0.09-mm/7-Level Cu Metal Process (CMOS)

• 3.3-/1.8-/1.5-V I/Os,

1.25-/1.2-V Internal

• Pin-Compatible with the TMS320C6455
Fixed-Point Digital Signal Processor

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testingof all parameters.

Copyright © 2006–2010, Texas Instruments Incorporated

ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW)

A

2

B

1

345678910111213141516171819202122232425

26

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

272829

AG

AH

AJ

NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information,

see the Mechanical Data section of this document.

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

1.1 ZTZ/GTZ BGA Package (Bottom View)

Figure 1-1 shows the TMS320C6454 device 697-pin ball grid array package (bottom view).

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Figure 1-1. ZTZ/GTZ BGA Package (Bottom View)

1.2 Description

The TMS320C64x+™ DSPs (including the TMS320C6454 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The C6454 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making these DSPs an excellent choice for applications including video and
telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are
upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C6454 device offers a lower cost pin-compatible migration path for C6455 customers who don't need
the 2MB of the C6455 or the high-speed interconnect provided by Serial RapidIO. The C6454 device also
provides an excellent migration path for existing C6414/6415/6416 customers who require C6454
advanced peripherals; DDR2 at 533 MHz provides 2x performance boost over older SDRAM interface,
gigabit Ethernet provides low-cost high-performance ubiquitous packet interface, and 66-MHz PCI
(revision 2.3 complaint) provides legacy high-bandwidth interconnect.

Based on 90-nm process technology and with performance of up to 8000 million instructions per second
(MIPS) [or 8000 16-bit MMACs per cycle] at a 1-GHz clock rate, the C6454 device offers cost-effective
solutions to high-performance DSP programming challenges. The C6454 DSP possesses the operational
flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles
the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates
(MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+
core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each
multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock
cycle.

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The C6454 DSP integrates a large amount of on-chip memory organized as a two-level memory system.
The level-1 (L1) program and data memories on the C6454 device are 32KB each. This memory can be
configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1
program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The
level-2 (L2) memory is shared between program and data space and is 1048KB in size. L2 memory can
also be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule
also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system
component with reset/boot control, interrupt/exception control, a power-down control, and a free-running
32-bit timer for time stamp.

The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral
component interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable
interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which
provides an efficient interface between the C6454 DSP core processor and the network; a management
data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in
order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA),
which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM
interface.

The I2C ports on the C6454 device allows the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

The C6454 DSP has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into
source code execution.

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MDIO

EMAC

10/100/1000

Serial

RapidIO

DDR2

Mem Ctlr

64

C6454

HI

I2C

16

RMGII

(D)

L2

Cache

Memory

1048K

Bytes

HPI (32/16)

(B)

DDR2 SDRAM

32

LO

Timer1

(C)

PLL2 and

PLL2

Controller

(D)

GMII

RMII

MII

Primary

Switched

Central

Resource

L2 Memory Controller

(Memory Protect/

Bandwidth Mgmt)

System

C64x+ DSP Core

Data Path B

B Register File

B31−B16

B15−B0

Instruction Fetch

Data Path A

A Register File

A31−A16

A15−A0

.L1

.S1

.M1

xxxx.D1 .D2

.M2

xx
xx

.S2

.L2

Internal DMA

(IDMA)

M

e
g
a

m

o
d
u

l

e

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

Instruction

Decode

16-/32-bit

Instruction Dispatch

Power Control

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

Interrupt and Exception Controller

EMIFA

HI

LO

Timer1

(C)

EDMA 3.0

Secondary

Switched Central

Resource

PLL1 and

PLL1

Controller

Device

Configuration

Logic

Boot Configuration

L1D SRAM/Cache

2-Way Set-Associative

32K Bytes Total

L1P SRAM/Cache Direct-Mapped

32K Bytes

L2 ROM

32K

Bytes

(E)

Control Registers

SPLOOP Buffer

In-Circuit Emulation

PCI66

(B)

GPIO16

(B)

McBSP1

(A)

McBSP0

(A)

SBSRAM

ZBT SRAM

SRAM

ROM/FLASH

I/O Devices

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

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1.3 Functional Block Diagram

Figure 1-2 shows the functional block diagram of the C6454 device.

4 Features Copyright © 2006–2010, Texas Instruments Incorporated

Figure 1-2. Functional Block Diagram

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A. McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs.
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins . For more detailed information, see

Section 3, Device Configuration.

C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as a 64-bit general-purpose timer, dual 32-bit

general-purpose timers, or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.

TMS320C6454

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1 Features ................................................... 1

1.1 ZTZ/GTZ BGA Package (Bottom View) ............. 2

1.2 Description ........................................... 2

1.3 Functional Block Diagram ............................ 4

5.4 Power-Down Control ............................... 83

5.5 Megamodule Resets ................................ 83

5.6 Megamodule Revision .............................. 84

5.7 C64x+ Megamodule Register Descriptions ......... 85

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Revision History .............................................. 6 6 Device Operating Conditions ....................... 93

2 Device Overview ........................................ 7

2.1 Device Characteristics ............................... 7

2.2 CPU (DSP Core) Description ........................ 8

2.3 Memory Map Summary ............................. 11

2.4 Boot Sequence ..................................... 13

2.5 Pin Assignments .................................... 15

2.6 Signal Groups Description .......................... 19

2.7 Terminal Functions ................................. 24

2.8 Development ........................................ 48

3 Device Configuration ................................. 52

3.1 Device Configuration at Device Reset .............. 52

3.2 Peripheral Configuration at Device Reset .......... 54

3.3 Peripheral Selection After Device Reset ........... 55

3.4 Device State Control Registers ..................... 57

3.5 Device Status Register Description ................ 67

3.6 JTAG ID (JTAGID) Register Description ........... 69

3.7 Pullup/Pulldown Resistors .......................... 70

3.8 Configuration Examples ............................ 70

4 System Interconnect .................................. 73

4.1 Internal Buses, Bridges, and Switch Fabrics ....... 73

4.2 Data Switch Fabric Connections ................... 74

4.3 Configuration Switch Fabric ........................ 76

4.4 Bus Priorities ....................................... 77

5 C64x+ Megamodule ................................... 79

5.1 Memory Architecture ............................... 79

5.2 Memory Protection ................................. 81

5.3 Bandwidth Management ............................ 82

6.1 Absolute Maximum Ratings Over Operating Case

Temperature Range (Unless Otherwise Noted) .... 93

6.2 Recommended Operating Conditions .............. 93

6.3 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 95

7 C64x+ Peripheral Information and Electrical

Specifications .......................................... 97

7.1 Parameter Information .............................. 97

7.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 98

7.3 Power Supplies ..................................... 99

7.4 Enhanced Direct Memory Access (EDMA3)

Controller .......................................... 101

7.5 Interrupts .......................................... 116

7.6 Reset Controller ................................... 120

7.7 PLL1 and PLL1 Controller ......................... 128

7.8 PLL2 and PLL2 Controller ......................... 143

7.9 DDR2 Memory Controller ......................... 152

7.10 External Memory Interface A (EMIFA) ............ 154

7.11 I2C Peripheral ..................................... 165

7.12 Host-Port Interface (HPI) Peripheral .............. 170

7.13 Multichannel Buffered Serial Port (McBSP) ....... 181

7.14 Ethernet MAC (EMAC) ............................ 195

7.15 Timers ............................................. 213

7.16 Peripheral Component Interconnect (PCI) ........ 215

7.17 General-Purpose Input/Output (GPIO) ............ 222

7.18 Emulation Features and Capability ............... 224

8 Mechanical Data ...................................... 226

8.1 Thermal Data ...................................... 226

8.2 Packaging Information ............................ 226

Copyright © 2006–2010, Texas Instruments Incorporated Contents 5

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the document in this revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6454 device,

have been incorporated.

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Table 3-1 C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN):

Modified Configuration Pin AEA11 Functional Description

Section 7.7 PLL1 and PLL1 Controller:

Modified Figure 7-10, PLL1 and PLL1 Controller

Table 7-71 Ethernet MAC (EMAC) Control Registers:

Corrected Hex Address Range for Registers RXINTSTATRAW - MACINTMASKCLEAR

Section 7.14.3.2 EMAC RMII Electrical Data/Timing:

Corrected signal names in Table 7-82, Switching Characteristics Over Recommended Operating Conditions
for EMAC RMII Transmit 10/100 Mbit/s, Figure 7-66, EMAC Transmit Interface Timing [RMII Operation],

Table 7-83, Timing Requirements for EMAC RMII Input Receive for 100 Mbps, and Figure 7-67, EMAC

Receive Interface Timing [RMII Operation]

Section 7.14.3.3 EMAC RGMII Electrical Data/Timing:

Corrected signal names in Table 7-85, Timing Requirements for RGRXC - RGMII Operation, Table 7-86,
Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps, Figure 7-69, EMAC Receive
Interface Timing [RGMII Operation], Table 7-87, Switching Characteristics Over Recommended Operating
Conditions for RGTXC - RGMII Operation for 10/100/1000 Mbit/s, Table 7-88, Switching Characteristics Over
Recommended Operating Conditions for EMAC RGMII Transmit, and Figure 7-70, EMAC Transmit Interface
Timing [RGMII Operation]

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Revision History

C6454 DSP Revision History

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

2 Device Overview

2.1 Device Characteristics

Table 2-1, provides an overview of the C6454 DSP. The tables show significant features of the C6454

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.

Table 2-1. Characteristics of the C6454 Processor

HARDWARE FEATURES C6454

EMIFA (64-bit bus width)
(clock source = AECLKIN or SYSCLK4)

DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock source = CLKIN2)

EDMA3 (64 independent channels) [CPU/3 clock rate] 1
Peripherals
Not all peripherals pins

are available at the same
time (For more detail, see

Section 3, Device

Configuration).

On-Chip Memory

C64x+ Megamodule Megamodule Revision ID Register (address location:
Revision ID 0181 2000h)

JTAG BSDL_ID JTAGID register (address location: 0x02A80008)
Frequency MHz 720, 850, and 1000 (1 GHz)
Cycle Time ns

Voltage

PLL1 and PLL1
Controller Options

PLL2 x20

BGA Package 24 x 24 mm
Process Technology mm 0.09 mm
Product Status

(2)

I2C 1

HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32)

PCI (32-bit), [66-MHz or 33-MHz] 1 (PCI66 or PCI33)

McBSPs (internal CPU/6 or external clock source up

to 100 Mbps)

10/100/1000 Ethernet MAC (EMAC) 1

Management Data Input/Output (MDIO) 1

64-Bit Timers (Configurable)

(internal clock source = CPU/6 clock frequency)

General-Purpose Input/Output Port (GPIO) 16

Size (Bytes) 1144K

32K-Byte (32KB) L1 Program Memory Controller

Organization 32KB Data Memory Controller [SRAM/Cache]

See Section 5.6, Megamodule Revision

See Section 3.6, JTAG ID (JTAGID) Register

1.39 ns (C6454-720), 1.17 ns (C6454-850),

1 ns (C6454 A-1000, -1000) [1-GHz CPU]

Core (V)

I/O (V)

CLKIN1 frequency multiplier Bypass (x1), x15, x20, x25, x30, x32

CLKIN2 frequency multiplier

[DDR2 Memory Controller and EMAC support only]

697-Pin Flip-Chip Plastic BGA (ZTZ)

Product Preview (PP), Advance Information (AI),

or Production Data (PD)

2 64-bit or 4 32-bit

1024KB L2 Unified Memory/Cache

1.25 V (A-1000/-1000)

1.5/1.8 [EMAC RGMII], and

1.8 and 3.3 V [I/O Supply Voltage]

697-Pin Plastic BGA (GTZ)

1

1

2

[SRAM/Cache]

32KB L2 ROM

Description

1.2 V (-850/-720)

PD

(1)

(1) The extended temperature device's (A-1000) electrical characteristics and ac timings are the same as those for the corresponding

commercial temperature devices (-1000).

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Table 2-1. Characteristics of the C6454 Processor (continued)

HARDWARE FEATURES C6454

Device Part Numbers TMS320C6454ZTZ8 , TMS320C6454GTZ8

(For more details on the C64x+™ DSP part

numbering, see Figure 2-12)

TMS320C6454ZTZ7, TMS320C6454GTZ7

TMS320C6454ZTZ , TMS320C6454GTZ

2.2 CPU (DSP Core) Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two

16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add
operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There
is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms
such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes
for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex
multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and
16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for
audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.

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Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common

• Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit

• Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a

• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)

• TMS320C64x+ Megamodule Reference Guide (literature number SPRU871)

• TMS320C6455 Technical Reference (literature number SPRU965)

• TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84)

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.

multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.

detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).

basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.

free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

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src2

src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

src1

src1

src1

even dst

even dst

odd dst

dst1

dst

src2

src2

src2

long src

DA1

ST1b

LD1b
LD1a

ST1a

Data path A

Odd

register

file A

(A1, A3,

A5...A31)

Odd

register

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a
LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a
ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB
32 LSB

dst2

(A)

32 MSB
32 LSB

2x

1x

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B)
(A)

8

8

8

8

32

32

32

32

(C)

(C)

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

(D)

(D)

(D)

(D)

A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

www.ti.com

Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths

10 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the C6454 device. The external memory

configuration register address ranges in the C6454 device begin at the hex address location 0x7000 0000
for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.

Table 2-2. C6454 Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 1024K 0000 0000 - 000F FFFF
Internal ROM 32K 0010 0000 - 0010 7FFF
Reserved 7M - 32K 0010 8000 - 007F FFFF
Internal RAM (L2) [L2 SRAM] 1M 0080 0000 - 009F FFFF
Reserved 4M 00A0 0000 - 00DF FFFF
L1P SRAM 32K 00E0 0000 - 00E0 7FFF
Reserved 1M - 32K 00E0 8000 - 00EF FFFF
L1D SRAM 32K 00F0 0000 - 00F0 7FFF
Reserved 1M - 32K 00F0 8000 - 00FF FFFF
Reserved 8M 0100 0000 - 017F FFFF
C64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFF
Reserved 12.5M 01C0 0000 - 0287 FFFF
HPI Control Registers 256K 0288 0000 - 028B FFFF
McBSP 0 Registers 256K 028C 0000 - 028F FFFF
McBSP 1 Registers 256K 0290 0000 - 0293 FFFF
Timer 0 Registers 256K 0294 0000 - 0297 FFFF
Timer 1 Registers 128K 0298 0000 - 0299 FFFF
PLL1 Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FF
Reserved 256K - 512 029A 0200 - 029B FFFF
PLL2 Controller Registers 512 029C 0000 - 029C 01FF
Reserved 64K 029C 0200 - 029C FFFF
EDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFF
Reserved 96K 02A0 8000 - 02A1 FFFF
EDMA3 Transfer Controller 0 Registers 32K 02A2 0000 - 02A2 7FFF
EDMA3 Transfer Controller 1 Registers 32K 02A2 8000 - 02A2 FFFF
EDMA3 Transfer Controller 2 Registers 32K 02A3 0000 - 02A3 7FFF
EDMA3 Transfer Controller 3 Registers 32K 02A3 8000 - 02A3 FFFF
Reserved 256K 02A4 0000 - 02A7 FFFF
Chip-Level Registers 256K 02A8 0000 - 02AB FFFF
Device State Control Registers 256K 02AC 0000 - 02AF FFFF
GPIO Registers 16K 02B0 0000 - 02B0 3FFF
I2C Data and Control Registers 256K 02B0 4000 - 02B3 FFFF
Reserved 720K 02B4 0000 - 02BF FFFF
PCI Control Registers 256K 02C0 0000 - 02C3 FFFF
Reserved 256K 02C4 0000 - 02C7 FFFF
EMAC Control 4K 02C8 0000 - 02C8 0FFF
EMAC Control Module Registers 2K 02C8 1000 - 02C8 17FF
MDIO Control Registers 2K 02C8 1800 - 02C8 1FFF
EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF
Reserved 496K 02C8 4000 - 02CF FFFF
Reserved 220M 02D0 0000 - 0FFF FFFF
Reserved 256M 1000 0000 - 1FFF FFFF

Copyright © 2006–2010, Texas Instruments Incorporated Device Overview 11

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Table 2-2. C6454 Memory Map Summary (continued)

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Reserved 256M 2000 0000 - 2FFF FFFF
McBSP 0 Data 256 3000 0000 - 3000 00FF
Reserved 64M - 256 3000 0100 - 33FF FFFF
McBSP 1 Data 256 3400 0000 - 3400 00FF
Reserved 64M - 256 3400 0100 - 37FF FFFF
Reserved 64M 3800 0000 - 3BFF FFFF
Reserved 2K 3C00 0000 - 3C00 07FF
Reserved 16M - 2K 3C00 0800 - 3CFF FFFF
Reserved 48M 3D00 0000 - 3FFF FFFF
PCI External Memory Space 256M 4000 0000 - 4FFF FFFF
Reserved 256M 5000 0000 - 5FFF FFFF
Reserved 256M 6000 0000 - 6FFF FFFF
EMIFA (EMIF64) Configuration Registers 128M 7000 0000 - 77FF FFFF
DDR2 Memory Controller Configuration Registers 128M 7800 0000 - 7FFF FFFF
Reserved 256M 8000 0000 - 8FFF FFFF
Reserved 256M 9000 0000 - 9FFF FFFF
EMIFA CE2 - SBSRAM/Async
Reserved 256M - 8M A080 0000 - AFFF FFFF
EMIFA CE3 - SBSRAM/Async
Reserved 256M - 8M B080 0000 - BFFF FFFF
EMIFA CE4 - SBSRAM/Async
Reserved 256M - 8M C080 0000 - CFFF FFFF
EMIFA CE5 - SBSRAM/Async
Reserved 256M - 8M D080 0000 - DFFF FFFF
DDR2 Memory Controller CE0 - DDR2 SDRAM 512M E000 0000 - FFFF FFFF

(1) The EMIFA CE0 and CE1 are not functionally supported on the C6454 device and, therefore, are not pinned out.

(1)

(1)

(1)

(1)

8M A000 0000 - A07F FFFF

8M B000 0000 - B07F FFFF

8M C000 0000 - C07F FFFF

8M D000 0000 - D07F FFFF

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12 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated

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2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections and the DSP's internal registers are programmed with predetermined values. The boot sequence
is started automatically after each power-on reset, warm reset, and system reset. For more details on the
initiators of these resets, see Section 7.6, Reset Controller.

There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset through the
BOOTMODE[3:0] pins.

Each boot mode can be classified as a hardware boot mode or as a software boot mode. Software boot
modes require the use of the on-chip bootloader. The bootloader is DSP code that transfers application
code from an external source into internal or external program memory after the DSP is taken out of reset.
The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010
0000h. Hardware boot modes are carried out by the boot configuration logic. The boot configuration logic
is actual hardware that does not require the execution of DSP code. Section 2.4.1, Boot Modes
Supported, describes each boot mode in more detail.

When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not
exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU
frequency can be programmed to the frequency required by the application.

2.4.1 Boot Modes Supported

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

The C6454 device has five boot modes:

• No boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 SRAM located at address 0x80 0000.

Note: device operations is undefined if invalid code is located at address 0x80 0000. This boot mode is
a hardware boot mode.

• Host boot (BOOTMODE[3:0] = 0001b and BOOTMODE[3:0] = 0111b)
If host boot is selected, after reset, the CPU is internally "stalled" while the remainder of the device is

released. During this period, an external host can initialize the CPU's memory space as necessary
through Host Port Interface (HPI) or the Peripheral Component Interconnect (PCI) interface. Internal
configuration registers, such as those that control the EMIF can also be initialized by the host with two
exceptions: Device State Control registers (Section 3.4), PLL1 and PLL2 Controller registers
(Section 7.7 and Section 7.8) cannot be accessed through any host interface, including HPI and PCI.

Once the host is finished with all necessary initialization, it must generate a DSP interrupt (DSPINT) to
complete the boot process. This transition causes boot configuration logic to bring the CPU out of the
"stalled" state. The CPU then begins execution from the internal L2 SRAM located at 0x80 0000. Note
that the DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event
must be cleared by software before triggering transfers on DMA channel 0.

All memory, with the exceptions previously described, may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled"
state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.

As previously mentioned, for the C6454 device, the Host Port Interface (HPI) and the Peripheral
Component Interconnect (PCI) interface can be used for host boot. To use the HPI for host boot, the
PCI_EN pin (Y29) must be low [default] (enabling the HPI peripheral) and BOOTMODE[3:0] must be
set to 0001b at device reset. Conversely, to use the PCI interface for host boot, the PCI_EN pin (Y29)
must be high (enabling the PCI peripheral) and BOOTMODE[3:0] must be set to 0111b at device reset.
For the HPI host boot, the DSP interrupt can be generated through the use of the DSPINT bit in the
HPI Control (HPIC) register.

For the HPI host boot, the CPU is actually held in reset until a DSP interrupt is generated by the host.
The DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control (HPIC)
register. Since the CPU is held in reset during HPI host boot, it will not respond to emulation software

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TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

such as Code Composer Studio.
For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt

is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting
the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the
Status Set Register (PCISTATSET).

Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode.
If PCI boot is selected, the on-chip bootloader configures the PLL1 Controller such that CLKIN1 is

multiplied by 15. More specifically, PLLM is set to 0Eh (x15) and RATIO is set to 0 (÷1) in the PLL1
Multiplier Control Register (PLLM) and PLL1 Pre-Divider Register (PREDIV), respectively. The CLKIN1
frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM, 750
MHz, is not violated. The CFGGP[2:0] pins must be set to 000b during reset for proper operation of the
PCI boot mode.

As mentioned previously, a DSP interrupt must be generated at the end of the host boot process to
begin execution of the loaded application. Since the DSP interrupt generated by the HPI and PCI is
mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA
Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.

• EMIFA 8-bit ROM boot (BOOTMODE[3:0] = 0100b)
After reset, the device will begin executing software out of an Asynchronous 8-bit ROM located in

EMIFA CE3 space using the default settings in the EMIFA registers. This boot mode is a hardware
boot mode.

• Master I2C boot (BOOTMODE[3:0] = 0101b)
After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a

device acting as an I2C slave to the DSP using a predefined boot table format. The destination
address and length are contained within the boot table. This boot mode is a software boot mode.

• Slave I2C boot (BOOTMODE[3:0] = 0110b)
A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a

Master to send data using a standard boot table format.
Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot

multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting
via an I2C EEPROM before acting as a Master and booting other DSPs.

The Slave I2C boot is a software boot mode.

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2.4.2 2nd-Level Bootloaders

Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for
any level of customization to current boot methods as well as definition of a completely customized boot.
TI offers a few 2nd-level bootloaders, such as an EMAC bootloader, which can be loaded using the
Master I2C boot.

14 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated

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AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

13121110987654321

13121110987654321

CLKR1/

GP[0]

HD15/

AD15

HD2/

AD2

PGNT

/

GP[12]

HD22/

AD22

DV

DD33

RSV15

PIDSEL

RSV16

HDS1

/

PSERR

HINT/

PFRAME

DV

DD33

HHWIL/

PCLK

V

SS

HD12/

AD12

HD24/

AD24

RSV03

HD20/

AD20

HD18/

AD18

HD6/

AD6

HD16/
AD16

V

SS

HD28/

AD28

HD17/

AD17

HD31/
AD31

HD14/

AD14

HCNTL1/

PDEVSEL

HR/W/

PCBE2

HRDY/
PIRDY

PRST/

GP[13]

HD21/

AD21

DV

DD33

V

SS

EMU8

RSV36

EMU11

EMU1

EMU10

EMU12

RSV37

EMU15

EMU4

EMU13

DV

DD33

DV

DD33

V

SS

EMU0

V

SS

DV

DD33

RSV38EMU6

CLKX1/

GP[3]

DV

DD33

V

SS

EMU18

DV

DD33

EMU5

V

SS

DV

DD33

HD9/

AD9

HD23/
AD23

HD3/

AD3

HD10/
AD10

GP[6]

V

SS

EMU14

GP[7]

RSV02

HD4/

AD4

HD30/

AD30

CV

DD

HD27/

AD27

V

SS

V

SS

V

SS

DV

DD33

V

SS

CV

DD

CV

DD

V

SS

DV

DD33

DV

DD33

V

SS

V

SS

DV

DD33

V

SS

V

SS

HD19/

AD19

HD13/

AD13

HD29/

AD29

DV

DD33

DV

DD33

HD25/

AD25

DV

DD33

HD0/

AD0

V

SS

HD11/
AD11

TOUTL0

EMU3

EMU7

TOUTL1

V

SS

DV

DD33

V

SS

DV

DD33

V

SS

HDS2

/

PCBE1

HCNTL0/

PSTOP

HCS/

PPERR

V

SS

HD8/

AD8

V

SS

HD26/

AD26

V

SS

HD7/

AD7

HD1/

AD1

EMU2

RSV39

V

SS

DV

DD33

HAS/

PPAR

HD5/

AD5

AH

TINPL0 EMU17TDONMI EMU16GP[4]V

SS

TRST

TDI

RSV27 EMU9

AJ

TINPL1 TMSV

SS

CLKS RSV40

GP[5]DV

DD33

DV

DD33

TCK

RSV26

SYSCLK4/

GP[1]

14

V

SS

DV

DD33

RESETSTAT

POR

V

SS

CV

DD

CV

DD

RESET

DV

DD33

V

SS

15

RSV64

V

SS

DV

DD33

RSV45

CV

DD

V

SS

V

SS

RSV46

V

SS

DV

DD33

14 15

V

SS

CV

DD

CV

DD

CV

DD

V

SS

V

SS

V

SS

CV

DD

RSV68

V

SS

V

SS

CV

DD

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

AH

AJFSX0 DR0

FSR0

DR1/

GP[8]

CLKR0

FSX1/
GP[11]

DX1/
GP[9]

CLKX0

DX0

FSR1/

GP[10]

TMS320C6454

www.ti.com

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

2.5 Pin Assignments

2.5.1 Pin Map

Figure 2-2 through Figure 2-5 show the C6454 device pin assigments in four quadrants (A, B, C, and D).

Copyright © 2006–2010, Texas Instruments Incorporated Device Overview 15

Figure 2-2. C6454 Pin Map (Bottom View) [Quadrant A]

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AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

17 18 19 20 21 22 23 24 25 26 27 28 29

17 18 19 20 21 22 23 24 25 26 27 28 29

SDA

AED27

V

SS

ASADS

/

ASRE

AED17

AHOLD

PLLV1

AEA13/

LENDIAN

AEA4/

SYSCLKOUT

_EN

AEA5/

MCBSP1

_EN

AEA6/
PCI66

AECLKOUTACE5

ACE4

ABA0/

DDR2_EN

ABE7

ACE2 RSV41

AAOE

/

ASOE

RSV42 RSV44

ABE2

ABE0

AED29

AED31

ACE3

AEA1/

CFGGP1

AEA11

AEA2/

CFGGP2

AEA14/

HPI_

WIDTH

AED21

DV

DD33

V

SS

V

SS

V

SS

DV

DD33

RSV73

RSV63

V

SS

V

SS

RSV17

V

SS

DV

DD33

V

SS

V

SS

RSV74

RSV50

DV

DD33

V

SS

DV

DD33

V

SS

AED3V

SS

RSV49

AED7

AED1

SCL

RSV65

V

SS

RSV72

RSV48

V

SS

DV

DD33

V

SS

AED25

AED28

AED11

AED4

AED9

AED15RSV47

AED16

ABA1/

EMIFA_EN

RSV43

ABE1

RSV71

AED24DV

DD33

V

SS

V

SS

AED19

DV

DD33

CV

DD

CV

DD

DV

DD33

V

SS

V

SS

DV

DD33

DV

DD33

V

SS

V

SS

V

SS

DV

DD33

V

SS

AED26V

SS

DV

DD33

AED22AED0

AED13AED12

AED10RSV54RSV75RSV51

AED30DV

DD33

AEA12

V

SS

V

SS

V

SS

V

SS

RSV20

AEA0/

CFGGP0

V

SS

DV

DD33

AR/W

DV

DD33

PCI_ENDV

DD33

AED23

AAWE

/

ASWE

RSV53RSV52DV

DD33

ABE3

AEA3

AED8

AH

DV

DD33

V

SS

RSV76 RSV58 AED14RSV55 AED2 AED18

V

SS

RSV62VSSV

SS

V

SS

RSV59

AJ

V

SS

DV

DD33

V

SS

RSV57 AED5RSV56 AED6 AED20 DV

DD33

RSV78RSV61RSV60RSV77

16

V

SS

RSV66

V

SS

DV

DD33

V

SS

RSV70

CV

DD

V

SS

DV

DD33

V

SS

16

V

SS

CV

DD

CV

DD

RSV69

V

SS

V

SS

V

SS

RSV67

V

SS

CV

DD

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

AH

AJ

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

www.ti.com

Figure 2-3. C6454 Pin Map (Bottom View) [Quadrant B]

16 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated

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C

D

E

F

G

H

J

K

L

M

N

P

17 18 19 20 21 22 23 24 25 26 27 28 29

17 18 19 20 21 22 23 24 25 26 27 28 29

RSV09

AED52

DV

DD33

V

SS

V

SS

V

SS

AECLKIN

AEA9/

MACSEL0

CLKIN1

DV

DD33

AEA15/

AECLKIN

_SEL

AED40AED44 AED42

AED34

ABE6

AED32

ABE4

AEA18/

BOOT

MODE2

AED37

ABUSREQ

AED46

AEA16/

BOOT

MODE0

AEA19/

BOOT

MODE3

AHOLDA

AEA10/

MACSEL1

V

SS

V

SS

DV

DD18

DED19

V

SS

CV

DD

VSSDSDDQS2

DSDDQ

GATE2

DED23

DV

DD18

DV

DD33

DSDDQS3

DSDDQS3

V

SS

DV

DD18

RSV11

RSV12 RSV33DSDDQM2 DED26

V

SS

RSV32

RSV23

V

SS

V

SS

DEA4

DEA1

AV

DLL2

DV

DD33

DV

DD33

AED56

AED50

AED45

AED59

AED61

AED58DEA5

AED60

AED33

AEA17/

BOOT

MODE1

DSDDQ

GATE3

RSV19

AED55V

SS

DV

DD18

DV

DD18

AED39

DV

DD33

V

SS

V

SS

RSV30

DV

DD33

V

SS

V

SS

DV

DD18

V

SS

DV

DD18

DV

DD18

AED35AED48AED54DV

DD18

V

SS

DV

DD33

AED47

DV

DD33

DV

DD33

AED57DED27DSDDQS2

DEA0

AED41DSDDQM3

DV

DD33

V

SS

CV

DD

V

SS

CV

DD

V

SS

AEA8/

PCI_EEAI

RSV31

AED38

V

SS

AARDY

V

SS

AED36AED63

V

SS

DED22DED18DEA6

ABE5

AEA7

AED43

B

DED29 DED31DV

DD18

DED25

RSV22

DEA2 AED49 AED51

V

SS

DV

DD18

DED21DED16DEA7

A

DED28 DED30V

SS

DED24 DV

DD18MON

DEA3 AED62 AED53 DV

DD33

V

SS

DED20DED17DEODT1

16

DV

DD18

CV

DD

DEODT0

DEA8

CV

DD

V

SS

V

SS

DEA9

DEA10

DEA11

16

CV

DD

V

SS

V

SS

CV

DD

V

SS

CV

DD

C

D

E

F

G

H

J

K

L

M

N

P

B

A

TMS320C6454

www.ti.com

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Figure 2-4. C6454 Pin Map (Bottom View) [Quadrant C]

Copyright © 2006–2010, Texas Instruments Incorporated Device Overview 17

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A

D

E

F

G

H

J

K

L

M

N

P

13121110987654321

13121110987654321

RGRXD2

RGTXD3

DV

DD33

MTXD2

V

SS

MTXD0/

RMTXD0

CV

DDMON

MTXD6

V

SS

PREQ

/

GP[15]

PINTA/
GP[14]

MRXD2 MRXD3

MRXD0/

RMRXD0

V

SS

MTXD3MCOL

MRXD5

MTXD1/

RMTXD1

DV

DD15

MTXD4

MCRS/

RMCRSDV

PTRDY

MTXD7

MTCLK/

RMREFCLK

MDCLK

RGRXD3

DV

DD18

DED1

DSDDQS0

DSDDQM0 DED2

DSDDQS0

DED6

DED7

DED8

DED9

DED10

DSDDQM1

DSDDQS1

DED15

DED14

V

SS

RSV25

RSV35

RSV34

V

SS

DV

DD15

V

SS

V

SS

DV

DD15

V

SS

V

SS

DSDWE

DSDRAS

DSDCAS

V

SS

DED3

RSV29

DV

DD33

RGTXD0

RGTXD1

RGREFCLK

RGTXCTL

DV

DD15MON

RGRXD1 RSV18

RSV13

GMTCLK

MTXD5

DSDDQ

GATE0

DED0

DV

DD15

DED12 DV

DD18

DED5

RGRXD0

DV

DD33

V

SS

V

SS

V

SS

DV

DD33MONVSS

RSV21 DED13 DED4 V

SS

AV

DLL1

V

SSVREFHSTL

RGMDCLK RSV24

DSDDQ

GATE1

RGRXCTL V

SS

DV

DD15

RGTXC

RGRXC DSDDQS1 DV

DD18

DV

DD18

RSV14

DV

DD18

MRXD7 V

SS

CV

DD

RSV28 CV

DD

PCBE0

/

GP[2]

PCBE3 DV

DD33

MTXEN/

RMTXEN

V

SS

DV

DD33

V

SS

RGMDIO PLLV2 V

SS

DED11

DV

DD18

DV

DD18

MRXD4

MDIO

RGTXD2

B

DV

DD15

V

SS

DV

DD18

DV

DD18

RSV07 DV

DD18

CLKIN2DV

DD33

V

SS

V

SS

V

SS

V

SS

V

SS

C

V

SS

MRXDV

MRXER/

RMRXER

CV

DD

MRXD1/

RMRXD1

MRXD6MRCLK DV

DD15

V

SS

V

SS

14

DDR2

CLKOUT

V

REFSSTL

DSDCKE

DCE0

CV

DD

DDR2

CLKOUT

V

SS

V

SS

DV

DD18

CV

DD

15

DEA13

DBA0

DBA1

DBA2

V

SS

DEA12

CV

DD

DV

DD18

V

SS

V

SS

14 15

CV

DD

RSV04

V

SS

CV

DD

V

SS

CV

DD

RSV05

F

D

E

A

G

H

J

K

L

M

N

P

B

C

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

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Figure 2-5. C6454 Pin Map (Bottom View) [Quadrant D]

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TRST

IEEE Standard

1149.1

(JTAG)

Emulation

Reserved

Reset and
Interrupts

Control/Status

TDI

TDO

TMS

TCK

NMI

RESET

RSV03
RSV04

Clock/PLL1

and

PLL Controller

CLKIN1

EMU0
EMU1

SYSCLK4/GP[1]

(A)

EMU14
EMU15
EMU16

EMU17

RSV02

EMU18

RSV06
RSV07

RSV05

RSV77
RSV78

RSV76

•

•

•

•

•

•

RESETSTAT

CLKIN2

POR

PCI_EN

Peripheral

Enable/Disable

Clock/PLL2

PLLV2

PLLV1

A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.

TMS320C6454

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2.6 Signal Groups Description

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

A. This pin functions as GP[1] by default. For more details, see Section 3.

Figure 2-6. CPU and Peripheral Signals

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A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For

more details, see the Device Configuration section of this document.

C. These PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For more

details, see the Device Configuration section of this document.

GPIO

General-Purpose Input/Output 0 (GPIO) Port

CLKX1/GP[3]

(B)

PCBE0

/GP[2]

(C)

SYSCLK4/GP[1]

(A)

PREQ

/GP[15]

(C)

PINTA

/GP[14]

(C)

PRST

/GP[13]

(C)

PGNT

/GP[12]

(C)

FSX1/GP[11]

(B)

FSR1/GP[10]

(B)

DX1/GP[9]

(B)

DR1/GP[8]

(B)

GP[7]
GP[6]
GP[5]
GP[4]

CLKR1/GP[0]

(B)

Timers (64-Bit)

TINPL1

Timer 1

Timer 0

TOUTL1

TINPL0

TOUTL0

TMS320C6454

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Figure 2-7. Timers/GPIO Peripheral Signals

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ACE4

(A)

AECLKOUT

AED[63:0]

ACE3

(A)

ACE2

(A)

AEA[19:0]

AARDY

Data

Memory Map

Space Select

Address

Byte Enables

64

20

External

Memory I/F

Control

EMIFA (64-bit Data Bus)

AECLKIN

AHOLD
AHOLDA
ABUSREQ

Bus

Arbitration

ABE3
ABE2
ABE1
ABE0

ASWE/AAWE

DDR2CLKOUT

DED[31:0]

DCE0

DEA[13:0]

Data

Memory Map

Space Select

Address

Byte Enables

32

14

External

Memory I/F

Control

DDR2 Memoty Controller (32-bit Data Bus)

DSDCAS

DSDCKE

DDR2CLKOUT

DSDDQS[3:0]

DSDRAS
DSDWE

DSDDQS[3:0]

ABE7
ABE6
ABE5

ABE4

ACE5

(A)

Bank Address

ABA[1:0]

AR/W
AAOE/ASOE
ASADS/ASRE

Bank Address

DBA[2:0]

DEODT[1:0]

DSDDQGATE[0]

DSDDQM3
DSDDQM2

DSDDQM1
DSDDQM0

DSDDQGATE[1]
DSDDQGATE[2]
DSDDQGATE[3]

TMS320C6454

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Figure 2-8. EMIFA and DDR2 Memory Controller Peripheral Signals

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McBSPs

(Multichannel Buffered Serial Ports)

(B)

CLKX0
FSX0
DX0

CLKR0
FSR0

DR0

Transmit

McBSP0

Receive

Clock

CLKX1/GP[3]

FSX1/GP[11]

DX1/GP[9]

CLKR1/GP[0]

FSR1/GP[10]

DR1/GP[8]

Transmit

McBSP1

Receive

Clock

HHWIL/PCLK

HCNTL0/PSTOP

HCNTL1/PDEVSEL

Data

Register Select

Half-Word

Select

Control

HPI

(A)

(Host-Port Interface)

32

HAS/PPAR

HR/W

/PCBE2

HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HINT/PFRAME

(HPI16 ONL Y)

HD[15:0]/AD[15:0]

HD[31:16]/AD[31:16]

SCL

I2C

SDA

A. These HPI pins are muxed with the PCI peripheral. By default, these pins function as HPI. When the HPI is enabled, the number of HPI pins

used depends on the HPI configuration (HPI16 or HPI32). For more details on these muxed pins, see the Device Configuration section of this
document.

B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For

more details, see the Device Configuration section of this document.

CLKS

(SHARED)

TMS320C6454

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Figure 2-9. HPI/McBSP/I2C Peripheral Signals

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RGTXCTL, RGRXCTL

MRXER/RMRXER,

MRXDV,

MCRS/RMCRSDV,

MCOL,

MTXEN/RMTXEN

Ethernet MAC (EMAC) and MDIO

MDIO

MDCLK

MDIO

Clock

Clocks

Error Detect

and Control

Input/Output

Receive

RGMDIO

RGMDCLK

RGTXD[3:0]

A. RGMII signals are mutually exclusive to all other EMAC signals.

RGTXC,

RGRXC,

RGREFCLK

MTXD[7:2],

MTXD[1:0]/RMTXD[1:0]

Transmit

RGMII

(A)

GMII

RMII

MII

RGRXD[3:0]

MRXD[7:2],

MRXD[1:0]/RMRXD[1:0]

RGMII

(A)

GMII

RMII

MII

RGMII

(A)

GMII

RMII

MII

RGMII

(A)

GMII

RMII

MII

RGMII

(A)

GMII

RMII

MII

GMII

RMII

MII

RGMII

(A)

MTCLK/RMREFCLK,

MRCLK,

GMTCLK

Ethernet MAC

(EMAC)

TMS320C6454

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Copyright © 2006–2010, Texas Instruments Incorporated Device Overview 23

Figure 2-10. EMAC/MDIO [MII, GMII, RMII, and RGMII] Peripheral Signals

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HD[15:0]/AD[15:0]

HR/W

/PCBE2
HDS2/PCBE1
PCBE0/GP[2]

HHWIL/PCLK

HINT/PFRAME
PINTA/GP[14]

Data/Address

Arbitration

32

Clock

Control

PCI Interface

(A)

HAS/PPAR
PRST

/GP[13]

HRDY

/PIRDY
HCNTL0/PSTOP
PTRDY

PCBE3

PIDSEL
HCNTL1/PDEVSEL

HDS1/PSERR

Error

Command

Byte Enable

HCS/PPERR

PGNT/GP[12]
PREQ

/GP[15]

HD[31:16]/AD[31:16]

A. These PCI pins are muxed with the HPI or GPIO peripherals. By default, these signals function as HPI or GPIO or EMAC. For more

details on these muxed pins, see the Device Configuration section of this document.

TMS320C6454

SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Figure 2-11. PCI Peripheral Signals

www.ti.com

2.7 Terminal Functions

The terminal functions table (Table 2-3) identifies the external signal names, the associated pin (ball)
numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin
has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information
on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see

Section 3, Device Configuration.

Table 2-3. Terminal Functions

SIGNAL

NAME NO.

CLKIN1 N28 I IPD Clock Input for PLL1.
CLKIN2 G3 I IPD Clock Input for PLL2.
PLLV1 T29 A 1.8-V I/O supply voltage for PLL1
PLLV2 A5 A 1.8-V I/O supply voltage for PLL2

SYSCLK4/GP[1]

TMS AJ10 I IPU JTAG test-port mode select
TDO AH8 O/Z IPU JTAG test-port data out
TDI AH9 I IPU JTAG test-port data in
TCK AJ9 I IPU JTAG test-port clock

TRST AH7 I IPD

(4)

EMU0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD. For more detailed

information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7,

Pullup/Pulldown Resistors.
(3) These pins are multiplexed pins. For more details, see Section 3, Device Configuration.
(4) The C6454 DSP does not require external pulldown resistors on the EMU0 and EMU1 pins for normal or boundary-scan operation.

24 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated

(3)

AJ13 I/O/Z IPD

AF7 I/O/Z IPU Emulation pin 0

TYPE

(1)

IPD/IPU

(2)

CLOCK/PLL CONFIGURATIONS

SYSCLK4 is the clock output at 1/8 of the device speed (O/Z) or this pin can be
programmed as the GP1 pin (I/O/Z) [default].

JTAG EMULATION

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see

Section 7.18.3.1.1.

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

(4)

EMU1

AE11 I/O/Z IPU Emulation pin 1
EMU2 AG9 I/O/Z IPU Emulation pin 2
EMU3 AF10 I/O/Z IPU Emulation pin 3
EMU4 AF9 I/O/Z IPU Emulation pin 4
EMU5 AE12 I/O/Z IPU Emulation pin 5
EMU6 AG8 I/O/Z IPU Emulation pin 6
EMU7 AF12 I/O/Z IPU Emulation pin 7
EMU8 AF11 I/O/Z IPU Emulation pin 8
EMU9 AH13 I/O/Z IPU Emulation pin 9
EMU10 AD10 I/O/Z IPU Emulation pin 10
EMU11 AD12 I/O/Z IPU Emulation pin 11
EMU12 AE10 I/O/Z IPU Emulation pin 12
EMU13 AD8 I/O/Z IPU Emulation pin 13
EMU14 AF13 I/O/Z IPU Emulation pin 14
EMU15 AE9 I/O/Z IPU Emulation pin 15
EMU16 AH12 I/O/Z IPU Emulation pin 16
EMU17 AH10 I/O/Z IPU Emulation pin 17
EMU18 AE13 I/O/Z IPU Emulation pin 18

RESET AG14 I Device reset

NMI AH4 I IPD

RESETSTAT AE14 O Reset Status pin. The RESETSTAT pin indicates when the device is in reset
POR AF14 I Power on reset.
GP[7] AG2 I/O/Z IPD
GP[6] AG3 I/O/Z IPD
GP[5] AJ2 I/O/Z IPD
GP[4] AH2 I/O/Z IPD
PREQ/ GP[15] P2 I/O/Z

(5)

PINTA

/ GP[14] P3 I/O/Z
PRST/ GP[13] R5 I/O/Z
PGNT/ GP[12] R4 I/O/Z
FSX1/GP[11] AG4 I/O/Z IPD
FSR1/GP[10] AE5 I/O/Z IPD
DX1/GP[9] AG5 I/O/Z IPD
DR1/GP[8] AH5 I/O/Z IPD
CLKX1/GP[3] AF5 I/O/Z IPD
PCBE0/ GP[2] P1 I/O/Z
SYSCLK4/GP[1] AJ13 O/Z IPD
CLKR1/GP[0] AF4 I/O/Z IPD

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)

PCI_EN Y29 I IPD

TYPE

(1)

IPD/IPU

(2)

DESCRIPTION

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

Nonmaskable interrupt, edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin
is not used, it is recommended that the NMI pin be grounded versus relying on
the IPD.

General-purpose input/output (GPIO) pins (I/O/Z).

PCI peripheral pins or General-purpose input/output (GPIO) [15:12, 2] pins
(I/O/Z) [default]

PCI bus request (O/Z) or GP[15] (I/O/Z) [default]
PCI interrupt A (O/Z) or GP[14] (I/O/Z) [default]
PCI reset (I) or GP[13] (I/O/Z) [default]
PCI bus grant (I) or GP[12] (I/O/Z) [default]
PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z) [default]

McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]

GP[1] pin (I/O/Z). SYSCLK4 is the clock output at 1/8 of the device speed (O/Z)
or this pin can be programmed as a GP[1] pin (I/O/Z) [default].

PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
GP[15:8], or PCI peripherals. This pin works in conjunction with the
MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details,
see Section 3, Device Configuration).

(5) These pins function as open-drain outputs when configured as PCI pins.

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Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

HINT/PFRAME U3 I/O/Z Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z)
HCNTL1/PDEVSEL U4 I/O/Z

HCNTL0/PSTOP U5 I/O/Z

HHWIL/PCLK V3 I/O/Z order)

HR/W/PCBE2 T5 I/O/Z Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
HAS/PPAR T3 I/O/Z Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR U6 I/O/Z Host chip select (I) [default] or PCI parity error (I/O/Z)
HDS1/PSERR

(5)

U2 I/O/Z Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
HDS2/PCBE1 U1 I/O/Z Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
HRDY/PIRDY T4 I/O/Z Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z)
PREQ/ GP[15] P2 I/O/Z PCI bus request (O/Z) or GP[15] (I/O/Z) [default]

(6)

PINTA

/ GP[14] P3 I/O/Z PCI interrupt A (O/Z) or GP[14] (I/O/Z) default]
PRST/ GP[13] R5 I/O/Z PCI reset (I) or GP[13] (I/O/Z) [default]
PGNT/ GP[12] R4 I/O/Z or PCI bus grant (I) or GP[12] (I/O/Z)[default]
PCBE0/ GP[2] P1 I/O/Z PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z)[default]
PCBE3 P5 I/O/Z PCI command/byte enable 3 (I/O/Z). By default, this pin has no function.
PIDSEL R3 I PCI initialization device select (I). By default, this pin has no function.
PTRDY P4 I/O/Z PCI target ready (PRTDY) (I/O/Z). By default, this pin has no function.
HD31/AD31 AA3
HD30/AD30 AA5
HD29/AD29 AC4
HD28/AD28 AA4
HD27/AD27 AC5
HD26/AD26 Y1
HD25/AD25 AD2
HD24/AD24 W1
HD23/AD23 AC3
HD22/AD22 AE1
HD21/AD21 AD1
HD20/AD20 W2
HD19/AD19 AC1
HD18/AD18 Y2
HD17/AD17 AB1
HD16/AD16 Y3

TYPE

I/O/Z

(1)

IPD/IPU

(2)

DESCRIPTION

Host control - selects between control, address, or data registers (I) [default] or
PCI device select (I/O/Z)

Host control - selects between control, address, or data registers (I) [default] or
PCI stop (I/O/Z)

Host half-word select - first or second half-word (not necessarily high or low
[For HPI16 bus width selection only] (I) [default] or PCI clock (I)

Host-port data [31:16] pin (I/O/Z) [default] or PCI data-address bus [31:16]
(I/O/Z)

(6) These pins function as open-drain outputs when configured as PCI pins.
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Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

HD15/AD15 AB2
HD14/AD14 W4
HD13/AD13 AC2
HD12/AD12 V4
HD11/AD11 AF3
HD10/AD10 AE3
HD9/AD9 AB3
HD8/AD8 W5
HD7/AD7 AB4
HD6/AD6 Y4
HD5/AD5 AD3
HD4/AD4 Y5
HD3/AD3 AD4
HD2/AD2 W6
HD1/AD1 AB5
HD0/AD0 AE2

EMIFA (64-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

ABA1/EMIFA_EN V25 O/Z IPD EMIFA bank address control (ABA[1:0])

ABA0/DDR2_EN V26 O/Z IPD

ACE5 V27 O/Z IPU
ACE4 V28 O/Z IPU
ACE3 W26 O/Z IPU
ACE2 W27 O/Z IPU
ABE7 W29 O/Z IPU
ABE6 K26 O/Z IPU
ABE5 L29 O/Z IPU
ABE4 L28 O/Z IPU
ABE3 AA29 O/Z IPU
ABE2 AA28 O/Z IPU
ABE1 AA25 O/Z IPU
ABE0 AA26 O/Z IPU

AHOLDA N26 O IPU EMIFA hold-request-acknowledge to the host
AHOLD R29 I IPU EMIFA hold request from the host
ABUSREQ L27 O IPU EMIFA bus request output

EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

AECLKIN N29 I IPD clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin.

(1)

TYPE

I/O/Z Host-port data [15:0] pin (I/O/Z) [default] or PCI data-address bus [15:0] (I/O/Z)

IPD/IPU

(2)

• Active-low bank selects for the 64-bit EMIFA.
When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the
byte address.
For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and
0 of the byte address

DDR2 Memory Controller enable (DDR2_EN) [ABA0]
0 - DDR2 Memory Controller peripheral pins are disabled (default)
1 - DDR2 Memory Controller peripheral pins are enabled

EMIFA enable (EMIFA_EN) [ABA1]
0 - EMIFA peripheral pins are disabled (default)
1 - EMIFA peripheral pins are enabled

EMIFA memory space enables

• Enabled by bits 28 through 31 of the word address

• Only one pin is asserted during any external data access

Note: The C6454 device does not have ACE0 and ACE1 pins

EMIFA byte-enable control

• Decoded from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.

• Byte-write enables for most types of memory.

EMIFA (64-BIT) - BUS ARBITRATION

EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK4
Note: AECLKIN is the default for the EMIFA input clock.

DESCRIPTION

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Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

AECLKOUT V29 O/Z IPD EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK4) frequency]
AAWE/ASWE AB25 O/Z IPU
AARDY K29 I IPU Asynchronous memory ready input

AR/W W25 O/Z IPU Asynchronous memory read/write
AAOE/ASOE Y28 O/Z IPU Asynchronous/Programmable synchronous memory output-enable

ASADS/ASRE R26 O/Z IPU

AEA19/BOOTMODE3 N25 EMIFA external address (word address) (O/Z)
AEA18/BOOTMODE2 L26
AEA17/BOOTMODE1 L25
AEA16/BOOTMODE0 P26
AEA15/AECLKIN_SEL P27
AEA14/HPI_WIDTH R25
AEA13/LENDIAN R27 O/Z IPU
AEA12 R28

AEA11 T25 0 - AECLKIN (default mode)

(1)

TYPE

O/Z IPD

O/Z IPD

IPD/IPU

(2)

Asynchronous memory write-enable/Programmable synchronous interface
write-enable

Programmable synchronous address strobe or read-enable

• For programmable synchronous interface, the R_ENABLE field in the Chip
Select x Configuration Register selects between ASADS and ASRE:

– If R_ENABLE = 0, then the ASADS/ASRE signal functions as the

ASADS signal.

– If R_ENABLE = 1, then the ASADS/ASRE signal functions as the

ASRE signal.

EMIFA (64-BIT) - ADDRESS

Controls initialization of the DSP modes at reset (I) via pullup/pulldown resistors
[For more detailed information, see Section 3, Device Configuration.]
Note: If a configuration pin must be routed out from the device and 3-stated
(not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied
upon; TI recommends the use of an external pullup/pulldown resistor. For more
detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown
Resistors.

• Boot mode - device boot mode configurations (BOOTMODE[3:0]) [Note:
the peripheral must be enabled to use the particular boot mode.]

AEA[19:16]:
0000 - No boot (default mode)
0001 - Host boot (HPI)
0010 -Reserved
0011 - Reserved
0100 - EMIFA 8-bit ROM boot
0101 - Master I2C boot
0110 - Slave I2C boot
0111 - Host boot (PCI)
1000 thru 1111 - Reserved
For more detailed information on the boot modes, see Section 2.4, Boot
Sequence.
CFGGP[2:0] pins must be set to 000b during reset for proper operation of
the PCI boot mode.

• EMIFA input clock source select
Clock mode select for EMIFA (AECLKIN_SEL)

AEA15:
1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software

selectable via the Software PLL1 Controller. By default, SYSCLK4 is
selected as CPU/8 clock rate.

• HPI peripheral bus width (HPI_WIDTH) select
[Applies only when HPI is enabled; PCI_EN pin = 0]

AEA14:
0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0]
pins are used and the remaining HD[31:16] pins are reserved pins in the
Hi-Z state.)
1 - HPI operates as an HPI32.

• Device Endian mode (LENDIAN)
AEA13:

0 - System operates in Big Endian mode
1 - System operates in Little Endian mode(default)

Note: For proper C6454 device operation, the AEA12 and AEA11 pins must
be externally pulled down with a 1-kΩ resistor at device reset.

DESCRIPTION

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

AEA10/MACSEL1 M25
AEA9/MACSEL0 M27
AEA8/PCI_EEAI P25
AEA7 N27
AEA6/PCI66 U27
AEA5/MCBSP1_EN U28
AEA4/ [RGMII interface requires a 1.8-V or 1.5-V I/O supply]

SYSCLKOUT_EN

T28

AEA3 T27
AEA2/CFGGP2 T26
AEA1/CFGGP1 U26

AEA0/CFGGP0 U25

(1)

TYPE

IPD/IPU

O/Z IPD

(2)

DESCRIPTION

• EMAC/MDIO interface select bits (MACSEL[1:0])
There are two configuration pins — MACSEL[1:0] — to select the
EMAC/MDIO interface.
AEA[10:9]: MACSEL[1:0]

00 - 10/100 EMAC/MDIO MII Mode Interface (default)
01 - 10/100 EMAC/MDIO RMII Mode Interface
10 - 10/100/1000 EMAC/MDIO GMII Mode Interface
11 - 10/100/1000 with RGMII Mode Interface

• PCI I2C EEPROM Auto-Initialization (PCI_EEAI)
AEA8: PCI auto-initialization via external I2C EEPROM

If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be
pulled up.
0 - PCI auto-initialization through I2C EEPROM is disabled (default).
1 - PCI auto-initialization through I2C EEPROM is enabled.

• PCI Frequency Selection (PCI66)
[The PCI peripheral needs be enabled (PCI_EN = 1) to use this function]
Selects the PCI operating frequency of 66-MHz or 33-MHz PCI operating
frequency is selected at reset via the pullup/pulldown resistor on the PCI66
pin:

AEA6:
0 - PCI operates at 33 MHz (default).
1 - PCI operates at 66 MHz.
Note: If the PCI peripheral is disabled (PCI_EN = 0), this pin must not be
pulled up.

• McBSP1 Enable bit (MCBSP1_EN)
Selects which function is enabled on the McBSP1/GPIO muxed pins

AEA5:
0 - GPIO pin functions enabled (default).
1 - McBSP1 pin functions enabled.

• SYSCLKOUT Enable pin (SYSCLKOUT_EN)
Selects which function is enabled on the SYSCLK4/GP[1] muxed pin

AEA4:
0 - GP[1] pin function of the SYSCLK4/GP[1] pin enabled (default).
1 - SYSCLK4 pin function of the SYSCLK4/GP[1] pin enabled.

• Configuration GPI (CFGGP[2:0]) (AEA[2:0])
These pins are latched during reset and their values are shown in the
DEVSTAT register. These values can be used by software routines for boot
operations.

AEA3:
For proper C6454 device operation, the AEA3 pin must be pulled down to V
using a 1-kΩ resistor.

SS

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SPRS311F–APRIL 2006–REVISED SEPTEMBER 2010

Table 2-3. Terminal Functions (continued)

SIGNAL

NAME NO.

AED63 F25
AED62 A27
AED61 C27
AED60 C28
AED59 E27
AED58 D28
AED57 D27
AED56 F27
AED55 G25
AED54 G26
AED53 A28
AED52 F28
AED51 B28
AED50 G27
AED49 B27
AED48 G28
AED47 H25
AED46 J26
AED45 H26
AED44 J27
AED43 H27
AED42 J28
AED41 C29
AED40 J29
AED39 D29
AED38 J25
AED37 F29
AED36 F26
AED35 G29
AED34 K28
AED33 K25
AED32 K27
AED31 AA27
AED30 AG29
AED29 AB29
AED28 AC27
AED27 AB28
AED26 AC26
AED25 AB27
AED24 AC25
AED23 AB26
AED22 AD28

(1)

TYPE

I/O/Z IPU EMIFA external data

IPD/IPU

(2)

EMIFA (64-BIT) - DATA

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DESCRIPTION

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