Texas Instruments TMS320C6452 User Manual
TMS320C6452 DSP
Host Port Interface (HPI)
User's Guide
Literature Number: SPRUF87A
October 2007 – Revised May 2008
2 SPRUF87A – October 2007 – Revised May 2008
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Contents
Preface ........................................................................................................................................ 6
1 Introduction ......................................................................................................................... 9
1.1 Purpose of the Peripheral ................................................................................................ 9
1.2 Features .................................................................................................................... 9
1.3 Functional Block Diagram .............................................................................................. 10
1.4 Industry Standard(s) Compliance Statement ........................................................................ 11
1.5 Terminology Used in This Document ................................................................................. 11
2 Peripheral Architecture ....................................................................................................... 12
2.1 Clock Control ............................................................................................................. 12
2.2 Memory Map ............................................................................................................ 12
2.3 Signal Descriptions ...................................................................................................... 12
2.4 Pin Multiplexing .......................................................................................................... 12
2.5 Protocol Description ..................................................................................................... 12
2.6 Endianness Considerations ............................................................................................ 12
2.7 Architecture and Operation ............................................................................................. 14
2.8 Reset Considerations ................................................................................................... 31
2.9 Initialization ............................................................................................................... 32
2.10 Interrupt Support ......................................................................................................... 32
2.11 EDMA Event Support ................................................................................................... 34
2.12 Power Management ..................................................................................................... 34
2.13 Emulation Considerations .............................................................................................. 34
3 Registers ........................................................................................................................... 35
3.1 Peripheral Identification Register (PID) ............................................................................... 35
3.2 Power and Emulation Management Register (PWREMU_MGMT) ............................................... 36
3.3 Host Port Interface Control Register (HPIC) ......................................................................... 37
3.4 Host Port Interface Write Address Register (HPIAW) .............................................................. 39
3.5 Host Port Interface Read Address Register (HPIAR) ............................................................... 40
SPRUF87A – October 2007 – Revised May 2008 Table of Contents 3
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List of Figures
1 HPI Block Diagram ......................................................................................................... 11
2 Example of Host-Processor Signal Connections ....................................................................... 15
3 HPI Strobe and Select Logic .............................................................................................. 16
4 16-bit Multiplexed-Mode Host Read Cycle .............................................................................. 19
5 16-bit Multiplexed-Mode Host Write Cycle .............................................................................. 20
6 Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) .................................................... 21
7 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-bit Multiplexed Mode ........................... 22
8 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonauto-increment HPID Read Cycle) ........................................................... 22
9 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Auto-increment HPID Read Cycles) .............................................................. 23
10 HRDY Behavior During an HPIC Write Cycle in the 16-bit Multiplexed Mode ..................................... 23
11 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 1:
No Auto-incrementing) ..................................................................................................... 24
12 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 2:
Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 24
13 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 3:
Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 24
14 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode .......................... 25
15 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Non-auto-increment HPID Read Cycle) .......................................................... 25
16 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Auto-increment HPID Read Cycles) .............................................................. 26
17 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode ..................................... 26
18 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No
Auto-incrementing) ......................................................................................................... 27
19 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:
Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 27
20 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:
Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 28
21 FIFOs in the HPI ........................................................................................................... 29
22 Host-to-CPU Interrupt State Diagram.................................................................................... 32
23 CPU-to-Host Interrupt State Diagram.................................................................................... 33
24 Peripheral Identification Register (PID) .................................................................................. 35
25 Power and Emulation Management Register (PWREMU_MGMT) .................................................. 36
26 Host Port Interface Control Register (HPIC) – Owner (Host) Access Permissions................................ 37
27 Host Port Interface Control Register (HPIC)–Non-owner (DSP) Access Permissions ............................ 37
28 Host Port Interface Write Address Register (HPIAW) ................................................................. 39
29 Host Port Interface Read Address Register (HPIAR) ................................................................. 40
List of Figures4 SPRUF87A – October 2007 – Revised May 2008
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List of Tables
1 HPI Pins ..................................................................................................................... 13
2 Options for Connecting Host and HPI Data Strobe Pins .............................................................. 17
3 Access Types Selectable With the HCNTL Signals ................................................................... 17
4 Cycle Types Selectable With the HCNTL and HR/ W Signals ........................................................ 18
5 HPI Registers Relative to Base Address 0200 0030h ................................................................. 35
6 Peripheral Identification Register (PID) Field Descriptions ........................................................... 35
7 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ............................ 36
8 Host Port Interface Control Register (HPIC) Field Descriptions ..................................................... 38
9 Host Port Interface Write Address Register (HPIAW) Field Descriptions ........................................... 39
10 Host Port Interface Read Address Register (HPIAR) Field Descriptions ........................................... 40
SPRUF87A – October 2007 – Revised May 2008 List of Tables 5
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About This Manual
Notational Conventions
Preface
SPRUF87A – October 2007 – Revised May 2008
Read This First
This document describes the features and operation of the host port interface (HPI) in the TMS320C6452
Digital Signal Processor (DSP).
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3
port gigabit switch.
TMS320C6452 DSP
Related Documents From Texas Instruments
The following documents describe the TMS320C6452 Digital Signal Processor (DSP). Copies of these
documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box
provided at www.ti.com .
Data Manual—
SPRS371 — TMS320C6452 Digital Signal Processor Data Manual describes the signals, specifications
and electrical characteristics of the device.
CPU—
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
Reference Guides—
SPRUF85 — C6452 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory
controller in the TMS320C6452 Digital Signal Processor (DSP). The DDR2/mDDR memory
controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices and
standard Mobile DDR SDRAM devices.
6 Preface SPRUF87A – October 2007 – Revised May 2008
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TMS320C6452 DSP
SPRUF86 — C6452 Peripheral Component Interconnect (PCI) User's Guide describes the peripheral
component interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP). The PCI
port supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave bus
interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. This
architecture allows for both PCI master and slave transactions, while keeping the EDMA channel
resources available for other applications.
SPRUF87 — C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface
(HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which
a host processor can directly access the CPU memory space. The host device functions as a
master to the interface, which increases ease of access. The host and CPU can exchange
information via internal or external memory. The host also has direct access to memory-mapped
peripherals. Connectivity to the CPU memory space is provided through the enhanced direct
memory access (EDMA) controller.
SPRUF89 — C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320C6452
Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface for
connecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial bus
where transmit and receive operations occur separately and simultaneously without interference.
SPRUF90 — C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer in the
C6452 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers, or a watchdog timer.
SPRUF91 — C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes the
multichannel audio serial port (McASP) in the C6452 Digital Signal Processor (DSP). The McASP
functions as a general-purpose audio serial port optimized for the needs of multichannel audio
applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated
Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
SPRUF92 — C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface
(SPI) in the C6452 Digital Signal Processor (DSP). This reference guide provides the specifications
for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length
shift register, used for high speed communication between external peripherals or other DSPs.
SPRUF93 — C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide
describes the universal asynchronous receiver/transmitter (UART) peripheral in the C6452 Digital
Signal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUF94 — C6452 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the
inter-integrated circuit (I2C) peripheral in the C6452 Digital Signal Processor (DSP). The I2C
peripheral provides an interface between the DSP and other devices compliant with the I2C-bus
specification and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2C
peripheral. This document assumes the reader is familiar with the I2C-bus specification.
SPRUF95 — C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes the
general-purpose input/output (GPIO) peripheral in the C6452 Digital Signal Processor (DSP). The
GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an input, you can detect the state of the input by reading the state of
an internal register. When configured as an output, you can write to an internal register to control
the state driven on the output pin.
SPRUF96 — C6452 DSP Telecom Serial Interface Port (TSIP) User's Guide is a multi-link serial
interface consisting of a maximum of two transmit data signals (or links), two receive data signals
(or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP offers single
channel of timeslot data management and single DMA capability that allow individual timeslots to
be selectively processed.
SPRUF87A – October 2007 – Revised May 2008 Read This First 7
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TMS320C6452 DSP
SPRUF97 — TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes
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the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal
Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet
communication and can be configured as an ethernet switch. It provides the serial gigabit media
independent interface (SGMII), the management data input output (MDIO) for physical layer device
(PHY) management.
Read This First8 SPRUF87A – October 2007 – Revised May 2008
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1 Introduction
The host port interface (HPI) provides a parallel port interface through which an external host processor
can directly access the TMS320C6452 processor's resources (configuration and program/data memories).
The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface.
The HPI enables a host device and the C6452 processor to exchange information via internal or external
memory. Dedicated address (HPIA) and data (HPID) registers within the HPI provide the data path
between the external host interface and the processor resources. An HPI control register (HPIC) is
available to the host and the CPU for various configuration and interrupt functions.
1.1 Purpose of the Peripheral
The HPI enables an external host processor (host) to directly access program/data memory on the
processor using a parallel interface. The primary purpose is to provide a mechanism to move data to and
from the processor. In addition to data transfer, the host can also use the HPI to bootload the processor
by downloading program and data information to the processor's memory after power-up.
User's Guide
SPRUF87A – October 2007 – Revised May 2008
Host Port Interface (HPI)
1.2 Features
The HPI supports the following features:
• Multiplexed address/data
• Dual 16-bit halfword cycle access (internal data word is 32-bits wide)
• 32-bit-wide host data bus interface
• Internal data bursting using 8-word read and write, first-in first-out (FIFO) buffers
• HPI control register (HPIC) accessible by both the DSP CPU and the external host
• HPI address register (HPIA) accessible by both the DSP CPU and the external host
• Separate HPI address registers for read (HPIAR) and write (HPIAW) with configurable option for
operating as a single HPI address register
• HPI data register (HPID)/FIFOs providing data-path between external host interface and CPU
resources
• Multiple strobes and control signals to allow flexible host connection
• Asynchronous HRDY output to allow the HPI to insert wait states to the host
• Software control of data prefetching to the HPID/FIFOs
• Processor-to-Host interrupt output signal controlled by HPIC accesses
• Host-to-Processor interrupt controlled by HPIC accesses
• Memory-mapped peripheral identification register (PID)
• Bus holders on host data and address buses (these are actually external to HPI module)
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 9
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Introduction
1.3 Functional Block Diagram
Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and the
processor internal memory (right side of figure). Host activity is asynchronous to the internal processor
clock that drives the HPI. The host functions as a master to the HPI. When HPI resources are temporarily
busy or unavailable, the HPI communicates this to the host by de-asserting the HPI ready ( HRDY) output
signal.
The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the host
drives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that the
bus can then be used for data.
The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 mode
with the help of HPI_WIDTH device configuration pin at reset.
-16-bit multiplexed mode (HPI16): The HPI is called HPI16 when operating as a 16-bit wide host port. This
mode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this mode, a
16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive 16-bit transfers
to provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is used on the HPI16 to
identify the first or second half word of a word transfer.
-32-bit multiplexed mode (HPI32): HPI operates in this mode as a 32-bit wide host port. This mode is
selected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bit
data bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.
The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers for
read accesses and write accesses(for details, see Section 2.7.1 ).
A control register (HPIC) is accessible by the CPU and the host. The CPU uses HPIC to send an interrupt
request to the host, to clear an interrupt request from the host, and to configure and monitor the HPI.
Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID).
Data arriving from the host is held in HPID until the data can be stored elsewhere in the processor. Data
to be sent to the host is held in HPID until the HPI is ready to perform the transfer. When address
auto-incrementing is used, read and write FIFOs are used to store burst data. If auto-incrementing is not
used, the FIFO memory acts as a single register (only one location is used).
Note: To manage data transfers between HPID and the internal memory, the DSP contains dedicated HPI
DMA logic. The HPI DMA logic is not programmable. It automatically stores or fetches data using the
address provided by the host. The HPI DMA logic is independent of the EDMA3 controller included in the
DSP.
In the DSP system, master and slave peripherals communicate with each other via the Switched Central
Resource (SCR). By definition, master peripherals are capable of initiating read and write transfers in the
system and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely on
the EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directly
communicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for its
data transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specific
data manual for a list of resources accessible through the HPI.
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HPID
R/WFIFOs
HPIA
Increment
HPIC
Access
type
HD[15:0]
HDS1,HDS2
HR/W
HAS
HCNTL0
HCNTL1
HINT
HRDY
HPI
Host
Data
Address
orI/O
R/W
Data
strobes
IRQ
Ready
CPU
HCSChipselect
Processor
memory
HPIDMA
logic
Processor
HHWIL
high
Logic
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Introduction
Figure 1. HPI Block Diagram
1.4 Industry Standard(s) Compliance Statement
The HPI is not an industry standard interface that is developed and monitored by an international
organization. It is a generic parallel interface that can be configured to gluelessly interface, a variety of
parallel devices.
1.5 Terminology Used in This Document
The following is a brief explanation of some terms used in this document:
Term Meaning
CPU DSP CPU
host External host device
HPI DMA logic Logic used to communicate between the HPI and the DMA system that moves data to
processor the entire digital media system-on-chip
and from memory. This is independent of the EDMA system on the processor
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 11
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Peripheral Architecture
2 Peripheral Architecture
2.1 Clock Control
The HPI clock is derived from SYSCLK2, which is the PLL1 clock divided by 6. For detailed information on
the PLLs and clock distribution on the processor, see the Subsystem User's Guide.
2.2 Memory Map
The HPI can be used by the host to access the following processor resources:
• HPI configuration registers
• Most on-chip device memory, peripherals, and memory-mapped registers (see Section 4, System
Interconnect, in the device-specific data manual for more detailed information)
• DDR2 Memory Controller configuration register file and memory address ranges
• Power and Sleep Controller (PSC) registers
• PLL1 and PLL2 registers
Consult the device-specific data manual for the memory address ranges of the above resources.
2.3 Signal Descriptions
Table 1 shows the a description of the HPI signals.
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2.4 Pin Multiplexing
2.5 Protocol Description
2.6 Endianness Considerations
On the C6452 extensive pin multiplexing is used to accommodate the largest number of peripheral
functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. UHPI pins are multiplexed with
PCI pins' functionality. The configuration pin UHPIEN is to be set to 1 to enable UHPI. Refer to the
device-specific data manual to determine how pin multiplexing affects the HPI.
The HPI does not conform to any industry standard protocol. Details on the nature of address, data and
control transactions are found in the following sections.
The HPI operation is independent of the C6452 endianness mode; therefore, there are no endianness
considerations for the HPI.
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Peripheral Architecture
Table 1. HPI Pins
Pin Type Host Connection Function
HCNTL[1:0] I Address or control pins HPI access control inputs. The HPI latches the logic levels of these pins
HCS I Chip select pin HPI chip select. HCS must be low for the HPI to be selected by the host.
HR/ W I R/W strobe pin HPI read/write. On the falling edge of internal HSTRB, HR/ W indicates
HHWIL I Address or control pins Halfword identification line. The host uses HHWIL to identify the first
HAS I None Address strobe. Connect to logic high.
HINT O/Z Interrupt pin Host Interrupt. The CPU can interrupt the host processor by writing a 1
HDS1 and I Read strobe and write HPI data strobe pins. These pins are used for strobing data in and out of
HDS2 strobe pins or any data the HPI (for data strobing details, see Section 2.7.4 ). The direction of the
strobe pin data transfer depends on the logic level of the HR/ W signal. The HDS
HD[31:0] I/O/Z Data bus HPI data bus. The HPI data bus carries the address and data to/from the
HD[15:0] HPI. HD[31:0] applies to HPI32 and HD[15:0] applies to HPI16.
HRDY O/Z Asynchronous ready pin HPI-ready signal. When the HPI drives HRDY low, the host has
HINT O/Z Interrupt pin The DSP can interrupt the host processor by writing a 1 to the HINT bit of
on the falling edge of internal HSTRB (for details about internal HSTRB,
see Section 2.7.4 ). The four binary states of these pins determine the
access type of the current transfer (HPIC, HPIA, HPID with and without
auto-incrementing).
HCS can be kept low between accesses. HCS normally precedes an
active HDS (data strobe) signal, but can be connected to an HDS pin for
simultaneous select and strobe activity.
whether the current access is to be a read or write operation. Driving
HR/ W high indicates the transfer is a read from the HPI, while driving
HR/ W low indicates a write to the HPI.
and second halfwords of the host cycle. HHWIL must be driven low for the
first halfword and high for the second halfword.
to the HINT bit of HPIC. Before subsequent HINT interrupts can occur,
the host must acknowledge interrupts by writing a 1 to the HINT bit. This
pin is active-low (that is, when an interrupt is asserted from the host, the
state of this signal is low) and inverted from the HINT bit value in HPIC.
signals are also used to latch control information on the falling edge.
During an HPID write access, data is latched into the HPID register on the
rising edge of HDS. During read operations, these pins act as
output-enable pins of the host data bus.
permission to complete the current host cycle. When the HPI drives
HRDY high, the HPI is not ready for the current host cycle to complete.
HPIC. Before subsequent HINT interrupts can occur, the host must clear
previous interrupts by writing a 1 to the HINT bit. This pin is active-low
and inverted from the HINT bit value in HPIC.
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 13
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