查询SM320C6413GTS400供应商
TMS320C6413, TMS320C6410
Fixed-Point Digital Signal
Processors
Data Manual
Literature Number: SPRS247E
April 2004 − Revised May 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data manual revision history highlights the technical changes made to the SPRS247D device-specific data
manual to make it an SPRS247E revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6413 and
TMS320C6410 devices, have been incorporated.
PAGE(s)
NO.
63 Terminal Functions table:
Host-port data [7:0] pins (I/O/Z) description:
Changed sentence from “Host-Port bus width user-configurable at device reset via a 10-kW resistor pullup/pulldown resistor
on the HD5 pin (I):“ to “Host-Port bus width user-configurable at device reset via a 1-kW pullup/pulldown resistor on the HD5
pin (I):“
78 I2C section:
Updated/added “For more detailed information...”
90 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature:
I
Low-level output current, TEST CONDITIONS:
OH,
Moved/added HPI to “Timer, TDO, GPIO, McBSP”
ADDS/CHANGES/DELETES
paragraph
April 2004 − Revised May 2005 SPRS247E
3
Contents
4
April 2004 − Revised May 2005SPRS247E
Contents
Section Page
1 Features 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Overview 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 GTS and ZTS BGA Packages (Bottom View) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Description 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Device Characteristics 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Functional Block Diagram 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 CPU (DSP Core) Description 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Memory Map Summary 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 L2 Architecture Expanded 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Peripheral Register Descriptions 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 EDMA Channel Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Interrupt Sources and Interrupt Selector 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Signal Groups Description 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Device Configurations 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Device Configuration at Device Reset 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Peripheral Configuration at Device Reset 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Peripheral Selection After Device Reset 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Configuration Lock 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Device Status Register Description 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 JTAG ID Register Description 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Multiplexed Pins 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Debugging Considerations 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Configuration Examples 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Terminal Functions 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Development Support 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Device Support 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 Device and Development-Support Tool Nomenclature 68. . . . . . . . . . . . . . . . . . . . .
3.12.2 Documentation Support 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Peripherals Detailed Description (Device-Specific) 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Clock PLL and Oscillator 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Host-Port Interface (HPI) Peripheral 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Multichannel Audio Serial Port (McASP) Peripheral 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 McASP Block Diagram 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 I2C 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 General-Purpose Input/Output (GPIO) 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Power-Down Modes Logic 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 Triggering, Wake-up, and Effects 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 C64x Power-Down Mode with an Emulator 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Power-Supply Sequencing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Power-Supply Design Considerations 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Power-Supply Decoupling 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Peripheral Power-Down Operation 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
5
April 2004 − Revised May 2005 SPRS247E
Section Page
4.10 IEEE 1149.1 JTAG Compatibility Statement 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 EMIF Device Speed 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Bootmode 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Reset 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Device Electrical Specifications 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range 89. . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Recommended Clock and Control Signal Transition Behavior 90. . . . . . . . . . . . . . . . . . . . . . . . . .
6 Parameter Information 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Signal Transition Levels 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Signal Transition Rates 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Timing Parameters and Board Routing Analysis 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Peripheral Electrical Specifications 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Input and Output Clocks 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Asynchronous Memory Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Programmable Synchronous Interface Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Synchronous DRAM Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 HOLD
/HOLDA Timing 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 BUSREQ Timing 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Reset Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 External Interrupt Timing 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Multichannel Audio Serial Port (McASP) Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Inter-Integrated Circuits (I2C) Timing 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Host-Port Interface (HPI) Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Multichannel Buffered Serial Port (McBSP) Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Timer Timing 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 General-Purpose Input/Output (GPIO) Port Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 JTAG Test-Port Timing 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Data 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Thermal Data 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Packaging Information 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
6
April 2004 − Revised May 2005SPRS247E
List of Figures
Figure Page
2−1 GTS and ZTS BGA Packages (Bottom View) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Functional Block Diagram 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 TMS320C64xE CPU (DSP Core) Data Paths 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 TMS320C6413 L2 Architecture Memory Configuration 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 TMS320C6410 L2 Architecture Memory Configuration 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 CPU and Peripheral Signals 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Peripheral Signals 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000] 46. . . . . . . . . . . . . . . . . .
3−2 Peripheral Enable/Disable Flow Diagram 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses 49. . . . . . . .
3−4 Device Status Register (DEVSTAT) Description − 0x01B3 F004 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 JTAG ID Register Description − TMS320C6413/C6410 Register Value − 0x0007 902F 51. . . . . . . . . . . .
3−6 Configuration Example A
(HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO) 54. . . . . . . . . . . . . . . . . . . . . . . .
3−7 TMS320C6413/C6410 DSP Device Nomenclature 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 72. . . . . . . . . . . . . . . . . . . . . .
4−2 McASP0 and McASP1 Configuration 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 I2Cx Module Block Diagram 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Power-Down Mode Logic† 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 PWRD Field of the CSR Register 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Schottky Diode Diagram 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Test Load Circuit for AC Timing Measurements 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Input and Output Voltage Reference Levels for AC Timing Measurements 91. . . . . . . . . . . . . . . . . . . . . .
6−3 Rise and Fall Transition Time Voltage Reference Levels 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Board-Level Input/Output Timings 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 CLKIN Timing 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 CLKOUT4 Timing 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 CLKOUT6 Timing 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 AECLKIN Timing for EMIFA 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−5 AECLKOUT1 Timing for the EMIFA Module 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6 AECLKOUT2 Timing for the EMIFA Module 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−7 Asynchronous Memory Read Timing for EMIFA 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−8 Asynchronous Memory Write Timing for EMIFA 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
7
April 2004 − Revised May 2005 SPRS247E
7−9 Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2) 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10 Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0) 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−11 Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1) 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−12 SDRAM Read Command (CAS Latency 3) for EMIFA 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−13 SDRAM Write Command for EMIFA 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−14 SDRAM ACTV Command for EMIFA 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−15 SDRAM DCAB Command for EMIFA 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−16 SDRAM DEAC Command for EMIFA 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−17 SDRAM REFR Command for EMIFA 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−18 SDRAM MRS Command for EMIFA 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−19 SDRAM Self-Refresh Timing for EMIFA 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−20 HOLD
/HOLDA Timing for EMIFA 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−21 BUSREQ Timing for EMIFA 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−22 Reset Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−23 External/NMI Interrupt Timing 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−24 McASP Input Timings 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−25 McASP Output Timings 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−26 I2C Receive Timings 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−27 I2C Transmit Timings 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−28 HPI16 Read Timing (HAS Not Used, Tied High) 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−29 HPI16 Read Timing (HAS Used) 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−30 HPI16 Write Timing (HAS Not Used, Tied High) 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−31 HPI16 Write Timing (HAS Used) 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−32 HPI32 Read Timing (HAS Not Used, Tied High) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−33 HPI32 Read Timing (HAS Used) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−34 HPI32 Write Timing (HAS Not Used, Tied High) 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−35 HPI32 Write Timing (HAS Used) 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−36 McBSP Timing 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−37 FSR Timing When GSYNC = 1 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−38 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 128. . . . . . . . . . . . . . . . . . . . . . . . . .
7−39 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 129. . . . . . . . . . . . . . . . . . . . . . . . . .
7−40 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 130. . . . . . . . . . . . . . . . . . . . . . . . . .
7−41 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 131. . . . . . . . . . . . . . . . . . . . . . . . . .
7−42 Timer Timing 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−43 GPIO Port Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−44 JTAG Test-Port Timing 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
8
April 2004 − Revised May 2005SPRS247E
List of Tables
Table Page
2−1 Characteristics of the C6413 and C6410 Processors 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 TMS320C6413/C6410 Memory Map Summary 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 EMIFA Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 L2 Cache Registers (C64x) 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Quick DMA (QDMA) and Pseudo Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 EDMA Registers (C64x) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 EDMA Parameter RAM (C64x) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Interrupt Selector Registers (C64x) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Device Configuration Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 McBSP 0 Registers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 McBSP 1 Registers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 Timer 0 Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Timer 1 Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Timer 2 Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 HPI Registers 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 GP0 Registers 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 McASP0 and McASP1 Control Registers 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 McASP0 Data Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−19 McASP1 Data Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−20 I2C0 and I2C1 Registers 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−21 TMS320C6413/C6410 EDMA Channel Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−22 C6413/C6410 DSP Interrupts 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS) 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 TOUT0/HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins) 45. . . . . . . . . . .
3−3 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions 47. . . . . . . . . . . . . . . . . . . . . . .
3−4 PCFGLOCK Register Selection Bit Descriptions − Read Accesses 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 PCFGLOCK Register Selection Bit Descriptions − Write Accesses 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Device Status (DEVSTAT) Register Selection Bit Descriptions 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 JTAG ID Register Selection Bit Descriptions 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 C6413/C6410 Device Multiplexed Pins 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Terminal Functions 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 TMS320C6413 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −500 Devices 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −400 Devices 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Crystal and Tank Circuit Recommendations 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Characteristics of the Power-Down Modes 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Board-Level Timing Example 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT) 93. . . . . . . . . . . . . . .
Tables
9
April 2004 − Revised May 2005 SPRS247E
Table Page
7−2 Timing Requirements for CLKIN 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 94. . . . . . . . . . . . . .
7−4 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 94. . . . . . . . . . . . . .
7−5 Timing Requirements for AECLKIN for EMIFA 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1
for the EMIFA Module 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−7 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2
for the EMIFA Module 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−8 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 97. . . . . . . . . . . . . . . . . . . . .
7−9 Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module 100. . . . . . .
7−11 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous
Interface Cycles for EMIFA Module 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−12 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . .
7−13 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−14 Timing Requirements for the HOLD
/HOLDA Cycles for EMIFA Module 110. . . . . . . . . . . . . . . . . . . . . . . .
7−15 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−16 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ
Cycles for EMIFA Module 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−17 Timing Requirements for Reset 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−18 Switching Characteristics Over Recommended Operating Conditions During Reset 112. . . . . . . . . . . . .
7−19 Timing Requirements for External Interrupts 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−20 Timing Requirements for McASP 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−21 Switching Characteristics Over Recommended Operating Conditions for McASP 115. . . . . . . . . . . . . . .
7−22 Timing Requirements for I2C Timings 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−23 Switching Characteristics for I2C Timings 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−24 Timing Requirements for Host-Port Interface Cycles 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−25 Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−26 Timing Requirements for McBSP 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−27 Switching Characteristics Over Recommended Operating Conditions for McBSP 126. . . . . . . . . . . . . . .
7−28 Timing Requirements for FSR When GSYNC = 1 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−29 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−30 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−31 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−32 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−33 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−34 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−35 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
10
April 2004 − Revised May 2005SPRS247E
7−36 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−37 Timing Requirements for Timer Inputs 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−38 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 132. . . . . . . . .
7−39 Timing Requirements for GPIO Inputs 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−40 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs 133. . . . . . . . .
7−41 Timing Requirements for JTAG Test Port 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−42 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port 134. . . . . . . .
8−1 Thermal Resistance Characteristics (S-PBGA Package) [GTS] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 Thermal Resistance Characteristics (S-PBGA Package) [ZTS] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Features
Features
High-Performance Fixed-Point Digital
D
Signal Processor (TMS320C6413/C6410)
− TMS320C6413
− 2-ns Instruction Cycle Time
− 500-MHz Clock Rate
− 4000 MIPS
− TMS320C6410
− 2.5-ns Instruction Cycle Time
− 400-MHz Clock Rate
− 3200 MIPS
− Eight 32-Bit Instructions/Cycle
− Fully Software-Compatible With C64x™
− Extended Temperature Devices Available
D VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
D VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache [C6413]
(Flexible RAM/Cache Allocation)
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [C6410]
(Flexible RAM/Cache Allocation)
D Endianess: Little Endian, Big Endian
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1024M-Byte Total Addressable External
Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D Host-Port Interface (HPI) [32-/16-Bit]
D Two Multichannel Audio Serial Ports
(McASPs) - with Six Serial Data Pins each
D Two Inter-Integrated Circuit (I
− Additional GPIO Capability
2
C) Buses
D Two Multichannel Buffered Serial Ports
D Three 32-Bit General-Purpose Timers
D Sixteen General-Purpose I/O (GPIO) Pins
D Flexible PLL Clock Generator
D On-Chip Fundamental Oscillator
D IEEE-1149.1 (JTAG
Boundary-Scan-Compatible
†
)
D 288-Pin Ball Grid Array (BGA) Packages
(GTS and ZTS Suffixes), 1.0-mm Ball Pitch
D 0.13-µm/6-Level Cu Metal Process (CMOS)
D 3.3-V I/Os, 1.2-V Internal
VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
April 2004 − Revised May 2005 SPRS247E
11
Functional Overview
2 Functional Overview
2.1 GTS and ZTS BGA Packages (Bottom View)
GTS and ZTS 288-PIN BALL GRID ARRAY (BGA) PACKAGES
( BOTTOM VIEW )
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21
19
17
15
13
11
5
31
4
2
9
10
876
14
12
18
16
22
20
Figure 2−1. GTS and ZTS BGA Packages (Bottom View)
12
April 2004 − Revised May 2005SPRS247E
2.2 Description
The TMS320C64x™ DSPs (including the TMS320C6413, TMS320C6410 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6413
and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance,
advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas
Instruments (TI). The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system
costs for telecom, medical, industrial, office, and photo lab equipment. The C64x™ is a code-compatible
member of the C6000™ DSP platform.
With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410
device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device
also provides excellent value for packet telephony and for other cost−sensitive applications demanding high
performance.
The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The C6413 can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4000 MMACS. The C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000™ DSP platform devices.
Description
The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit
memory space that is shared between program and data space [for C6413 device] and the Level 2
memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for
C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The
peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus
modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a
user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output
port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory
interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all six serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I
2
S)
format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously, with a single RAM containing the full implementation of user data and
channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
April 2004 − Revised May 2005 SPRS247E
13
Device Characteristics
Not all peripherals pins
Confi
The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
2.3 Device Characteristics
Table 2−1, provides an overview of the C6413 and C6410 DSPs. The tables show significant features of the
C6413 and C6410 devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and
the package type with pin count.
Table 2−1. Characteristics of the C6413 and C6410 Processors
HARDWARE FEATURES C6413 AND C6410
EMIFA (32-bit bus width)
(clock source = AECLKIN, CLKOUT4, or CLKOUT6)
Peripherals
Not all peripherals pins
are available at the
same time (For more
detail, see the Device
guration section).
On-Chip Memory
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz
Cycle Time ns
Voltage
PLL Options CLKIN frequency multiplier
BGA Package 23 x 23 mm 288-Pin Flip-Chip Plastic BGA (GTS and ZTS)
Process Technology µm 0.13 µm
Product Status
†
On this C64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
‡
EDMA (64 independent channels) 1
McASPs (use Peripheral Clock and AUXCLK) 2
I2Cs (use Peripheral Clock) 2
HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32)
McBSPs
(internal clock source = CPU/4 clock frequency)
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
General-Purpose Input/Output Port (GP0) 16
Size (Bytes)
16K-Byte (16KB) L1 Program (L1P) Cache
Organization
Core (V) 1.2 V
I/O (V) 3.3 V
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
16KB L1 Data (L1D) Cache
256KB Unified Mapped RAM/Cache (L2) [C6413]
128KB Unified Mapped RAM/Cache (L2) [C6410]
2 ns (C6413-500, C6413 A−500)
[500 MHz CPU, 100 MHz EMIF
2.5 ns (C6410-400, C6410 A−400)
[400 MHz CPU, 100 MHz EMIF†]
Bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16,
x18, x19, x20, x21, x22, and x24
1
2
3
288K (C6413)
160K (C6410)
500 (C6413)
400 (C6410)
PD
†
]
14
April 2004 − Revised May 2005SPRS247E
2.3.1 Functional Block Diagram
Figure 2−2 shows the functional block diagram of the C6413/C6410 device.
Functional Block Diagram
SDRAM
SBSRAM
ZBT SRAM
FIFO
SRAM
ROM/FLASH
I/O Devices
32
EMIF A
L1P Cache
Direct-Mapped
16K Bytes Total
TMS320C6413/C6410
Timer 2
Timer 1
Timer 0
McBSP0
McBSP1
McASP0
McASP1
and
HPI16
or
Enhanced
DMA
Controller
(edma)
L2
Cache
Memory
256KBytes
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A Register File
A31−A16
A15−A0
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
§
C64x DSP Core
Control
Registers
Control
Logic
Data Path B
B Register File
B31−B16
B15−B0
L1D Cache 2-Way Set-Associative
16K Bytes Total
Test
Advanced
In-Circuit
Emulation
Interrupt
Control
HPI32
I2C0
I2C1
16
16
†
McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
‡
GP0[15:8] pins are muxed with the HPI HD[15:8] pins and GP0[2:1] pins are muxed with CLKOUT6 and CLKOUT4,
respectively.
§
Note: the C6413 device has 256K-Bytes L2 Cache Memory; the C6410 device has only 128K-Bytes L2 Cache Memory.
GP0
GP0
‡
OSCILLATOR
and PLL
(x1, x5 − x12, x16,
x18, x19 − x22, x24)
Boot Configuration
Power-Down
Logic
Figure 2−2. Functional Block Diagram
April 2004 − Revised May 2005 SPRS247E
15
CPU (DSP Core) Description
2.4 CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x™ VelociTI.2™ extensions add enhancements to the TMS320C62x™ DSP
VelociTI™ architecture. These enhancements include:
• Register file enhancements
• Data path extensions
• Quad 8-bit and dual 16-bit extensions with data flow enhancements
• Additional functional unit hardware
• Increased orthogonality of the instruction set
• Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW architecture, the
C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 2−3]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
16
April 2004 − Revised May 2005SPRS247E
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x™ DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x™/TMS320C67x™ DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x™ DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
• TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
• TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
April 2004 − Revised May 2005 SPRS247E
17
CPU (DSP Core) Description
ST1b (Store Data)
ST1a (Store Data)
Data Path A
LD1b (Load Data)
LD1a (Load Data)
DA1 (Address)
32 MSBs
32 LSBs
32 MSBs
32 LSBs
src1
.L1
src2
long dst
long src
long src
long dst
src1
.S1
src2
long dst
long dst
src1
.M1
src2
src2
src1
.D1
src2
dst
dst
dst
dst
dst
8
8
8
8
Register
File A
(A0−A31)
See Note A
See Note A
2X
Data Path B
DA2 (Address)
LD2a (Load Data)
LD2b (Load Data)
ST2a (Store Data)
ST2b (Store Data)
32 LSBs
32 MSBs
32 MSBs
32 LSBs
src2
.D2
src1
src2
src1
.M2
long dst
src2
.S2
src1
long dst
long src
long src
long dst
src2
.L2
src1
dst
dst
dst
dst
1X
See Note A
See Note A
Register
File B
(B0− B31)
8
8
8
8
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 2−3. TMS320C64x™ CPU (DSP Core) Data Paths
18
April 2004 − Revised May 2005SPRS247E
2.5 Memory Map Summary
Table 2−2 shows the memory map address ranges of the C6413 and C6410 devices. Internal memory is
always located at address 0 and can be used as both program and data memory. The external memory
address ranges in the C6413/C6410 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 2−2. TMS320C6413/C6410 Memory Map Summary
Memory Map Summary
MEMORY BLOCK DESCRIPTION
Internal RAM (L2) [C6413] 256K
Reserved [C6413] 1024K minus 256K
Internal RAM (L2) [C6410] 128K
Reserved [C6410] 1024K minus 128K
Reserved 15M
Reserved 8M
External Memory Interface A (EMIFA) Registers 256K
L2 Registers 256K
HPI Registers 256K
McBSP 0 Registers 256K
McBSP 1 Registers 256K
Timer 0 Registers 256K
Timer 1 Registers 256K
Interrupt Selector Registers 256K
EDMA RAM and EDMA Registers 256K
Reserved 512K
Timer 2 Registers 256K
GP0 Registers 256K minus 4K
Device Configuration Registers 4K
I2C0 Data and Control Registers 16K
I2C1 Data and Control Registers 16K
Reserved 16K
McASP0 Control Registers 16K
McASP1 Control Registers 16K
Reserved 176K
Reserved 128K
Reserved 128K
Emulation 256K
Reserved 528K
Reserved 3.5M
QDMA Registers 52
Reserved 928M minus 52
McBSP 0 Data 64M
McBSP 1 Data 64M
Reserved 64M
McASP0 Data 1M
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
0000 0000 – 0003 FFFF
0004 0000 – 000F FFFF
0000 0000 – 0001 FFFF
0002 0000 – 000F FFFF
0010 0000 – 00FF FFFF
0100 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 EFFF
01B3 F000 – 01B3 FFFF
01B4 0000 – 01B4 3FFF
01B4 4000 – 01B4 7FFF
01B4 8000 – 01B4 BFFF
01B4 C000 – 01B4 FFFF
01B5 0000 – 01B5 3FFF
01B5 4000 – 01B7 FFFF
01B8 0000 – 01B9 FFFF
01BA 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C8 3FFF
01C8 4000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3C0F FFFF
April 2004 − Revised May 2005 SPRS247E
19
Memory Map Summary
Table 2−2. TMS320C6413/C6410 Memory Map Summary (Continued)
MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE
McASP1 Data 1M
Reserved 62M
Reserved 1G
EMIFA CE0 256M
EMIFA CE1 256M
EMIFA CE2 256M
EMIFA CE3 256M
Reserved 1G
BLOCK SIZE
(BYTES)
3C10 0000 – 3C1F FFFF
3C20 0000 – 3FFF FFFF
4000 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
20
April 2004 − Revised May 2005SPRS247E
2.5.1 L2 Architecture Expanded
Figure 2−4 and Figure 2−5 show the detail of the L2 architecture on the TMS320C6413 and TMS320C6410
devices, respectively . For more information on the L2MODE bits, see the cache configuration (CCFG) register
bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number
SPRU610).
L2MODE L2 Memory Block Base Address
Memory Map Summary
000
256K SRAM (All)
011010001 111
0x0000 0000
128K-Byte SRAM
128K SRAM
192K SRAM
224K SRAM
0x0002 0000
256K Cache (4 Way) [All]
64K-Byte RAM
0x0003 0000
128K Cache (4 Way)
32K-Byte RAM
0x0003 8000
(4 Way)
32K Cache
64K Cache (4 Way)
32K-Byte RAM
0x0003 FFFF
0x0004 0000
Figure 2−4. TMS320C6413 L2 Architecture Memory Configuration
April 2004 − Revised May 2005 SPRS247E
21
Memory Map Summary
L2MODE
000
†
L2 Memory Block Base Address
011010001
64K-Byte RAM
64K SRAM
96K SRAM
128K SRAM (All)
(4 Way)
32K Cache
†
The L2MODE = 111b is not supported on the C6410 device.
64K Cache (4 Way)
128K Cache (4 Way)
32K-Byte RAM
32K-Byte RAM
Figure 2−5. TMS320C6410 L2 Architecture Memory Configuration
0x0000 0000
0x0001 0000
0x0001 8000
0x0001 FFFF
0x0002 0000
22
April 2004 − Revised May 2005SPRS247E
Peripheral Register Descriptions
2.6 Peripheral Register Descriptions
Table 2−3 through Table 2−20 identify the peripheral registers for the C6413/C6410 device by their register
names, acronyms, and hex address or hex address range. For more detailed information on the register
contents, bit names and their descriptions, see the specific peripheral reference guide listed in the
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
Table 2−3. EMIFA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0180 0000 GBLCTL EMIFA global control
0180 0004 CECTL1 EMIFA CE1 space control
0180 0008 CECTL0 EMIFA CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIFA CE2 space control
0180 0014 CECTL3 EMIFA CE3 space control
0180 0018 SDCTL EMIFA SDRAM control
0180 001C SDTIM EMIFA SDRAM refresh control
0180 0020 SDEXT EMIFA SDRAM extension
0180 0024 − 0180 003C − Reserved
0180 0040 PDTCTL Peripheral device transfer (PDT) control
0180 0044 CESEC1 EMIFA CE1 space secondary control
0180 0048 CESEC0 EMIFA CE0 space secondary control
0180 004C − Reserved
0180 0050 CESEC2 EMIFA CE2 space secondary control
0180 0054 CESEC3 EMIFA CE3 space secondary control
0180 0058 − 0183 FFFF – Reserved
Table 2−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0184 0000 CCFG Cache configuration register
0184 0004 − 0184 0FFC − Reserved
0184 1000 EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC − Reserved
0184 2000 L2ALLOC0 L2 allocation register 0
0184 2004 L2ALLOC1 L2 allocation register 1
0184 2008 L2ALLOC2 L2 allocation register 2
0184 200C L2ALLOC3 L2 allocation register 3
0184 2010 − 0184 3FFC − Reserved
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback invalidate base address register
0184 4014 L2WIWC L2 writeback invalidate word count register
0184 4018 L2IBAR L2 invalidate base address register
0184 401C L2IWC L2 invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback invalidate base address register
April 2004 − Revised May 2005 SPRS247E
23
Peripheral Register Descriptions
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 4034 L1DWIWC L1D writeback invalidate word count register
0184 4038 − 0184 4044 − Reserved
0184 4048 L1DIBAR L1D invalidate base address register
0184 404C L1DIWC L1D invalidate word count register
0184 4050 − 0184 4FFC − Reserved
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback invalidate all register
0184 5008 − 0184 7FFC − Reserved
0184 8000 − 0184 81FC
0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 − A0FF FFFF
MAR0 to
MAR127
Reserved
24
April 2004 − Revised May 2005SPRS247E
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 − A2FF FFFF
0184 828C MAR163 Controls EMIFA CE2 range A300 0000 − A3FF FFFF
0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF
0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF
0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 8300 −0184 83FC
0184 8400 −0187 FFFF − Reserved
MAR192 to
MAR255
Reserved
Peripheral Register Descriptions
April 2004 − Revised May 2005 SPRS247E
25
Peripheral Register Descriptions
Table 2−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA psuedo source address register
0200 0028 QSCNT QDMA psuedo frame count register
0200 002C QSDST QDMA destination address register
0200 0030 QSIDX QDMA psuedo index register
Table 2−6. EDMA Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FF98 − Reserved
01A0 FF9C EPRH Event polarity high register
01A0 FFA4 CIPRH Channel interrupt pending high register
01A0 FFA8 CIERH Channel interrupt enable high register
01A0 FFAC CCERH Channel chain enable high register
01A0 FFB0 ERH Event high register
01A0 FFB4 EERH Event enable high register
01A0 FFB8 ECRH Event clear high register
01A0 FFBC ESRH Event set high register
01A0 FFC0 PQAR0 Priority queue allocation register 0
01A0 FFC4 PQAR1 Priority queue allocation register 1
01A0 FFC8 PQAR2 Priority queue allocation register 2
01A0 FFCC PQAR3 Priority queue allocation register 3
01A0 FFDC EPRL Event polarity low register
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPRL Channel interrupt pending low register
01A0 FFE8 CIERL Channel interrupt enable low register
01A0 FFEC CCERL Channel chain enable low register
01A0 FFF0 ERL Event low register
01A0 FFF4 EERL Event enable low register
01A0 FFF8 ECRL Event clear low register
01A0 FFFC ESRL Event set low register
01A1 0000 − 01A3 FFFF – Reserved
26
April 2004 − Revised May 2005SPRS247E
Peripheral Register Descriptions
Table 2−7. EDMA Parameter RAM (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words)
01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words)
01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words)
01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words)
01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words)
01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words)
01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words)
01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words)
01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words)
01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words)
01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words)
01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words)
01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words)
01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words)
01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words)
01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words)
01A0 0150 − 01A0 0197 − Parameters for Event 16 (6 words)
01A0 0168 − 01A0 01AF − Parameters for Event 17 (6 words)
... ...
01A0 05D0 − 01A0 05E7 − Parameters for Event 62 (6 words)
01A0 05E8 − 01A0 05FF − Parameters for Event 63 (6 words)
01A0 0600 − 01A0 0617 − Reload/link parameters for Event 0 (6 words)
01A0 0618 − 01A0 062F − Reload/link parameters for Event 1 (6 words)
... ...
01A0 07E0 − 01A0 07F7 − Reload/link parameters for Event 20 (6 words)
01A0 07F8 − 01A0 080F − Reload/link parameters for Event 21 (6 words)
01A0 0810 − 01A0 0827 − Reload/link parameters for Event 22 (6 words)
... ...
01A0 13C8 − 01A0 13DF − Reload/link parameters for Event 147 (6 words)
01A0 13E0 − 01A0 13F7 − Reload/link parameters for Event 148 (6 words)
01A0 13F8 − 01A0 13FF − Scratch pad area (2 words)
01A0 1400 − 01A3 FFFF − Reserved
†
The C6413/C6410 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each]
that can be used to reload/link EDMA transfers.
†
Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
Reload/Link Parameters for
other Event 0−15
April 2004 − Revised May 2005 SPRS247E
27
Peripheral Register Descriptions
Table 2−8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high
019C 0004 MUXL Interrupt multiplexer low
019C 0008 EXTPOL External interrupt polarity
019C 000C − 019F FFFF − Reserved
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
Table 2−9. Device Configuration Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
Enables or disables specific
01B3 F000 PERCFG Peripheral Configuration Register
01B3 F004 DEVSTAT Device Status Register
01B3 F008 JTAGID JTAG Identification Register
01B3 F00C − 01B3 F014 − Reserved
01B3 F018 PCFGLOCK Peripheral Configuration Lock Register
01B3 F01C − 01B3 FFFF − Reserved
peripherals. This register is also
used for power-down of disabled
peripherals.
Read-only. Provides status of
the User’s device configuration
on reset.
Read-only. Provides 32-bit
JTAG ID of the device.
28
April 2004 − Revised May 2005SPRS247E
Peripheral Register Descriptions
Table 2−10. McBSP 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
The CPU and EDMA controller
018C 0000 DRR0 McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus
018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus
0x3000 0000 − 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus
018C 0008 SPCR0 McBSP0 serial port control register
018C 000C RCR0 McBSP0 receive control register
018C 0010 XCR0 McBSP0 transmit control register
018C 0014 SRGR0 McBSP0 sample rate generator register
018C 0018 MCR0 McBSP0 multichannel control register
018C 001C RCERE00 McBSP0 enhanced receive channel enable register 0
018C 0020 XCERE00 McBSP0 enhanced transmit channel enable register 0
018C 0024 PCR0 McBSP0 pin control register
018C 0028 RCERE10 McBSP0 enhanced receive channel enable register 1
018C 002C XCERE10 McBSP0 enhanced transmit channel enable register 1
018C 0030 RCERE20 McBSP0 enhanced receive channel enable register 2
018C 0034 XCERE20 McBSP0 enhanced transmit channel enable register 2
018C 0038 RCERE30 McBSP0 enhanced receive channel enable register 3
018C 003C XCERE30 McBSP0 enhanced transmit channel enable register 3
018C 0040 − 018F FFFF – Reserved
can only read this register; they
cannot write to it.
Table 2−11. McBSP 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
The CPU and EDMA controller
0190 0000 DRR1 McBSP1 data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF DRR1 McBSP1 data receive register via peripheral bus
0190 0004 DXR1 McBSP1 data transmit register via configuration bus
0x3400 0000 − 0x37FF FFFF DXR1 McBSP1 data transmit register via peripheral bus
0190 0008 SPCR1 McBSP1 serial port control register
0190 000C RCR1 McBSP1 receive control register
0190 0010 XCR1 McBSP1 transmit control register
0190 0014 SRGR1 McBSP1 sample rate generator register
0190 0018 MCR1 McBSP1 multichannel control register
0190 001C RCERE01 McBSP1 enhanced receive channel enable register 0
0190 0020 XCERE01 McBSP1 enhanced transmit channel enable register 0
0190 0024 PCR1 McBSP1 pin control register
0190 0028 RCERE11 McBSP1 enhanced receive channel enable register 1
0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1
0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2
0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2
0190 0038 RCERE31 McBSP1 enhanced receive channel enable register 3
0190 003C XCERE31 McBSP1 enhanced transmit channel enable register 3
0190 0040 − 0193 FFFF – Reserved
can only read this register; they
cannot write to it.
April 2004 − Revised May 2005 SPRS247E
29
Peripheral Register Descriptions
Table 2−12. Timer 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0194 0000 CTL0 Timer 0 control register
0194 0004 PRD0 Timer 0 period register
0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter.
0194 000C − 0197 FFFF − Reserved
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
Table 2−13. Timer 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0198 0000 CTL1 Timer 1 control register
0198 0004 PRD1 Timer 1 period register
0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter.
0198 000C − 019B FFFF − Reserved
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
Table 2−14. Timer 2 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01AC 0000 CTL2 Timer 2 control register
01AC 0004 PRD2 Timer 2 period register
01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter.
01AC 000C − 01AF FFFF − Reserved
Determines the operating mode of the timer, monitors the
timer status.
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
30
April 2004 − Revised May 2005SPRS247E
Peripheral Register Descriptions
Table 2−15. HPI Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
− HPID HPI data register Host read/write access only
0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access
0188 0004
0188 0008
0188 000C − 0189 FFFF − Reserved
018A 0000 HPI_TRCTL
018A 0004 − 018B FFFF − Reserved
†
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
HPIA
(HPIAW)
HPIA
(HPIAR)
HPI address register
†
(Write)
HPI address register
†
(Read)
HPI transfer request control
register
HPIA has both Host/CPU read/write access
Table 2−16. GP0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GP0 enable register
01B0 0004 GPDIR GP0 direction register
01B0 0008 GPVAL GP0 value register
01B0 000C − Reserved
01B0 0010 GPDH GP0 delta high register
01B0 0014 GPHM GP0 high mask register
01B0 0018 GPDL GP0 delta low register
01B0 001C GPLM GP0 low mask register
01B0 0020 GPGC GP0 global control register
01B0 0024 GPPOL GP0 interrupt polarity register
01B0 0028 − 01B3 EFFF − Reserved
April 2004 − Revised May 2005 SPRS247E
31
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers
HEX ADDRESS RANGE
McASP0 McASP1
01B4 C000 01B5 0000 PID
01B4 C004 01B5 0004 PWRDEMU Power down and emulation management register
01B4 C008 01B5 0008 − Reserved
01B4 C00C 01B5 000C − Reserved
01B4 C010 01B5 0010 PFUNC Pin function register
01B4 C014 01B5 0014 PDIR Pin direction register
01B4 C018 01B5 0018 PDOUT Pin data out register
01B4 C01C 01B5 001C PDIN/PDSET
01B4 C020 01B5 0020 PDCLR Pin data clear register
01B4 C024 − 01B4 C040 01B5 0024 − 01B5 0040 − Reserved
01B4 C044 01B5 0044 GBLCTL Global control register
01B4 C048 01B5 0048 AMUTE Mute control register
01B4 C04C 01B5 004C DLBCTL Digital Loop-back control register
01B4 C050 01B5 0050 DITCTL DIT mode control register
01B4 C054 − 01B4 C05C 01B5 0054 − 01B5 005C − Reserved
01B4 C060 01B5 0060 RGBLCTL
01B4 C064 01B5 0064 RMASK Receiver format unit bit mask register
01B4 C068 01B5 0068 RFMT Receive bit stream format register
01B4 C06C 01B5 006C AFSRCTL Receive frame sync control register
01B4 C070 01B5 0070 ACLKRCTL Receive clock control register
01B4 C074 01B5 0074 AHCLKRCTL High-frequency receive clock control register
01B4 C078 01B5 0078 RTDM Receive TDM slot 0−31 register
01B4 C07C 01B5 007C RINTCTL Receiver interrupt control register
01B4 C080 01B5 0080 RSTAT Status register − Receiver
01B4 C084 01B5 0084 RSLOT Current receive TDM slot register
01B4 C088 01B5 0088 RCLKCHK Receiver clock check control register
01B4 C08C − 01B4 C09C 01B5 008C − 01B5 009C − Reserved
01B4 C0A0 01B5 00A0 XGBLCTL
01B4 C0A4 01B5 00A4 XMASK Transmit format unit bit mask register
01B4 C0A8 01B5 00A8 XFMT Transmit bit stream format register
01B4 C0AC 01B5 00AC AFSXCTL Transmit frame sync control register
01B4 C0B0 01B5 00B0 ACLKXCTL Transmit clock control register
01B4 C0B4 01B5 00B4 AHCLKXCTL High-frequency Transmit clock control register
01B4 C0B8 01B5 00B8 XTDM Transmit TDM slot 0−31 register
01B4 C0BC 01B5 00BC XINTCTL Transmit interrupt control register
01B4 C0C0 01B5 00C0 XSTAT Status register − Transmitter
01B4 C0C4 01B5 00C4 XSLOT Current transmit TDM slot
01B4 C0C8 01B5 00C8 XCLKCHK Transmit clock check control register
ACRONYM REGISTER NAME
Peripheral Identification register
[Register value: 0x0010 0101]
Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
Alias of GBLCTL containing only Receiver Reset bits,
allows transmit to be reset independently from receive.
Alias of GBLCTL containing only Transmitter Reset bits,
allows transmit to be reset independently from receive.
32
April 2004 − Revised May 2005SPRS247E
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers (Continued)
HEX ADDRESS RANGE
McASP0
01B4 C0CC − 01B4 C0FC 01B5 00CC − 01B5 00FC − Reserved
01B4 C100 01B5 0100 DITCSRA0 Left (even TDM slot) channel status register file
01B4 C104 01B5 0104 DITCSRA1 Left (even TDM slot) channel status register file
01B4 C108 01B5 0108 DITCSRA2 Left (even TDM slot) channel status register file
01B4 C10C 01B5 010C DITCSRA3 Left (even TDM slot) channel status register file
01B4 C110 01B5 0110 DITCSRA4 Left (even TDM slot) channel status register file
01B4 C114 01B5 0114 DITCSRA5 Left (even TDM slot) channel status register file
01B4 C118 01B5 0118 DITCSRB0 Right (odd TDM slot) channel status register file
01B4 C11C 01B5 011C DITCSRB1 Right (odd TDM slot) channel status register file
01B4 C120 01B5 0120 DITCSRB2 Right (odd TDM slot) channel status register file
01B4 C124 01B5 0124 DITCSRB3 Right (odd TDM slot) channel status register file
01B4 C128 01B5 0128 DITCSRB4 Right (odd TDM slot) channel status register file
01B4 C12C 01B5 012C DITCSRB5 Right (odd TDM slot) channel status register file
01B4 C130 01B5 0130 DITUDRA0 Left (even TDM slot) user data register file
01B4 C134 01B5 0134 DITUDRA1 Left (even TDM slot) user data register file
01B4 C138 01B5 0138 DITUDRA2 Left (even TDM slot) user data register file
01B4 C13C 01B5 013C DITUDRA3 Left (even TDM slot) user data register file
01B4 C140 01B5 0140 DITUDRA4 Left (even TDM slot) user data register file
01B4 C144 01B5 0144 DITUDRA5 Left (even TDM slot) user data register file
01B4 C148 01B5 0148 DITUDRB0 Right (odd TDM slot) user data register file
01B4 C14C 01B5 014C DITUDRB1 Right (odd TDM slot) user data register file
01B4 C150 01B5 0150 DITUDRB2 Right (odd TDM slot) user data register file
01B4 C154 01B5 0154 DITUDRB3 Right (odd TDM slot) user data register file
01B4 C158 01B5 0158 DITUDRB4 Right (odd TDM slot) user data register file
01B4 C15C 01B5 015C DITUDRB5 Right (odd TDM slot) user data register file
01B4 C160 − 01B4 C17C 01B5 0160 − 01B5 017C − Reserved
01B4 C180 01B5 0180 SRCTL0 Serializer 0 control register
01B4 C184 01B5 0184 SRCTL1 Serializer 1 control register
01B4 C188 01B5 0188 SRCTL2 Serializer 2 control register
01B4 C18C 01B5 018C SRCTL3 Serializer 3 control register
01B4 C190 01B5 0190 SRCTL4 Serializer 4 control register
01B4 C194 01B5 0194 SRCTL5 Serializer 5 control register
01B4 C198 01B5 0198 − Reserved
01B4 C19C 01B5 019C − Reserved
01B4 C1A0 − 01B4 C1FC 01B5 01A0 − 01B5 01FC − Reserved
01B4 C200 01B5 0200 XBUF0 Transmit Buffer for Serializer 0
01B4 C204 01B5 0204 XBUF1 Transmit Buffer for Serializer 1
01B4 C208 01B5 0208 XBUF2 Transmit Buffer for Serializer 2
01B4 C20C 01B5 020C XBUF3 Transmit Buffer for Serializer 3
01B4 C210 01B5 0210 XBUF4 Transmit Buffer for Serializer 4
01B4 C214 01B5 0214 XBUF5 Transmit Buffer for Serializer 5
McASP1
REGISTER NAMEACRONYM
REGISTER NAMEACRONYM
April 2004 − Revised May 2005 SPRS247E
33
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers (Continued)
HEX ADDRESS RANGE
McASP0
01B4 C218 01B5 0218 − Reserved
01B4 C21C 01B5 021C − Reserved
01B4 C220 − 01B4 C27C 01B5 0220 − 01B5 027C − Reserved
01B4 C280 01B5 0280 RBUF0 Receive Buffer for Serializer 0
01B4 C284 01B5 0284 RBUF1 Receive Buffer for Serializer 1
01B4 C288 01B5 0288 RBUF2 Receive Buffer for Serializer 2
01B4 C28C 01B5 028C RBUF3 Receive Buffer for Serializer 3
01B4 C290 01B5 0290 RBUF4 Receive Buffer for Serializer 4
01B4 C294 01B5 0294 RBUF5 Receive Buffer for Serializer 5
01B4 C298 01B5 0298 − Reserved
01B4 C29C 01B5 029C − Reserved
01B4 C2A0 − 01B4 FFFF 01B5 02A0 − 01B5 3FFF − Reserved
McASP1
REGISTER NAMEACRONYM
REGISTER NAMEACRONYM
Table 2−18. McASP0 Data Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
(Used when RSEL or XSEL
3C00 0000 − 3C0F FFFF RBUF/XBUFx
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
bits = 0 [these bits are located
in the RFMT or XFMT
registers, respectively].)
Table 2−19. McASP1 Data Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
(Used when RSEL or XSEL
3C10 0000 − 3C1F FFFF RBUF/XBUFx
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
bits = 0 [these bits are located
in the RFMT or XFMT
registers, respectively].)
34
April 2004 − Revised May 2005SPRS247E
Table 2−20. I2C0 and I2C1 Registers
Peripheral Register Descriptions
HEX ADDRESS RANGE
I2C0 I2C1
01B4 0000 01B4 4000 I2COARx I2Cx own address register
01B4 0004 01B4 4004 I2CIMRx I2Cx interrupt mask/status register
01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register
01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register
01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register
01B4 0014 01B4 4014 I2CCNTx I2Cx data count register
01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register
01B4 001C 01B4 401C I2CSARx I2Cx slave address register
01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register
01B4 0024 01B4 4024 I2CMDRx I2Cx mode register
01B4 0028 01B4 4028 I2CIVRx I2Cx interrupt vector register
01B4 002C 01B4 402C I2CEMDRx I2Cx Extended mode register
01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register
01B4 0034 01B4 4034 I2CPID1x
01B4 0038 01B4 4038 I2CPID2x
01B4 003C − 01B4 0044 01B4 403C − 01B4 4044 − Reserved
01B4 0048 01B4 4048 I2CPFUNCx I2Cx pin function register
01B4 004C 01B4 404C I2CPDIRx I2Cx pin direction register
01B4 0050 01B4 4050 I2CPDINx I2Cx pin data in register
01B4 0054 01B4 4054 I2CPDOUTx I2Cx pin data out register
01B4 0058 01B4 4058 I2CPDSETx I2Cx pin data set register
01B4 005C 01B4 405C I2CPDCLRx I2Cx pin data clear register
01B4 0060 − 01B4 3FFF 01B4 4060 − 01B4 7FFF − Reserved
ACRONYM REGISTER NAME
I2Cx Peripheral Identification register 1
[Value: 0x0000 0105
I2Cx Peripheral Identification register 2
[Value: 0x0000 0005
]
]
April 2004 − Revised May 2005 SPRS247E
35
EDMA Channel Synchronization Events
2.7 EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 2−21 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the C6413/C6410 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the EDMA
event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,
EERH). The priority of each event can be specified independently in the transfer parameters stored in the
EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are
enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced
Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
Table 2−21. TMS320C6413/C6410 EDMA Channel Synchronization Events
†
EDMA
CHANNEL
0 DSP_INT HPI-to-DSP interrupt
1 TINT0 Timer 0 interrupt
2 TINT1 Timer 1 interrupt
3 SD_INTA EMIFA SDRAM timer interrupt
4 GPINT4/EXT_INT4 GP0 event 4/External interrupt pin 4
5 GPINT5/EXT_INT5 GP0 event 5/External interrupt pin 5
6 GPINT6/EXT_INT6 GP0 event 6/External interrupt pin 6
7 GPINT7/EXT_INT7 GP0 event 7/External interrupt pin 7
8 GPINT0 GP0 event 0
9 GPINT1 GP0 event 1
10 GPINT2 GP0 event 2
11 GPINT3 GP0 event 3
12 XEVT0 McBSP0 transmit event
13 REVT0 McBSP0 receive event
14 XEVT1 McBSP1 transmit event
15 REVT1 McBSP1 receive event
16−18 – None
19 TINT2 Timer 2 interrupt
20−27 – None
28 – None
29 – None
30−31 – None
32 AXEVTE0 McASP0 transmit even event
33 AXEVTO0 McASP0 transmit odd event
34 AXEVT0 McASP0 transmit event
35 AREVTE0 McASP0 receive even event
36 AREVTO0 McASP0 receive odd event
37 AREVT0 McASP0 receive event
38 AXEVTE1 McASP1 transmit even event
39 AXEVTO1 McASP1 transmit odd event
40 AXEVT1 McASP1 transmit event
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
EVENT NAME EVENT DESCRIPTION
36
April 2004 − Revised May 2005SPRS247E
Interrupt Sources and Interrupt Selector
Table 2−21. TMS320C6413/C6410 EDMA Channel Synchronization Events† (Continued)
EDMA
CHANNEL
41 AREVTE1 McASP1 receive even event
42 AREVTO1 McASP1 receive odd event
43 AREVT1 McASP1 receive event
44 ICREVT0 I2C0 receive event
45 ICXEVT0 I2C0 transmit event
46 ICREVT1 I2C1 receive event
47 ICXEVT1 I2C1 transmit event
48 GPINT8 GP0 event 8
49 GPINT9 GP0 event 9
50 GPINT10 GP0 event 10
51 GPINT11 GP0 event 11
52 GPINT12 GP0 event 12
53 GPINT13 GP0 event 13
54 GPINT14 GP0 event 14
55 GPINT15 GP0 event 15
56−63 – None
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
EVENT DESCRIPTIONEVENT NAME
2.8 Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 2−22. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 2−22. The interrupt source for interrupts 4−15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
April 2004 − Revised May 2005 SPRS247E
37
Interrupt Sources and Interrupt Selector
Table 2−22. C6413/C6410 DSP Interrupts
CPU
INTERRUPT
NUMBER
†
INT_00
†
INT_01
†
INT_02
†
INT_03
‡
INT_04
‡
INT_05
‡
INT_06
‡
INT_07
‡
INT_08
‡
INT_09
‡
INT_10
‡
INT_11
‡
INT_12
‡
INT_13
‡
INT_14
‡
INT_15
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
INTERRUPT SOURCE
− − RESET
− − NMI
− − Reserved Reserved. Do not use.
− − Reserved Reserved. Do not use.
MUXL[4:0] 00100 GPINT4/EXT_INT4 GP0 interrupt 4/External interrupt pin 4
MUXL[9:5] 00101 GPINT5/EXT_INT5 GP0 interrupt 5/External interrupt pin 5
MUXL[14:10] 00110 GPINT6/EXT_INT6 GP0 interrupt 6/External interrupt pin 6
MUXL[20:16] 00111 GPINT7/EXT_INT7 GP0 interrupt 7/External interrupt pin 7
MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt
MUXL[30:26] 01001 EMU_DTDMA EMU DTDMA
MUXH[4:0] 00011 SD_INTA EMIFA SDRAM timer interrupt
MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive
MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit
MUXH[20:16] 00000 DSP_INT HPI-to-DSP interrupt
MUXH[25:21] 00001 TINT0 Timer 0 interrupt
MUXH[30:26] 00010 TINT1 Timer 1 interrupt
− − 01100 XINT0 McBSP0 transmit interrupt
− − 01101 RINT0 McBSP0 receive interrupt
− − 01110 XINT1 McBSP1 transmit interrupt
− − 01111 RINT1 McBSP1 receive interrupt
− − 10000 GPINT0 GP0 interrupt 0
− − 10001 Reserved Reserved. Do not use.
− − 10010 Reserved Reserved. Do not use.
− − 10011 TINT2 Timer 2 interrupt
− − 10100 Reserved Reserved. Do not use.
− − 10101 Reserved Reserved. Do not use.
− − 10110 ICINT0 I2C0 interrupt
− − 10111 ICINT1 I2C1 interrupt
− − 11000 AXINT1 McASP1 transmit interrupt
− − 11001 ARINT1 McASP1 receive interrupt
− − 11010 Reserved Reserved. Do not use.
− − 11011 Reserved Reserved. Do not use.
− − 11100 AXINT0 McASP0 transmit interrupt
− − 11101 ARINT0 McASP0 receive interrupt
− − 11110 Reserved Reserved. Do not use.
− − 11111 Reserved Reserved. Do not use.
†
Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 2−22 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
38
April 2004 − Revised May 2005SPRS247E
2.9 Signal Groups Description
Signal Groups Description
CLKINSEL
CLKIN
CLKOUT4/GP0[1]
CLKOUT6/GP0[2]
CLKMODE3
CLKMODE2
CLKMODE1
CLKMODE0
PLLV
OSCIN
OSCOUT
OSCV
OSCV
OSC_DIS
TMS
TDO
TDI
TCK
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
DD
SS
RESET
†
†
Reset and
Interrupts
Clock/PLL
NMI
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
GP0[4]/EXT_INT4
‡
‡
‡
‡
and
Oscillator
RSV
RSV
RSV
RSV
RSV
RSV
Reserved
w
w
IEEE Standard
1149.1
(JTAG)
Emulation
Control/Status
w
RSV
RSV
RSV
HD15/GP0[15]
HD14/GP0[14]
HD13/GP0[13]
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
§
§
§
§
§
§
§
§
GP0
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
GP0[4]/EXT_INT4
GP0[3]
CLKOUT6/GP0[2]
CLKOUT4/GP0[1]
GP0[0]
General-Purpose Input/Output 0 (GP0) Port
†
These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these muxed
pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more
details, see the Device Configurations section of this data sheet.
‡
These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO
as input-only.
§
These pins are muxed with the HPI peripheral pins and by default these signals function as HPI. For more details on these muxed pins,
see the Device Configurations section of this data sheet.
Figure 2−6. CPU and Peripheral Signals
April 2004 − Revised May 2005 SPRS247E
‡
‡
‡
‡
†
†
39
Signal Groups Description
AED[31:0]
ACE3
ACE2
ACE1
ACE0
AEA[22:3]
ABE3
ABE2
ABE1
ABE0
HD[31,30]
HD[29:16]/McASP1
HD[15:8]/GP0[15:8]
HD[7:0]
HCNTL0/AFSR1[1]
HCNTL1
HHWIL/AFSR1[2]
(HPI16 ONLY)
32
Data
AECLKIN
AECLKOUT1
AECLKOUT2
ASDCKE
AARE/ASDCAS/ASADS/ASRE
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
20
Memory Map
Space Select
Address
External
Memory I/F
Control
ASOE3
APDT
Byte Enables
Bus
Arbitration
AHOLD
AHOLDA
ABUSREQ
EMIFA (32-bit)
†
†
32
†
†
Data
(Host-Port Interface)
Register Select
HPI
Control
HAS/ACLKR1[1]
HR/W/AFSR1[3]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
†
†
†
†
HDS2
†
Half-Word
Select
HRDY
HINT
40
†
These HPI pins are muxed with the McASP1 or GP0 peripherals. By default, these signals function as HPI and no function,
respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 2−7. Peripheral Signals
April 2004 − Revised May 2005SPRS247E
Signal Groups Description
CLKX1
FSX1
CLKR1
FSR1
CLKS1
TOUT1/LENDIAN
TINP1
DX1
DR1
McBSP1
Transmit
Receive
Timer 1
Timer 2
Clock
McBSP0
Transmit
Receive
Clock
McBSPs
(Multichannel Buffered
Serial Ports)
Timer 0
Timers
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
TOUT0
TINP0
SCL1
SDA1
I2C1
I2Cs
I2C0
Figure 2−7. Peripheral Signals (Continued)
SCL0
SDA0
April 2004 − Revised May 2005 SPRS247E
41
Signal Groups Description
(Transmit/Receive Data Pins)(Transmit/Receive Data Pins)
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
(Receive Bit Clock)
ACLKR0
AHCLKR0
(Receive Master Clock) (Transmit Master Clock)
AFSR0
(Receive Frame Sync or
Left/Right Clock)
Receive Clock
Generator
Receive Clock
Check Circuit
Receive
Frame Sync
Error Detect
(see Note A)
6-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
Transmit
Clock
Generator
Transmit
Clock Check
Circuit
Transmit
Frame Sync
Auto Mute
Logic
AXR0[4]
AXR0[5]
(Transmit Bit Clock)
ACLKX0
AHCLKX0
AFSX0
(Transmit Frame Sync or
Left/Right Clock)
AMUTE0
AMUTEIN0
(Multichannel Audio Serial Port 0)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
McASP0
Figure 2−7. Peripheral Signals (Continued)
42
April 2004 − Revised May 2005SPRS247E
Signal Groups Description
(Transmit/Receive Data Pins)(Transmit/Receive Data Pins)
HD16/AXR1[0]
HD17/AXR1[1]
HD18/AXR1[2]
HD19/AXR1[3]
(Receive Bit Clock)
AFCMUX[1:0]
(PERCFG[10:9])
HD25/ACLKR1
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1
/ACLKR1[3]
HD26/AHCLKR1
(Receive Master Clock)
HD23/AFSR1
HCNTL0/AFSR1[1]
HHWIL/AFSR1[2]
/AFSR1[3]
HR/W
AFCMUX[1:0]
(PERCFG[10:9])
(Receive Frame Sync or
Left/Right Clock)
Receive Clock
Generator
Receive Clock
Check Circuit
Receive
Frame Sync
Error Detect
(see Note A)
6-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
Auto Mute
Logic
Transmit
Clock
Generator
Transmit
Clock Check
Circuit
Transmit
Frame Sync
HD20/AXR1[4]
HD21/AXR1[5]
(Transmit Bit Clock)
HD24/ACLKX1
HD27/AHCLKX1
(Transmit Master Clock)
HD22/AFSX1
(Transmit Frame Sync or
Left/Right Clock)
HD28/AMUTE1
HD29/AMUTEIN1
(Multichannel Audio Serial Port 1)
McASP1
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 2−7. Peripheral Signals (Continued)
April 2004 − Revised May 2005 SPRS247E
43
Device Configurations
3 Device Configurations
On the C6413/C6410 device, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are software-configurable
via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
3.1 Device Configuration at Device Reset
Table 3−1 describes the C6413/C6410 device configuration pins. The logic level of the AEA[22:19],
TOUT1/LENDIAN, TOUT0/HPI_EN
The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by
using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The
CLKINSEL and OSC_DIS configuration pins should remain driven to the correct levels during device operation
and must only be changed when RESET
are driven after the reset is removed. At this time, the control device should ensure it has stopped driving the
device configuration pins of the DSP to again avoid contention.
Table 3−1. C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
, and HD5 pins is latched at reset to determine the device configuration.
is low. The device configuration pins are sampled during reset and
HD5, CLKINSEL, and OSC_DIS)
CONFIGURATION
PIN
TOUT1/LENDIAN AA1 IPU
AEA[22:21]
AEA[20:19]
TOUT0/HPI_EN AA2 IPD
HD5 Y13 IPU
NO. IPD/IPU
[M21,
N21]
[P22,
N22]
IPD
IPD
†
Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 − System operates in Little Endian mode (default)
Bootmode [1:0]
00 – No boot (default mode)
01 − HPI boot (based on HPI_EN
10 − Reserved
11 − EMIFA 8-bit ROM boot
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
HPI, McASP1, GP0[15:8] select
Selects whether the HPI peripheral or McASP1 peripheral, and GP0[15:8] pins are
functionally enabled
0 – HPI is enabled and the McASP1 peripheral and GP0 [15:8] pins are disabled
(default mode);
[HPI32, if HD5 = 1; HPI16 if HD5 = 0]
1 − HPI I is disabled and the McASP1 peripheral and GP0 [15:8] pins are enabled
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3−2.
HPI peripheral bus width (HPI_WIDTH) select
0 − HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used for HPI and the remaining
HD[31:16] muxed
pins function as McASP1 peripheral pins or are reserved pins in the Hi-Z state.)
1 − HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3−2.
FUNCTIONAL DESCRIPTION
pin)
44
April 2004 − Revised May 2005SPRS247E
Device Configurations
Table 3−1. C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS) (Continued)
CONFIGURATION
PIN
CLKINSEL A11 IPU
OSC_DIS B7 IPU
†
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
NO.
†
PLL input clock source select
Selects whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]. For proper device operation, this pin must be used in
conjunction with the OSC_DIS pin.
0 − Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator)
For proper device operation, OSC_DIS must be 0
1 − CLKIN square wave (default)
For proper device operation, OSC_DIS must be 1
This pin must be pulled to the correct level even after reset.
Oscillator disable
Selects whether the Oscillator is enabled or disabled. For proper device operation, this pin
must follow the CLKINSEL pin operation.
0 − OSC enabled
1 − OSC disabled (default)
This pin must be pulled to the correct level even after reset.
FUNCTIONAL DESCRIPTIONIPD/IPU
3.2 Peripheral Configuration at Device Reset
Some C6413/C6410 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,
general-purpose input/output 0 pins GP0[15:8], and McASP1).
• HPI, McASP1, and GP0 peripherals
The TOUT0/HPI_EN
(AA2 pin) is latched at reset. This pin selects whether the HPI peripheral or McASP1
peripheral, and GP0[15:8] pins are functionally enabled (see Table 3−2).
Table 3−2. TOUT0/HPI_EN
PERIPHERAL SELECTION PERIPHERALS SELECTED
HPI_EN
(AA2)
0 0 16-bit HPI Available N/A
0 1 32-bit HPI N/A
1 x N/A
†
The TOUT0/HPI_EN pin has an internal pulldown that enables the HPI by default. The TOUT0/HPI_EN pin can disable the HPI via an external
pullup resistor or be driven high during reset. The TOUT0/HPI_EN
‡
N/A = Not available
HD5
[HPI_WIDTH]
(Y13)
and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins)
HPI McASP1 GP0 [15:8]
‡
‡
‡
Available Available
‡
N/A
pin is not software-controllable.
HPI_EN = 0, HD5 = 0
HPI16 is enabled and McASP1 peripheral is enabled
and GP0 [15:8] pins are disabled. All multiplexed
HPI/McASP1 pins function as McASP1 pins. All
multiplexed HPI/GP0 are reserved pins in the Hi-Z state.
HPI_EN = 0, HD5 = 1
HPI32 is enabled and McASP1 peripheral and GP0
[15:8] pins are disabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as HPI pins.
HPI_EN = 1, HD5 = x (don’t care)
HPI is disabled and the McASP1 peripheral and GP0
[15:8] pins are enabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as McASP1 and GP0 pins,
respectively. To use the GP0 pins, the appropriate bits
in the GP0EN and GP0DIR registers need to be set. All
standalone HPI pins are reserved pins in the Hi-Z state
DESCRIPTION
†
April 2004 − Revised May 2005 SPRS247E
45
Device Configurations
3.3 Peripheral Selection After Device Reset
HPI, McBSP1, McBSP0, McASP1, McASP0, I2C1, and I2C0
The C6413/C6410 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
McASP1, McASP0, I2C1, and I2C0 peripherals. For more detailed information on the PERCFG register
control bits, see Figure 3−1 and Table 3−3.
31 28 27 24
Reserved
23
15 11
†
R-0 R-0
Reserved
Reserved
†
R-0 R/W-0 R/W-0
†
R-0
Reserved
10 9 8
AFCMUX[1:0] MCASP1EN
†
16
76543
I2C1EN
R/W-0 R-0 R-0 R-0 R/W-0 R-1 R-1 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
†
For proper device operation, all reserved bits have to be written with “0”.
Reserved
†
Reserved
†
Reserved
†
I2C0EN MCBSP1EN MCBSP0EN MCASP0EN
21 0
Figure 3−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000]
46
April 2004 − Revised May 2005SPRS247E
Device Configurations
Table 3−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:11 Reserved Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
Clocks and frame syncs select bits.
Determines which of the clock and frame sync pairs are input to McASP1.
00 = ACLKR1, AFSR1 pins (default).
10:9 AFCMUX[1:0]
8 MCASP1EN
7 I2C1EN
6:4 Reserved Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
3 I2C0EN
2 MCBSP1EN
1 MCBSP0EN
0 MCASP0EN
01 = ACLKR1[1], AFSR1[1] pins
10 = ACLKR1[2], AFSR1[2] pins
11 = ACLKR1[3], AFSR1[3] pins
[designed for multiple non-simultaneous I2S sources with different clock sources].
McASP1 select bit.
Selects whether the McASP1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0 = McASP1 is disabled and the module is powered down [default].
1 = McASP1 is enabled.
Inter-integrated circuit 1 (I2C1) enable bit.
Selects whether I2C1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0 = I2C1 is disabled, and the module is powered down (default).
1 = I2C1 is enabled.
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0 = I2C0 is disabled, and the module is powered down (default).
1 = I2C0 is enabled.
McBSP1 enable bit.
This bit is read-only as a “1” (McBSP1 always enabled).
McBSP0 enable bit .
This bit is read-only as a “1” (McBSP0 always enabled).
McASP0 select bit.
Selects whether the McASP0 peripheral is enabled or disabled.
(This feature allows power savings by disabling the peripheral when not in use.)
0 = McASP0 is disabled.
1 = McASP0 is enabled.
April 2004 − Revised May 2005 SPRS247E
47
Device Configurations
3.4 Peripheral Configuration Lock
By default, the McASP1, McASP0, I2C1, and I2C0 peripherals are disabled on power up. In order to use these
peripherals on the C6413/C6410 device, the peripheral must first be enabled in the Peripheral Configuration
register (PERCFG). Software muxed pins should not be programmed to switch functionalities during
run-time. Care should also be taken to ensure that no accesses are being performed before disabling
the peripherals. To help minimize power consumption in the C6413/C6410 device, unused peripherals may
be disabled..
Figure 3−2 shows the flow needed to enable (or disable) a given peripheral on the C6413/C6410 device.
Unlock the PERCFG Register
Using the PCFGLOCK Register
Write to
PERCFG Register
to Enable/Disable Peripherals
Read from
PERCFG Register
Wait 128 CPU Cycles Before
Accessing Enabled Peripherals
Figure 3−2. Peripheral Enable/Disable Flow Diagram
A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register
(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register
determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT
bit = 0), see Figure 3−3. A peripheral can only be enabled when the PERCFG register is “unlocked”
(LOCKSTAT bit = 0).
48
April 2004 − Revised May 2005SPRS247E
Device Configurations
Read Accesses
31 10
Reserved
R-0 R-1
LOCKSTAT
Write Accesses
31 0
LOCK
W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 3−3. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses
Table 3−4. PCFGLOCK Register Selection Bit Descriptions − Read Accesses
BIT NAME DESCRIPTION
31:1 Reserved Reserved. Read-only, writes have no effect.
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0 LOCKSTAT
0 = Unlocked, read accesses to the PERCFG register allowed.
1 = Locked, write accesses to the PERCFG register do not modify the register state [default].
Reads are unaffected by Lock Status.
Table 3−5. PCFGLOCK Register Selection Bit Descriptions − Write Accesses
BIT NAME DESCRIPTION
Lock bits.
31:0 LOCK
0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a
peripheral while it is disabled.
In addition to the normal usage, the PCFGLOCK register can be used to override the power saver settings
specified in the PERCFG register. When the power saver feature is disabled (PCFGLOCK written with
0xC0100C01), all peripherals controlled by PERCFG are enabled. If the power saver is returned to normal
operation (PCFGLOCK written with 0x0C01C010), then the peripherals return to the operating condition
specified by PERCFG. Turning off the power saver settings will add a worst-case 50 mW of power to the overall
DSP power consumption.
Note: overriding the settings of the PERCFG register will not cause a conflict on the multiplexed pins. For
example, with the HPI and McASP1 peripherals, the HPI will still have control over the multiplexed pins
provided the TOUT0/HPI_EN
April 2004 − Revised May 2005 SPRS247E
pin was “0” at reset.
49
Device Configurations
3.5 Device Status Register Description
The device status register depicts the status of the device peripheral selection. Once set, these bits will remain
set until a device reset; therefore, these bits should be masked when reading the DEVSTAT register since their
values can change. For the actual register bit names and their associated bit field descriptions, see Figure 3−4
and Table 3−6.
31 24
Reserved
R-100x0111
23 19
PLLM
R-xxxxx R-1 R-x R-x
15 14 13 12 11
Reserved
R-000 R-x R-0 R-x R-0 R-x
CLKMODE3 Reserved HPI-WIDTH Reserved HPI_EN
18 17 16
Reserved OSC EXT RES CLKINSEL
10 9 8
76543
CLKMODE2
R-x R-x R-x R-x R-x R-x R-x R-x
Legend: R = Read only; R/W = Read/Write; -n = value after reset
CLKMODE1 CLKMODE0 LENDIAN BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0
210
Figure 3−4. Device Status Register (DEVSTAT) Description − 0x01B3 F004
Table 3−6. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:24 Reserved Reserved. Read-only, writes have no effect.
PLL multiply factor status bits.
Shows the status of the PLL multiply mode selected; whether the CPU clock frequency equals the input
23:19 PLLM
18 Reserved Reserved. Read-only, writes have no effect.
17 OSC EXT RES
16 CLKINSEL
15:13 Reserved Reserved. Read-only, writes have no effect.
11 Reserved Reserved. Read-only, writes have no effect.
10 HPI_WIDTH
9 Reserved Reserved. Read-only, writes have no effect.
8 HPI_EN
clock frequency x1 (Bypass), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more detailed information on the PLL multiply factors, see the Clock PLL and Oscillator section of this
data sheet.
Oscillator external resistor status bit.
Shows the status internal or external of the OSC bias resistor.
0 = Normal functional mode with internal bias resistor.
1 = Normal functional mode with external bias resistor [default; internally tied high].
PLL input clock select status bit.
Shows the status of whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]
0 = Crystal oscillator (OSCIN and OSCOUT).
1 = CLKIN (default).
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
0 = HPI operates in 16-bit mode. (default).
1 = HPI operates in 32-bit mode.
HPI_EN pin status bit.
Shows the status at device reset of the HPI_EN
or disabled.
0 = HPI_EN pin is low, meaning the HPI peripheral is enabled (default).
1 = HPI_EN
pin is high, meaning the HPI peripheral is disabled.
pin, which controls the HPI peripheral as enabled [default]
50
April 2004 − Revised May 2005SPRS247E
Table 3−6. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
Sh
the status (”1 or 0”) of the CLKMODE[3:0] select bit
y
12 CLKMODE3
7 CLKMODE2
6 CLKMODE1
5 CLKMODE0
4 LENDIAN
3 BOOTMODE1
2 BOOTMODE0
1 AECLKINSEL1
0 AECLKINSEL0
Device Configurations
DESCRIPTIONNAMEBIT
Clock mode select status bits
ows
Clock mode select for CPU clock frequency (CLKMODE[3:0]), for example:
0000– Bypass (x1) (default mode)
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this
data sheet.
Device Endian mode (LENDIAN)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).
0 – System is operating in Big Endian mode
1 − System is operating in Little Endian mode (default)
Bootmode configuration bits (AEA[22:21] pins)
Shows the status of what device bootmode configuration is operational.
Bootmode [1:0]
00 – No boot (default mode)
01 − HPI boot (based on HPI_EN
10 − Reserved
11 − EMIFA 8-bit ROM boot
EMIFA input clock select (AEA[20:19] pins)
Shows the status of what clock mode is enabled or disabled for the EMIF.
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
”
”
pin)
s:
3.6 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
C6413/C6410 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value
for the C6413/C6410 device is: 0x0007 902F. For the actual register bit names and their associated bit field
descriptions, see Figure 3−5 and Table 3−7.
31−28 27−12 11−1 0
VARIANT (4-Bit)
R-0000 R-0000 0000 1000 0100 R-0000 0010 111 R-1
Legend: R = Read only; -n = value after reset
Figure 3−5. JTAG ID Register Description − TMS320C6413/C6410 Register Value − 0x0007 902F
BIT NAME DESCRIPTION
31:28 VARIANT Variant (4-Bit) value. C6413/C6410 value: 0000.
27:12 PART NUMBER Part Number (16-Bit) value. C6413/C6410 value: 0000 0000 1000 0100.
11−1 MANUFACTURER Manufacturer (11-Bit) value. C6413/C6410 value: 0000 0010 111.
0 LSB LSB. This bit is read as a “1” for C6413/C6410.
PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB
Table 3−7. JTAG ID Register Selection Bit Descriptions
April 2004 − Revised May 2005 SPRS247E
51
Device Configurations
DEFAULT
DEFAULT
g
y
the GPIO Direction Register must be properly
(McASP1 is disabled).
To enable the McASP1 peripheral, the
dri
l device (disabling the HPI)
HPI pin
TOUT0/HPI_EN 0,
HHWIL pin
HD5 = 0]
(HPI16 only)
McASP1 pins disabled.
determine which of the clock and frame sync
pa s a e pu o c S o o e de a ed
(McASP1 is disabled).
HPI pin
p
McASP1 pins disabled
McASP1 pin direction is controlled by the
3.7 Multiplexed Pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should not be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 3−8 identifies the multiplexed pins on the C6413/C6410 device; shows the default (primary) function and
the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 3−8. C6413/C6410 Device Multiplexed Pins
MULTIPLEXED PINS
NAME NO.
CLKOUT4/GP0[1] A2 IPU CLKOUT4 GP1EN = 0 (disabled)
CLKOUT6/GP0[2] B3 IPU CLKOUT6 GP2EN = 0 (disabled)
HCNTL0/AFSR1[1] Y6
HHWIL/AFSR1[2] Y7
HR/W/AFSR1[3] AA5
HAS/ACLKR1[1] Y5
HCS/ACLKR1[2] AA11
HDS1/ACLKR1[3] AB11
HD29/AMUTEIN1 W11
HD28/AMUTE1 W10
HD27/AHCLKX1 Y4
HD26/AHCLKR1 AB4
HD25/ACLKR1 AA9
HD24/ACLKX1 AA4
HD23/AFSR1 AB9
HD22/AFSX1 AB5
HD21/AXR1[5] Y9
HD20/AXR1[4] AB8
HD19/AXR1[3] AA6
HD18/AXR1[2] AB7
HD17/AXR1[1] AA7
IPD/IPU
IPU
IPU
DEFAULT DEFAULT
†
FUNCTION
HPI pin TOUT0/HPI_EN = 0,
function
SETTING
HD5 = 1
(32-Bit HPI enabled)
(HPI16 only) McASP1 pins disabled.
TOUT0/HPI_EN = 0,
HPI pin
function
HD5 = 1
(32-Bit HPI enabled)
McASP1
ins disabled.
DESCRIPTION
These pins are software-configurable. To use
these pins as GPIO pins, the GPxEN bits in the
GPIO Enable Register and the GPxDIR bits in
the GPIO Direction Re
configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
By default, HPI32 is enabled upon reset
To enable the McASP1 peripheral, the
TOUT0/HPI_EN pin must be high at reset either
via an external pullup (PU) resistor (1 kΩ) or
ven by a contro
or the McASP1 peripheral pins can be used if the
HPI is used as a 16-bit width [HPI_EN = 0,
=
.
The clocks and frame syncs select bits
(AFCMUX[1:0]) located in the PERCFG register
pairs are input to McASP1. For more detailed
information, see the Device Configuration
section of this data sheet.
By default, HPI32 is enabled upon reset
(McASP1 is disabled).
To enable the McASP1 peripheral, the
TOUT0/HPI_EN
via an external pullup (PU) resistor (1 kΩ) or
driven by a control device (disabling the HPI).
or the McASP1 peripheral pins can be used if the
HPI is used as a 16-bit width [HPI_EN
.
HD5 = 0].
pin must be high at reset either
ister must be properl
.
= 0,
HD16/AXR1[0] AB6
52
PDIR[x] bits in the McASP1PDIR register.
McASP1PDIR = 0 input, = 1 output
April 2004 − Revised May 2005SPRS247E
Table 3−8. C6413/C6410 Device Multiplexed Pins (Continued)
]
By default, HPI is enabled upon reset (GP0[15:9]
p)
HPI_EN = 0
HD5
1
(
)
disabled (HPI_EN =
HD5
))
g
HPI pin
(32-Bit HPI enabled)
the GPxEN bits in the GPIO Enable Register and
g
GPxEN = 1
GPx pin
d
GPxDIR = 0: GPx pin is an input
Configuration Examples
MULTIPLEXED PINS
HD15/GP0[15] Y12
HD14/GP0[14] AA12
HD13/GP0[13
HD12/GP0[12] Y14
HD11/GP0[11] AB14
HD10/GP0[10] AA15
HD9/GP0[9] Y16
HD8/GP0[8] AB16
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
]
AB13
IPD/IPU
IPD/IPU
NO.NAME
IPU
†
†
DEFAULT
DEFAULT
FUNCTION
FUNCTION
HPI pin
function
DEFAULT
DEFAULT
SETTING
SETTING
,
32-Bit HPI enabled
GPIO pins disabled.
=
DESCRIPTION
DESCRIPTION
By default, HPI is enabled upon reset (GP0[15:9
pins are disabled).
To use GP0[15:9] as GPIO pins, the HPI needs
to be
the GPxEN bits in the GPIO Enable Re
the GPxDIR bits in the GPIO Direction Register
must be properly configured.
:
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
1,
enable
’
= x (don’t care
ister and
3.8 Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including
TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN
pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user
in debugging and flexibility in switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:3]). Do not
oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown
resistors. If an external controller provides signals to these non-configuration pins, these signals must be
driven to the default state of the pins at reset, or not be driven at all.
, CLKINSEL, and OSC_DIS. Although internal
,
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
3.9 Configuration Examples
Figure 3−6 illustrates an example of peripheral selections/options that are configurable on the C6413/C610
device.
April 2004 − Revised May 2005 SPRS247E
53
Configuration Examples
CLKOUT4, CLKOUT6,
PLLV, CLKIN,
CLKMODE[3:0], OSC_DIS,
CLKINSEL, OSCIN,
OSCOUT, OSCV
OSCV
SS
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AHCLKR0, AFSR0,
,
DD
AMUTEIN0,
ACLKR0
AXR0[5:0]
Clock and
System
McASP0
EMIFA
TIMER2
32
AED[31:0]
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA
AARE
AAOE
AAWE
, ABUSREQ,
/ASDCAS/ASADS/ASRE,
/ASDRAS/ASOE,
/ASDWE/ASWE
AHCLKX1, AFSX1,
ACLKX1, AMUTE1,
AMUTEIN1, AHCLKR1,
AFSR1, AFSR1[1],
AFSR1[2], AFSR1[3],
ACLKR1, ACLKR1[1],
ACLKR1[2], ACLKR1[3]
AXR1[5:0]
HD[15:0]
HCNTL0, HCNTL1,
HHWIL, HAS
HCS
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
, HR/W,
, HDS1, HDS2
CLKX0
CLKX1
16
McASP1
HPI
(16-Bit)
McBSP0
McBSP1
TIMER1
TIMER0
GP0
and
EXT_INT
I2C0
I2C1
TINP1
TOUT1/LENDIAN
TINP0
TOUT0
GP0[ 3:0]
GP0[7:4]
SCL0
SDA0
SCL1
SDA1
PERCFG Register Value: 0x0000_018F [CPU/4 option [default] and AFSR1, ACLKR1 pins selected]
External Pins: TOUT0/HPI_EN
= 0; HD5 = 0 (IPU)
Figure 3−6. Configuration Example A
(HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO)
54
April 2004 − Revised May 2005SPRS247E
3.10 Terminal Functions
The terminal functions table (Table 3−9) identifies the external signal names, the associated pin (ball) numbers
along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
Terminal Functions
April 2004 − Revised May 2005 SPRS247E
55
Terminal Functions
†
IPD/
DESCRIPTION
Clock mode selects
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
Table 3−9. Terminal Functions
SIGNAL
NAME NO.
TYPE
IPD/
IPU
‡
CLOCK/PLL CONFIGURATION
CLKIN A12 I IPD Clock Input. This clock is the input to the on-chip PLL.
CLKOUT4/GP0[1]
CLKOUT6/GP0[2]
§
§
A2 I/O/Z IPU
B3 I/O/Z IPU
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 1 pin (I/O/Z).
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
CLKIN select. Selects whether the PLL input clock is CLKIN [pin high] or directly from
CLKINSEL A11 I IPU
the crystal oscillator (OSCIN and OSCOUT) [pin low].
For proper device operation, this pin must be used in conjunction with the OSC_DIS
pin.
CLKMODE3 C11 I IPD
CLKMODE2 B10 I IPD
CLKMODE1 A13 I IPD
CLKMODE0 C13 I IPD
¶
PLLV
C12 A PLL voltage supply
Clock mode selects
• Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x5,
x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
PLL section of this data sheet.
OSCIN A6 I — Crystal oscillator Input (XI)
OSCOUT A7 O — Crystal oscillator output (XO)
Power for crystal oscillator (1.2 V), Do not connect to board power 1.4 V; for optimum
OSCV
DD
B6 S —
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to CV
DD
.
Ground for crystal oscillator, Do not connect to board ground; for optimum
OSCV
SS
C6 GND —
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to VSS.
Oscillator disable select.
OSC_DIS B7 I IPU
For proper device operation, this pin must follow the CLKINSEL pin operation.
0 − OSC enabled; CLKINSEL must be 0
1 − OSC disabled (default); CLKINSEL must be 1
JTAG EMULATION
TMS U3 I IPU JTAG test-port mode select
TDO T4 O/Z IPU JTAG test-port data out
TDI T1 I IPU JTAG test-port data in
TCK T2 I IPU JTAG test-port clock
TRST U1 I IPD
EMU0 R1 I/O/Z IPU Emulation pin 0
EMU1 T3 I/O/Z IPU Emulation pin 1
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
¶
PLLV is not part of external voltage supply. See the Clock PLL and Oscillator section for information on how to connect this pin.
#
The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
#
#
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ
resistor.
56
April 2004 − Revised May 2005SPRS247E
Terminal Functions
pp p p ( )p ( )p(py)
p
• When these pins function as External Interrupts [by selecting the corresponding
pp()[ ] p p p p ( )[ ]p
GP0 [3:0] pins (I/O/Z)
g
Clock output at 1/4 of the device
d (O/Z) [default] or this pin
a GP0 1 pin (I/O/Z)
Table 3−9. Terminal Functions (Continued)
IPD/
NAME NO.
EMU2 R2 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU3 U2 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU4 R3 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU5 P2 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU6 R4 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected.
EMU7 V2 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected.
EMU8 V1 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected.
EMU9 V3 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected.
EMU10 W3 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected.
EMU11 W2 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET C9 I Device reset
NMI B9 I IPD Nonmaskable interrupt, edge-driven (rising edge)
GP0[7]/EXT_INT7 Y1 I/O/Z IPU
GP0[6]/EXT_INT6 C4 I/O/Z IPU
GP0[5]/EXT_INT5 B4 I/O/Z IPU
GP0[4]/EXT_INT4 A4 I/O/Z IPU
HD15/GP0[15] Y12
HD14/GP0[14] AA12
HD13/GP0[13
]
AB13
HD12/GP0[12] Y14
HD11/GP0[11] AB14
HD10/GP0[10] AA15
HD9/GP0[9] Y16
HD8/GP0[8] AB16
GP0[3] B13 I/O/Z IPD
CLKOUT6/GP0[2]
CLKOUT4/GP0[1]
§
§
B3 I/O/Z IPU
A2 I/O/Z IPU
GP0[0] D13 I/O/Z IPD
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
I/O/Z IPU
‡
DESCRIPTION
JTAG EMULATION (CONTINUED)
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only).
The default after reset setting is GPIO enabled as input-only.
• When these
ins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
Host-port data pins (I/O/Z) [default] or General-purpose input/output (GP0) [15:8] pins
(I/O/Z)
GP0 [3:0] pins (I/O/Z)
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
a GP0 1 pin (I/O/Z).
.
spee
can be programmed as
April 2004 − Revised May 2005 SPRS247E
57
Terminal Functions
Only one p
asserted d
access
• Only one pin is asserted during any external data access
EMIFA byte enable control
• Byte-write enables for most types of memory
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
EMIFA (32-BIT) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3 H19 O/Z IPU
ACE2 N20 O/Z IPU
ACE1 R20 O/Z IPU
ACE0 F20 O/Z IPU
ABE3 AB21 O/Z IPU
ABE2 P21 O/Z IPU
ABE1 A22 O/Z IPU
ABE0 D16 O/Z IPU
APDT T19 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals
AHOLDA J21 O IPU EMIFA hold-request-acknowledge to the host
AHOLD J22 I IPU EMIFA hold request from the host
ABUSREQ R19 O IPU EMIFA bus request output
EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
AECLKIN K22 I IPD
AECLKOUT2 U22 O/Z IPD
AECLKOUT1 F22 O/Z IPD
AARE/
ASDCAS
ASADS
/
/ASRE
D20 O/Z IPU
AAOE/
ASDRAS
/
E20 O/Z IPU
ASOE
AAWE/
ASDWE
/
C20 O/Z IPU
ASWE
ASDCKE K21 O/Z IPU
ASOE3 P19 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
AARDY L21 I IPU Asynchronous memory ready input
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
TYPE
†
IPU
‡
EMIFA memory space enables
• Enabled by bits 28 through 31 of the word address
•
in is
EMIFA byte-enable control
• Decoded from the low-order address bits. The number of address bits or byte
enables used depends on the width of external memory.
•
-
• Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFA (32-BIT) − BUS ARBITRATION
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) frequency divided-by-1, -2, or -4.
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
• For programmable synchronous interface, the RENEN field in the CE Space
Secondary Control Register (CExSEC) selects between ASADS
If RENEN = 0, then the ASADS
If RENEN = 1, then the ASADS
EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
EMIFA SDRAM clock-enable (used for self-refresh mode).
• If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
uring any external data
and ASRE:
/ASRE signal functions as the ASADS signal.
/ASRE signal functions as the ASRE signal.
58
April 2004 − Revised May 2005SPRS247E
Terminal Functions
a
ces (e.g., C6
,
maintain signal name compatibility with other C64x™ devices (e.g., C6411, C6414
,)[ g
p/p
• Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors
([ ])
10−Reserved
EMIF clock sel
[] ( _[])
01−CPU/4 Clock Rat
10 CPU/6 Clock Rate
For
the Device Confi
f this data sheet
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
AEA22 M21
AEA21 N21
AEA20 P22
AEA19 N22
AEA18 H22
AEA17 H21
AEA16 J20
AEA15 H20
AEA14 G20
AEA13 K20
AEA12 B21
AEA11 B22
AEA10 D21
AEA9 D22
AEA8 E21
AEA7 E22
AEA6 F21
AEA5 M20
AEA4 J19
AEA3 L20
AED31 W21
AED30 W22
AED29 V20
AED28 W20
AED27 AA22
AED26 Y20
AED25 AA21
AED24 AB22
AED23 P20
AED22 R22
AED21 R21
AED20 U21
AED19 V21
AED18 T20
AED17 V22
AED16 U20
AED15 A18
AED14 D17
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
‡
EMIFA (32-BIT) − ADDRESS
I/O/Z IPD
EMIFA external address (word address)
Note: EMIF address numbering for the C6413/C6410 devices starts with AEA3 to
intain signal name compatibility with other C64x™ devi
m
C6415, and C6416) [see the 64-bit EMIF adressing scheme in the TMS320C6000 DSP
External Memory Interface (EMIF) Reference Guide (literature number SPRU266)].
• Also controls initialization of DSP modes at reset (I) via pullu
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI boot (based on HPI_EN pin)
10 − Reserved
11 − EMIFA 8-bit ROM boot
O/Z IPD
−
− AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
−
10 − CPU/6 Clock Rate
11 − Reserved
more details, see
EMIFA (32-BIT) − DATA
I/O/Z IPU EMIFA external data
ect
e
gurations section o
411, C6414
ulldown resistors
.
,
April 2004 − Revised May 2005 SPRS247E
59
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
AED13 B18
AED12 C18
AED11 A19
AED10 C19
AED9 B19
AED8 A21
AED7 D15
AED6 A15
AED5 B15
AED4 C15
AED3 A16
AED2 C16
AED1 B16
AED0 C17
− No external pins. The timer 2 peripheral pins are not pinned out as external pins.
TOUT1/LENDIAN AA1 I/O/Z IPU
TINP1 AB1 I IPD Timer 1 or general-purpose input
TOUT0/HPI_EN AA2 I/O/Z IPD
TINP0 AB2 I IPD Timer 0 or general-purpose input
SCL1 AA18 I/O/Z — I2C1 clock. When the I2C module is used, use an external pullup resistor on this pin.
SDA1 AA19 I/O/Z — I2C1 data. When I2C is used, ensure there is an external pullup resistors on this pin.
SCL0 AB18 I/O/Z — I2C0 clock. When I2C is used, ensure there is an external pullup resistors on this pin.
SDA0 AB19 I/O/Z — I2C0 data. When I2C is used, ensure there is an external pullup resistors on this pin.
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
‡
EMIFA (32-BIT) − DATA (CONTINUED)
I/O/Z IPU EMIFA external data
TIMER 2
TIMER 1
Timer 1 output (O/Z) or device endian mode (I).
Also controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode
0 – Big Endian
1 − Little Endian (default)
For more details on LENDIAN, see the Device Configurations section of this data sheet.
TIMER 0
Timer 0 output pin and HPI enable HPI_EN pin function
The HPI_EN
pin function selects whether the HPI peripheral or McASP1 peripheral,
and GP0[15:8] pins are functionally enabled
0 – HPI is enabled and the McASP1 peripheral and GP0 [15:8] pins are disabled
(default mode); [HPI32, if HD5 = 1; HPI16 if HD5 = 0]
1 − HPI I is disabled and the McASP1 peripheral and GP0 [15:8] pins are
enabled
For more details, see the Device Configurations section of this data sheet.
INTER-INTEGRATED CIRCUIT 1 (I2C1)
INTER-INTEGRATED CIRCUIT 0 (I2C0)
60
April 2004 − Revised May 2005SPRS247E
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
CLKR1 G3 I/O/Z IPD McBSP1 receive clock
FSR1 G2 I/O/Z IPD McBSP1 receive frame sync
DR1 F1 I IPD McBSP1 receive data
CLKS1 G1 I IPD McBSP1 external clock source (as opposed to internal)
DX1 H2 O/Z IPD McBSP1 transmit data
FSX1 H3 I/O/Z IPD McBSP1 transmit frame sync
CLKX1 H1 I/O/Z IPD McBSP1 transmit clock
CLKR0 C2 I/O/Z IPD McBSP0 receive clock
FSR0 D1 I/O/Z IPD McBSP0 receive frame sync
DR0 D2 I IPD McBSP0 receive data
CLKS0 D3 I IPD McBSP0 external clock source (as opposed to internal)
DX0 E2 O/Z IPD McBSP0 transmit data
FSX0 E4 I/O/Z IPD McBSP0 transmit frame sync
CLKX0 E3 I/O/Z IPD McBSP0 transmit clock
AHCLKX0 N1 I/O/Z IPD McASP0 transmit high-frequency master clock.
AFSX0 M2 I/O/Z IPD McASP0 transmit frame sync or left/right clock (LRCLK).
ACLKX0 M1 I/O/Z IPD McASP0 transmit bit clock.
AMUTE0 K4 I/O/Z IPD McASP0 mute output.
AMUTEIN0 J4 I IPD McASP0 mute input.
AHCLKR0 L1 I/O/Z IPD McASP0 receive high-frequency master clock.
AFSR0 K2 I/O/Z IPD McASP0 receive frame sync or left/right clock (LRCLK).
ACLKR0 K1 I/O/Z IPD McASP0 receive bit clock.
AXR0[5] P3 McASP0 TX/RX data pin [5].
AXR0[4] N3 McASP0 TX/RX data pin [4].
AXR0[3] M3
AXR0[2] L3
AXR0[1] K3 McASP0 TX/RX data pin [1].
AXR0[0] L2 McASP0 TX/RX data pins[0].
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
‡
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)
I/O/Z IPD
McASP0 TX/RX data pins [3].
McASP0 TX/RX data pin [2].
April 2004 − Revised May 2005 SPRS247E
61
Terminal Functions
I
IPU
I
IPU
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
HCNTL0/AFSR1[1] Y6
HHWIL/AFSR1[2] Y7
HR/W/AFSR1[3] AA5
HAS/ACLKR1[1] Y5 Host address strobe (I) [default] or McASP1 receive clock input 1 (I).
HCS/ACLKR1[2] AA11 Host chip select (I) [default] or McASP1 receive clock input 2 (I).
HDS1/ACLKR1[3] AB11 Host data strobe 1 (I) [default] or McASP1 receive clock input 3 (I).
HD27/AHCLKX1 Y4 I/O/Z IPU
HD22/AFSX1 AB5 I/O/Z IPU
HD24/ACLKX1 AA4 I/O/Z IPU Host-port data pin 24 (I/O/Z) [default] or McASP1 transmit bit clock (I/O/Z).
HD28/AMUTE1 W10 I/O/Z IPU Host-port data pin 28 (I/O/Z) [default] or McASP1 mute output (I/O/Z).
HD29/AMUTEIN1 W11 I IPU Host-port data pin 29 (I/O/Z) [default] or McASP1 mute input (I).
HD26/AHCLKR1 AB4 I/O/Z IPU
HD23/AFSR1 AB9 I/O/Z IPU
HD25/ACLKR1 AA9 I/O/Z IPU Host-port data pin 25 (I/O/Z) [default] or McASP1 receive bit clock (I/O/Z).
HD21/AXR1[5] Y9
HD20/AXR1[4] AB8
HD19/AXR1[3] AA6
HD18/AXR1[2] AB7
HD17/AXR1[1] AA7
HD16/AXR1[0] AB6
HINT AA8 O/Z IPU Host interrupt from DSP to host (O)
HCNTL1 W7 I IPU Host control − selects between control, address, or data registers (I)
HCNTL0/AFSR1[1] Y6
HHWIL/AFSR1[2] Y7
HR/W/AFSR1[3] AA5
HAS/ACLKR1[1] Y5 Host address strobe (I) [default] or McASP1 receive clock input 1 (I).
HCS/ACLKR1[2] AA11 Host chip select (I) [default] or McASP1 receive clock input 2 (I).
HDS1/ACLKR1[3] AB11 Host data strobe 1 (I) [default] or McASP1 receive clock input 3 (I).
HDS2 AB12 I IPU Host data strobe 2 (I)
HRDY Y10 O/Z IPU Host ready from DSP to host (O)
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
‡
MCASP1
Host control − selects between control, address, or data registers (I) [default] or
McASP1 receive frame sync input 1 (I).
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] oror McASP1 receive frame sync
input 2 (I) .
Host read or write select (I) [default] or McASP1 receive frame sync input 3 (I).
Host-port data pin 27 (I/O/Z) [default] or McASP1 transmit high-frequency master clock
(I/O/Z).
Host-port data pin 22 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (I/O/Z) .
Host-port data pin 26 (I/O/Z) [default] or McASP1 receive high-frequency master clock
(I/O/Z).
Host-port data pin 23 (I/O/Z) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
I/O/Z IPU Host-port data pins [21:16] (I/O/Z) [default] or McASP1 TX/RX data pins [5:0] (I/O/Z).
HOST-PORT INTERFACE (HPI)
Host control − selects between control, address, or data registers (I) [default] or
McASP1 receive frame sync input 1 (I).
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or McASP1 receive frame sync
input 2 (I).
Host read or write select (I) [default] or McASP1 receive frame sync input 3 (I).
62
April 2004 − Revised May 2005SPRS247E
Terminal Functions
Host port data [15:8] pins (I/O/Z) [default] or General purpose input/output (GP0) [15:8]
Host port data [7:0] pins (I/O/Z)
p
pulldown resistor on the HD5 pin (I):
(
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
pgp )
HD5 pin = 1: HPI operates as an HPI32
Table 3−9. Terminal Functions (Continued)
IPD/
NAME DESCRIPTION
NO.
HD31 Y8 I/O/Z IPU Host-port data pin 31 (I/O/Z)
HD30 Y11 I/O/Z IPU Host-port data pin 30 (I/O/Z)
HD29/AMUTEIN1 W11 I IPU Host-port data pin 29 (I/O/Z) [default] or McASP1 mute input (I).
HD28/AMUTE1 W10 I/O/Z IPU Host-port data pin 28 (I/O/Z) [default] or McASP1 mute output (I/O/Z).
HD27/AHCLKX1 Y4 I/O/Z IPU
HD26/AHCLKR1 AB4 I/O/Z IPU
HD25/ACLKR1 AA9 I/O/Z IPU Host-port data pin 25 (I/O/Z) [default] or McASP1 receive bit clock (I/O/Z).
HD24/ACLKX1 AA4 I/O/Z IPU Host-port data pin 24 (I/O/Z) [default] or McASP1 transmit bit clock (I/O/Z).
HD23/AFSR1 AB9 I/O/Z IPU
HD22/AFSX1 AB5 I/O/Z IPU
HD21/AXR1[5] Y9
HD20/AXR1[4] AB8
HD19/AXR1[3] AA6
HD18/AXR1[2] AB7
HD17/AXR1[1] AA7
HD16/AXR1[0] AB6
HD15/GP0[15] Y12
HD14/GP0[14] AA12
HD13/GP0[13
]
AB13
HD12/GP0[12] Y14
HD11/GP0[11] AB14
HD10/GP0[10] AA15
HD9/GP0[9] Y16
HD8/GP0[8] AB16
HD7 W12
HD6 AA13
HD5 Y13
HD4 AA14
HD3 AB15
HD2 AA16
HD1 Y15
HD0 W15
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
†
TYPE
IPU
‡
HOST-PORT INTERFACE (HPI) (CONTINUED)
Host-port data pin 27 (I/O/Z) [default] or McASP1 transmit high-frequency master clock
(I/O/Z).
Host-port data pin 26 (I/O/Z) [default] or McASP1 receive high-frequency master clock
(I/O/Z).
Host-port data pin 23 (I/O/Z) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
Host-port data pin 22 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
I/O/Z IPU Host-port data [21:16] pin (I/O/Z) [default] or McASP1 TX/RX data pins [5:0] (I/O/Z).
I/O/Z IPU
Host-port data [15:8] pins (I/O/Z) [default] or General-purpose input/output (GP0) [15:8]
pins (I/O/Z).
Host-port data [7:0] pins (I/O/Z)
Host-Port bus width user-configurable at device reset via a 1-kΩ pullup/
ulldown resistor on the HD5 pin (I):
I/O/Z IPU
HD5 pin = 0: HPI operates as an HPI16.
HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
=
.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
April 2004 − Revised May 2005 SPRS247E
63
Terminal Functions
†
IPD/
DESCRIPTION
RSV
Reserved (leave unconnected, do not connect to power or ground)
DV
DD
S
3.3 V supply voltage
Table 3−9. Terminal Functions (Continued)
SIGNAL
NAME NO.
TYPE
IPD/
IPU
‡
RESERVED FOR TEST
RSV U4 A — Reserved. This pin must be connected directly to CVDD for proper device operation.
RSV F3 A — Reserved. This pin must be connected directly to DVDD for proper device operation.
RSV C8 I IPD Reserved. This pin must be connected directly to VSS for proper device operation.
B11 A —
B12 I —
RSV
C10 O IPU
Reserved (leave unconnected, do not connect to power or ground)
D7 O/Z —
D8 O/Z —
SUPPLY VOLTAGE PINS
A3
A5
A8
A9
A14
A17
A20
B1
C22
E1
G22
DV
DD
J1
S 3.3-V supply voltage
M22
P1
T22
W1
Y2
Y17
Y19
Y22
AB3
AB10
AB17
AB20
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
64
April 2004 − Revised May 2005SPRS247E
Table 3−9. Terminal Functions (Continued)
Terminal Functions
SIGNAL
NAME
NO.
TYPE
TYPE
IPD/
IPD/
†
†
IPU
IPU
‡
‡
DESCRIPTION
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
D5
D6
D9
D11
D12
D14
D18
E19
F19
G4
H4
CV
DD
L19
S 1.2-V supply voltage (-400, -500 devices)
M4
M19
N4
V4
V19
W5
W9
W13
W16
W18
GROUND PINS
A1
A10
B2
B5
B8
B14
V
SS
B17
GND Ground pins
B20
C1
C3
C5
C7
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
April 2004 − Revised May 2005 SPRS247E
65
Terminal Functions
Table 3−9. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE
TYPE
IPD/
IPD/
†
†
IPU
IPU
‡
‡
DESCRIPTION
DESCRIPTION
GROUND PINS (CONTINUED)
C14
C21
D4
D10
D19
F2
F4
G19
G21
J2
J3
K19
L4
L22
N2
N19
V
SS
P4
GND Ground pins
T21
U19
W4
W6
W8
W14
W17
W19
Y3
Y18
Y21
AA3
AA10
AA17
AA20
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
66
April 2004 − Revised May 2005SPRS247E
3.11 Development Support
In case the customer would like to develop their own features and software on the TMS320C6413/C6410
device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool’s support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of C6000™ DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Development Support
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
April 2004 − Revised May 2005 SPRS247E
67
Device Support
3.12 Device Support
3.12.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications.
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification.
TMS Fully qualified production device.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GTS), the temperature range (for example, “A” is the extended temperature range), and
the device speed range in megahertz (for example, -500 is 500 MHz). Figure 3−7 provides a legend for
reading the complete device name for any TMS320C6000™ DSP platform member.
The ZTS package, like the GTS package, is a 288-ball plastic BGA only with PB-free balls. For device part
numbers and further ordering information for TMS320C6413/C6410 in the GTS and ZTS package types, see
the TI website (http://www.ti.com) or contact your TI sales representative.
68
April 2004 − Revised May 2005SPRS247E
Device Support
TMS 320 C6413 GTS 500
( A )
PREFIX DEVICE SPEED RANGE
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
SMX= Experimental device, MIL
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
500 (500-MHz CPU, 100-MHz EMIF) [C6413]
400 (400-MHz CPU, 100-MHz EMIF) [C6410]
Blank = 0°C to 90°C, commercial temperature
A=−40°C to 105°C, extended temperature
†
DEVICE FAMILY
320 = TMS320t DSP family
†
The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices.
For more details, see the recommended operating conditions portion of this data sheet.
‡
BGA = Ball Grid Array
§
The ZTS mechanical package designator represents the version of the GTS package with Pb-free balls. For more detailed
information, see the Mechanical Data section of this document.
¶
For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
PACKAGE TYPE
GTS = 288-pin plastic BGA
ZTS = 288-pin plastic BGA, with Pb-free soldered balls
¶
DEVICE
C64x DSP:
6413
6410
§
‡
Figure 3−7. TMS320C6413/C6410 DSP Device Nomenclature
For additional information, see the TMS320C6413, TMS320C6410 Digital Signal Processors Silicon Errata
(literature number SPRZ219)
April 2004 − Revised May 2005 SPRS247E
69
Device Support
3.12.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets, such as this document, with design specifications; complete user’s reference guides for all devices
and tools; technical briefs; development-support tools; on-line help; and hardware and software applications.
The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000™ DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x™
digital signal processor, and discusses the application areas that are enhanced by the C64x™ DSP
VelociTI.2™ VLIW architecture.
The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripheral.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
describes the functionality of the I2C peripherals available on the C6413/C6410 device except for the
additional interrupt and new GPIO capability. For more detailed information on the additional interrupt and
GPIO capability, see the I2C section of this data manual and the TMS320C6410/C6413 DSP Inter-Integrated
Circuit (I2C) Module Reference Guide (literature number SPRZ221).
The TMS320C6413, TMS320C6410 Digital Signal Processors Silicon Errata (literature number SPRZ219)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320C6413 and TMS320C6410 devices.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio™ Integrated
Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
TMS320 is a trademark of Texas Instruments.
70
April 2004 − Revised May 2005SPRS247E
Peripherals Detailed Description (Device-Specific)
4 Peripherals Detailed Description (Device-Specific)
4.1 Clock PLL and Oscillator
Most of the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 4−1
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
April 2004 − Revised May 2005 SPRS247E
71
Clock PLL and Oscillator
‡
CLKMODE0
CLKMODE1
CLKMODE2
CLKMODE3
C5
470 pF
†
C7
†
C8
3.3 V
†
R
C6
470 pF
CPU Clock
EMI
Filter
C2C1
10 µF 0.1 µF
PLLV
PLLMULT
/2
/8
/4
/6
Peripheral Bus, EDMA
Clock
Timer Internal Clock
CLKOUT4, Peripheral Clock
CLKOUT6
PLL
x5, x6−x12, x16,
x18−x22, x24
PLLCLK
1
0
00 01 10
/4
/2
CLKINSEL
CLKIN
OSCV
OSCIN
DD
‡
1
EMIF 00 01 10
0
†
†
S
OSCOUT
R
B
SS
‡
OSCV
Osc.
EK2RATE
(GBLCTL.[19,18])
AUXCLK
for McASPs
OSC_DIS
AECLKIN
AEA[20:19]
Internal to C6413/10
(For the PLL options, CLKMODE pins setup, and PLL clock frequency ranges,
see Table 4−1 and Table 4−2.)
†
Exact values for these components depend on choice of crystal. For recommended crystal and component values, see Table 4−3.
‡
Do not connect any of these nodes to board power or ground if the oscillator is used. They are internally connected for proper operation.
If CLKIN is being used instead of the oscillator, then OSCV
OSCV
may be tied to ground.
SS
and OSCVSS may either be left open, or OSCVDD may be tied to CVDD and
DD
ECLKOUT2ECLKOUT1
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000™ DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
DD
.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
E. If CLKIN is used instead of OSCIN, tie OSCIN to Ground to minimize noise and current. (Do not leave OSCIN floating.)
Figure 4−1. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
72
April 2004 − Revised May 2005SPRS247E
Clock PLL and Oscillator
75
For proper C6413/C6410 device operation, the CLKINSEL pin must be used in conjunction with the OSC_DIS
pin. The OSC_DIS pin must follow the CLKINSEL pin operation. For more details on these two configuration
pins, see the Device Configuration at Device Reset section of this data sheet.
Table 4−1. TMS320C6413 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −500 Devices
GTS and ZTS PACKAGES − 23 x 23 mm BGA
CLKMODE[3:0]
0 0 0 0 Bypass (x1) 12−100 12−100 12−30 12−30 N/A
0 0 0 1 x5 28−100 140−500 28−30 140−150
0 0 1 0 x6 23−83 140−500 23−30 140−180
0 0 1 1 x7 20−71 140−500 20−30 140−210
0 1 0 0 x8 17−63 140−500 17−30 140−240
0 1 0 1 x9 15−56 140−500 15−30 140−270
0 1 1 0 x10 14−50 140−500 14−30 140−300
0 1 1 1 x11 12−45 140−500 12−30 140−330
1 0 0 0 x12 12−42 144−500 12−30 144−360
1 0 0 1 x16 12−31 192−500 12−30 192−480
1 0 1 0 x18 12−28 216−500 12−28 216−500
1 0 1 1 x19 12−26 228−500 12−26 228−500
1 1 0 0 x20 12−25 240−500 12−25 240−500
1 1 0 1 x21 12−24 252−500 12−24 252−500
1 1 1 0 x22 12−23 264−500 12−23 264−500
1 1 1 1 x24 12−21 288−500 12−21 288−500
†
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6413/C6410 device to one of the valid PLL
multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). With internal pulldown resistors on the CLKMODE
pins (CLKMODE3, CLKMODE2, CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
‡
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
(PLL MULTIPLY FACTORS)
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
†
OSCIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
TYPICAL
LOCK TIME
‡
(µs)
75
April 2004 − Revised May 2005 SPRS247E
73
Clock PLL and Oscillator
75
Table 4−2. TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −400 Devices
GTS and ZTS PACKAGES − 23 x 23 mm BGA
CLKMODE[3:0]
0 0 0 0 Bypass (x1) 12−100 12−100 12−30 12−30 N/A
0 0 0 1 x5 28−80 140−400 28−30 140−150
0 0 1 0 x6 23−67 140−400 23−30 140−180
0 0 1 1 x7 20−57 140−400 20−30 140−210
0 1 0 0 x8 17−50 140−400 17−30 140−240
0 1 0 1 x9 15−44 140−400 15−30 140−270
0 1 1 0 x10 14−40 140−400 14−30 140−300
0 1 1 1 x11 12−36 140−400 12−30 140−330
1 0 0 0 x12 12−33 144−400 12−30 144−360
1 0 0 1 x16 12−25 192−400 12−25 192−400
1 0 1 0 x18 12−22 216−400 12−22 216−400
1 0 1 1 x19 12−21 228−400 12−21 228−400
1 1 0 0 x20 12−20 240−400 12−20 240−400
1 1 0 1 x21 12−19 252−400 12−19 252−400
1 1 1 0 x22 12−18 264−400 12−18 264−400
1 1 1 1 x24 12−17 288−400 12−17 288−400
†
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6413/C6410 device to one of the valid PLL
multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). With internal pulldown resistors on the CLKMODE
pins (CLKMODE3, CLKMODE2, CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
‡
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
(PLL MULTIPLY FACTORS)
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
†
OSCIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
TYPICAL
LOCK TIME
‡
(µs)
75
For the lowest jitter on the oscillator circuit, it is recommended that a pair of 470-pF capacitors be connected
between isolated (not directly connected to the board supply) OSCV
and OSCVSS pins. This helps to cancel
DD
out switching noise from other circuits on the DSP device.
Table 4−3 shows a recommended crystal and tank circuit values for the C6413/C6410 PLL circuitry.
Table 4−3. Crystal and Tank Circuit Recommendations
Components RECOMMENDED PART NUMBERS or VALUES MANUFACTURER
1AS245766AHA (SMD-49)
1AF245766AAA (AT-49)
1AS225796AG (SMD-49)
1AF225796A (AT-49)
1 MΩ —
0 Ω —
8 pF —
KDS™ Diashinku Corp.
Crystal
R
B
R
S
C7
C8
24.576 MHz
22.5792 MHz
74
April 2004 − Revised May 2005SPRS247E
4.2 Host-Port Interface (HPI) Peripheral
The TMS320C6413/C6410 device includes a user-configurable 16-bit or 32-bit Host-port interface
(HPI16/HPI32). On the C6413/C6410 device the HPI peripheral pins are muxed with the McASP1 and GP0
peripheral pins. By default, the HPI peripheral pin functions are enabled. For more detailed information on the
C6413/C6410 device pin muxing, see the Device Configurations section of this data sheet.
The HPI peripheral can be disabled or enabled at reset through the HPI enable function of the TOUT0/HPI_EN
pin. The HPI is enabled when the TOUT0/HPI_EN pin is sampled low at reset and it is disabled if the pin is
sample high at reset. The TOUT0/HPI_EN
However, the HPI can be disabled via an external pullup resistor or by having an external device such as an
FPGA/CPLD drive that pin high at reset. In the latter case, the external device should ensure it has stopped
driving this pin to avoid contention. The HPI enable function can only be set a reset and cannot be changed
via software.
The HD5 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.
For more details on HPI peripheral configuration and the associated pins, see the Device Configurations
section of this data sheet.
Host-Port Interface (HPI) Peripheral
pin has an internal pulldown that enables the HPI by default.
April 2004 − Revised May 2005 SPRS247E
75
Multichannel Audio Serial Port (McASP) Peripheral
4.3 Multichannel Audio Serial Port (McASP) Peripheral
The TMS320C6413/C6410 device includes two multichannel audio serial port (McASP) interface peripheral
(McASP0 and McASP1). On the C6413/C6410 device the McASP1 peripheral pins are muxed with the HPI
peripheral pins. By default, the HPI peripheral pin functions are enabled. For the C6413/C6410 device
McASP1 is a standalone peripheral, not muxed. For more detailed information on the C6413/C6410 device
pin muxing, see the Device Configurations section of this data sheet.
The McASP is a serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely independently
with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit
and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that
may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio
data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as
well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP
Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
4.3.1 McASP Block Diagram
Figure 4−2 illustrates the major blocks along with external signals of the TMS320C6413/C6410 McASP
peripheral; and shows the 6 serial data [AXRx] pins. The McASP also includes full general-purpose I/O (GPIO)
control, so any pins not needed for serial transfers can be used for general-purpose I/O.
76
April 2004 − Revised May 2005SPRS247E
McASPx
Multichannel Audio Serial Port (McASP) Peripheral
DMA Transmit
DIT
RAM
Transmit
Clock Check
(High-
Frequency)
Error
Detect
Receive
Clock Check
(High-
Frequency)
Transmit
Data
Serializer 0
Serializer 1
Serializer 2
Serializer 3
Serializer 4
Serializer 5
Serializer 6
Transmit
Frame Sync
Generator
Transmit
Clock
Generator
Receive
Clock
Generator
Receive
Frame Sync
GeneratorFormatter
AFSXx
AHCLKXx
ACLKXx
AMUTEx
AMUTEINx
AHCLKRx
ACLKRx
†
AFSRx
AXRx[0]
AXRx[1]
AXRx[2]
AXRx[3]
AXRx[4]
AXRx[5]
†
Serializer 7
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
Receive
Data
Formatter
GPIO
Control
DMA Receive
†
On the C6413/C6410 device, the McASP1 peripheral has some additional pins muxed with AFSR1 and with ACLKR1 pins (i.e.,
AFSR1[1], AFSR1[2], AFSR1[3] and ACLKR1[1]. ACLKR1[2], ACLKR1[3], respectively).
‡
On the C6413/C6410 device, the McASP0 peripheral is standalone, not muxed and the McASP1 peripheral is muxed with the HPI
peripheral. For more detailed information on multiplexed pins, see the Device Configurations section of this data sheet.
Figure 4−2. McASP0 and McASP1‡ Configuration
April 2004 − Revised May 2005 SPRS247E
77
I2C
4.4 I2C
The TMS320C6413/C6410 device includes two I2C peripheral modules (I2C0 and I2C1). NOTE: when using
the I2C modules (any mode), ensure there are external pullup resistors on the SDAx and SCLx pins.
One of the I2C modules on the TMS320C6413/C6410 may be used by the DSP to control local peripherals
ICs (DACs, ADCs, etc.) while the other module may be used to communicate with other controllers in a system
or to implement a user interface.
The I2Cx port supports:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to remove noise 50 ns or less
• 7- and 10-Bit Device Addressing Modes
• Multi-Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• Slew-Rate Limited Open-Drain Output Buffers
• General-purpose input and output (GPIO) functionality for I2C pins
For more detailed information on C6413/6410 I2C additional features, such as GPIO capability, etc., see the
TMS320C6000 DSP Inter−Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
and the TMS320C6410/C6413/C6418 DSP Inter−Integrated Circuit (I2C) Module Reference Guide (literature
number SPRZ221) addendum.
78
April 2004 − Revised May 2005SPRS247E
Figure 4−3 is a block diagram of the I2C0 and I2C1 modules.
General-Purpose Input/Output (GPIO)
I2C Clock
I2C Data
SCL
SDA
I2Cx Module
GPIO Control
I2CPFUNCx
I2CPDIRx
I2CPDINx
I2CPDOUTx
I2CPDSETx
I2CPDCLRx
Noise
Filter
Pin
Function
Pin
Direction
Pin Data
In
Pin Data
Out
Pin Data
Set
Pin Data
Clear
Noise
Filter
Clock
Prescale
I2CPSCx
Bit Clock
Generator
I2CCLKHx
I2CCLKLx
Transmit
I2CXSRx
I2CDXRx
Receive
I2CDRRx
I2CRSRx
Transmit
Shift
Transmit
Buffer
Receive
Buffer
Receive
Shift
Peripheral Clock
(CPU/4)
Control
I2COARx
I2CSARx
I2CMDRx
I2CCNTx
I2CEMDRx
Interrupt/DMA
I2CIERx
I2CSTRx
I2CISRCx
Own
Address
Slave
Address
Mode
Data
Count
Extended
Mode
Interrupt
Enable
Interrupt
Status
Interrupt
Source
NOTE A: Shading denotes control/status registers.
Figure 4−3. I2Cx Module Block Diagram
4.5 General-Purpose Input/Output (GPIO)
On the C6413/C6410 device the GPIO peripheral pins GP0[15:9] are muxed with the HPI peripheral pins
HD[15:9], respectively. By default, the HPI peripheral pin functions are enabled [TOUT0/HPI_EN
pulled low]. For more detailed information on device/peripheral configuration and the C6413/C6410 device
pin muxing, see the Device Configurations section of this data sheet.
To use the GP0[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register
and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN = 1 GP[x] pin is enabled
GPxDIR = 0 GP[x] pin is an input
GPxDIR = 1 GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 4−4 shows the GPIO enable bits in the GPEN register for the C6413/C6410 device. To use any of the
GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 4−4 for the C6413/C6410 default
configuration.
April 2004 − Revised May 2005 SPRS247E
pin internall
79
General-Purpose Input/Output (GPIO)
31 24 23 16
Reserved
R-0
15 14 13 12 11
GP15
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend:
GP14ENGP13ENGP12ENGP11ENGP10ENGP9ENGP8ENGP7ENGP6ENGP5ENGP4ENGP3ENGP2ENGP1ENGP0
EN
R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
10 9 8 7 6543210
EN
Figure 4−4. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
80
April 2004 − Revised May 2005SPRS247E
General-Purpose Input/Output (GPIO)
Figure 4−5 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin
is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register.
By default, all the GPIO pins are configured as input pins.
31 24 23 16
Reserved
R-0
15 14 13 12 11
GP15
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
DIR
GP14
DIR
GP13
DIR
GP12
DIR
GP11
DIR
10
GP10
DIR
98
GP9
DIR
GP8
DIR
GP7
DIR
6
7
GP6
DIR
5
GP5
DIR
43
GP4
DIR
GP3
DIR
2
GP2
DIR
10
GP1
DIR
GP0
DIR
Figure 4−5. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
April 2004 − Revised May 2005 SPRS247E
81
Power-Down Modes Logic
4.6 Power-Down Modes Logic
Figure 4−6 shows the power-down mode logic on the C6413/C6410.
CLKOUT4
Internal Clock Tree
Clock
Distribution
and Dividers
PD1
PD2
CPU
IFR
IER
CSR
Internal
Peripherals
TMS320C6413/C6410
PD3
Power-
Down
Logic
PWRD
Clock
PLL
CLKIN RESET
†
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
CLKOUT6
Figure 4−6. Power-Down Mode Logic
Note: to further save power, the PERCFG register can be used to disable unused peripherals. For more
detailed information on disabling peripherals using the PERCFG register, see the Device Configurations
section of this data sheet.
4.6.1 Triggering, Wake-up, and Effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4−7 and described in
Table 4−4. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should
be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
†
82
April 2004 − Revised May 2005SPRS247E
Power-Down Modes Logic
31 16
15 14 13 12 11 10 9 8
Enable or
Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
PD3 PD2 PD1
Figure 4−7. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to
account for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect
upon PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 4−4 summarizes all the power-down modes.
April 2004 − Revised May 2005 SPRS247E
83
Power-Supply Sequencing
Power down mode blocks the internal clock inputs at the
Table 4−4. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
000000 No power-down — —
001001 PD1 Wake by an enabled interrupt
010001 PD1
011010 PD2
011100 PD3
All others Reserved — —
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
POWER-DOWN
MODE
†
†
WAKE-UP METHOD EFFECT ON CHIP’S OPERATION
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
Wake by an enabled or
non-enabled interrupt
Wake by a device reset
Wake by a device reset
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed between
peripherals and internal memory.
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
4.6.2 C64x Power-Down Mode with an Emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail.
A DSP reset will be required to get the DSP out of PD2/PD3.
4.7 Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
4.7.1 Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 4−8).
84
April 2004 − Revised May 2005SPRS247E
Power-Supply Sequencing
I/O Supply
DV
DD
Schottky
Diode
Core Supply
CV
V
GND
C6000
DSP
DD
SS
Figure 4−8. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the
other supply is below the proper operating voltage.
4.8 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the
core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than
1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF)
should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small
package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total)
be placed immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the
“exterior”.
Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the
order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per supply
(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any
component, verification of capacitor availability over the product’s production lifetime should be considered.
April 2004 − Revised May 2005 SPRS247E
85
Peripheral Power-Down Operation
4.9 Peripheral Power-Down Operation
The C6413/C6410 device can be powered down in two ways:
• Power-down due to software configuration − relates to the default state of the peripheral configuration bits
in the PERCFG register.
• Power-down during run-time via software configuration
On the C6413/C6410 device, the HPI, McASP1, and GP0 peripherals pin muxing is controlled (selected) at
the pin level during chip reset (e.g., HPI_EN
MCASP1EN bit in the peripheral configuration register (PERCFG.8) must be configured properly to enable
the McASP1 peripheral.
The McASP1, McASP0, I2C1, and I2C0 peripheral functions are selected via the peripheral configuration
(PERCFG) register bits.
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
and HD5 pins). If McASP1 pin muxing is selected, then the
86
April 2004 − Revised May 2005SPRS247E
4.10 IEEE 1149.1 JTAG Compatibility Statement
The TMS320C6413/C6410 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET
resets are required for proper operation.
initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
IEEE 1149.1 JTAG Compatibility Statement
Note: TRST
after TRST
While both TRST
DSP to boot properly. TRST
and DSP’s emulation logic in the reset state. TRST
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET
is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
is asserted.
and RESET need to be asserted upon power up, only RESET needs to be released for the
may be asserted indefinitely for normal operation, keeping the JTAG port interface
only needs to be released when it is necessary to use a
must be
released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET
For maximum reliability, the TMS320C6413/C6410 DSP includes an internal pulldown (IPD) on the TRST
to ensure that TRST
will always be asserted upon power up and the DSP’s internal emulation logic will always
be properly initialized. JTAG controllers from Texas Instruments actively drive TRST
third-party JTAG controllers may not drive TRST
using this type of JTAG controller, assert TRST
high but expect the use of a pullup resistor on TRST. When
to intialize the DSP after powerup and externally drive TRST
.
pin
high. However, some
high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320C6413/C6410 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6413/C6410 JTAG emulation, see the TMS320C6000 DSP Designing
for JTAG Emulation Reference Guide (literature number SPRU641).
4.11 EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
• 1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
• up to 1 CE space of buffers connected to EMIF
• EMIF trace lengths between 1 and 3 inches
• 143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the C6413/C6410 EMIF peripheral, see the TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide (literature number SPRU266).
April 2004 − Revised May 2005 SPRS247E
87
Bootmode
4.12 Bootmode
The C6413/C6410 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET
device configuration and boot mode.
The C6413/C6410 has three types of boot modes:
• Host boot
starts the processor running with the prescribed
If host boot is selected, upon release of RESET
, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the C6413/C6410 device, the HPI peripheral is used for host boot
providing the TOUT0/HPI_EN
pin is low, enabling the HPI peripheral [default]. Once the host is finished
with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot
process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The
CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it
occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only
if the host boot process is selected. All memory may be written to and read by the host. This allows for the
host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs
to clear the DSPINT, otherwise, no more DSPINTs can be received.
• EMIF boot (using default ROM timings)
Upon the release of RESET
, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
• No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
4.13 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET
operating conditions and CLKIN should also be running at the correct frequency.
88
(low-to-high transition), the core and I/O voltages should be at their proper
April 2004 − Revised May 2005SPRS247E
5 Device Electrical Specifications
Device Electrical Specifications
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)
†
Supply voltage ranges: CVDD (see Note 1) − 0.3 V to 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD (see Note 1) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: V
Output voltage range: V
I
O
Operating case temperature range, T
: (default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
−0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(A version) [GTSA and ZTSA] −40_C to 105_C. . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Temperature Cycling: Temperature Range −40_C to 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Number of Cycles (GTS, GTSA) 1000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Number of Cycles (ZTS, ZTSA) 500. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
5.2 Recommended Operating Conditions
MIN NOM MAX UNIT
CV
DV
V
V
V
V
T
C
‡
Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices.
§
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
Supply voltage, Core (-400, -500 device)
DD
Supply voltage, I/O 3.14 3.3 3.46 V
DD
Supply ground 0 0 0 V
SS
High-level input voltage 2 V
IH
Low-level input voltage 0.8 V
IL
Maximum voltage during overshoot/undershoot −1.0
OS
Operating case temperature
‡
Commercial temperature devices
(GTS and ZTS)
Extended temperature devices
(GTSA and ZTSA)
1.14 1.2 1.26 V
§
0 90 _C
−40 105 _C
4.3
§
V
April 2004 − Revised May 2005 SPRS247E
89
Device Electrical Specifications
IOLLow level output current
5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS
V
V
High-level output voltage DVDD = MIN, I
OH
Low-level output voltage DVDD = MIN, I
OL
VI = VSS to DVDD no opposing internal
resistor
= VSS to DVDD opposing internal
V
I
I
I
OH
Input current
High-level output current
I
pullup resistor
VI = VSS to DVDD opposing internal
pulldown resistor
‡
‡
EMIF, CLKOUT4, CLKOUT6, EMUx −16 mA
Timer, TDO, GPIO, McBSP, HPI
EMIF, CLKOUT4, CLKOUT6, EMUx 16 mA
I
OL
Low-level output current
Timer, TDO, GPIO, McBSP, HPI
SCL1, SDA1, SCL0, and SDA0 3 mA
I
OZ
I
CDD
I
DDD
C
C
†
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§
Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF for -500 and -400 speeds. This model
Off-state output current VO = DV
Core supply current
I/O supply current
Input capacitance 10 pF
i
Output capacitance 10 pF
o
§
§
CVDD = 1.2 V, CPU clock = 500 MHz 568 mA
CVDD = 1.2 V, CPU clock = 400 MHz 465 mA
DVDD = 3.3 V, CPU clock = 500 MHz 140 mA
DVDD = 3.3 V, CPU clock = 400 MHz 132 mA
or 0 V ±10 uA
DD
represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The
high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6410/13 Power
Consumption Summary application report (literature number SPRAA59).
†
= MAX 2.4 V
OH
= MAX 0.4 V
OL
MIN TYP MAX UNIT
±10 uA
50 100 150 uA
−150 −100 −50 uA
−8 mA
8 mA
5.4 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
90
April 2004 − Revised May 2005SPRS247E
6 Parameter Information
Device Electrical Specifications
Tester Pin Electronics
42 Ω 3.5 nH
4.0 pF 1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Transmission Line
Z0 = 50 Ω
(see note)
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
Figure 6−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Figure 6−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
and V
MIN for output clocks.
OH
Figure 6−3. Rise and Fall Transition Time Voltage Reference Levels
6.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
V
= 1.5 V
ref
MAX and VIH MIN for input clocks, V
IL
V
= VIH MIN (or VOH MIN)
ref
V
= VIL MAX (or VOL MAX)
ref
OL
MAX
April 2004 − Revised May 2005 SPRS247E
91
Device Electrical Specifications
6.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device
and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time
margin, but also tends to improve the input hold time margins (see Table 6−1 and Figure 6−4).
Figure 6−4 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 6−1. Board-Level Timing Example (see Figure 6−4)
NO. DESCRIPTION
1 Clock route delay
2 Minimum DSP hold time
3 Minimum DSP setup time
4 External device hold time requirement
5 External device setup time requirement
6 Control signal route delay
7 External device hold time
8 External device access time
9 DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
92
ECLKOUTx
(Output from DSP)
(Input to External Device)
(Input to External Device)
(Output from External Device)
† Control signals include data for Writes.
‡Data signals are generated during Reads from an external device.
ECLKOUTx
Control Signals
(Output from DSP)
Control Signals
Data Signals
Data Signals
(Input to DSP)
†
‡
‡
3
6
8
Figure 6−4. Board-Level Input/Output Timings
1
2
4
5
7
9
11
10
April 2004 − Revised May 2005SPRS247E
Peripheral Electrical Specifications
NO
UNIT
7 Peripheral Electrical Specifications
7.1 Input and Output Clocks
Table 7−1. Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT)
−400
.
NO.
1 f
OSC
†
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
Input oscillator frequency 12 30 MHz
OSCIN. For more details on these limitations, see Table 4−1 and Table 4−2 of the Clock PLL and Oscillator section of this data sheet.
Table 7−2. Timing Requirements for CLKIN
†‡§
(see Figure 7−1)
−400
−500
NO.
PLL MULT MODE x1 (BYPASS)
MIN MAX MIN MAX
1 t
c(CLKIN)
2 t
w(CLKINH)
3 t
w(CLKINL)
4 t
t(CLKIN)
5 t
J(CLKIN)
†
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
OSCIN. For more details on these limitations, see Table 4−1 and Table 4−2 of the Clock PLL and Oscillator section of this data sheet.
‡
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
Cycle time, CLKIN 10
Pulse duration, CLKIN high 0.45C 0.45C ns
Pulse duration, CLKIN low 0.45C 0.45C ns
Transition time, CLKIN 5 1 ns
Period jitter, CLKIN 0.02C 0.02C ns
5
1
2
†
83.3 10
4
−500
MIN MAX
†
83.3 ns
UNIT
UNIT
CLKIN
3
4
Figure 7−1. CLKIN Timing
April 2004 − Revised May 2005 SPRS247E
93
Input and Output Clocks
NO
PARAMETER
UNIT
NO
PARAMETER
UNIT
Table 7−3. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4
(see Figure 7−2)
−400
NO. PARAMETER
.
−500
MIN MAX
1 t
c(CKO4)
2 t
w(CKO4H)
3 t
w(CKO4L)
4 t
†
The reference points for the rise and fall transitions are measured at VOL MAX and V
‡
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§
P = 1/CPU clock frequency in nanoseconds (ns)
t(CKO4)
Cycle time, CLKOUT4 4P − 0.7 4P + 0.7 ns
Pulse duration, CLKOUT4 high 2P − 0.7 2P + 0.7 ns
Pulse duration, CLKOUT4 low 2P − 0.7 2P + 0.7 ns
Transition time, CLKOUT4 1 ns
MIN.
OH
21
4
CLKOUT4
3
4
Figure 7−2. CLKOUT4 Timing
Table 7−4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6
(see Figure 7−3)
†‡§
UNIT
†‡§
NO. PARAMETER
.
1 t
c(CKO6)
2 t
w(CKO6H)
3 t
w(CKO6L)
4 t
†
The reference points for the rise and fall transitions are measured at VOL MAX and V
‡
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§
P = 1/CPU clock frequency in nanoseconds (ns)
t(CKO6)
Cycle time, CLKOUT6 6P − 0.7 6P + 0.7 ns
Pulse duration, CLKOUT6 high 3P − 0.7 3P + 0.7 ns
Pulse duration, CLKOUT6 low 3P − 0.7 3P + 0.7 ns
Transition time, CLKOUT6 1 ns
21
CLKOUT6
Figure 7−3. CLKOUT6 Timing
−400
−500
UNIT
MIN MAX
MIN.
OH
4
3
4
94
April 2004 − Revised May 2005SPRS247E
Input and Output Clocks
NO
UNIT
NO
PARAMETER
UNIT
Table 7−5. Timing Requirements for AECLKIN for EMIFA
†‡§
(see Figure 7−4)
−400
NO.
.
−500
UNIT
MIN MAX
1 t
c(EKI)
2 t
w(EKIH)
3 t
w(EKIL)
4 t
t(EKI)
5 t
J(EKI)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
‡
The reference points for the rise and fall transitions are measured at VIL MAX and V
§
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
¶
Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
Cycle time, AECLKIN 6¶16P ns
Pulse duration, AECLKIN high 2.7 ns
Pulse duration, AECLKIN low 2.7 ns
Transition time, AECLKIN 3 ns
Period jitter, AECLKIN 0.02E ns
MIN.
IH
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. 100-MHz operation is achievable
if the requirements of the EMIF Device Speed section are met.
5
1
2
4
AECLKIN
3
4
Figure 7−4. AECLKIN Timing for EMIFA
Table 7−6. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module
NO. PARAMETER
.
1 t
c(EKO1)
2 t
w(EKO1H)
3 t
w(EKO1L)
4 t
t(EKO1)
5 t
d(EKIH-EKO1H)
6 t
d(EKIL-EKO1L)
§
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
#
The reference points for the rise and fall transitions are measured at VOL MAX and V
||
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN
AECLKOUT1
Cycle time, AECLKOUT1 E − 0.7 E + 0.7 ns
Pulse duration, AECLKOUT1 high EH − 0.7 EH + 0.7 ns
Pulse duration, AECLKOUT1 low EL − 0.7 EL + 0.7 ns
Transition time, AECLKOUT1 1 ns
Delay time, AECLKIN high to AECLKOUT1 high 1 8 ns
Delay time, AECLKIN low to AECLKOUT1 low 1 8 ns
1
5
§#||
(see Figure 7−5)
6
OH
MIN.
−400
−500
UNIT
MIN MAX
2
3
4
4
Figure 7−5. AECLKOUT1 Timing for the EMIFA Module
April 2004 − Revised May 2005 SPRS247E
95
Input and Output Clocks
NO
PARAMETER
UNIT
Table 7−7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module
NO. PARAMETER
.
1 t
c(EKO2)
2 t
w(EKO2H)
3 t
w(EKO2L)
4 t
t(EKO2)
5 t
d(EKIH-EKO2H)
6 t
d(EKIH-EKO2L)
†
The reference points for the rise and fall transitions are measured at VOL MAX and V
‡
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
AECLKIN
AECLKOUT2
Cycle time, AECLKOUT2 NE − 0.7 NE + 0.7 ns
Pulse duration, AECLKOUT2 high 0.5NE − 0.7 0.5NE + 0.7 ns
Pulse duration, AECLKOUT2 low 0.5NE − 0.7 0.5NE + 0.7 ns
Transition time, AECLKOUT2 1 ns
Delay time, ECLKIN high to AECLKOUT2 high 1 8 ns
Delay time, ECLKIN high to AECLKOUT2 low 1 8 ns
1
†‡
(see Figure 7−6)
5
6
OH
MIN.
−400
−500
UNIT
MIN MAX
3
2
4
4
Figure 7−6. AECLKOUT2 Timing for the EMIFA Module
96
April 2004 − Revised May 2005SPRS247E
Asynchronous Memory Timing
NO
UNIT
NO
PARAMETER
UNIT
7.2 Asynchronous Memory Timing
−400
−500
†‡
UNIT
Table 7−8. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(see Figure 7−7 and Figure 7−8)
NO.
.
MIN MAX
3 t
su(EDV-AREH)
4 t
h(AREH-EDV)
6 t
su(ARDY-EKO1H)
7 t
†
h(EKO1H-ARDY)
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. The ARDY signal is only recognized two cycles before the end of the programmed strobe time
and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after
ARDY is recognized high To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width
= 2E) to ensure setup and hold time is met.
‡
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
Setup time, AEDx valid before AARE high 6.5 ns
Hold time, AEDx valid after AARE high 1 ns
Setup time, AARDY valid before AECLKOUTx high 3 ns
Hold time, AARDY valid after AECLKOUTx high 3 ns
Table 7−9. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
NO. PARAMETER
.
1 t
osu(SELV-AREL)
2 t
oh(AREH-SELIV)
5 t
d(EKO1H-AREV)
8 t
osu(SELV-AWEL)
9 t
oh(AWEH-SELIV)
10 t
‡
§
¶
d(EKO1H-AWEV)
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
E = ECLKOUT1 period in ns for EMIFA
Select signals for EMIFA include: ACEx, ABE[3.:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].
Output setup time, select signals valid to AARE low RS * E − 1.5 ns
Output hold time, AARE high to select signals invalid RH * E − 1.9 ns
Delay time, AECLKOUTx high to AARE valid 1 7 ns
Output setup time, select signals valid to AAWE low WS * E − 1.7 ns
Output hold time, AAWE high to select signals invalid WH * E − 1.8 ns
Delay time, AECLKOUTx high to AAWE valid 1.3 7.1 ns
द
(see Figure 7−7 and Figure 7−8)
−400
−500
MIN MAX
UNIT
April 2004 − Revised May 2005 SPRS247E
97
Asynchronous Memory Timing
AECLKOUTx
ACEx
Setup = 2 Strobe = 3 Not Ready Hold = 2
1
2
2
2
ABE[3:0]
AEA[22:3]
1
BE
1
Address
3
4
AED[31:0]
2
/ASDRAS/ASOE
AAOE
AARE/ASDCAS/ASADS/ASRE
AAWE/ASDWE/ASWE
1
†
5
†
†
7
Read Data
5
7
66
AARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 7−7. Asynchronous Memory Read Timing for EMIFA
98
April 2004 − Revised May 2005SPRS247E
Asynchronous Memory Timing
Setup = 2
Strobe = 3 Not Ready
Hold = 2
AECLKOUTx
8
9
ACEx
9
9
9
10
ABE[3:0]
AEA[22:3]
AED[31:0]
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/ASRE
AAWE/ASDWE/ASWE
8
BE
8
Address
8
Write Data
†
†
10
†
77
6
6
AARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 7−8. Asynchronous Memory Write Timing for EMIFA
April 2004 − Revised May 2005 SPRS247E
99
Programmable Synchronous Interface Timing
NO
UNIT
NO
PARAMETER
UNIT
7.3 Programmable Synchronous Interface Timing
Table 7−10. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7−9)
−400
NO.
6 t
7 t
.
su(EDV-EKOxH)
h(EKOxH-EDV)
Setup time, read AEDx valid before AECLKOUTx high 3.1 ns
Hold time, read AEDx valid after AECLKOUTx high 1.5 ns
−500
MIN MAX
UNIT
Table 7−11. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module
NO. PARAMETER
.
1 t
d(EKOxH-CEV)
2 t
d(EKOxH-BEV)
3 t
d(EKOxH-BEIV)
4 t
d(EKOxH-EAV)
5 t
d(EKOxH-EAIV)
8 t
d(EKOxH-ADSV)
9 t
d(EKOxH-OEV)
10 t
d(EKOxH-EDV)
11 t
d(EKOxH-EDIV)
12 t
†
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
d(EKOxH-WEV)
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx
assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx
− Function of ASADS
/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
Delay time, AECLKOUTx high to ACEx valid 1.3 6.4 ns
Delay time, AECLKOUTx high to ABEx valid 6.4 ns
Delay time, AECLKOUTx high to ABEx invalid 1.3 ns
Delay time, AECLKOUTx high to AEAx valid 6.4 ns
Delay time, AECLKOUTx high to AEAx invalid 1.3 ns
Delay time, AECLKOUTx high to ASADS/ASRE valid 1.3 6.4 ns
Delay time, AECLKOUTx high to, ASOE valid 1.3 6.4 ns
Delay time, AECLKOUTx high to AEDx valid 6.4 ns
Delay time, AECLKOUTx high to AEDx invalid 1.3 ns
Delay time, AECLKOUTx high to ASWE valid 1.3 6.4 ns
is active when ASOE is active (CEEXT = 1).
/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
†
(see Figure 7−9−Figure 7−11)
MIN MAX
−400
−500
UNIT
100
April 2004 − Revised May 2005SPRS247E
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