Texas Instruments TMS320C6202 User Manual

Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6202 – 4-ns Instruction Cycle Time – 250-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 2000 MIPS

VelociTI Advanced Very Long Instruction Word (VLIW) ’C6200 CPU Core – Eight Highly Independent Functional

Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Result)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional

Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization

3M-Bit On-Chip SRAM – 2M-Bit Internal Program/Cache

– Two 128K-Byte Blocks Offer Improved

Concurrency Block 0: 128K Bytes Memory-Mapped Block 1: 128K Bytes Direct-Mapped

Cache/Memory-Mapped

– 1M-Bit Dual-Access Internal Data

(128K Bytes)

– Two 64K-Byte Blocks Offer Improved

Concurrency

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous

Memories: SDRAM or SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

Flexible Phase-Locked-Loop (PLL) Clock Generator

32-Bit Expansion Bus – Glueless/Low-Glue Interface to Popular

PCI Bridge Chips

– Glueless/Low-Glue Interface to Popular

Synchronous or Asynchronous

Microprocessor Buses – Master/Slave Functionality – Glueless Interface to Synchronous FIFOs

and Asynchronous Peripherals

Three Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA

Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

Two 32-Bit General-Purpose Timers

IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible

352-Pin BGA Package (GJL Suffix)

384-Pin BGA Package (GLS Suffix)

0.18-µm/5-Level Metal Process – CMOS Technology

3.3-V I/Os, 1.8-V Internal

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE

AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

111

GLS 384-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW)

16121314 1810

2622

19 211715

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16 18

10 12

3 9 21

4 6

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

description

The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

With performance of up to 2000 million instructions per second (MIPS) at a clock rate of 250 MHz, the ’C6202 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6202 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32–bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The ’C6202 can produce two multiply-accumulates (MACs) per cycle for a total of 500 million MACs per second (MMACS). The ’C6202 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6202 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of two 128K-byte blocks, with one block configured as memory-mapped program space, and the other block user-configured as cache or memory-mapped program space. Data memory consists of two 64K-byte blocks of RAM. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, an expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6202 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

device characteristics

T able 1 provides an overview of the ’C6202 DSP . The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

Table 1. Characteristics of the ’C6202 Processors

CHARACTERISTICS DESCRIPTION

Device Number TMS320C6202

2 Mbit Program Memory

On-Chip Memory

Peripherals

Cycle Time 4 ns Package Type

Nominal Voltage

(organized as 2 blocks) 1 Mbit Data Memory (organized as 2 blocks)

3 Multichannel Buffered Serial Ports (McBSP) 2 General-Purpose Timers External Memory Interface (EMIF) Expansion Bus (XB)

27 mm × 27 mm, 352-Pin BGA (GJL) 18 mm × 18 mm, 384-Pin BGA (GLS)

1.8 V Core

3.3 V I/O

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TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation.

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SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

functional block diagram

Timers

Interrupt Selector

McBSPs

XB Control

DMA Control

EMIF Control

Expansion Bus (XB)

Interface

PLL

Power

Down

Boot-

Config.

EMIF

Peripheral

Bus

Controller

DMA

Controller

Data Memory

Controller

CPU

Program Memory Controller

Program Memory/Cache

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C6200 CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally , each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

Another key feature of the ’C6200 CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

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SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

CPU description (continued)

Program Memory

32-Bit Address

256-Bit Data

External Memory

Interface

Data Path A Data Path B

.S1

.L1

.M1 .D1 .D2

Program Fetch

Instruction Dispatch

Instruction Decode

.M2

.S2 .L2

’C62x CPU

Control

Registers

Control

Logic

Test Emulation Interrupts

ADVANCE INFORMATION

Data Memory

32-Bit Address

8-, 16-, 32-Bit Data

Figure 1. TMS320C62x CPU Block Diagram

Additional

Peripherals:

Timers, Serial Ports,

etc.

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CPU description (continued)

Data Path A

DA1

DA2

ST1

LD1

LD2

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

src

dst

long dst

long src

long src long dst

dst

src src

dst

src src

dst src src

src src

dst

src src

dst

1 2

File A

(A0–A15)

2X 1X

.L1

.S1

.M1

.D1

.D2

.M2

Data Path B

src

dst

long dst

long src

long dst

dst src

src

.S2

ST2

.L2

Figure 2. TMS320C62x CPU Data Paths

File B

(B0–B15)

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Control

File

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SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

signal groups description

CLKIN CLKOUT2 CLKOUT1

CLKMODE0 CLKMODE1 CLKMODE2

PLLV

PLLG

PLLF

TMS TDO

TDI

TCK

TRST EMU1 EMU0

† †

Clock/PLL

IEEE Standard

1149.1

(JTAG)

Emulation

Reset and Interrupts

DMA Status

RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4

IACK INUM3 INUM2 INUM1 INUM0

DMAC3 DMAC2 DMAC1 DMAC0

ADVANCE INFORMATION

RSV4 RSV3 RSV2

RSV1 RSV0

†

For GLS devices only

Reserved

Figure 3. CPU Signals

Power-Down

Status

Control/Status

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signal groups description (continued)

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ED[31:0]

CE3 CE2 CE1 CE0

EA[21:2]

BE3 BE2 BE1 BE0

TOUT1

TINP1

Data

Memory Map

Space Select

Word Address

Byte Enables

Timer 1

Asynchronous

Memory

Control

Synchronous

Memory

Control

HOLD/

HOLDA

EMIF

(External Memory Interface)

Timer 0

Timers

McBSP0

Transmit

ARE AOE AWE ARDY

SDA10 SDRAS

/SSOE SDCAS/SSADS SDWE/SSWE

HOLD HOLDA

TOUT0 TINP0

CLKX0 FSX0 DX0

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

McBSP1

Transmit

Receive

Clock

McBSPs

(Multichannel Buffered Serial Ports)

Receive

Clock

McBSP2

Transmit

Receive

Clock

Figure 4. Peripheral Signals

CLKR0 FSR0 DR0

CLKS0

ADVANCE INFORMATION

CLKX2 FSX2 DX2

CLKR2 FSR2 DR2

CLKS2

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

signal groups description (continued)

XD[31:0]

XBE3/XA5

/XA4

XBE2

/XA3

XBE1 XBE0

/XA2

XRDY

XHOLD

XHOLDA

Data

Byte-Enable

Control/ Address

Control

Arbitration

Interface

Expansion Bus

Figure 4. Peripheral Signals (Continued)

Clocks

I/O Port Control

Host

Control

XCLKIN XFCLK

XOE XRE XWE/XWAIT XCE3 XCE2 XCE1 XCE0

XCS XAS XCNTL XW/R XBLAST XBOFF

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TYPE

†

DESCRIPTION

• Selects whether the CPU clock frequency = in ut clock frequency x4 or x1

lid duri

IACK f

• Encoding order follows the interru t service fetch acket ordering

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions

SIGNAL

NAME

CLKIN C12 B10 I Clock Input CLKOUT1 AD20 Y18 O Clock output at full device speed

CLKOUT2 AC19 AB19 O CLKMODE0 B15 B12 I

CLKMODE1 – A9 I CLKMODE2 – A14 I

‡

PLLV

‡

PLLG PLLF C13 A11 A

TMS AD7 Y5 I JTAG test-port mode select (features an internal pullup) TDO AE6 AA4 O/Z JTAG test-port data out TDI AF5 Y4 I JTAG test-port data in (features an internal pullup) TCK AE5 AB2 I JTAG test-port clock TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown) EMU1 AF6 AA5 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor EMU0 AC8 AB4 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor

RESET K2 J3 I Device reset NMI L2 K2 I EXT_INT7 V4 U2

EXT_INT6 Y2 U3 EXT_INT5 AA1 W1 EXT_INT4 W4 V2 IACK Y1 V1 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 V2 R3 INUM2 U4 T1 INUM1 V3 T2 INUM0 W2 T3

PD AB2 Y2 O Power-down modes 2 or 3 (active if high)

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

‡

PLLV and PLLG are not part of external voltage supply or ground. See the

A = Analog Signal (PLL Filter)

For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor.

PIN NO.

GJL GLS

D13 C11 A D14 C12 A

CLOCK/PLL

Clock output at half of device speed

• Used for synchronous memory interface

Clock mode selects (Note: CLKMODE1 and CLKMODE2 selects are for GLS devices only)

PLL analog VCC connection for the low-pass filter

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

RESET AND INTERRUPTS

Nonmaskable interrupt

• Edge-driven (rising edge)

External interrupts

• Edge-driven (rising edge)

Active interrupt identification number

•Va

• Encoding order follows the interrupt-service fetch-packet orderin

POWER-DOWN STATUS

or all active interrupts (not just externa

clock PLL

section for information on how to connect these pins.

¶ ¶

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TMS320C6202

TYPE

†

DESCRIPTION

Ex ansion bus data

XCE[3:0] memory ty e

I/O/Z

– Arbitration mode (internal or external)

O/Z

bits 28, 29

Only

asserted du

access

• Only one asserted during any I/O ort data access

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

XCLKIN A9 C8 I Expansion bus synchronous host interface clock input XFCLK B9 A8 O Expansion bus FIFO interface clock output XD31 D15 C13 XD30 B16 A13 XD29 A17 C14 XD28 B17 B14 XD27 D16 B15 XD26 A18 C15 XD25 B18 A15 XD24 D17 B16 XD23 C18 C16 XD22 A20 A17 XD21 D18 B17 XD20 C19 C17 XD19 A21 B18 XD18 D19 A19 XD17 C20 C18 XD16 B21 B19 XD15 A22 C19 XD14 D20 B20 XD13 B22 A21 XD12 E25 C21 XD11 F24 D20 XD10 E26 B22 XD9 F25 D21 XD8 G24 E20 XD7 H23 E21

ADVANCE INFORMATION

XD6 F26 D22 XD5 G25 F20 XD4 J23 F21 XD3 G26 E22 XD2 H25 G20 XD1 J24 G21 XD0 K23 G22 XCE3 F2 D2 XCE2 E1 B1 XCE1 F3 D3 XCE0 E2 C2

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EXPANSION BUS

• Used for transfer of data, address, and control

• Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown

resistors –

– – XBLAST polarity – XW/R polarity – Asynchronous or synchronous host operation – – FIFO mode – Little endian/big endian –Boot mode

Expansion bus I/O port memory space enables

•Enabled by

one

•

, and 30 of the word address

ring any I/O port data

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TYPE

†

DESCRIPTION

I/O/Z

• Act as address for I/O ort o eration

O/Z

bits 24

Only

asserted du

access

• Only one asserted during any external data access

Byte-enable control

O/Z

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

XBE3/XA5 C7 C5 XBE2/XA4 D8 A4 XBE1/XA3 A6 B5 XBE0/XA2 C8 C6 XOE A7 A6 O/Z Expansion bus I/O port output enable XRE C9 C7 O/Z Expansion bus I/O port read enable XWE/XWAIT D10 B7 O/Z Expansion bus I/O port write enable and host port wait signals XCS A10 C9 I Expansion bus host port chip-select input XAS D9 B6 I/O/Z Expansion bus host port address strobe XCNTL B10 B9 I Expansion bus host control. XCNTL selects between expansion bus address or data register XW/R D11 B8 I/O/Z Expansion bus host port write/read enable. XW/R polarity selected at reset XRDY A5 C4 I/O/Z Expansion bus host port ready (active low) and I/O port ready (active high) XBLAST B6 B4 I/O/Z Expansion bus host port burst last–polarity selected at reset XBOFF B11 A10 I Expansion bus back off XHOLD B5 A2 I/O/Z Expansion bus hold request XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge

CE3 AB25 Y21 CE2 AA24 W20 CE1 AB26 AA22 CE0 AA25 W21 BE3 Y24 V20 BE2 W23 V21 BE1 AA26 W22 BE0 Y25 U20

EA21 J25 H20 EA20 J26 H21 EA19 L23 H22 EA18 K25 J20 EA17 L24 J21 EA16 L25 K21 EA15 M23 K20 EA14 M24 K22 EA13 M25 L21 EA12 N23 L20 EA11 P24 L22

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EXPANSION BUS (CONTINUED)

Expansion bus multiplexed byte-enable control/address signals

•Act as byte enable for host port operation

• Act as address for I/O port operation

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

Memory space enables

•Enabled by

one

•

• Decoded from the two lowest bits of the internal address

• Byte-write enables for most types of memory

• Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIF – ADDRESS

O/Z External address (word address)

and 25 of the word address

ring any external data

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TMS320C6202

TYPE

†

DESCRIPTION

I/O/Z

External data

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

EA10 P23 M20 EA9 R25 M21 EA8 R24 N22 EA7 R23 N20 EA6 T25 N21 EA5 T24 P21 EA4 U25 P20 EA3 T23 R22 EA2 V26 R21

ED31 AD8 Y6 ED30 AC9 AA6 ED29 AF7 AB6 ED28 AD9 Y7 ED27 AC10 AA7 ED26 AE9 AB8 ED25 AF9 Y8 ED24 AC11 AA8 ED23 AE10 AA9 ED22 AD11 Y9 ED21 AE11 AB10 ED20 AC12 Y10 ED19 AD12 AA10 ED18 AE12 AA11 ED17 AC13 Y11 ED16 AD14 AB12 ED15 AC14 Y12

ADVANCE INFORMATION

ED14 AE15 AA12 ED13 AD15 AA13 ED12 AC15 Y13 ED11 AE16 AB13 ED10 AD16 Y14 ED9 AE17 AA14 ED8 AC16 AA15 ED7 AF18 Y15 ED6 AE18 AB15 ED5 AC17 AA16 ED4 AD18 Y16 ED3 AF20 AB17 ED2 AC18 AA17 ED1 AD19 Y17 ED0 AF21 AA18

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EMIF – ADDRESS (CONTINUED)

O/Z External address (word address)

EMIF – DATA

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TYPE

†

DESCRIPTION

DMA action complete

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

ARE V24 T21 O/Z Asynchronous memory read enable AOE V25 R20 O/Z Asynchronous memory output enable AWE U23 T22 O/Z Asynchronous memory write enable ARDY W25 T20 I Asynchronous memory ready input

SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command) SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output enable SDWE/SSWE AC20 AA20 O/Z SDRAM write enable/SBSRAM write enable

HOLD Y26 V22 I Hold request from the host HOLDA V23 U21 O Hold-request-acknowledge to the host

TOUT1 J4 F2 O Timer 1 or general-purpose output TINP1 G2 F3 I Timer 1 or general-purpose input TOUT0 F1 D1 O Timer 0 or general-purpose output TINP0 H4 E2 I Timer 0 or general-purpose input

DMAC3 Y3 V3 DMAC2 AA2 W2 DMAC1 AB1 AA1 DMAC0 AA3 W3

CLKS0 M4 K3 I External clock source (as opposed to internal) CLKR0 M2 L2 I/O/Z Receive clock CLKX0 M3 K1 I/O/Z Transmit clock DR0 R2 M2 I Receive data DX0 P4 M3 O/Z Transmit data FSR0 N3 M1 I/O/Z Receive frame sync FSX0 N4 L3 I/O/Z Transmit frame sync

CLKS1 G1 E1 I External clock source (as opposed to internal) CLKR1 J3 G2 I/O/Z Receive clock CLKX1 H2 G3 I/O/Z Transmit clock DR1 L4 H1 I Receive data DX1 J1 H2 O/Z Transmit data FSR1 J2 H3 I/O/Z Receive frame sync FSX1 K4 G1 I/O/Z Transmit frame sync

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EMIF – ASYNCHRONOUS MEMORY CONTROL

EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL

EMIF – BUS ARBITRATION

TIMERS

DMA ACTION COMPLETE STATUS

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

TMS320C6202

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TMS320C6202

TYPE

†

DESCRIPTION

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

CLKS2 R3 N1 I External clock source (as opposed to internal) CLKR2 T2 N2 I/O/Z Receive clock CLKX2 R4 N3 I/O/Z Transmit clock DR2 V1 R2 I Receive data DX2 T4 R1 O/Z Transmit data FSR2 U2 P3 I/O/Z Receive frame sync FSX2 T3 P2 I/O/Z Transmit frame sync

RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 C15 B13 O Reserved (leave unconnected, RSV4 D12 C10 O Reserved (leave unconnected,

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

A11 A3

A16 A7

B7 A16

B8 A20 B19 D4 B20 D6

C6 D7 C10 D9 C14 D10 C17 D13 C21 D14

G4 D16 G23 D17

H3 D19 H24 F1

K3 F4 K24 F19

L1 F22

L26 G4

N24 G19

P3 J4

MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)

RESERVED FOR TEST

do not

connect to power or ground)

do not

connect to power or ground)

SUPPLY VOLTAGE PINS

S 3.3-V supply voltage

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

T1 J19

T26 K4

U3 K19

U24 L1

W3 M22

W24 N4

Y4 N19

Y23 P4

AD6 P19 AD10 T4 AD13 T19 AD17 U1 AD21 U4

AE7 U19

AE8 U22 AE19 W4 AE20 W6

AF11 W7

AF16 W9

– W10 – W13 – W14 – W16 – W17 – W19 – AB5 – AB9 – AB14

– AB18 A1 E7 A2 E8 A3 E10

A24 E11 A25 E12 A26 E13

B1 E15 B2 E16 B3 F7

B24 F8 B25 F9 B26 F11

C1 F12

SUPPLY VOLTAGE PINS (CONTINUED)

S 3.3-V supply voltage

S 1.8-V supply voltage

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

TYPE

†

DESCRIPTION

1.8-V suppl

oltage

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

C2 F14 C3 F15

C4 F16 C23 G5 C24 G6 C25 G17 C26 G18

D3 H5

D4 H6

D5 H17 D22 H18 D23 J6 D24 J17

E4 K5 E23 K18 AB4 L5

AB23 L6

AC3 L17 AC4 L18 AC5 M5

AC22 M6 AC23 M17 AC24 M18

AD1 N5 AD2 N18 AD3 P6 AD4 P17

AD23 R5 AD24 R6 AD25 R17 AD26 R18

AE1 T5 AE2 T6 AE3 T17

AE24 T18 AE25 U7 AE26 U8

AF1 U9 AF2 U11 AF3 U12

AF24 U14 AF25 U15

SUPPLY VOLTAGE PINS (CONTINUED)

y v

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

AF26 U16

– V7 – V8 – V10 – V11 – V12 – V13 – V15 – V16

A4 A1

A8 A5 A13 A12 A14 A18 A15 A22 A19 B2 A23 B21

B4 C1 B12 C3 B13 C20 B14 C22 B23 D5

C5 D8 C11 D11 C16 D12 C22 D15

D1 D18

D2 E4

D6 E5 D21 E6 D25 E9 D26 E14

E3 E17 E24 E18

F4 E19

F23 F5

H1 F6 H26 F10

SUPPLY VOLTAGE PINS (CONTINUED)

S 1.8-V supply voltage

GROUND PINS

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

TYPE

†

DESCRIPTION

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

K1 F13

K26 F17

M1 F18

M26 H4

N1 H19

N2 J1 N25 J5 N26 J18

P1 J22

P2 K6 P25 K17 P26 L4

R1 L19 R26 M4

U1 M19 U26 N6

W1 N17

W26 P1

AA4 P5

AA23 P18

AB3 P22

AB24 R4

AC1 R19 AC2 U5 AC6 U6

AC21 U10 AC25 U13 AC26 U17

AD5 U18

AD22 V4

AE4 V5

AE13 V6 AE14 V9 AE23 V14

AF4 V17 AF8 V18

GROUND PINS (CONTINUED)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

AF10 V19 AF12 W5 AF13 W8 AF14 W11 AF15 W12 AF17 W15 AF19 W18 AF23 Y1

– Y3 – Y20 – Y22 – AA2 – AA21 – AB1 – AB3 – AB7 – AB11 – AB16 – AB20 – AB22

GROUND PINS (CONTINUED)

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE INFORMATION

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

development support

Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of ’C6200-based applications:

Software Development Tools:

Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler

Hardware Development Tools:

Extended development system (XDS) emulator (supports ’C6200 multiprocessor system debug) EVM (Evaluation Module)

The

TMS320 DSP Development Support Reference Guide

development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the

TMS320 Third-Party Support Reference Guide

information about TMS320-related products from other companies in the industry . T o receive TMS320 literature, contact the Literature Response Center at 800/477-8924.

(SPRU011) contains information about

(SPRU052), contains

See Table 2 for a complete listing of development-support tools for the ’C6200. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

Table 2. TMS320C6xx Development-Support Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER

Software

C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07 C Compiler/Assembler/Linker/Assembly Optimizer SPARCSolaris TMDX3246555-07 Simulator Win32 TMDS3246851-07 Simulator SPARCSolaris TMDS3246551-07

ADVANCE INFORMATION

XDS510 Debugger/Emulation Software Win32, Windows NT TMDX324016X-07

Hardware

XDS510 Emulator XDS510WS Emulator

EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201

†

Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.

‡

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.

†

‡

Software/Hardware

PC TMDS00510

SCSI TMDS00510WS

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

device and development-support tool nomenclature

T o designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical

specifications

TMP Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow: TMDX Development-support product that has not yet completed T exas Instruments internal qualification

testing.

TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully , and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. T exas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJL), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -250 is 250 MHz). Figure 5 provides a legend for reading the complete device name for any TMS320 family member.

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

device and development-support tool nomenclature (continued)

TMS 320 C 6202 GJL –250

PREFIX DEVICE SPEED RANGE

TMX= Experimental device TMP= Prototype device TMS= Qualified device SMJ = MIL-STD-883C SM = High Rel (non-883C)

DEVICE FAMILY

320 = TMS320 family

TECHNOLOGY

C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM

(A)

DEVICE

ADVANCE INFORMATION

†

DIP = Dual-In-Line Package PGA = Pin Grid Array CC = Chip Carrier QFP = Quad Flat Package TQFP = Thin Quad Flat Package BGA = Ball Grid Array

–100 MHz –150 MHz –167 MHz –200 MHz –233 MHz –250 MHz –300 MHz

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature A = –40°C to 105°C, extended temperature

PACKAGE TYPE

N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA

’1x DSP:

’2x DSP:

’2xx DSP:

’3x DSP:

’4x DSP:

’5x DSP:

’54x DSP:

’6x DSP:

10 16 14 17 15

25 26

203 206 240 204 209

30 31 32

40 44

50 53 51 56 52 57

541 545 542 546 543 548

6201 6201B 6202 6203 6211 6701 6711

†

Figure 5. TMS320 Device Nomenclature (Including TMS320C6202)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices:

The

TMS320C6000 CPU and Instruction Set Reference Guide

’C6000 CPU architecture, instruction set, pipeline, and associated interrupts. The

TMS320C6000 Peripherals Reference Guide

the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories.

The

TMS320C6000 Programmer’s Guide

assembly code for ’C6x devices and includes application program examples. The

TMS320C6x C Source Debugger User’s Guide

’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.

(literature number SPRU198) describes ways to optimize C and

(literature number SPRU190) describes the functionality of

(literature number SPRU188) describes how to invoke the

(literature number SPRU189) describes the

The

TMS320C6x Peripheral Support Library Programmer’s Reference

the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically , provides a complete description of each, and gives code examples to show how they are used.

TMS320C6000 Assembly Language T ools User’s Guide

language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of devices.

The

TMS320C6x Evaluation Module Reference Guide

installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module User’s Guide

instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module Technical Reference

reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software documentation, application programming interface references, and hardware descriptions for the ’C62x McEVM.

TMS320C6000 DSP/BIOS User’s Guide

and APIs to analyze embedded real-time DSP applications.

Code Composer User’s Guide

development environment to build and debug embedded real-time DSP applications.

(literature number SPRU296) explains how to use the Code Composer

(literature number SPRU303) describes how to use DSP/BIOS tools

(literature number SPRU186) describes the assembly

(literature number SPRU269) provides instructions for

(literature number SPRU273) describes

(literature number SPRU285) provides

(SPRU308) provides provides technical

ADVANCE INFORMATION

Code Composer Studio T utorial

development environment and software tools.

(literature number SPRU301) introduces the Code Composer Studio integrated

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

documentation support (continued)

The

TMS320C6000 Technical Brief

devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and

education. The TMS320 newsletter, update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the TMS320 family , including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

(literature number SPRU197) gives an introduction to the ’C62x/C67x

Details on Signal Processing

, is published quarterly and distributed to

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

clock PLL

All of the internal ’C6202 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.

To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. To configure the ’C6202 PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter,

a single clean power supply should power both the ’C6202 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the clock timing requirements.

input and output clocks

section for input

3.3 V

1 IN

NOTES: A. The ’C6202 PLL can generate CPU clock frequencies in the range of 130 MHz to 250 MHz. For frequencies below 130 MHz, the

B. For the ’C6202, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CPU clock frequency.

C. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal

D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

E. EMI filter manufacturer TDK part number ACF451832-153-T F. CLKMODE2 and CLKMODE1 exist only on the GLS device. There are no equivalent connections on the GJL device.

G. The reserved PLL clock modes (GLS devices only) may or may not be supported on future devices as additional PLL multiply factors.

3 OUT

EMI Filter

GND

PLL should be configured to operate in bypass mode.

has to be connected to a clean 3.3-V supply and the PLLG and PLLF terminals should be tied together.

For future flexibility, a board can be designed so that these inputs are configurable (either through jumpers, switches, or 0-Ω resistors).

10 µF 0.1 µF

(Bypass)

C1 C2

PLLV PLLF

PLLG

CLKIN

All Other Modes

’320C6202

CPU Clock

CLKMODE2

CLKMODE1

CLKMODE0

– MULT×1

– MULT×4 – Reserved

CLKOUT1÷ 1 CLKOUT2÷ 2

f(CPU Clock)=f(CLKIN) f(CPU Clock)=f(CLKIN)×4

Figure 6. PLL Block Diagram

ADVANCE INFORMATION

Table 3. TMS320C6202 PLL Component Selection Table

CLKIN

CLKMODE

x4 32.5–62.5 130–250 65–125 60.4 27 560 75

†

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

RANGE

(MHz)

CPU CLOCK

FREQUENCY

(CLKOUT1)

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

(Ω)

(nF)

†

(pF)

TYPICAL

LOCK TIME

(µs)

power-supply sequencing

The 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers supply . This is to ensure that the I/O buf fers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

absolute maximum ratings over operating case temperature range (unless otherwise noted)

†

Supply voltage range, CVDD (see Note 1) – 0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, DV

(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

stg

0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

CV DV V V V I

SS IH IL

Supply voltage 1.71 1.8 1.89 V

Supply voltage 3.14 3.30 3.46 V

Supply ground 0 0 0 V High-level input voltage 2.0 V Low-level input voltage 0.8 V High-level output current –8 mA Low-level output current 8 mA Operating case temperature 0 90_C

electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD2V

ADVANCE INFORMATION

DD3V

‡

TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.

Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle

Measured with average peripheral activity: 50% of time: Timers at max rate

50% of time: Timers at max rate

Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity

High-level output voltage DV Low-level output voltage DV Input current Off-state output current V Supply current, CPU + CPU memory access§CV Supply current, peripherals Supply current, I/O pins Input capacitance 10 pF Output capacitance 10 pF

‡

McBSPs at E1 rate

DMA burst transfer between DMEM and SDRAM

McBSPs at E1 rate

DMA servicing McBSPs

= MIN, I

= V

to DV

= DV

= NOM, CPU clock = 200 MHz TBD mA

or 0 V ±10 uA

= MAX 2.4 V

= MAX 0.6 V

±10 uA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

Output Under Test

†

Typical distributed load circuit capacitance

ref

CT = 30 pF

50 Ω

†

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

ref

Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements

= 1.5 V

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE INFORMATION

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

INPUT AND OUTPUT CLOCKS

timing requirements for CLKIN

NO.

1 t

c(CLKIN)

2 t

w(CLKINH)

3 t

w(CLKINL)

4 t

t(CLKIN)

†

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.

CLKIN

Cycle time, CLKIN

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

†

(see Figure 8)

’C6202-200 ’C6202-233 ’C6202-250

CLKMODE

= x4

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

20 5 17.2 4.3 16 4 ns

8 2.25 6.9 1.9 6.4 1.8 ns

CLKMODE

= x1

5 0.6 5 0.6 5 0.6 ns

CLKMODE

= x4

CLKMODE

= x1

Figure 8. CLKIN Timings

CLKMODE

= x4

CLKMODE

= x1

UNIT

timing requirements for XCLKIN†‡ (see Figure 9)

NO.

1 t

c(XCLKIN)

2 t

ADVANCE INFORMATION

w(XCLKINH)

3 t

w(XCLKINL)

4 t

t(XCLKIN)

†

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.

‡

P = 1/CPU clock frequency in nanoseconds (ns).

XCLKIN

Cycle time, XCLKIN 4P ns Pulse duration, XCLKIN high 1.8P ns Pulse duration, XCLKIN low 1.8P ns Transition time, XCLKIN 0.6 ns

Figure 9. XCLKIN Timings

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER

UNIT

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

INPUT AND OUTPUT CLOCKS (CONTINUED)

switching characteristics for CLKOUT1

1 t

c(CKO1)

2 t

w(CKO1H)

3 t

w(CKO1L)

4 t

† ‡

t(CKO1)

PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns).

CLKOUT1

Cycle time, CLKOUT1 P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.5 ns Transition time, CLKOUT1 0.6 0.6 ns

†‡

(see Figure 10)

CLKMODE = x4 CLKMODE = x1

MIN MAX MIN MAX

Figure 10. CLKOUT1 Timings

switching characteristics for CLKOUT2‡ (see Figure 11)

NO. PARAMETER

1 t

c(CKO2)

2 t

w(CKO2H)

3 t

w(CKO2L)

4 t

‡

t(CKO2)

P = 1/CPU clock frequency in nanoseconds (ns).

Cycle time, CLKOUT2 2P – 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high P – 0.7 P + 0.7 ns Pulse duration, CLKOUT2 low P – 0.7 P + 0.7 ns Transition time, CLKOUT2 0.6 ns

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

ADVANCE INFORMATION

CLKOUT2

Figure 11. CLKOUT2 Timings

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

INPUT AND OUTPUT CLOCKS (CONTINUED)

switching characteristics for XFCLK

NO. PARAMETER

1 t

c(XFCK)

2 t

w(XFCKH)

3 t

w(XFCKL)

4 t

† ‡

t(XFCK)

P = 1/CPU clock frequency in ns. D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable

XFCLK

Cycle time, XFCLK D * P – 0.7 D * P + 0.7 ns Pulse duration, XFCLK high (D/2) * P – 0.7 (D/2) * P + 0.7 ns Pulse duration, XFCLK low (D/2) * P – 0.7 (D/2) * P + 0.7 ns Transition time, XFCLK 0.6 ns

†‡

Figure 12. XFCLK Timings

(see Figure 12)

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles

NO.

6 t

su(EDV-CKO1H)

7 t

h(CKO1H-EDV)

10 t

su(ARDY-CKO1H)

11 t

†

h(CKO1H-ARDY)

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

Setup time, read EDx valid before CLKOUT1 high 4.0 ns Hold time, read EDx valid after CLKOUT1 high 0 ns Setup time, ARDY valid before CLKOUT1 high 4.0 ns Hold time, ARDY valid after CLKOUT1 high 0 ns

†

(see Figure 13 – Figure 14)

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

switching characteristics for asynchronous memory cycles‡ (see Figure 13 – Figure 14)

’C6202-200

NO. PARAMETER

1 t

d(CKO1H-CEV)

2 t

d(CKO1H-BEV)

3 t

d(CKO1H-BEIV)

4 t

d(CKO1H-EAV)

5 t

d(CKO1H-EAIV)

8 t

d(CKO1H-AOEV)

9 t

d(CKO1H-AREV)

12 t

d(CKO1H-EDV)

13 t

d(CKO1H-EDIV)

14 t

‡

d(CKO1H-AWEV)

The minimum delay is also the minimum output hold after CLKOUT1 high.

Delay time, CLKOUT1 high to CEx valid 0 4.0 ns Delay time, CLKOUT1 high to BEx valid 0 4.0 ns Delay time, CLKOUT1 high to BEx invalid 0 4.0 ns Delay time, CLKOUT1 high to EAx valid 0 4.0 ns Delay time, CLKOUT1 high to EAx invalid 0 4.0 ns Delay time, CLKOUT1 high to AOE valid 0 4.0 ns Delay time, CLKOUT1 high to ARE valid 0 4.0 ns Delay time, CLKOUT1 high to EDx valid 4.0 ns Delay time, CLKOUT1 high to EDx invalid 0 ns Delay time, CLKOUT1 high to AWE valid 0 4.0 ns

’C6202-233 ’C6202-250

MIN MAX

UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE INFORMATION

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

CLKOUT1

CEx

BE[3:0]

EA[21:2]

ED[31:0]

AOE

ARE

AWE

ARDY

Setup = 2 Strobe = 5

1111

Figure 13. Asynchronous Memory Read Timing

Not ready = 2

HOLD = 1

ADVANCE INFORMATION

CLKOUT1

CEx

BE[3:0]

EA[21:2]

ED[31:0]

AOE

ARE

AWE

ARDY

Setup = 2 Strobe = 5

Figure 14. Asynchronous Memory Write Timing

Not ready = 2

HOLD = 1

1414

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

UNIT

PARAMETER

UNIT

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (see Figure 15)

TMS320C6202

7 t

su(EDV-CKO2H)

8 t

h(CKO2H-EDV)

Setup time, read EDx valid before CLKOUT2 high

Hold time, read EDx valid after CLKOUT2 high 1.5 1.5 1.5 ns

switching characteristics for synchronous-burst SRAM cycles

1 t

osu(CEV-CKO2H)

2 t

oh(CKO2H-CEV)

3 t

osu(BEV-CKO2H)

4 t

oh(CKO2H-BEIV)

5 t

osu(EAV-CKO2H)

6 t

oh(CKO2H-EAIV)

9 t

osu(ADSV-CKO2H)

10 t

oh(CKO2H-ADSV)

11 t

osu(OEV-CKO2H)

12 t

oh(CKO2H-OEV)

13 t

osu(EDV-CKO2H)

14 t

oh(CKO2H-EDIV)

15 t

osu(WEV-CKO2H)

16 t

oh(CKO2H-WEV)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡

SDCAS

/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively , during SBSRAM accesses. For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

Output setup time, CEx valid before CLKOUT2 high

Output hold time, CEx valid after CLKOUT2 high

Output setup time, BEx valid before CLKOUT2 high

Output hold time, BEx invalid after CLKOUT2 high

Output setup time, EAx valid before CLKOUT2 high

Output hold time, EAx invalid after CLKOUT2 high

Output setup time, SDCAS

/SSADS valid before

CLKOUT2 high Output hold time,

SDCAS

/SSADS valid after

CLKOUT2 high Output setup time,

SDRAS

/SSOE valid before

CLKOUT2 high Output hold time, SDRAS/SSOE

valid after CLKOUT2 high Output setup time, EDx valid

before CLKOUT2 high Output hold time, EDx invalid

after CLKOUT2 high Output setup time, SDWE/SSWE

valid before CLKOUT2 high Output hold time, SDWE/SSWE

valid after CLKOUT2 high

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX MIN MAX MIN MAX

2P – 5.5 2P – 4.4 2P – 3.8 ns

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX MIN MAX MIN MAX

2.5 2.1 2 ns

†‡

(see Figure 15 and Figure 16)

1 1 1 ns

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

CLKOUT2

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SDCAS/SSADS

SDRAS

/SSOE

/SSWE

SDWE

†

BE1 BE2 BE3 BE4

A1 A2 A3 A4

Q1 Q2 Q3 Q4

109

1211

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively , during SBSRAM accesses.

Figure 15. SBSRAM Read Timing

CLKOUT2

CEx

1413

109

1615

ADVANCE INFORMATION

†

SDCAS

BE[3:0]

EA[21:2]

ED[31:0]

/SSADS

/SSOE

/SSWE

†

SDCAS

SDRAS

SDWE

/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

BE1 BE2 BE3 BE4

A1 A2 A3 A4

Q1 Q2 Q3 Q4

Figure 16. SBSRAM Write Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

UNIT

PARAMETER

UNIT

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 17)

7 t

su(EDV-CKO2H)

8 t

h(CKO2H-EDV)

Setup time, read EDx valid before CLKOUT2 high 1 1 0.5 ns Hold time, read EDx valid after CLKOUT2 high 3 3 3 ns

switching characteristics for synchronous DRAM cycles†‡ (see Figure 17–Figure 22)

1 t

osu(CEV-CKO2H)

2 t

oh(CKO2H-CEV)

3 t

osu(BEV-CKO2H)

4 t

oh(CKO2H-BEIV)

5 t

osu(EAV-CKO2H)

6 t

oh(CKO2H-EAIV)

9 t

osu(CASV-CKO2H)

10 t

oh(CKO2H-CASV)

11 t

osu(EDV-CKO2H)

12 t

oh(CKO2H-EDIV)

13 t

osu(WEV-CKO2H)

14 t

oh(CKO2H-WEV)

15 t

osu(SDA10V-CKO2H)

16 t

oh(CKO2H-SDA10IV)

17 t

osu(RASV-CKO2H)

18 t

oh(CKO2H-RASV)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡

SDCAS

/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses. For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

Output setup time, CEx valid before CLKOUT2 high

Output hold time, CEx valid after CLKOUT2 high

Output setup time, BEx valid before CLKOUT2 high

Output hold time, BEx invalid after CLKOUT2 high

Output setup time, EAx valid before CLKOUT2 high

Output hold time, EAx invalid after CLKOUT2 high

Output setup time, SDCAS

/SSADS valid before

CLKOUT2 high Output hold time, SDCAS/SSADS

valid after CLKOUT2 high Output setup time, EDx valid

before CLKOUT2 high Output hold time, EDx invalid after

CLKOUT2 high Output setup time, SDWE/SSWE

valid before CLKOUT2 high Output hold time, SDWE/SSWE

valid after CLKOUT2 high Output setup time, SDA10 valid

before CLKOUT2 high Output hold time, SDA10 invalid

after CLKOUT2 high Output setup time, SDRAS/SSOE

valid before CLKOUT2 high Output hold time, SDRAS/SSOE

valid after CLKOUT2 high

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX MIN MAX MIN MAX

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

2P – 6 2P – 4.6 2P – 4 ns

1.5 1.5 1.5 ns

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

CLKOUT2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

/SSADS

/SSWE

†

SDRAS/SSOE

SDCAS

SDWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses.

CA1 CA2 CA3

READ

BE1 BE2 BE3

READ

D1 D2 D3

1615

109

Figure 17. Three SDRAM READ Commands

WRITE

CLKOUT2

CEx

BE[3:0]

ADVANCE INFORMATION

EA[15:2]

ED[31:0]

SDA10

/SSADS

/SSWE

†

SDRAS/SSOE

SDCAS

SDWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses.

BE1 BE2 BE3

CA1 CA2 CA3

D1 D2 D3

WRITE

1615

109

1413

Figure 18. Three SDRAM WRT Commands

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SDRAS

SDCAS

CLKOUT2

CEx

BE[3:0]

EA[15:2] ED[31:0]

SDA10

/SSOE

/SSADS

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

Bank Activate/Row Address

† †

Row Address

/SSWE

†

SDWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses.

Figure 19. SDRAM ACTV Command

DCAB

CLKOUT2

†

SDCAS

CEx

BE[3:0]

EA[15:2] ED[31:0]

SDA10

†

/SSOE

SDRAS

/SSWE

†

SDCAS

/SSADS

SDWE

/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

ADVANCE INFORMATION

Figure 20. SDRAM DCAB Command

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

CLKOUT2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

REFR

SDA10

†

/SSOE

SDRAS

†

/SSADS

SDCAS

/SSWE

†

SDWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses.

Figure 21. SDRAM REFR Command

MRS

CLKOUT2

ADVANCE INFORMATION

SDRAS

SDCAS

SDWE

CEx

BE[3:0]

EA[15:2] ED[31:0]

SDA10

/SSOE

/SSADS

/SSWE

MRS Value

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively , during SDRAM accesses.

Figure 22. SDRAM MRS Command

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

HOLD/HOLDA TIMING

timing requirements for the HOLD

NO.

3 t

†

oh(HOLDAL-HOLDL)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Hold time, HOLD low after HOLDA low P ns

/HOLDA cycles† (see Figure 23)

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

switching characteristics for the HOLD/HOLDA cycles†‡ (see Figure 23)

’C6202-200

NO. PARAMETER

1 t

R(HOLDL-EMHZ)

2 t

d(EMHZ-HOLDAL)

4 t

R(HOLDH-EMLZ)

5 t

† ‡

d(EMLZ-HOLDAH)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. EMIF Bus consists of CE[3:0] All pending EMIF transactions are allowed to complete before HOLDA external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

Response time, HOLD low to EMIF Bus high impedance 4P Delay time, EMIF Bus high impedance to HOLDA low 0 2P ns Response time, HOLD high to EMIF Bus low impedance 3P 7P ns Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns

, BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

DSP Owns Bus

is asserted. The worst case for this is an asynchronous read or write with

External Requestor

Owns Bus

DSP Owns Bus

’C6202-233 ’C6202-250

MIN MAX

UNIT

HOLD

HOLDA

EMIF Bus

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

†

C6202 C6202

Figure 23. HOLD/HOLDA Timing

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

w(RST)

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

RESET TIMING

timing requirements for reset (see Figure 24)

’C6202-200

NO.

1 t

11 t

su(XD)

12 t

h(XD)

†

This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.

‡

This parameter only applies to CLKMODE x4. The RESET need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET to ensure proper device operation. See the

XD[31:0] are the boot configuration pins during device reset.

Width of the RESET pulse (PLL stable) Width of the RESET pulse (PLL needs to sync up) Setup time, XD configuration bits valid before RESET high

Hold time, XD configuration bits valid after RESET high

clock PLL

section for PLL lock times.

†

‡

signal is not connected internally to the clock PLL circuit. The PLL, however, may

’C6202-233 ’C6202-250

MIN MAX

250 µs

UNIT

CLKOUT1

cycles

CLKOUT1

cycles

CLKOUT1

cycles

must be asserted

switching characteristics during reset¶ (see Figure 24)

NO. PARAMETER

2 t

R(RST)

3 t

d(CKO1H-CKO2IV)

4 t

d(CKO1H-CKO2V)

5 t

d(CKO1H-XFCKIV)

6 t

d(CKO1H-XFCKV)

7 t

d(CKO1H-LOWIV)

8 t

d(CKO1H-LOWV)

9 t

ADVANCE INFORMATION

d(CKO1H-ZHZ)

10 t

d(CKO1H-ZV)

High group consists of: XFCLK Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 Z group consists of: EA[21:2], ED[31:0], CE[3:0]

Response time to change of value in RESET signal 2 Delay time, CLKOUT1 high to CLKOUT2 invalid –1 10 ns

Delay time, CLKOUT1 high to CLKOUT2 valid –1 10 ns Delay time, CLKOUT1 high to high group invalid –1 10 ns Delay time, CLKOUT1 high to high group valid –1 10 ns Delay time, CLKOUT1 high to low group invalid –1 10 ns Delay time, CLKOUT1 high to low group valid –1 10 ns Delay time, CLKOUT1 high to Z group high impedance –1 10 ns Delay time, CLKOUT1 high to Z group valid –1 10 ns

SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0] and XHOLDA

, XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,

, BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

CLKOUT1

cycles

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

RESET TIMING (CONTINUED)

CLKOUT1

RESET

CLKOUT2

HIGH GROUP

LOW GROUP

Z GROUP

XD[31:0]

†

‡

109

†

High group consists of: XFCLK Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

‡

XD[31:0] are the boot configuration pins during device reset.

SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0] and XHOLDA.

, XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,

Figure 24. Reset Timing

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXTERNAL INTERRUPT TIMING

timing requirements for interrupt response cycles

NO.

2 t

w(ILOW)

3 t

†

w(IHIGH)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Width of the interrupt pulse low 2P ns Width of the interrupt pulse high 2P ns

†

(see Figure 25)

switching characteristics during interrupt response cycles† (see Figure 25)

NO. PARAMETER

1 t

R(EINTH – IACKH)

4 t

d(CKO2L-IACKV)

5 t

d(CKO2L-INUMV)

6 t

†

d(CKO2L-INUMIV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

CLKOUT2

EXT_INTx, NMI

Response time, EXT_INTx high to IACK high 9P ns Delay time, CLKOUT2 low to IACK valid 0 10 ns Delay time, CLKOUT2 low to INUMx valid 0 10 ns Delay time, CLKOUT2 low to INUMx invalid 0 10 ns

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

ADVANCE INFORMATION

Intr Flag

IACK

INUMx

Figure 25. Interrupt Timing

Interrupt Number

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING

timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO. MIN MAX UNIT

5 t

su(XDV-XFCKH)

6 t

h(XFCKH-XDV)

switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO. PARAMETER MIN MAX UNIT

1 t

d(XFCKH-XCEV)

2 t

d(XFCKH-XAV)

3 t

d(XFCKH-XOEV)

4 t

d(XFCKH-XREV)

7 t

d(XFCKH-XWEV)

8 t

d(XFCKH-XDV)

9 t

† ‡

d(XFCKH-XDIV)

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. XWE

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Setup time, read XDx valid before XFCLK high 2.5 ns Hold time, read XDx valid after XFCLK high 2 ns

Delay time, XFCLK high to XCEx valid 1.5 5.2 ns Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid Delay time, XFCLK high to XOE valid 1.5 5.2 ns Delay time, XFCLK high to XRE valid 1.5 5.2 ns Delay time, XFCLK high to XWE/XWAIT‡ valid 1.5 5.2 ns Delay time, XFCLK high to XDx valid 5.2 ns Delay time, XFCLK high to XDx invalid 1.5 ns

†

1.5 5.2 ns

XFCLK

†

XCE3

‡

XBE[3:0]

†

FIFO read (glueless) mode only available in XCE3.

‡

XBE[3:0]

XWE

/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

/XA[5:2]

XOE

XRE

XWE/XWAIT

XD[31:0]

XA1 XA2 XA3 XA4

D1 D2 D3 D4

Figure 26. FIFO Read Timing (Glueless Read Mode)

ADVANCE INFORMATION

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

XFCLK

XCEx

XBE[3:0]/XA[5:2]

XOE

XRE

†

XA1 XA2 XA3 XA4

XD[31:0]

‡

D1 D2 D3 D4

XWE/XWAIT

†

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

‡

XWE

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 27. FIFO Read Timing

XFCLK

XCEx

ADVANCE INFORMATION

†

XBE[3:0]

‡

XWE

XBE[3:0]/XA[5:2]

XWE/XWAIT

/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

†

XOE

XRE

‡

XD[31:0]

XA1 XA2 XA3 XA4

D1 D2 D3 D4

Figure 28. FIFO Write Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING

timing requirements for asynchronous peripheral cycles

NO.

4 t

su(XDV-CKO1H)

5 t

h(CKO1H-XDV)

8 t

su(XRY-CKO1H)

9 t

†

h(CKO1H-XRY)

To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.

Setup time, read XDx valid before CLKOUT1 high 4.0 ns Hold time, read XDx valid after CLKOUT1 high 0 ns Setup time, XRDY valid before CLKOUT1 high 4.0 ns Hold time, XRDY valid after CLKOUT1 high 0 ns

switching characteristics for asynchronous peripheral cycles

NO. PARAMETER

1 t

d(CKO1H-XCEV)

2 t

d(CKO1H-XAV)

3 t

d(CKO1H-XAIV)

6 t

d(CKO1H-XOEV)

7 t

d(CKO1H-XREV)

10 t

d(CKO1H-XDV)

11 t

d(CKO1H-XDIV)

12 t

‡

§ ¶

d(CKO1H-XWEV)

The minimum delay is also the minimum output hold after CLKOUT1 high. XBE[3:0] XWE

/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.

/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.

Delay time, CLKOUT1 high to XCEx valid 0 4.0 ns Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] valid 0 4.0 ns Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] invalid 0 4.0 ns Delay time, CLKOUT1 high to XOE valid 0 4.0 ns Delay time, CLKOUT1 high to XRE valid 0 4.0 ns Delay time, CLKOUT1 high to XDx valid 4.0 ns Delay time, CLKOUT1 high to XDx invalid 0 ns Delay time, CLKOUT1 high to XWE/XWAIT valid 0 4.0 ns

†

(see Figure 29–Figure 30)

’C6202-200 ’C6202-233 ’C6202-250

‡§¶

(see Figure 29–Figure 30)

’C6202-200 ’C6202-233 ’C6202-250

UNIT

MIN MAX

UNIT

MIN MAX

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)

Setup = 2 Strobe = 5

CLKOUT1

XCEx

Not ready = 2

HOLD = 2

XD[31:0]

XOE

XRE

XRDY

†

‡

XBE[3:0]/XA[5:2]

XWE/XWAIT

†

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.

‡

XWE

/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.

XRDY operates as active-high ready input during asynchronous peripheral accesses.

Figure 29. Expansion Bus Asynchronous Peripheral Read Timing

Setup = 2 Strobe = 5

CLKOUT1

XCEx

Not ready = 2

HOLD = 2

XD[31:0]

XOE

XRE

XRDY

†

‡

ADVANCE INFORMATION

XBE[3:0]/XA[5:2]

XWE/XWAIT

†

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.

‡

XWE

/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.

XRDY operates as active-high ready input during asynchronous peripheral accesses.

Figure 30. Expansion Bus Asynchronous Peripheral Write Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

1212

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING

timing requirements with external device as bus master (see Figure 31 and Figure 32)

NO. MIN MAX UNIT

1 t

su(XCSV-XCKIH)

2 t

h(XCKIH-XCS)

3 t

su(XAS-XCKIH)

4 t

h(XCKIH-XAS)

5 t

su(XCTL-XCKIH)

6 t

h(XCKIH-XCTL)

7 t

su(XWR-XCKIH)

8 t

h(XCKIH-XWR)

9 t

su(XBLTV-XCKIH)

10 t

h(XCKIH-XBLTV)

16 t

su(XBEV-XCKIH)

17 t

h(XCKIH-XBEV)

18 t

su(XD-XCKIH)

19 t

† ‡

h(XCKIH-XD)

XW/R input/output polarity selected at boot. XBLAST input polarity selected at boot. XBE[3:0]

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

Setup time, XCS valid before XCLKIN high 4 ns Hold time, XCS valid after XCLKIN high 2.3 ns

Setup time, XAS valid before XCLKIN high 4 ns Hold time, XAS valid after XCLKIN high 2.3 ns

Setup time, XCNTL valid before XCLKIN high 4 ns Hold time, XCNTL valid after XCLKIN high 2.3 ns

Setup time, XW/R valid before XCLKIN high Hold time, XW/R valid after XCLKIN high

Setup time, XBLAST valid before XCLKIN high Hold time, XBLAST valid after XCLKIN high

Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high

Setup time, XDx valid before XCLKIN high 4 ns Hold time, XDx valid after XCLKIN high 2.3 ns

†

‡

4 ns

2.3 ns 4 ns

2.3 ns

switching characteristics with external device as bus master¶ (see Figure 31 and Figure 32)

NO. PARAMETER MIN MAX UNIT

11 t

d(XCKIH-XDLZ)

12 t

d(XCKIH-XDV)

13 t

d(XCKIH-XDIV)

14 t

d(XCKIH-XDHZ)

15 t

d(XCKIH-XRY)

20 t

d(XCKIH-XRYLZ)

21 t

¶ #

d(XCKIH-XRYHZ)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. XRDY operates as active-low ready input/output during host-port accesses.

Delay time, XCLKIN high to XDx low impedance 5 ns Delay time, XCLKIN high to XDx valid 15.5 ns Delay time, XCLKIN high to XDx invalid 5 ns Delay time, XCLKIN high to XDx high impedance 18 ns Delay time, XCLKIN high to XRDY valid Delay time, XCLKIN high to XRDY low impedance 5 15.5 ns Delay time, XCLKIN high to XRDY high impedance

5 15.5 ns

2P + 5 3P + 15.5 ns

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

XBE[3:0]

XCS

XAS

XCNTL

XW/R

/XA[5:2]

XBLAST

XD[31:0]

XRDY

†

† ‡

D1 D2 D3 D4

†

XW/R input/output polarity selected at boot

‡

XBE[3:0]

XBLAST input polarity selected at boot

XRDY operates as active-low ready input/output during host-port accesses.

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

Figure 31. External Host as Bus Master—Read

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EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

XCS

XAS

XCNTL

†

XW/R

†

XW/R

XD[31:0]

XRDY

‡

XBE[3:0]/XA[5:2]

XBLAST

†

XW/R input/output polarity selected at boot

‡

XBE[3:0]

XBLAST input polarity selected at boot

XRDY operates as active-low ready input/output during host-port accesses.

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

XBE1 XBE2 XBE3 XBE4

D1 D2 D3 D4

Figure 32. External Host as Bus Master—Write

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

timing requirements with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)

NO. MIN MAX UNIT

9 t

su(XDV-XCKIH)

10 t

h(XCKIH-XDV)

11 t

su(XRY-XCKIH)

12 t

h(XCKIH-XRY)

14 t

su(XBFF-XCKIH)

15 t

†

h(XCKIH-XBFF)

XRDY operates as active-low ready input/output during host-port accesses.

switching characteristics with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)

NO. PARAMETER MIN MAX UNIT

1 t

d(XCKIH-XASV)

2 t

d(XCKIH-XWRV)

3 t

d(XCKIH-XBLTV)

4 t

d(XCKIH-XBEV)

5 t

d(XCKIH-XDLZ)

6 t

d(XCKIH-XDV)

7 t

d(XCKIH-XDIV)

8 t

d(XCKIH-XDHZ)

13 t

‡

§ ¶ #

d(XCKIH-XWTV)

XW/R input/output polarity selected at boot. XBLAST output polarity is always active low. XBE[3:0] XWE

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

/XWAIT operates as XWAIT output signal during host-port accesses.

Setup time, XDx valid before XCLKIN high 4 ns Hold time, XDx valid after XCLKIN high 2.3 ns

Setup time, XRDY valid before XCLKIN high Hold time, XRDY valid after XCLKIN high

Setup time, XBOFF valid before XCLKIN high 4 ns Hold time, XBOFF valid after XCLKIN high 2.3 ns

Delay time, XCLKIN high to XAS valid 5 15.5 ns Delay time, XCLKIN high to XW/R valid Delay time, XCLKIN high to XBLAST valid Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid Delay time, XCLKIN high to XDx low impedance 5 ns Delay time, XCLKIN high to XDx valid 15.5 ns Delay time, XCLKIN high to XDx invalid 5 ns Delay time, XCLKIN high to XDx high impedance 18 ns

Delay time, XCLKIN high to XWE/XWAIT valid

†

‡

§ ¶

4 ns

2.3 ns

5 15.5 ns 5 15.5 ns 5 15.5 ns

5 15.5 ns

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

1211

XBE[3:0]

XWE

XAS

XW/R

XBLAST

/XA[5:2]

XD[31:0]

XRDY

/XWAIT

†

‡

§ 5

AD D1 D2 D3 D4

†

XW/R input/output polarity selected at boot

‡

XBLAST output polarity is always active low.

XBE[3:0]

XWE

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

/XWAIT operates as XWAIT output signal during host-port accesses.

Figure 33. ’C6202 as Bus Master—Read

XCLKIN

XAS

†

XW/R

†

XW/R

XD[31:0]

XRDY

/XWAIT

‡

Addr D1 D2 D3 D4

XBLAST

XBE[3:0]

†

XW/R input/output polarity selected at boot

‡

XBLAST output polarity is always active low.

XBE[3:0]

XWE

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

/XWAIT operates as XWAIT output signal during host-port accesses.

/XA[5:2]

XWE

1211

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Figure 34. ’C6202 as Bus Master—Write

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

XAS

†

XW/R

†

XW/R

XD[31:0]

XRDY

XBOFF

‡

§ 6

Addr D1 D2

XBLAST

XBE[3:0]/XA[5:2]

XHOLD

¶ #

XHOLDA

†

XW/R input/output polarity selected at boot

‡

XBLAST output polarity is always active low.

XBE[3:0]

Internal arbiter enabled

External arbiter enabled

This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 38 and Figure 39.

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

Figure 35. ’C6202 as Bus Master—BOFF Operation

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING

timing requirements with external device as asynchronous bus master

†

(see Figure 36 and

Figure 37)

NO. MIN MAX UNIT

1 t

w(XCSL)

2 t

w(XCSH)

3 t

su(XSEL-XCSL)

4 t

h(XCSL-XSEL)

10 t

h(XRYL-XCSL)

11 t

su(XBEV-XCSH)

12 t

h(XCSH-XBEV)

13 t

su(XDV-XCSH)

14 t

† ‡

h(XCSH-XDV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. Expansion bus select signals include XCNTL and XR/W. XBE[3:0]

/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

Pulse duration, XCS low 4P ns Pulse duration, XCS high 4P ns

Setup time, expansion bus select signals‡ valid before XCS low 2 ns Hold time, expansion bus select signals‡ valid after XCS low 2 ns Hold time, XCS low after XRDY low P ns Setup time, XBE[3:0]/XA[5:2] valid before XCS high Hold time, XBE[3:0]/XA[5:2] valid after XCS high Setup time, XDx valid before XCS high 2 ns Hold time, XDx valid after XCS high 2 ns

2 ns 2 ns

switching characteristics with external device as asynchronous bus master (see Figure 36 and Figure 37)

NO. PARAMETER MIN MAX UNIT

5 t

d(XCSL-XDLZ)

6 t

d(XCSH-XDIV)

7 t

d(XCSH-XDHZ)

8 t

d(XRYL-XDV)

9 t

d(XCSH-XRYH)

XCS

XCNTL

Delay time, XCS low to XDx low impedance 0 ns Delay time, XCS high to XDx invalid 0 12 ns Delay time, XCS high to XDx high impedance 12 ns Delay time, XRDY low to XDx valid 0 4 ns Delay time, XCS high to XRDY high 0 12 ns

XR/W

XD[31:0]

XRDY

†

‡

7 685

Word

XBE[3:0]

†

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

‡

XW/R input/output polarity selected at boot

/XA[5:2]

Figure 36. External Device as Asynchronous Master—Read

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7 685

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCS

XCNTL

XR/W

XD[31:0]

XRDY

†

‡

XBE[3:0]

†

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

‡

XW/R input/output polarity selected at boot

/XA[5:2]

word

Word

ADVANCE INFORMATION

Figure 37. External Device as Asynchronous Master—Write

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

XHOLD/XHOLDA TIMING

timing requirements for expansion bus arbitration (internal arbiter enabled)

NO. MIN MAX UNIT

3 t

†

oh(XHDAH-XHDH)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Output hold time, XHOLD high after XHOLDA high P ns

†

(see Figure 38)

switching characteristics for expansion bus arbitration (internal arbiter enabled)†‡ (see Figure 38)

NO. PARAMETER MIN MAX UNIT

1 t

R(XHDH-XBHZ)

2 t

d(XBHZ-XHDAH)

4 t

R(XHDL-XHDAL)

5 t

† ‡

†

d(XHDAL-XBLZ)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. XBus consists of XBE[3:0] All pending XBus transactions are allowed to complete before XHOLDA is asserted.

XHOLD (input)

XHOLDA (output)

XBus

XBus consists of XBE[3:0]

Response time, XHOLD high to XBus high impedance 4P Delay time, XBus high impedance to XHOLDA high 0 2P ns Response time, XHOLD low to XHOLDA low 4P ns Delay time, XHOLDA low to XBus low impedance 0 2P ns

/XA[5:2], XAS, XW/R, and XBLAST.

DSP Owns Bus

†

/XA[5:2], XAS, XW/R, and XBLAST.

C6202 C6202

External Requestor

Owns Bus

DSP Owns Bus

Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

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XHOLD/XHOLDA TIMING (CONTINUED)

switching characteristics for expansion bus arbitration (internal arbiter disabled)

NO. PARAMETER MIN MAX UNIT

1 t

d(XHDAH-XBLZ)

2 t

† ‡

†

d(XBHZ-XHDL)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. XBus consists of XBE[3:0]

XHOLD (output) XHOLDA (input)

XBus

XBus consists of XBE[3:0]

Delay time, XHOLDA high to XBus low impedance Delay time, XBus high impedance to XHOLD low

/XA[5:2], XAS, XW/R, and XBLAST.

†

/XA[5:2], XAS, XW/R, and XBLAST.

‡

C6202

†

(see Figure 39)

2P 2P + 10 ns

0 2P ns

Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled

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Setup time, external FSR high before CLKR lo

Hold time, external FSR high after CLKR lo

Setup time, DR valid before CLKR lo

Hold time, DR valid after CLKR lo

Setup time, external FSX high before CLKX lo

Hold time, external FSX high after CLKX lo

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP

NO.

2 t

c(CKRX)

3 t

w(CKRX)

su(FRH-CKRL)

h(CKRL-FRH)

su(DRV-CKRL)

h(CKRL-DRV)

su(FXH-CKXL)

h(CKXL-FXH)

†

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Cycle time, CLKR/X CLKR/X ext 2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–1 ns

†‡

(see Figure 40)

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

CLKR int 9 CLKR ext CLKR int 6 CLKR ext CLKR int 8 CLKR ext CLKR int 3 CLKR ext CLKX int 9 CLKX ext CLKX int 6 CLKX ext 3

UNIT

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TMS320C6202

Delay time, CLKX high to internal FSX valid

,g g

Delay time, CLKX high to DX valid

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP

NO. PARAMETER

1 t

d(CKSH-CKRXH)

2 t

c(CKRX)

3 t

w(CKRX)

4 t

d(CKRH-FRV)

d(CKXH-FXV)

dis(CKXH-DXHZ)

d(CKXH-DXV)

d(FXH-DXV)

†

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡

Minimum delay times also represent minimum output hold times.

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input

Cycle time, CLKR/X CLKR/X int 2P Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶C + 1 Delay time, CLKR high to internal FSR valid CLKR int –2 3 ns

Disable time, DX high impedance following last data bit from CLKX high

Delay time, FSX high to DX valid

ONLY applies when in data delay 0 (XDATDLY = 00b) mode.

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

†‡

(see Figure 40)

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

4 10 ns

CLKX int –2 3 CLKX ext 3 9 CLKX int –1 4 CLKX ext CLKX int –1 4 CLKX ext 3 9

FSX int –1 3

FSX ext 3 9

3 9

UNIT

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

CLKR

FSR (int)

FSR (ext)

CLKX

FSX (int)

FSX (ext)

Bit(n-1) (n-2) (n-3)

FSX (XDATDLY=00b)

1312

Bit 0 Bit(n-1) (n-2) (n-3)

Figure 40. McBSP Timings

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 41)

NO.

1 t

su(FRH-CKSH)

2 t

h(CKSH-FRH)

CLKR/X (no need to resync)

CLKR/X(needs resync)

Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns

CLKS

FSR external

Figure 41. FSR Timing When GSYNC = 1

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

UNIT

PARAMETER

UNIT

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

’C6202-200 ’C6202-233

4 t

su(DRV-CKXL)

5 t

† ‡

h(CKXL-DRV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX low 12 2 – 3P ns Hold time, DR valid after CLKX low 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6202-250

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

†‡

(see Figure 42)

†‡

(see Figure 42)

’C6202-200 ’C6202-233

1 t

h(CKXL-FXL)

2 t

d(FXL-CKXH)

3 t

d(CKXH-DXV)

6 t

dis(CKXL-DXHZ)

7 t

dis(FXH-DXHZ)

8 t

† ‡

d(FXL-DXV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high Delay time, CLKX high to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX low Disable time, DX high impedance following last data bit from

FSX high Delay time, FSX low to DX valid 2P + 2 4P + 17 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

MASTER

MIN MAX MIN MAX

T – 2 T + 3 ns

L – 2 L + 3 ns

’C6202-250

SLAVE

P + 3 3P + 17 ns

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

FSX

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

UNIT

PARAMETER

UNIT

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0

’C6202-200 ’C6202-233

4 t

su(DRV-CKXH)

5 t

† ‡

h(CKXH-DRV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX high 12 2 – 3P ns Hold time, DR valid after CLKX high 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6202-250

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0

†‡

(see Figure 43)

†‡

(see Figure 43)

’C6202-200 ’C6202-233

1 t

h(CKXL-FXL)

2 t

d(FXL-CKXH)

3 t

d(CKXL-DXV)

6 t

dis(CKXL-DXHZ)

7 t

† ‡

d(FXL-DXV)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX low Delay time, FSX low to DX valid H – 2 H + 4 2P + 2 4P + 17 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

MASTER

MIN MAX MIN MAX

L – 2 L + 3 ns

T – 2 T + 3 ns

’C6202-250

–2 4 3P + 3 5P + 17 ns

SLAVE

ADVANCE INFORMATION

CLKX

FSX

376

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

UNIT

PARAMETER

UNIT

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1

’C6202-200 ’C6202-233

4 t

su(DRV-CKXH)

5 t

† ‡

h(CKXH-DRV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX high 12 2 – 3P ns Hold time, DR valid after CLKX high 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6202-250

†‡

(see Figure 44)

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 44)

’C6202-200 ’C6202-233

1 t

h(CKXH-FXL)

2 t

d(FXL-CKXL)

3 t

d(CKXL-DXV)

6 t

dis(CKXH-DXHZ)

7 t

dis(FXH-DXHZ)

8 t

† ‡

ADVANCE INFORMATION

d(FXL-DXV)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX high Disable time, DX high impedance following last data bit from

FSX high Delay time, FSX low to DX valid 2P + 2 4P + 17 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

MASTER

MIN MAX MIN MAX

T – 2 T + 3 ns

H – 2 H + 3 ns

’C6202-250

SLAVE

P + 3 3P + 17 ns

†‡

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

FSX

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE INFORMATION

TMS320C6202

UNIT

PARAMETER

UNIT

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1

’C6202-200 ’C6202-233

4 t

su(DRV-CKXL)

5 t

† ‡

h(CKXL-DRV)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX low 12 2 – 3P ns Hold time, DR valid after CLKX low 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6202-250

†‡

(see Figure 45)

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 45)

’C6202-200 ’C6202-233

1 t

h(CKXH-FXL)

2 t

d(FXL-CKXL)

3 t

d(CKXH-DXV)

6 t

dis(CKXH-DXHZ)

7 t

† ‡

ADVANCE INFORMATION

d(FXL-DXV)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low Delay time, CLKX high to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX high Delay time, FSX low to DX valid L – 2 L + 4 2P + 2 4P + 17 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

MASTER

MIN MAX MIN MAX

H – 2 H + 3 ns

T – 2 T + 1 ns

’C6202-250

–2 4 3P + 3 5P + 17 ns

SLAVE

†‡

CLKX

FSX

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

DMAC, TIMER, POWER-DOWN TIMING

switching characteristics for DMAC outputs

NO. PARAMETER

1 t

†

w(DMACH)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

DMAC[3:0]

Pulse duration, DMAC high 2P–3 ns

†

(see Figure 46)

Figure 46. DMAC Timing

timing requirements for timer inputs† (see Figure 47)

NO.

1 t

w(TINPH)

2 t

†

w(TINPL)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Pulse duration, TINP high 2P ns Pulse duration, TINP low 2P ns

switching characteristics for timer outputs† (see Figure 47)

NO. PARAMETER

3 t

w(TOUTH)

4 t

†

w(TOUTL)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

TINPx

TOUTx

Pulse duration, TOUT high 2P–3 ns Pulse duration, TOUT low 2P–3 ns

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

ADVANCE INFORMATION

Figure 47. Timer Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)

switching characteristics for power-down outputs

NO. PARAMETER

1 t

†

w(PDH)

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Pulse duration, PD high 10P ns

†

(see Figure 48)

Figure 48. Power-Down Timing

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

FIXED-POINT DIGITAL SIGNAL PROCESSOR

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 49)

NO.

1 t

c(TCK)

3 t

su(TDIV-TCKH)

4 t

h(TCKH-TDIV)

switching characteristics for JTAG test port (see Figure 49)

NO. PARAMETER

2 t

d(TCKL-TDOV)

Cycle time, TCK 50 ns Setup time, TDI/TMS/TRST valid before TCK high 10 ns Hold time, TDI/TMS/TRST valid after TCK high 5 ns

Delay time, TCK low to TDO valid 0 15 ns

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

’C6202-200 ’C6202-233 ’C6202-250

MIN MAX

UNIT

TCK

TDO

TDI/TMS/TRST

Figure 49. JTAG Test-Port Timing

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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MECHANICAL DATA

GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY

27,20

26,80 25,20

16,30 NOM

Heat Slug

24,80

16,30 NOM

AF AD AB Y V T P M K H F D B

See Note E

AE AC AA W U R N L J G E C A

1 3 5 7 9 11131517192123

1,00

25,00 TYP

0,50

1,00

0,50

2622201612 14 1810862

3,50 MAX

1,00 NOM

Seating Plane

ADVANCE INFORMATION

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with heat slug (HSL). D. Flip chip application only

E. Possible protrusion in this area, but within 3,50 max package height specification

F. Falls within JEDEC MO-151/AAL-1

0,70 0,50

∅ 0,10

0,60 0,40

0,15

4173516-2/C 07/99

thermal resistance characteristics (S-PBGA package)

NO °C/W Air Flow LFPM

1 RΘ 2 RΘ 3 RΘ 4 RΘ 5 RΘ

†

LFPM = Linear Feet Per Minute

Junction-to-case 0.47 N/A

Junction-to-free air 14.2 0

Junction-to-free air 12.3 100

Junction-to-free air 10.2 250

Junction-to-free air 8.6 500

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

MECHANICAL DATA

GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY

18,10 17,90

Heat Slug

3 9

0,80

16,80 TYP

0,40

0,80

0,40

1,00 NOM

0,55 0,45

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with heat slug (HSL) D. Flip chip application only

0,10

2,80 MAX

0,45 0,35

Seating Plane

0,15

4188959/B 12/98

thermal resistance characteristics (S-PBGA package)

NO °C/W Air Flow LFPM

1 RΘ 2 RΘ 3 RΘ 4 RΘ 5 RΘ

†

LFPM = Linear Feet Per Minute

Junction-to-case 0.85 N/A

Junction-to-free air 21.6 0

Junction-to-free air 17.9 100

Junction-to-free air 14.2 250

Junction-to-free air 11.8 500

ADVANCE INFORMATION

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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Texas Instruments TMS320C6202 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual