Texas Instruments TMS320C6202 User Manual

D

Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6202
– 4-ns Instruction Cycle Time
– 250-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 2000 MIPS

D

VelociTI Advanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core
– Eight Highly Independent Functional

Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional

D

Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization

D

3M-Bit On-Chip SRAM
– 2M-Bit Internal Program/Cache

– Two 128K-Byte Blocks Offer Improved

Concurrency
Block 0: 128K Bytes Memory-Mapped
Block 1: 128K Bytes Direct-Mapped

Cache/Memory-Mapped

– 1M-Bit Dual-Access Internal Data

(128K Bytes)

– Two 64K-Byte Blocks Offer Improved

Concurrency

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

D

32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous

Memories: SDRAM or SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

D

Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel

D

Flexible Phase-Locked-Loop (PLL) Clock
Generator

D

32-Bit Expansion Bus
– Glueless/Low-Glue Interface to Popular

PCI Bridge Chips

– Glueless/Low-Glue Interface to Popular

Synchronous or Asynchronous

Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs

and Asynchronous Peripherals

D

Three Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA

Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

D

Two 32-Bit General-Purpose Timers

D

IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible

D

352-Pin BGA Package (GJL Suffix)

D

384-Pin BGA Package (GLS Suffix)

D

0.18-µm/5-Level Metal Process
– CMOS Technology

D

3.3-V I/Os, 1.8-V Internal

ADVANCE INFORMATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1999, Texas Instruments Incorporated

1

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE

AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A

3

111

2

GLS 384-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW)

9

75

8

64

(BOTTOM VIEW)

16121314 1810

20

23

24

2622

19 211715

25

ADVANCE INFORMATION

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

19

14

15

16 18

17

20

22

13

8

11

10 12

1

3 9 21

2

75

4 6

2

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

description

The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the
TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced
VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this
DSP an excellent choice for multichannel and multifunction applications.

With performance of up to 2000 million instructions per second (MIPS) at a clock rate of 250 MHz, the ’C6202
offers cost-effective solutions to high-performance DSP programming challenges. The ’C6202 DSP possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. This
processor has 32 general-purpose registers of 32–bit word length and eight highly independent functional units.
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit
multipliers for a 32-bit result. The ’C6202 can produce two multiply-accumulates (MACs) per cycle for a total
of 500 million MACs per second (MMACS). The ’C6202 DSP also has application-specific hardware logic,
on-chip memory, and additional on-chip peripherals.

The ’C6202 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of two 128K-byte blocks, with one block configured as memory-mapped program
space, and the other block user-configured as cache or memory-mapped program space. Data memory
consists of two 64K-byte blocks of RAM. The peripheral set includes three multichannel buffered serial ports
(McBSPs), two general-purpose timers, an expansion bus (XB) that offers ease of interface to synchronous or
asynchronous industry-standard host bus protocols, and a glueless external memory interface (EMIF) capable
of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6202 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.

device characteristics

T able 1 provides an overview of the ’C6202 DSP . The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

Table 1. Characteristics of the ’C6202 Processors

CHARACTERISTICS DESCRIPTION

Device Number TMS320C6202

2 Mbit Program Memory

On-Chip Memory

Peripherals

Cycle Time 4 ns
Package Type

Nominal Voltage

(organized as 2 blocks)
1 Mbit Data Memory
(organized as 2 blocks)

3 Multichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
External Memory Interface (EMIF)
Expansion Bus (XB)

27 mm × 27 mm, 352-Pin BGA (GJL)
18 mm × 18 mm, 384-Pin BGA (GLS)

1.8 V Core

3.3 V I/O

ADVANCE INFORMATION

TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.

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3

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

functional block diagram

Timers

Interrupt Selector

McBSPs

XB Control

DMA Control

EMIF Control

Expansion Bus (XB)

Interface

PLL

Power

Down

Boot-

Config.

EMIF

Peripheral

Bus

Controller

DMA

Controller

Data Memory

Data Memory

Controller

CPU

Program Memory Controller

Program Memory/Cache

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C6200 CPU from other VLIW
architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units
on each side of the CPU can freely share the 16 registers belonging to that side. Additionally , each side features
a single data bus connected to all the registers on the other side, by which the two sets of functional units can
access data from the register files on the opposite side. While register access by functional units on the same
side of the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.

Another key feature of the ’C6200 CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.

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5

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

CPU description (continued)

Program Memory

32-Bit Address

256-Bit Data

External Memory

Interface

Data Path A Data Path B

Register File A Register File B

.S1

.L1

.M1 .D1 .D2

Program Fetch

Instruction Dispatch

Instruction Decode

.M2

.S2 .L2

’C62x CPU

Control

Registers

Control

Logic

Test
Emulation
Interrupts

ADVANCE INFORMATION

Data Memory

32-Bit Address

8-, 16-, 32-Bit Data

Figure 1. TMS320C62x CPU Block Diagram

Additional

Peripherals:

Timers,
Serial Ports,

etc.

6

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CPU description (continued)

Data Path A

DA1

DA2

ST1

LD1

LD2

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

src

1

src

dst

long dst

long src

long src
long dst

dst

src
src

dst

src
src

dst
src
src

src
src

dst

src
src

dst

2

8

8

8

1
2

1

2

1

2

2

1

2

1

32

Register

File A

(A0–A15)

2X
1X

.L1

.S1

.M1

.D1

.D2

.M2

Data Path B

src

2

src

dst

long dst

long src

long src

long dst

dst
src

src

1

8

32

8

8

2

1

.S2

ST2

.L2

Figure 2. TMS320C62x CPU Data Paths

Register

File B

(B0–B15)

ADVANCE INFORMATION

Control

Register

File

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7

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

signal groups description

CLKIN
CLKOUT2
CLKOUT1

CLKMODE0
CLKMODE1
CLKMODE2

PLLV

PLLG

PLLF

TMS
TDO

TDI

TCK

TRST
EMU1
EMU0

†
†

Clock/PLL

IEEE Standard

1149.1

(JTAG)

Emulation

Reset and
Interrupts

DMA Status

RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4

IACK
INUM3
INUM2
INUM1
INUM0

DMAC3
DMAC2
DMAC1
DMAC0

ADVANCE INFORMATION

RSV4
RSV3
RSV2

RSV1
RSV0

†

For GLS devices only

Reserved

Figure 3. CPU Signals

Power-Down

Status

Control/Status

PD

8

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signal groups description (continued)

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ED[31:0]

CE3
CE2
CE1
CE0

EA[21:2]

BE3
BE2
BE1
BE0

TOUT1

TINP1

32

20

Data

Memory Map

Space Select

Word Address

Byte Enables

Timer 1

Asynchronous

Memory

Control

Synchronous

Memory

Control

HOLD/

HOLDA

EMIF

(External Memory Interface)

Timer 0

Timers

McBSP0

Transmit

ARE
AOE
AWE
ARDY

SDA10
SDRAS

/SSOE
SDCAS/SSADS
SDWE/SSWE

HOLD
HOLDA

TOUT0
TINP0

CLKX0
FSX0
DX0

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

McBSP1

Transmit

Receive

Clock

McBSPs

(Multichannel Buffered Serial Ports)

Receive

Clock

McBSP2

Transmit

Receive

Clock

Figure 4. Peripheral Signals

CLKR0
FSR0
DR0

CLKS0

ADVANCE INFORMATION

CLKX2
FSX2
DX2

CLKR2
FSR2
DR2

CLKS2

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9

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

signal groups description (continued)

XD[31:0]

XBE3/XA5

/XA4

XBE2

/XA3

XBE1
XBE0

/XA2

XRDY

XHOLD

XHOLDA

32

Data

Byte-Enable

Control/
Address

Control

Arbitration

Interface

Expansion Bus

Figure 4. Peripheral Signals (Continued)

Clocks

I/O Port
Control

Host

Control

XCLKIN
XFCLK

XOE
XRE
XWE/XWAIT
XCE3
XCE2
XCE1
XCE0

XCS
XAS
XCNTL
XW/R
XBLAST
XBOFF

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TYPE

†

DESCRIPTION

• Selects whether the CPU clock frequency = in ut clock frequency x4 or x1

I

O

lid duri

IACK f

l)

g

• Encoding order follows the interru t service fetch acket ordering

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions

SIGNAL

NAME

CLKIN C12 B10 I Clock Input
CLKOUT1 AD20 Y18 O Clock output at full device speed

CLKOUT2 AC19 AB19 O
CLKMODE0 B15 B12 I

CLKMODE1 – A9 I
CLKMODE2 – A14 I

‡

PLLV

‡

PLLG
PLLF C13 A11 A

TMS AD7 Y5 I JTAG test-port mode select (features an internal pullup)
TDO AE6 AA4 O/Z JTAG test-port data out
TDI AF5 Y4 I JTAG test-port data in (features an internal pullup)
TCK AE5 AB2 I JTAG test-port clock
TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown)
EMU1 AF6 AA5 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor
EMU0 AC8 AB4 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor

RESET K2 J3 I Device reset
NMI L2 K2 I
EXT_INT7 V4 U2

EXT_INT6 Y2 U3
EXT_INT5 AA1 W1
EXT_INT4 W4 V2
IACK Y1 V1 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 V2 R3
INUM2 U4 T1
INUM1 V3 T2
INUM0 W2 T3

PD AB2 Y2 O Power-down modes 2 or 3 (active if high)

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

‡

PLLV and PLLG are not part of external voltage supply or ground. See the

§

A = Analog Signal (PLL Filter)

¶

For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.

PIN NO.

GJL GLS

D13 C11 A
D14 C12 A

CLOCK/PLL

Clock output at half of device speed

• Used for synchronous memory interface

Clock mode selects (Note: CLKMODE1 and CLKMODE2 selects are for GLS devices only)

§

PLL analog VCC connection for the low-pass filter

§

PLL analog GND connection for the low-pass filter

§

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

RESET AND INTERRUPTS

Nonmaskable interrupt

• Edge-driven (rising edge)

External interrupts

• Edge-driven (rising edge)

Active interrupt identification number

•Va

• Encoding order follows the interrupt-service fetch-packet orderin

ng

POWER-DOWN STATUS

or all active interrupts (not just externa

clock PLL

p

section for information on how to connect these pins.

p

¶
¶

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11

TMS320C6202

TYPE

†

DESCRIPTION

Ex ansion bus data

,,

XCE[3:0] memory ty e

I/O/Z

y

– Arbitration mode (internal or external)

O/Z

bits 28, 29

Only

asserted du

access

• Only one asserted during any I/O ort data access

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

XCLKIN A9 C8 I Expansion bus synchronous host interface clock input
XFCLK B9 A8 O Expansion bus FIFO interface clock output
XD31 D15 C13
XD30 B16 A13
XD29 A17 C14
XD28 B17 B14
XD27 D16 B15
XD26 A18 C15
XD25 B18 A15
XD24 D17 B16
XD23 C18 C16
XD22 A20 A17
XD21 D18 B17
XD20 C19 C17
XD19 A21 B18
XD18 D19 A19
XD17 C20 C18
XD16 B21 B19
XD15 A22 C19
XD14 D20 B20
XD13 B22 A21
XD12 E25 C21
XD11 F24 D20
XD10 E26 B22
XD9 F25 D21
XD8 G24 E20
XD7 H23 E21

ADVANCE INFORMATION

XD6 F26 D22
XD5 G25 F20
XD4 J23 F21
XD3 G26 E22
XD2 H25 G20
XD1 J24 G21
XD0 K23 G22
XCE3 F2 D2
XCE2 E1 B1
XCE1 F3 D3
XCE0 E2 C2

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EXPANSION BUS

p

• Used for transfer of data, address, and control

• Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown

resistors
–

–
– XBLAST polarity
– XW/R polarity
– Asynchronous or synchronous host operation
–
– FIFO mode
– Little endian/big endian
–Boot mode

Expansion bus I/O port memory space enables

•Enabled by

one

•

p

, and 30 of the word address

ring any I/O port data

12

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TYPE

†

DESCRIPTION

I/O/Z

• Act as address for I/O ort o eration

O/Z

bits 24

Only

asserted du

access

• Only one asserted during any external data access

Byte-enable control

O/Z

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

XBE3/XA5 C7 C5
XBE2/XA4 D8 A4
XBE1/XA3 A6 B5
XBE0/XA2 C8 C6
XOE A7 A6 O/Z Expansion bus I/O port output enable
XRE C9 C7 O/Z Expansion bus I/O port read enable
XWE/XWAIT D10 B7 O/Z Expansion bus I/O port write enable and host port wait signals
XCS A10 C9 I Expansion bus host port chip-select input
XAS D9 B6 I/O/Z Expansion bus host port address strobe
XCNTL B10 B9 I Expansion bus host control. XCNTL selects between expansion bus address or data register
XW/R D11 B8 I/O/Z Expansion bus host port write/read enable. XW/R polarity selected at reset
XRDY A5 C4 I/O/Z Expansion bus host port ready (active low) and I/O port ready (active high)
XBLAST B6 B4 I/O/Z Expansion bus host port burst last–polarity selected at reset
XBOFF B11 A10 I Expansion bus back off
XHOLD B5 A2 I/O/Z Expansion bus hold request
XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge

CE3 AB25 Y21
CE2 AA24 W20
CE1 AB26 AA22
CE0 AA25 W21
BE3 Y24 V20
BE2 W23 V21
BE1 AA26 W22
BE0 Y25 U20

EA21 J25 H20
EA20 J26 H21
EA19 L23 H22
EA18 K25 J20
EA17 L24 J21
EA16 L25 K21
EA15 M23 K20
EA14 M24 K22
EA13 M25 L21
EA12 N23 L20
EA11 P24 L22

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EXPANSION BUS (CONTINUED)

Expansion bus multiplexed byte-enable control/address signals

•Act as byte enable for host port operation

• Act as address for I/O port operation

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

Memory space enables

•Enabled by

one

•

• Decoded from the two lowest bits of the internal address

• Byte-write enables for most types of memory

• Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIF – ADDRESS

O/Z External address (word address)

and 25 of the word address

p

p

ring any external data

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13

TMS320C6202

TYPE

†

DESCRIPTION

I/O/Z

External data

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

EA10 P23 M20
EA9 R25 M21
EA8 R24 N22
EA7 R23 N20
EA6 T25 N21
EA5 T24 P21
EA4 U25 P20
EA3 T23 R22
EA2 V26 R21

ED31 AD8 Y6
ED30 AC9 AA6
ED29 AF7 AB6
ED28 AD9 Y7
ED27 AC10 AA7
ED26 AE9 AB8
ED25 AF9 Y8
ED24 AC11 AA8
ED23 AE10 AA9
ED22 AD11 Y9
ED21 AE11 AB10
ED20 AC12 Y10
ED19 AD12 AA10
ED18 AE12 AA11
ED17 AC13 Y11
ED16 AD14 AB12
ED15 AC14 Y12

ADVANCE INFORMATION

ED14 AE15 AA12
ED13 AD15 AA13
ED12 AC15 Y13
ED11 AE16 AB13
ED10 AD16 Y14
ED9 AE17 AA14
ED8 AC16 AA15
ED7 AF18 Y15
ED6 AE18 AB15
ED5 AC17 AA16
ED4 AD18 Y16
ED3 AF20 AB17
ED2 AC18 AA17
ED1 AD19 Y17
ED0 AF21 AA18

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EMIF – ADDRESS (CONTINUED)

O/Z External address (word address)

EMIF – DATA

14

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TYPE

†

DESCRIPTION

O

DMA action complete

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

ARE V24 T21 O/Z Asynchronous memory read enable
AOE V25 R20 O/Z Asynchronous memory output enable
AWE U23 T22 O/Z Asynchronous memory write enable
ARDY W25 T20 I Asynchronous memory ready input

SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output enable
SDWE/SSWE AC20 AA20 O/Z SDRAM write enable/SBSRAM write enable

HOLD Y26 V22 I Hold request from the host
HOLDA V23 U21 O Hold-request-acknowledge to the host

TOUT1 J4 F2 O Timer 1 or general-purpose output
TINP1 G2 F3 I Timer 1 or general-purpose input
TOUT0 F1 D1 O Timer 0 or general-purpose output
TINP0 H4 E2 I Timer 0 or general-purpose input

DMAC3 Y3 V3
DMAC2 AA2 W2
DMAC1 AB1 AA1
DMAC0 AA3 W3

CLKS0 M4 K3 I External clock source (as opposed to internal)
CLKR0 M2 L2 I/O/Z Receive clock
CLKX0 M3 K1 I/O/Z Transmit clock
DR0 R2 M2 I Receive data
DX0 P4 M3 O/Z Transmit data
FSR0 N3 M1 I/O/Z Receive frame sync
FSX0 N4 L3 I/O/Z Transmit frame sync

CLKS1 G1 E1 I External clock source (as opposed to internal)
CLKR1 J3 G2 I/O/Z Receive clock
CLKX1 H2 G3 I/O/Z Transmit clock
DR1 L4 H1 I Receive data
DX1 J1 H2 O/Z Transmit data
FSR1 J2 H3 I/O/Z Receive frame sync
FSX1 K4 G1 I/O/Z Transmit frame sync

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

EMIF – ASYNCHRONOUS MEMORY CONTROL

EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL

EMIF – BUS ARBITRATION

TIMERS

DMA ACTION COMPLETE STATUS

p

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

TMS320C6202

ADVANCE INFORMATION

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15

TMS320C6202

TYPE

†

DESCRIPTION

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

CLKS2 R3 N1 I External clock source (as opposed to internal)
CLKR2 T2 N2 I/O/Z Receive clock
CLKX2 R4 N3 I/O/Z Transmit clock
DR2 V1 R2 I Receive data
DX2 T4 R1 O/Z Transmit data
FSR2 U2 P3 I/O/Z Receive frame sync
FSX2 T3 P2 I/O/Z Transmit frame sync

RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3 C15 B13 O Reserved (leave unconnected,
RSV4 D12 C10 O Reserved (leave unconnected,

DV

DD

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

A11 A3

A16 A7

B7 A16

B8 A20
B19 D4
B20 D6

C6 D7
C10 D9
C14 D10
C17 D13
C21 D14

G4 D16
G23 D17

H3 D19
H24 F1

K3 F4
K24 F19

L1 F22

L26 G4

N24 G19

P3 J4

MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)

RESERVED FOR TEST

do not

connect to power or ground)

do not

connect to power or ground)

SUPPLY VOLTAGE PINS

S 3.3-V supply voltage

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TYPE

†

DESCRIPTION

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

DV

DD

CV

DD

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

T1 J19

T26 K4

U3 K19

U24 L1

W3 M22

W24 N4

Y4 N19

Y23 P4

AD6 P19
AD10 T4
AD13 T19
AD17 U1
AD21 U4

AE7 U19

AE8 U22
AE19 W4
AE20 W6

AF11 W7

AF16 W9

– W10
– W13
– W14
– W16
– W17
– W19
– AB5
– AB9
– AB14

– AB18
A1 E7
A2 E8
A3 E10

A24 E11
A25 E12
A26 E13

B1 E15
B2 E16
B3 F7

B24 F8
B25 F9
B26 F11

C1 F12

SUPPLY VOLTAGE PINS (CONTINUED)

S 3.3-V supply voltage

S 1.8-V supply voltage

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ADVANCE INFORMATION

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17

TMS320C6202

TYPE

†

DESCRIPTION

CV

S

1.8-V suppl

oltage

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

DD

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

C2 F14
C3 F15

C4 F16
C23 G5
C24 G6
C25 G17
C26 G18

D3 H5

D4 H6

D5 H17
D22 H18
D23 J6
D24 J17

E4 K5
E23 K18
AB4 L5

AB23 L6

AC3 L17
AC4 L18
AC5 M5

AC22 M6
AC23 M17
AC24 M18

AD1 N5
AD2 N18
AD3 P6
AD4 P17

AD23 R5
AD24 R6
AD25 R17
AD26 R18

AE1 T5
AE2 T6
AE3 T17

AE24 T18
AE25 U7
AE26 U8

AF1 U9
AF2 U11
AF3 U12

AF24 U14
AF25 U15

SUPPLY VOLTAGE PINS (CONTINUED)

pp

y v

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TYPE

†

DESCRIPTION

V

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

CV

DD

SS

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

AF26 U16

– V7
– V8
– V10
– V11
– V12
– V13
– V15
– V16

A4 A1

A8 A5
A13 A12
A14 A18
A15 A22
A19 B2
A23 B21

B4 C1
B12 C3
B13 C20
B14 C22
B23 D5

C5 D8
C11 D11
C16 D12
C22 D15

D1 D18

D2 E4

D6 E5
D21 E6
D25 E9
D26 E14

E3 E17
E24 E18

F4 E19

F23 F5

H1 F6
H26 F10

SUPPLY VOLTAGE PINS (CONTINUED)

S 1.8-V supply voltage

GROUND PINS

p

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

19

TMS320C6202

TYPE

†

DESCRIPTION

V

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

NAME

SS

ADVANCE INFORMATION

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

K1 F13

K26 F17

M1 F18

M26 H4

N1 H19

N2 J1
N25 J5
N26 J18

P1 J22

P2 K6
P25 K17
P26 L4

R1 L19
R26 M4

U1 M19
U26 N6

W1 N17

W26 P1

AA4 P5

AA23 P18

AB3 P22

AB24 R4

AC1 R19
AC2 U5
AC6 U6

AC21 U10
AC25 U13
AC26 U17

AD5 U18

AD22 V4

AE4 V5

AE13 V6
AE14 V9
AE23 V14

AF4 V17
AF8 V18

GROUND PINS (CONTINUED)

p

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TYPE

†

DESCRIPTION

V

GND

Ground pins

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME

SS

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PIN NO.

GJL GLS

AF10 V19
AF12 W5
AF13 W8
AF14 W11
AF15 W12
AF17 W15
AF19 W18
AF23 Y1

– Y3
– Y20
– Y22
– AA2
– AA21
– AB1
– AB3
– AB7
– AB11
– AB16
– AB20
– AB22

GROUND PINS (CONTINUED)

p

TMS320C6202

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE INFORMATION

21

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

development support

Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.

The following products support development of ’C6200-based applications:

Software Development Tools:

Assembly optimizer
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler

Hardware Development Tools:

Extended development system (XDS) emulator (supports ’C6200 multiprocessor system debug)
EVM (Evaluation Module)

The

TMS320 DSP Development Support Reference Guide

development-support products for all TMS320 family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the

TMS320 Third-Party Support Reference Guide

information about TMS320-related products from other companies in the industry . T o receive TMS320 literature,
contact the Literature Response Center at 800/477-8924.

(SPRU011) contains information about

(SPRU052), contains

See Table 2 for a complete listing of development-support tools for the ’C6200. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.

Table 2. TMS320C6xx Development-Support Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER

Software

C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07
C Compiler/Assembler/Linker/Assembly Optimizer SPARCSolaris TMDX3246555-07
Simulator Win32 TMDS3246851-07
Simulator SPARCSolaris TMDS3246551-07

ADVANCE INFORMATION

XDS510 Debugger/Emulation Software Win32, Windows NT TMDX324016X-07

Hardware

XDS510 Emulator
XDS510WS Emulator

EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201
EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201

†

Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.

‡

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.

†

‡

Software/Hardware

PC TMDS00510

SCSI TMDS00510WS

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.
Win32 and Windows NT are trademarks of Microsoft Corporation.
SPARC is a trademark of SPARC International, Inc.
Solaris is a trademark of Sun Microsystems, Inc.

22

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

device and development-support tool nomenclature

T o designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX)
through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical

specifications

TMP Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed T exas Instruments internal qualification

testing.

TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully , and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. T exas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GJL), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -250 is 250 MHz). Figure 5 provides a legend for
reading the complete device name for any TMS320 family member.

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23