Texas Instruments TMS320C6000 DSP Reference Manual

TMS320C6000 DSP

Software-Programmable

Phase-Locked Loop (PLL) Controller

Reference Guide

Literature Number: SPRU233A

April 2003

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About This Manual

This document describes the operation of the software-programmable phase­locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000 DSP family. This type of controller is used on the following
devices:

- TMS320C6711C

- TMS320C6712C

- TMS320C6713

Notational Conventions

This document uses the following conventions.

- Hexadecimal numbers are shown with the suffix h. For example, the

Preface

Read This First

following number is 40 hexadecimal (decimal 64): 40h.

Related Documentation From Texas Instruments

The following documents describe the C6000 devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www .ti.com.

TMS320C6000 CPU and Instruction Set Reference Guide (literature

number SPRU189) describes the TMS320C6000 CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.

TMS320C6000 Peripherals Reference Guide (literature number SPRU190)

describes the peripherals available on the TMS320C6000 DSPs.

TMS320C6000 Technical Brief (literature number SPRU197) gives an

introduction to the TMS320C62x and TMS320C67x DSPs, develop-
ment tools, and third-party support.

TMS320C64x Technical Overview (SPRU395) gives an introduction to the

TMS320C64x DSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.

3Title of DocSPRU233A

Trademarks

Related Documentation From Texas Instruments / Trademarks

TMS320C6000 Programmer’s Guide (literature number SPRU198)

describes ways to optimize C and assembly code for the
TMS320C6000 DSPs and includes application program examples.

TMS320C6000 Code Composer Studio Tutorial (literature number

SPRU301) introduces the Code Composer Studio integrated develop­ment environment and software tools.

Code Composer Studio Application Programming Interface Reference

Guide (literature number SPRU321) describes the Code Composer

Studio application programming interface (API), which allows you to
program custom plug-ins for Code Composer.

TMS320C6x Peripheral Support Library Programmer’s Reference

(literature number SPRU273) describes the contents of the
TMS320C6000 peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.

TMS320C6000 Chip Support Library API Reference Guide (literature

number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.

Trademarks

Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.

4 Phase-Locked Loop (PLL) Controller SPRU233A

Contents

1 Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Multiplier and Dividers 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Reset Controller 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Configuration 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Initialization 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 PLL Mode (PLLEN = 1) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 Bypass Mode (PLLEN = 0) 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Power Down 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Power Wake Up 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . .

4.2 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 PLL Controller Divider Registers (PLLDIV0–3) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5Phase-Locked Loop (PLL) ControllerSPRU233A

Figures

1 PLL Controller Block Diagram 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Reset Controller Lengthening the Internal Reset Signal 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 PLL Controller Divider Register (PLLDIV) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1 PLL Controller Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 PLL Controller Peripheral Identification Register (PLLPID) Field Descriptions 15. . . . . . . . . .

3 PLL Control/Status Register (PLLCSR) Field Descriptions 16. . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PLL Multiplier Control Register (PLLM) Field Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . .

5 PLL Controller Divider Register (PLLDIV) Field Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . .

6 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . .

6 Phase-Locked Loop (PLL) Controller SPRU233A

1 Overview

Phase-Locked Loop (PLL) Controller

This document describes the operation of the software-programmable phase­locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000 DSP family. This type of controller is used on the following
devices:

- TMS320C6711C

- TMS320C6712C

- TMS320C6713

The PLL controller (Figure 1) features software-configurable PLL multiplier
controller, dividers (OSCDIV1, D0, D1, D2, and D3), and reset controller. The
PLL controller accepts an input clock, as determined by the logic state on the
CLKMODE0 pin, from the CLKIN pin or from the on-chip oscillator output
signal OSCIN. The PLL controller offers flexibility and convenience by way of
software-configurable multiplier and dividers to modify the input signal inter­nally . The resulting clock outputs are passed to the DSP core, peripherals, and
other modules inside the C6000 DSP.

- The input reference clocks to the PLL controller:
J CLKIN: input signal from external oscillator (3.3V), CLKMODE0 = 1
J OSCIN: output signal from on-chip oscillator (1.2V), CLKMODE0 = 0

- The resulting output clocks from the PLL controller:
J AUXCLK: internal clock output signal directly from CLKIN or OSCIN.
J CLKOUT3: output of divider OSCDIV1.
J SYSCLK1: internal clock output of divider D1.
J SYSCLK2: internal clock output of divider D2.
J SYSCLK3: internal clock output of divider D3.

Refer to your device-specific datasheet on how these inputs and outputs of the
PLL controller are used.

7Phase-Locked Loop (PLL) ControllerSPRU233A