Texas Instruments TMS320LC57SRBK80, TMS320LC57SRBK50, TMS320LC57SRBK, TMS320LC57SPJEA80, TMS320LC57SPJEA50 Datasheet
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Powerful 16-Bit TMS320C5x CPU
D
20-, 25-, 35-, and 50-ns Single-Cycle
Instruction Execution Time for 5-V
Operation
D
25-, 40-, and 50-ns Single-Cycle Instruction
Execution Time for 3-V Operation
D
Single-Cycle 16 × 16-Bit Multiply/Add
D
224K × 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global)
D
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
On-Chip Program ROM
D
1K, 3K, 6K, 9K × 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM)
D
1K Dual-Access On-Chip Program/Data
RAM (DARAM)
D
Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface
D
Time-Division-Multiplexed (TDM) Serial Port
D
Hardware or Software Wait-State
Generation Capability
D
On-Chip Timer for Control Operations
D
Repeat Instructions for Efficient Use of
Program Space
D
Buffered Serial Port
D
Host Port Interface
D
Multiple Phase-Locked Loop (PLL)
Clocking Options (×1, ×2, ×3, ×4, ×5, ×9
Depending on Device)
D
Block Moves for Data/Program
Management
D
On-Chip Scan-Based Emulation Logic
D
Boundary Scan
D
Five Packaging Options
– 100-Pin Quad Flat Package (PJ Suffix)
– 100-Pin Thin Quad Flat Package
(PZ Suffix)
– 128-Pin Thin Quad Flat Package
(PBK Suffix)
– 132-Pin Quad Flat Package (PQ Suffix)
– 144-Pin Thin Quad Flat Package
(PGE Suffix)
D
Low Power Dissipation and Power-Down
Modes:
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz
Clock (Average)
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz
Clock (Average)
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
– 5 µA at 5 V, Clocks Off (IDLE2 Mode)
D
High-Performance Static CMOS T echnology
D
IEEE Standard 1149.1† Test-Access Port
(JTAG)
description
The TMS320C5x generation of the Texas Instruments (TI) TMS320 digital signal processors (DSPs) is
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory , and a highly specialized instruction set is the basis of the operational flexibility and speed of
the ’C5x
‡
devices. They execute up to 50 million instructions per second (MIPS).
The ’C5x devices offer these advantages:
D
Enhanced TMS320 architectural design for increased performance and versatility
D
Modular architectural design for fast development of spin-off devices
D
Advanced integrated-circuit processing technology for increased performance
D
Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)
D
Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation
D
New static-design techniques for minimizing power consumption and maximizing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
TI is a trademark of Texas Instruments Incorporated.
†
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
‡
References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
T able 1 provides a comparison of the devices in the ’C5x generation. It shows the capacity of on-chip RAM and
ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of
package with total pin count.
Table 1. Characteristics of the ’C5x Processors
ON-CHIP MEMORY (16-BIT WORDS)
TMS320
DARAM SARAM ROM
I/O PORTS
POWER
CYCLE
PACKAGE
DEVICES
DATA
DATA +
PROG
DATA +
PROG
PROG SERIAL PARALLEL
†
SUPPLY
(V)
TIME
(ns)
TYPE
QFP
‡
TMS320C50 544 512 9K 2K
§
2 64K 5 50/35/25 132 pin
TMS320LC50 544 512 9K 2K
§
2 64K 3.3 50/40/25 132 pin
TMS320C51 544 512 1K 8K
§
2 64K 5 50/35/25/20 100/132 pin
TMS320LC51 544 512 1K 8K
§
2 64K 3.3 50/40/25 100/132 pin
TMS320C52 544 512 – 4K
§
1
¶
64K 5 50/35/25/20 100 pin
TMS320LC52 544 512 – 4K
§
1
¶
64K 3.3 50/40/25 100 pin
TMS320C53 544 512 3K 16K
§
2 64K 5 50/35/25 132 pin
TMS320LC53 544 512 3K 16K
§
2 64K 3.3 50/40/25 132 pin
TMS320C53S 544 512 3K 16K
§
2
¶
64K 5 50/35/25 100 pin
TMS320LC53S 544 512 3K 16K
§
2
¶
64K 3.3 50/40/25 100 pin
TMS320LC56 544 512 6K 32K 2
#
64K 3.3 35/25 100 pin
TMS320LC57 544 512 6K 32K 2
#
64K + HPI
||
3.3 35/25 128 pin
TMS320C57S 544 512 6K 2K
§
2
#
64K + HPI
||
5 50/35/25 144 pin
TMS320LC57S 544 512 6K 2K
§
2
#
64K + HPI
||
3.3 50/35 144 pin
†
Sixteen of the 64K parallel I/O ports are memory mapped.
‡
QFP = Quad flatpack
§
ROM boot loader available
¶
TDM serial port not available
#
Includes auto-buffered serial port (BSP) but TDM serial port not available
||
HPI = Host port interface
Pinouts for each package are device-specific.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53
PQ PACKAGE
(TOP VIEW)
WE
DDAVDDA
V
V
SSD
V
SSD
D7
D6
D5
D4
D3
D2
D1
D0
TMS
V
DDD
V
DDD
TCK
V
SSD
V
SSD
INT1
INT2
INT3
INT4
NMI
DR
TDR
FSR
CLKR
V
DDA
V
DDA
V
SSC
V
SSC
DS
IS
PS
R/W
STRB
BR
CLKIN2
X2/CLKIN
X1
V
DDC
V
DDC
TDO
V
SSI
V
SSI
FSX
TFSX/TFRM
DX
TDX
HOLDA
XF
CLKOUT1
NC
IACK
V
DDI
V
DDI
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
36
50
49
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DDDVDDD
VD8D9
D10
D11
D12
D13
D14
D15
MP/MC
TRST
IAQ
SSIVSSI
V
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 82 83
DDCVDDC
V
BIO
HOLD
READYRSTCLKR
TFSR/TADD
CLKX
TCLKX
TOUT
EMU1/OFF
EMU0
SSCVSSC
V
SSAVSSA
V
A0A1A2A3A4A5A6A7A8
TDI
A9
CLKMD1
A10
A11
A12
A13
A14
A15
DDIVDDI
V
SSAVSSA
V
RD
79
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLKMD2
NC
NC
NC
NOTE: NC = No connect (These pins are reserved.)
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for Devices in the PQ Package
SIGNAL TYPE DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0)
D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0)
PS, DS, IS O/Z Program, data, and I/O space select outputs, respectively
STRB I/O/Z Timing strobe for external cycles and external DMA
R/W I/O/Z Read/write select for external cycles and external DMA
RD, WE O/Z Read and write strobes, respectively, for external cycles
READY I External bus ready/wait-state control input
BR I/O/Z Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
RS I Reset. Initializes device and sets PC to zero
MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM
HOLD I Puts parallel I/F bus in high-impedance state after current cycle
HOLDA O/Z Hold acknowledge. Indicates external bus in hold state
XF O/Z External flag output. Set/cleared through software
BIO I I/O branch input. Implements conditional branches
TOUT O/Z Timer output signal. Indicates output of internal timer
IAQ O/Z Instruction acquisition signal
IACK O/Z Interrupt acknowledge signal
INT1–INT4 I External interrupt inputs
NMI I Nonmaskable external interrupt
SERIAL PORT INTERFACE (SPI)
DR I Serial receive-data input
DX O/Z Serial transmit-data output. In high-impedance state when not transmitting
CLKR I Serial receive-data clock input
CLKX I/O/Z Serial transmit-data clock. Internal or external source
FSR I Serial receive-frame-synchronization input
FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source
TDM SERIAL-PORT INTERFACE
TDR I TDM serial receive-data input
TDX O/Z TDM serial transmit-data output. In high-impedance state when not transmitting
TCLKR I TDM serial receive-data clock input
TCLKX I/O/Z TDM serial transmit-data clock. Internal or external source
TFSR / TADD I/O/Z
TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/
input the address of the port.
TFSX /TFRM I
TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
TFSX/TFRM becomes TFRM, the TDM frame synchronization.
LEGEND:
I = Input
O = Output
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for Devices in the PQ Package (Continued)
EMULATION/IEEE STANDARD 1149.1 TEST ACCESS PORT (TAP)
TDI I TAP scan data input
TDO O/Z TAP scan data output
TMS I TAP mode select input
TCK I TAP clock input
TRST I TAP reset (with pulldown resistor). Disables TAP when low
EMU0 I/O/Z Emulation control 0. Reserved for emulation use
EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
X1 O Oscillator output
X2/CLKIN I Clock/oscillator input
CLKIN2 I Clock input
CLKMD1, CLKMD2 I Clock-mode select inputs
CLKOUT1 O/Z Device system-clock output
POWER SUPPLY CONNECTIONS
V
DDA
S Supply connection, address-bus output
V
DDD
S Supply connection, data-bus output
V
DDC
S Supply connection, control output
V
DDI
S Supply connection, internal logic
V
SSA
S Supply connection, address-bus output
V
SSD
S Supply connection, data-bus output
V
SSC
S Supply connection, control output
V
SSI
S Supply connection, internal logic
LEGEND:
I = Input
O = Output
S = Supply
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HINT
EMU0
EMU1/OFF
V
SSC
V
SSC
TOUT
BCLKX
CLKX
BFSR
BCLKR
RS
READY
HOLD
BIO
V
DDC
V
DDC
IAQ
TRST
V
SSI
V
SSI
MP/MC
D15
D14
D13
D12
D11
D10
D9
D8
V
DDD
V
DDD
HD1
WE
RD
HD0
HRDY
V
DDA
A15
A14
A13
A12
A11
A10
CLKMD1
V
SSA
V
SSA
TDI
HDS1
HDS2
V
DDI
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
SSA
HCS
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
33
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SSDVSSD
V
D7 V
D6
CLKOUT1
D5XFD4
HOLDAD3BDXD2DXD1HD7D0BFSX
TMS
HD6
DDD
DDD
TCK
CLKMD2
SSD
SSD
INT1
INT2
TDO
INT3
INT4
X1
NMI
X2/CLKIN
CLKMD3
STRB
R/ W
DR
BDR
HD3
FSR
IS
CLKR
PS
DDA
HD2
DDA
HAS
DDC
DDI
DDI
V
V
V
V
V
V
V
V
TMS320LC57
PBK PACKAGE
( TOP VIEW )
FSX
HD5
HD4
V
SSIVSSIVDDC
BR
DSVV
SSC
SSC
V
DDI
HBIL
HR/W
HCNTL0
HCNTL1
V
DDC
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for the TMS320LC57 in the PBK Package
SIGNAL TYPE DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0)
D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0)
PS, DS, IS O/Z Program, data, and I/O space select outputs, respectively
STRB I/O/Z Timing strobe for external cycles and external DMA
R/W I/O/Z Read/write select for external cycles and external DMA
RD, WE O/Z Read and write strobes, respectively, for external cycles
READY I External bus ready/wait-state control input
BR I/O/Z Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
RS I Reset. Initializes device and sets PC to zero
MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM
HOLD I Puts parallel I/F bus in high-impedance state after current cycle
HOLDA O/Z Hold acknowledge. Indicates external bus in hold state
XF O/Z External flag output. Set/cleared through software
BIO I I/O branch input. Implements conditional branches
TOUT O/Z Timer output signal. Indicates output of internal timer
IAQ O/Z Instruction acquisition signal
INT1–INT4 I External interrupt inputs
NMI I Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR I Serial receive-data input
DX O/Z Serial transmit-data output. In high-impedance state when not transmitting
CLKR I Serial receive-data clock input
CLKX I/O/Z Serial transmit-data clock. Internal or external source
FSR I Serial receive-frame-synchronization input
FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source
HOST PORT INTERFACE (HPI)
HCNTL0 I HPI mode control 1
HCNTL1 I HPI mode control 2
HINT O/Z Host interrupt
HDS1 I HPI data strobe 1
HDS2 I HPI data strobe 2
HR/W I HPI read/write strobe
HAS I HPI address strobe
HRDY O/Z HPI ready signal
HCS I HPI chip select
HBIL I HPI byte identification input
HD0–HD7 I/O/Z HPI data bus
LEGEND:
I = Input
O = Output
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for the TMS320LC57 in the PBK Package (Continued)
SIGNAL TYPE DESCRIPTION
BUFFERED SERIAL PORT
BDR I BSP receive data input
BDX O/Z BSP transmit data output; in high-impedance state when not transmitting
BCLKR I BSP receive-data clock input
BCLKX I/O/Z BSP transmit-data clock; internal or external source
BFSR I BSP receive frame-synchronization input
BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source
EMULATION/JTAG INTERFACE
TDI I JTAG-test-port scan data input
TDO O/Z JTAG-test-port scan data output
TMS I JTAG-test-port mode select input
TCK I JTAG-port clock input
TRST I JTAG-port reset (with pull-down resistor). Disables JTAG when low
EMU0 I/O/Z Emulation control 0. Reserved for emulation use
EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
X1 O Oscillator output
X2/CLKIN I Clock input
CLKMD1, CLKMD2,
CLKMD3
I Clock-mode select inputs
CLKOUT1 O/Z Device system-clock output
POWER SUPPLY CONNECTIONS
V
DDA
S Supply connection, address-bus output
V
DDD
S Supply connection, data-bus output
V
DDC
S Supply connection, control output
V
DDI
S Supply connection, internal logic
V
SSA
S Supply connection, address-bus output
V
SSD
S Supply connection, data-bus output
V
SSC
S Supply connection, control output
V
SSI
S Supply connection, internal logic
LEGEND:
I = Input
O = Output
S = Supply
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
INT3
INT2
INT1
HOLDA
TMS320C51, TMS320LC51, TMS320C52, TMS320LC52, TMS320C53S, TMS320LC53S, TMS320LC56
PZ PACKAGE
(TOP VIEW)
EMU1/OFF
V
SSC
RS
READY
HOLD
BIO
TRST
V
SSI
MP/MC
D15
D14
D12
D11
D10
D9
D8
V
DDD
18
25
24
23
22
21
20
19
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1EMU0
TOUT
D13
V
SSI
58
51
52
53
54
55
56
57
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
7475RD
V
DDA
A15
A14
A13
A12
A11
A10
CLKMD1
V
SSA
V
SSA
V
DDI
A9
A8
A7
A5
A4
A3
A2
A1
WE
A6
TDI
A0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DDC
V
CLKOUT1XF†
†
CLKMD2
TDO
†
BR
R/W
DS
X1
DDIVDDI
V
SSI
V
SSI
V
DDC
V
SSC
V
STRB
PS
IS
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SSD
V
D7
D6
D3D2D1
D0
TMS
TCK
SSD
V
DDD
V
D5
D4
INT4
NMI
†††
†
X2/CLKIN
V
SSA
†
†
†
†
†
†
DDA
V
SSDVSSD
V
†
See Table 2 for device-specific pinouts.
NOTE: NC = No connect (These pins are reserved.)
Table 2. Device-Specific Pinouts for the PZ Package
PIN ’C51, ’LC51 ’C52, ’LC52 ’C53S, ’LC53S ’LC56
‡
5 TCLKX V
SSI
CLKX2 BCLKX
6
§
CLKX CLKX CLKX1 CLKX
7 TFSR/TADD V
SSI
FSR2 BFSR
8 TCLKR V
SSI
CLKR2 BCLKR
46
§
DR DR DR1 DR
47 TDR V
SSI
DR2 BDR
48
§
FSR FSR FSR1 FSR
49
§
CLKR CLKR CLKR1 CLKR
83 CLKIN2 CLKIN2 CLKIN2 CLKMD3
91
§
FSX FSX FSX1 FSX
92 TFSX/TFRM V
SSI
FSX2 BFSX
93
§
DX DX DX1 DX
94 TDX NC DX2 BDX
‡
Pin names beginning with “B” indicate signals on the buffered serial port (BSP).
§
No functional change
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for Devices in the PZ Package
SIGNAL TYPE DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0)
D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0)
PS, DS, IS O/Z Program, data, and I/O space select outputs, respectively
STRB I/O/Z Timing strobe for external cycles and external DMA
R/W I/O/Z Read/write select for external cycles and external DMA
RD, WE O/Z Read and write strobes, respectively, for external cycles
READY I External bus ready/wait-state control input
BR I/O/Z Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
RS I Reset. Initializes device and sets PC to zero
MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM
HOLD I Puts parallel I/F bus in high-impedance state after current cycle
HOLDA O/Z Hold acknowledge. Indicates external bus in hold state
XF O/Z External flag output. Set/cleared through software
BIO I I/O branch input. Implements conditional branches
TOUT O/Z Timer output signal. Indicates output of internal timer
INT1–INT4 I External interrupt inputs
NMI I Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR, DR1, DR2 I Serial receive-data input
DX, DX1, DX2 O/Z Serial transmit-data output. In high-impedance state when not transmitting
CLKR, CLKR1, CLKR2 I Serial receive-data clock input
CLKX, CLKX1, CLKX2 I/O/Z Serial transmit-data clock. Internal or external source
FSR, FSR1, FSR2 I Serial receive-frame-synchronization input
FSX, FSX1, FSX2 I/O/Z Serial transmit-frame-synchronization signal. Internal or external source
BUFFERED SERIAL PORT (BSP) (SEE NOTE 1)
BDR I BSP receive data input
BDX O/Z BSP transmit data output; in high-impedance state when not transmitting
BCLKR I BSP receive-data clock input
BCLKX I/O/Z BSP transmit-data clock; internal or external source
BFSR I BSP receive frame-synchronization input
BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source
LEGEND:
I = Input
O = Output
Z = High impedance
NOTE 1: ’LC56 devices only
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for Devices in the PZ Package (Continued)
SIGNAL TYPE DESCRIPTION
TDM SERIAL PORT INTERFACE
TDR I TDM serial receive-data input
TDX O/Z TDM serial transmit-data output. In high-impedance state when not transmitting
TCLKR I TDM serial receive-data clock input
TCLKX I/O/Z TDM serial transmit-data clock. Internal or external source
TFSR / TADD I/O/Z
TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/
input the address of the port
TFSX /TFRM I
TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
TFSX/TFRM becomes TFRM, the TDM frame sync.
EMULATION/JTAG INTERFACE
TDI I JTAG-test-port scan data input
TDO O/Z JTAG-test-port scan data output
TMS I JTAG-test-port mode select input
TCK I JTAG-port clock input
TRST I JTAG-port reset (with pull-down resistor). Disables JTAG when low
EMU0 I/O/Z Emulation control 0. Reserved for emulation use
EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL (SEE NOTE 2)
X1 O Oscillator output
X2/CLKIN I Clock/oscillator input (PLL clock input for ’C56)
CLKIN2 I Clock input (PLL clock input for ’C50, ’C51, ’C52, ’C53, ’C53S)
CLKMD1, CLKMD2,
CLKMD3
I Clock-mode select inputs
CLKOUT1 O/Z Device system-clock output
POWER SUPPLY CONNECTIONS
V
DDA
S Supply connection, address-bus output
V
DDD
S Supply connection, data-bus output
V
DDC
S Supply connection, control output
V
DDI
S Supply connection, internal logic
V
SSA
S Supply connection, address-bus output
V
SSD
S Supply connection, data-bus output
V
SSC
S Supply connection, control output
V
SSI
S Supply connection, internal logic
LEGEND:
I = Input
O = Output
S = Supply
Z = High impedance
NOTE 2: CLKIN2 pin is replaced by CLKMD3 pin on ’LC56 devices.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D8
V
DDD
V
SSD
V
SSD
D7
D6
D5
D4
D3
D2
D1
D0
TMS
V
DDD
V
DDD
TCK
V
SSD
V
SSD
INT1
INT2
INT3
INT4
NMI
DR
V
SSI
FSR
CLKR
V
DDA
V
SSA
A0
100
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
99
98
97 96 95
94 93 92
91 90 89
88 87
86 85 84
83 82
81
SSA
A2A3A4
A5A1A7A8A9
A6
DDI
TDI
CLKMD1
A11
A12
A13
A14
A10
A15
MP/MC
D10
D11
D12
D13D9D14
V
TRST
CLKX
HOLD
READY
BIO
RSVV
TOUT
V
V
D15
TMS320C52, TMS320LC52
PJ PACKAGE
(TOP VIEW)
DDA
SSI
SSI
SSI
SSC
SSI
EMU1/OFF
EMU0
V
DDC
V
DDC
V
DDI
V
DDI
CLKOUT1
XF
HOLDA
NC
DX
V
SSI
FSX
CLKMD2
V
SSI
V
SSI
TDO
V
DDC
X1
X2/CLKIN
CLKIN2
BR
STRB
R/W
PS
IS
DS
V
SSC
WE
RD
V
V
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NOTE: NC = No connect (These pins are reserved.)
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package
SIGNAL TYPE DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0)
D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0)
PS, DS, IS O/Z Program, data, and I/O space select outputs, respectively
STRB I/O/Z Timing strobe for external cycles and external DMA
R/W I/O/Z Read/write select for external cycles and external DMA
RD, WE O/Z Read and write strobes, respectively, for external cycles
READY I External bus ready/wait-state control input
BR I/O/Z Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
RS I Reset. Initializes device and sets PC to zero
MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM
HOLD I Puts parallel I/F bus in high-impedance state after current cycle
HOLDA O/Z Hold acknowledge. Indicates external bus in hold state
XF O/Z External flag output. Set/cleared through software
BIO I I/O branch input. Implements conditional branches
TOUT O/Z Timer output signal. Indicates output of internal timer
INT1–INT4 I External interrupt inputs
NMI I Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR I Serial receive-data input
DX O/Z Serial transmit-data output. In high-impedance state when not transmitting
CLKR I Serial receive-data clock input
CLKX I/O/Z Serial transmit-data clock. Internal or external source
FSR I Serial receive-frame-synchronization input
FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source
EMULATION/JTAG INTERFACE
TDI I JTAG-test-port scan data input
TDO O/Z JTAG-test-port scan data output
TMS I JTAG-test-port mode select input
TCK I JTAG-port clock input
TRST I JTAG-port reset (with pulldown resistor). Disables JTAG when low
EMU0 I/O/Z Emulation control 0. Reserved for emulation use
EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low
LEGEND:
I = Input
O = Output
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package (Continued)
SIGNAL TYPE DESCRIPTION
CLOCK GENERATION AND CONTROL
X1 O Oscillator output
X2/CLKIN I Clock/oscillator input
CLKIN2 I Clock input (PLL clock input for ’C52, ’LC52)
CLKMD1, CLKMD2 I Clock-mode select inputs
CLKOUT1 O/Z Device system-clock output
POWER SUPPLY CONNECTIONS
V
DDA
S Supply connection, address-bus output
V
DDD
S Supply connection, data-bus output
V
DDC
S Supply connection, control output
V
DDI
S Supply connection, internal logic
V
SSA
S Supply connection, address-bus output
V
SSD
S Supply connection, data-bus output
V
SSC
S Supply connection, control output
V
SSI
S Supply connection, internal logic
LEGEND:
I = Input
O = Output
S = Supply
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
15
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TMS320C57S, TMS320LC57S
PGE PACKAGE
(TOP VIEW)
TDO
WE
HD1
RD
HD0
HRDY
V
DDA
A15
NC
A14
A13
A12
NC
A11
A10
CLKMD1
V
SSA
V
SSA
TDI
HDS1
HDS2
V
DDI
V
DDI
A9
A8
A7
NC
A6
A5
A4
A3
NC
A2
A1
A0
V
SSA
HCS
HINT
EMU0
NC
EMU1/OFF
V
SSC
V
SSC
TOUT
BCLKX
CLKX
V
DDC
BFSR
BCLKR
RS
READY
HOLD
NC
BIO
V
DDC
V
DDC
IAQ
TRST
V
SSI
V
SSI
MP/MC
D15
D14
D13
NC
D12
D11
D10
D9
NC
D8
V
DDD
V
DDD
144
143
142
CLKOUT1
141XF140
139
BDX
138
137
136
BFSX
135
134
133
HD5
132
CLKMD2
131
130
129
128
127
126
125
X2/CLKIN
124
CLKMD3
123
122
HD3
121
STRB
120
119
PS
118
117
116
115
114
113
112
373839404142434445464748495051525354555657585960616263646566676869
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
D7
D6
D5
D3
D2
D1
HCNTL0
TMS
NMI
HR/W
INT2
INT3
INT4
DR
BDR
FSR
HAS
HCNTL1
111
NC
110
109
707172
NC
TCK
HD6
DX
V
SSI
HD4
V
DDC
DDD
V
CLKR
DDA
V
HBIL
SSD
V
D4
D0
INT1
NC
V
DDCVDDI
V
HOLDA
HD7
FSX
V
SSI
X1
BR
R/W
IS
DS
HD2
V
SSC
V
SSC
NC
NC
NC
SSD
V
DDI
SSD
V
DDD
V
SSD
V
DDA
V
NOTE: NC = No connect (These pins are reserved.)
NC
NC
ADVANCE INFORMATION
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package
SIGNAL TYPE DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0)
D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0)
PS, DS, IS O/Z Program, data, and I/O space select outputs, respectively
STRB I/O/Z Timing strobe for external cycles and external DMA
R/W I/O/Z Read/write select for external cycles and external DMA
RD, WE O/Z Read and write strobes, respectively, for external cycles
READY I External bus ready/wait-state control input
BR I/O/Z Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
RS I Reset. Initializes device and sets PC to zero
MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM
HOLD I Puts parallel I/F bus in high-impedance state after current cycle
HOLDA O/Z Hold acknowledge. Indicates external bus in hold state
XF O/Z External flag output. Set/cleared through software
BIO I I/O branch input. Implements conditional branches
TOUT O/Z Timer output signal. Indicates output of internal timer
IAQ O/Z Instruction acquisition signal
INT1–INT4 I External interrupt inputs
NMI I Nonmaskable external interrupt
SERIAL PORT INTERFACE (SPI)
DR I Serial receive-data input
DX O/Z Serial transmit-data output. In high-impedance state when not transmitting
CLKR I Serial receive-data clock input
CLKX I/O/Z Serial transmit-data clock. Internal or external source
FSR I Serial receive-frame-synchronization input
FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source
HOST PORT INTERFACE (HPI)
HCNTL0 I HPI mode control 1
HCNTL1 I HPI mode control 2
HINT O/Z Host interrupt
HDS1 I HPI data strobe 1
HDS2 I HPI data strobe 2
HR/W I HPI read/write strobe
HAS I HPI address strobe
HRDY O/Z HPI ready signal
HCS I HPI chip select
HBIL I HPI byte identification input
HD0–HD7 I/O/Z HPI data bus
LEGEND:
I = Input
O = Output
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package (Continued)
SIGNAL TYPE DESCRIPTION
BUFFERED SERIAL PORT
BDR I BSP receive data input
BDX O/Z BSP transmit data output; in high-impedance state when not transmitting
BCLKR I BSP receive-data clock input
BCLKX I/O/Z BSP transmit-data clock; internal or external source
BFSR I BSP receive frame-synchronization input
BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source
EMULATION/JTAG INTERFACE
TDI I JTAG-test-port scan data input
TDO O/Z JTAG-test-port scan data output
TMS I JTAG-test-port mode select input
TCK I JTAG-port clock input
TRST I JTAG-port reset (with pulldown resistor). Disables JTAG when low
EMU0 I/O/Z Emulation control 0. Reserved for emulation use
EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
X1 O Oscillator output
X2/CLKIN I PLL clock input
CLKMD1, CLKMD2,
CLKMD3
I Clock-mode select inputs
CLKOUT1 O/Z Device system-clock output
POWER SUPPLY CONNECTIONS
V
DDA
S Supply connection, address-bus output
V
DDD
S Supply connection, data-bus output
V
DDC
S Supply connection, control output
V
DDI
S Supply connection, internal logic
V
SSA
S Supply connection, address-bus output
V
SSD
S Supply connection, data-bus output
V
SSC
S Supply connection, control output
V
SSI
S Supply connection, internal logic
LEGEND:
I = Input
O = Output
S = Supply
Z = High impedance
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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architecture
The ’C5x’s advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memory bus structures, program and data, for full-speed execution. Instructions support data transfers between
the two spaces. This architecture permits coefficients stored in program memory to be read into the RAM,
eliminating the need for a separate coefficient ROM. The ’C5x architecture also makes available immediate
instructions and subroutines based on computed values. Increased throughput on the ’C5x for many DSP
applications is accomplished using single-cycle multiply/accumulate instructions with a data-move option, up
to eight auxiliary registers with a dedicated arithmetic unit, a parallel logic unit, and faster I/O necessary for
data-intensive signal processing. The architectural design emphasizes overall speed, communication, and
flexibility in processor configuration. Control signals and instructions provide floating-point support,
block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations
as shown in the functional block diagram.
Table 3 explains the symbols that are used in the functional block diagram.
Table 3. Symbols Used in Functional Block Diagram
SYMBOL DESCRIPTION SYMBOL DESCRIPTION
ABU Auto-buffering unit IFR Interrupt-flag register
ACCB Accumulator buffer IMR Interrupt-mask register
ACCH Accumulator high INDX Indirect-addressing-index register
ACCL Accumulator low IR Instruction register
ALU Arithmetic logic unit MCS Microcall stack
ARAU Auxiliary-register arithmetic unit MUX Multiplexer
ARB Auxiliary-register pointer buffer PAER Block-repeat-address end register
ARCR Auxiliary-register compare register PASR Block-repeat-address start register
ARP Auxiliary-register pointer PC Program counter
ARR Address-receive register (ABU) PFC Prefetch counter
AR0–AR7 Auxiliary registers PLU Parallel logic unit
AXR Address-transmit register (ABU) PMST Processor-mode-status register
BKR Receive-buffer-size register (ABU) PRD Timer-period register
BKX Transmit-buffer-size register (ABU) PREG Product register
BMAR Block-move-address register RPTC Repeat-counter register
BRCR Block-repeat-counter register SARAM Single-access RAM
BSP Buffered serial port SFL Left shifter
C Carry bit SFR Right shifter
CBER1 Circular buffer 1 end address SPC Serial-port interface-control register
CBER2 Circular buffer 2 end address ST0,ST1 Status registers
CBSR1 Circular buffer 1 start address TCSR TDM channel-select register
CBSR2 Circular buffer 2 start address TCR Timer-control register
DARAM Dual-access RAM TDM Time-division-multiplexed serial port
DBMR Dynamic bit manipulation register TDXR TDM data transmit register
DP Data memory page pointer TIM Timer-count register
DRR Serial-port data receive register TRAD TDM received-address register
DXR Serial-port data transmit register TRCV TDM data-receive register
GREG Global memory allocation register TREG0 Temporary register for multiplication
HPI Host port interface TREG1 Temporary register for dynamic shift count
HPIAH HPI-address register (high bytes) TREG2 Temporary register used as bit pointer in dynamic-bit test
HPIAL HPI-address register (low bytes) TRTA TDM receive-/transmit-address register
HPICH HPI-control register (high bytes) TSPC TDM serial-port-control register
HPICL HPI-control register (low bytes)
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
32
16
Data Bus
Program Bus
16
16
Shifter(0–7)
D15–D0
RBIT
A15–A0
16
16
16
16
DBMR(16)
MUX
16 16
32
ACCB(32)
32
ACCL(16)ACCH(16)C
32
ALU(32)
32
SFR(0–16)
32
MUX
MUX
SFL(0–16)
16
MUX
PREG(32)
Multiplier
TREG0(16)
MUX
16
16
16
MUX
B1 (512x16)
B2 (32x16)
DARAM
B0 (512x16)
DARAM
MUX
from IR
7 LSB
MUX
DP(9)
9
9
MUX
16
’C50 9K
’C51 1K
’C53 3K
’C56 6K
’C57 6K
SARAM
16
ARAU(16)
16
MUX
3
3
3
3
ARB(3)
ARP(3)
Program Bus
16
16
16
16
CBSR2(16)
CBSR1(16)
AR7(16)
AR6(16)
AR5(16)
AR3(16)
AR2(16)
AR1(16)
AR0(16)
ARCR(16)
INDX(16)
HDS(1–1)
HRDY
HAS
HR/W
HINT
HPI
HPICL
HD7
HD0
HBIL
HCNTL0
HCNTL1
HCSHPIAL
HPICH
HPIAH
TOUT
TCR
PRD
TIM
Timer
BDX
BCLKX
BDR
BCLKR
BFSR
DFSX
DXR
AXR(11)
BKX(11)
DRR
ARR(11)
BKR(11)
BSP
TDM
TCSR(8)
TRTA
TRAD(16)
TDR
TCLKX
TFRM
TADD
TCLKR
TRCV
TDXR
TSPC
TDX
CLKX2
FSX2
DX2
FSR2
CLKR2
DR2
SPC
DXR
DRR
Serial Port 2
CLKR
FSR
DR
FSX
CLKX
DX
DRR
DXR
SPC
Serial Port 1
16
16
TREG2(4)
TREG1(5)
BRCR(16)
GREG(16)
IFR(16)
IMR(16)
RPTC(16)
PMST(16)
ST1(16)
ST0(16)
BMAR(16)
IR(16)
16
16
16
16
16
PFC(16)
MCS(16)
Instruction
Address
32K’C57
32K’C56
16K’C53
4K’C52
8K’C51
2K’C50
ROMProgram
16
16
16
16
16
PASR(16)
Compare
PAER(16)
(8x16)
Stack
PC(16)
16
MUX
NMI
WE
RD
16
CLKIN2/CLKMD3
X2/CLKIN
CLKOUT1
X1
4
INT(1–4)
MP/MC
IACK
RS
HOLDA
HOLD
XF
BR
READY
STRB
RW
PS
DS
IS
CLKMD2
CLKMD1
Control
Data Bus
Program Bus
Data Bus
Data Bus
CBER2(16)
CBER1(16)
AR4(16)
16
BO
IAQ
†
†
†
†
MUXMUX
Data/Prog
Data/Prog
16
SFL (–6,0,1, 4)
PLU (16)
16
Data
32
16
16
16
16
16
16
32
32
16
†
Not available on all devices (see Table 1).
NOTES: A. Signals in shaded text are not available on
100-pin QFP packages.
B. Symbol descriptions appear in Table 3.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
32-bit ALU/accumulator
The 32-bit ALU and accumulator implement a wide range of arithmetic and logical functions, the majority of
which execute in a single cycle. The ALU is a general-purpose arithmetic/logic unit that operates on 16-bit words
taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions,
the ALU can perform Boolean operations, facilitating the bit manipulation ability required of a high-speed
controller. One input to the ALU always is supplied by the accumulator, and the other input can be furnished
from the product register (PREG) of the multiplier, the accumulator buf fer (ACCB), or the output of the scaling
shifter [which has been read from data memory or from the accumulator (ACC)]. After the ALU performs the
arithmetic or logical operation, the result is stored in the ACC where additional operations, such as shifting, can
be performed. Data input to the ALU can be scaled by the scaling shifter. The 32-bit ACC is split into two 16-bit
segments for storage in data memory . Shifters at the output of the ACC provide a left shift of 0 to 7 places. This
shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC remain
unchanged. When the postscaling shifter is used on the high word of the ACC (bits 31–16), the most significant
bits (MSBs) are lost and the least significant bits (LSBs) are filled with bits shifted in from the low word (bits
15–0). When the postscaling shifter is used on the low word, the LSBs are filled with zeros.
The ’C5x supports floating-point operations for applications requiring a large dynamic range. By performing left
shifts, the normalization instruction (NORM) is used to normalize fixed-point numbers contained in the ACC.
The four bits of the TREG1 define a variable shift through the scaling shifter for the ADDT/LACT/SUBT
instructions (add to/load to/subtract from ACC with shift specified by TREG1). These instructions are useful
in denormalizing a number (converting from floating point to fixed point). They are also useful for executing an
automatic gain control (AGC) going into a filter.
The single-cycle 1-bit to 16-bit right shift of the ACC efficiently aligns the ACC’s contents. This, coupled with
the 32-bit temporary buffer on the ACC, enhances the effectiveness of the ALU in extended-precision arithmetic.
The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB also can be used as an
input to the ALU. The minimum or maximum value in a string of numbers is found by comparing the contents
of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and,
if the condition is met, the carry bit (C) is set to 1. The minimum and maximum functions are executed by the
CRLT and CRGT instructions, respectively.
scaling shifters
The ’C5x provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output
connected to the ALU. This scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count
is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output
are filled with zeros; the MSBs may be either filled with zeros or sign extended, depending upon the value of
the sign-extension mode (SXM) bit of status register ST1.
The ’C5x also contains several other shifters that allow it to perform numerical scaling, bit extraction,
extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the
product register and the ACC.
parallel logic unit
The parallel logic unit (PLU) is a second logic unit, additional to the main ALU, that executes logic operations
on data without affecting the contents of the ACC. The PLU provides the bit-manipulation ability required of a
high-speed controller and simplifies control/status register operations. The PLU provides a direct logic
operation path to data memory space and can set, clear, test, or toggle multiple bits directly in a data memory
location, a control/status register, or any register that is mapped into data memory space.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
16 × 16-bit parallel multiplier
The ’C5x uses a 16 × 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit
product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction,
perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number.
There are two registers associated with the multiplier: TREG0, a 16-bit temporary register that holds one of the
operands for the multiplier, and PREG, the 32-bit product register that holds the product. Four product shift
modes (PM) are available at the PREG’s output. These shift modes are useful for performing
multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field
of status register ST1 specifies the PM shift mode.
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A 4-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can, instead, be right-shifted 6 bits to enable the execution of up
to 128 consecutive multiply/accumulates without the possibility of overflow.
The load-TREG0 (L T) instruction normally loads TREG0 to provide one operand (from the data bus), and the
MPY instruction provides the second operand (also from the data bus). A multiplication also can be performed
with a short or long immediate operand by using the MPY instruction with an immediate operand. A product is
obtained every two cycles except when a long immediate operand is used.
Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS as defined in Table 7) fully utilize the
computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data
for these operations is transferred to the multiplier during each cycle through the program and data buses. This
facilitates single-cycle multiply/accumulates when used with repeat ( RPT and RPTZ ) instructions. In these
instructions, the coefficient addresses are generated by the PC, while the data addresses are generated by the
ARAU. This allows the repeated instruction to access the values sequentially from the coefficient table and step
through the data in any of the indirect addressing modes. The RPTZ instruction also clears the accumulator and
the product register to initialize the multiply/accumulate operation.
The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so
that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample
and to eliminate the oldest sample. Circular addressing with MAC and MADS instructions also can be used to
support filter implementation.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The ’C5x provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are used
for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing
allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These
registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through
7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data
memory , the ACC, the product register , or by an immediate operand defined in the instruction. The contents of
these registers can be stored in data memory or used as inputs to the central arithmetic logic unit (CALU). These
registers are accessible as memory-mapped locations within the ’C5x data-memory space.
The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing can
be performed either by ±1 or by the contents of the INDX register. As a result, accessing tables of information
does not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory
The ’C5x implements three separate address spaces for program memory , data memory , and I/O. Each space
accommodates a total of 64K 16-bit words (see Figures 1 through 7). Within the 64K words of data space, the
256 to 32K words at the top of the address range can be defined to be external global memory in increments
of powers of two, as specified by the contents of the global memory allocation register (GREG). Access to global
memory is arbitrated using the global memory bus request (BR
) signal.
The ’C5x devices include a considerable amount of on-chip memory to aid in system performance and
integration including ROM, single-access RAM (SARAM), and dual-access RAM (DARAM). The amount and
types of memory available on each device are shown in Table 1.
On the ’C5x, the first 96 (0 – 5Fh) data-memory locations are allocated for memory-mapped registers. This
memory-mapped register space contains various control and status registers including those for the CPU, serial
port, timer, and software wait-state generators. Additionally, the first 16 I/O port locations are mapped into this
data-memory space, allowing them to be accessed either as data memory using single-word instructions or as
I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space.
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state
of the MP/MC
control input upon resetting the device or by manipulating the MP/MC bit in the PMST status
register after reset. The ROM occupies the lowest block of program memory when enabled. When disabled,
these addresses are located in the device’s external program-memory space.
The ’C5x also has a mask-programmable option that provides security protection for the contents of on-chip
ROM. When this internal option bit is programmed, no externally-originating instruction can access the on-chip
ROM. This feature can be used to provide security for proprietary algorithms.
An optional boot loader is available in the device’s on-chip ROM. This boot loader can be used to transfer a
program automatically from data memory or the serial port to anywhere in program memory . In data memory,
the program can be located on any 1K-word boundary and can be in either byte-wide or 16-bit word format. Once
the code is transferred, the boot loader releases control to the program for execution.
The ’C5x devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).
The single-access RAM requires a full machine cycle to perform a read or a write; however, this is not one large
RAM block in which only one access per cycle is allowed. It is made up of 2K-word size-independent RAM blocks
and each one allows one CPU access per cycle. The CPU can read or write one block while accessing another
block at the same time. All ’C5x processors support multiple accesses to its SARAM in one cycle as long as they
go to different RAM blocks. If the total SARAM size is not a multiple of two, one block is made smaller than 2K
words. With an understanding of this structure, programmers can arrange code and data appropriately to
improve code performance. Table 4 shows the sizes of available SARAM on the applicable ’C5x devices.
T able 4. SARAM Block Sizes
DEVICE NUMBER OF SARAM BLOCKS
’C50/’LC50 Four 2K blocks and one 1K block
’C51/’LC51 One 1K block
’C53/’C53S /’LC53 One 2K block and one 1K block
’LC56 Three 2K blocks
’C57S/’LC57/’LC57S Three 2K blocks
memory (continued)
The ’C5x dual-access RAM (DARAM) allows writes to, and reads from, the RAM in the same cycle without the
address restrictions of the SARAM. The dual-access RAM is configured in three blocks: block 0 (B0), block 1
(B1), and block 2 (B2). Block 1 is 512 words in data memory and block 2 is 32 words in data memory . Block 0
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
is a 512-word block which can be configured as data or program memory . The CLRC CNF (configure B0 as data
memory) and SETC CNF (configure B0 as program memory) instructions allow dynamic configuration of the
memory maps through software. When using block 0 as program memory , instructions can be downloaded from
external program memory into on-chip RAM and then executed.
When using on-chip RAM, ROM, or high-speed external memory , the ’C5x runs at full speed with no wait states.
The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature
of the ’C5x architecture, enables the device to perform three concurrent memory accesses in any given machine
cycle. Externally , the READY line can be used to interface the ’C5x to slower , less expensive external memory .
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
Program
Hex
Interrupts and
Reserved
(external)
Data
External
Interrupts and
Reserved
(on-chip)
On-Chip
ROM
External
Program
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
External
MP/MC
= 0
(microcomputer mode)
MP/MC = 1
(microprocessor mode)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
0000
003F
0040
07FF
0800
2BFF
2C00
FDFF
FE00
FFFF
0000
003F
0040
07FF
0800
2BFF
2C00
FDFF
FE00
FFFF
0000
005F
0060
007F
0080
0100
02FF
2C00
FFFF
00FF
0300
04FF
0500
07FF
0800
2BFF
Memory-Mapped
Registers
On-Chip
DARAM B2
Reserved
On-Chip
DARAM B1
Reserved
On-Chip SARAM
(OVLY = 1)
External (OVLY = 0)
External
On-Chip DARAM B0
(CNF = 0)
Reserved (CNF = 1)
Hex Hex
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
Figure 1. TMS320C50 and TMS320LC50 Memory Map
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Interrupts and
Reserved
(on-chip)
Interrupts and
Reserved
(external)
Memory-Mapped
Registers
On-Chip
DARAM B2
Reserved
On-Chip
DARAM B1
Reserved
On-Chip SARAM
(OVLY = 1)
External (OVLY = 0)
External
Data
External
Program
On-Chip
ROM
External
Program
External
MP/MC
= 0
(microcomputer mode)
MP/MC = 1
(microprocessor mode)
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
0000
003F
0040
1FFF
2000
23FF
2400
FDFF
FE00
FFFF
0000
003F
0040
1FFF
2000
23FF
2400
FDFF
FE00
FFFF
0000
005F
0060
007F
0080
0100
02FF
0C00
FFFF
00FF
0300
04FF
0500
07FF
0800
0BFF
Hex Hex Hex
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
Figure 2. TMS320C51 and TMS320LC51 Memory Map
Program
Hex
Interrupts and
Reserved
(external)
Data
Interrupts and
Reserved
(on-chip)
On-Chip
ROM
External
Program
External
MP/MC
= 0
(microcomputer mode)
MP/MC = 1
(microprocessor mode)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
0000
003F
0040
FDFF
FE00
FFFF
0000
003F
0040
0FFF
1000
FDFF
FE00
FFFF
0000
005F
0060
007F
0080
0100
02FF
FFFF
00FF
0300
04FF
0500
07FF
0800
Memory-Mapped
Registers
On-Chip
DARAM B2
Reserved
On-Chip
DARAM B1
Reserved
External
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
Hex Hex
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
Figure 3. TMS320C52 and TMS320LC52 Memory Map
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Interrupts and
Reserved
(external)
Memory-Mapped
Registers
On-Chip
DARAM B2
Reserved
On-Chip
DARAM B1
Reserved
External
Data
External
Program
Interrupts and
Reserved
(on-chip)
On-Chip
ROM
External
Program
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
External
MP/MC
= 0
(microcomputer mode)
MP/MC = 1
(microprocessor mode)
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
0000
003F
0040
3FFF
4000
4BFF
4C00
FDFF
FE00
FFFF
0000
005F
0060
007F
0080
0100
02FF
1400
FFFF
0000
003F
0040
3FFF
4000
FDFF
FE00
FFFF
00FF
0300
04FF
0500
07FF
0800
On-Chip SARAM
(OVLY = 1)
External (OVLY = 0)
13FF
Hex Hex Hex
4BFF
4C00
On-Chip SARAM
(RAM = 1)
External
(RAM = 0)
Figure 4. TMS320C53, TMS320C53S, TMS320LC53, and TMS320LC53S Memory Map
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Data
1800
FFFF
2000
1FFF
17FF
1000
0FFF
0800
07FF
0500
04FF
0300
02FF
0100
00FF
0080
007F
0060
005F
0000
Reserved
Reserved (CNF = 1)
On-Chip DARAM B1
(OVLY = 1)
External (OVLY = 0)
External (OVLY = 0)
(OVLY = 1)
External
External (OVLY = 0)
On-Chip DARAM B0 (CNF = 0)
On-Chip SARAM Blk0
BSP Block (OVLY = 1)
On-Chip SARAM Blk1
On-Chip SARAM Blk2
Reserved
On-Chip DARAM B2
Registers
Memory-Mapped
Hex
On-Chip ROM
0000
7FFF
8000
(RAM = 1)
(RAM = 1)
87FF
8800
External (RAM = 0)
External (RAM = 0)
(RAM = 1)
9000
97FF
9800
External (RAM = 0)
8FFF
External
(CNF = 1)
MP/MC
= 0
FDFF
FE00
FFFF
On-Chip DARAM B0
External (CNF = 0)
On-Chip SARAM Blk1
On-Chip SARAM Blk2
On-Chip SARAM Blk0
MP/MC = 1
External (CNF = 0)
(CNF = 1)
On-Chip DARAM B0
External
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk2
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk1
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk0
External
FFFF
FE00
FDFF
9800
97FF
9000
8FFF
8800
87FF
8000
7FFF
0000
Program Program
Hex Hex
Interrupts and Reserved
(on-chip)
Interrupts and Reservrd
(external)
0040
003F
0040
003F
Figure 5. TMS320LC56 Memory Map
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
On-Chip ROM
0000
7FFF
8000
(RAM = 1)
(RAM = 1)
87FF
8800
External (RAM = 0)
External (RAM = 0)
(RAM = 1)
9000
97FF
9800
External (RAM = 0)
8FFF
External
(CNF = 1)
MP/MC
= 0
FDFF
FE00
FFFF
On-Chip DARAM B0
External (CNF = 0)
On-Chip SARAM Blk1
On-Chip SARAM Blk2
On-Chip SARAM Blk0
MP/MC = 1
External (CNF = 0)
(CNF = 1)
On-Chip DARAM B0
External
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk2
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk1
External (RAM = 0)
(RAM = 1)
On-Chip SARAM Blk0
External
FFFF
FE00
FDFF
9800
97FF
9000
8FFF
8800
87FF
8000
7FFF
0000
Program Program
Hex Hex
Data
Memory-Mapped
Registers
Reserved
0000
0060
0080
005F
007F
0100
0300
00FF
02FF
On-Chip DARAM B2
Reserved (CNF = 1)
On-Chip DARAM (CNF = 0)
Reserved
0500
0800
04FF
07FF
1000
0FFF
External (OVLY = 0)
HPI Block (OVLY = 1)
(OVLY = 1)
1800
17FF
2000
1FFF
External (OVLY = 0)
External (OVLY = 0)
External
FFFF
On-Chip SARAM Blk2
On-Chip SARAM Blk1
On-Chip SARAM Blk0
BSP Block (OVLY = 1)
On-Chip DARAM B1
Hex
HPI Control Register
0501
Interrupts and Reserved
(on-chip)
Interrupts and Reservrd
(external)
0040
003F
0040
003F
Figure 6. TMS320LC57 Memory Map
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