Texas Instruments TMX320C44PDB50, TMS320C44PDB60, TMS320C44PDB50, TMS320C44GFWA, TMS320C44GFW60 Datasheet
...
PDB PACKAGE
(TOP VIEW)
‡
‡
See Pin Assignments table and Pin Functions table for location
and description of all pins.
76
1
304
77 152
153
228
229
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Highest Performance Floating-Point Digital
Signal Processor (DSP)
– TMS320C44-60:
33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 336M Bytes/s
– TMS320C44-50:
40-ns Instruction Cycle Time
D
Four Communication Ports
D
Six-Channel Direct Memory Address (DMA)
Coprocessor
D
Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format
D
Single Cycle, 1/x, 1/√x
D
Source-Code Compatible With ’320C3x and
’320C4x
D
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
D
Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers,
and Two Timers
D
IEEE-1149.1† (JTAG) Boundary-Scan
Compatible
D
Two Identical External Data and Address
Buses Supporting Shared Memory
Systems and High Data-Rate,
Single-Cycle Transfers
– High Port-Data Rate of 120M Bytes/s
(TMS320C44-60) (Each Bus)
– 128M-Byte Program/Data/Peripheral
Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-Bus, Data-Bus, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
D
304-Pin Plastic Quad Flatpack
(PDB Suffix)
D
Fabricated Using 0.72-µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
D
Separate Internal Program-, Data-, and
DMA-Coprocessor Buses for Support of
Massive Concurrent I/O of Program and
Data, Thereby Maximizing Sustained CPU
Performance
D
IDLE2 Clock-Stop Power-Down Mode
D
Communication-Port-Direction Pin
D
On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Boot Loader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports
D
Software-Communication-Port Reset
D
NMI With Bus-Grant Feature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
†
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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block diagram
32 32
32 32 32 32 32 32
D31–D0
A23–A0
DE
AE
STAT3 – STAT0
LOCK
STRB0, STRB1
R/W0, R/W1
PAGE0, PAGE1
RDY0
, RDY1
CE0, CE1
IR
PC
X1
X2/CLKIN
ROMEN
RESET
RESETLOC0,
RESETLOC1
NMI
IIOF(3–0)
IACK
H1
H3
CV
SS
DV
DD
DV
SS
IV
SS
DV
DD
DV
DD
V
DDL
V
SSL
V
SUBS
32 3232 32
40 404040
32-Bit Barrel
Shifter
40
40
ALU
Extended
Precision
Registers
(R0–R11)
40
40
32
40
40
ARAU0 ARAU1
BK
Auxiliary
Registers
(AR0–AR7)
Other
Registers
(14)
CPU1
CPU2
32
32
32
32
32
32
32
32
32
32
REG1
32
R
E
G
1
Multiplier
Continued on next page
REG2
REG 1
Controller
PDATA Bus
DMADATA Bus
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
PADDR Bus
DMAADDR Bus
DISP, IR0, IR1
CPU1
REG2
Cache
(512 bytes)
RAM Block 0
(4K bytes)
RAM Block 1
(4K bytes)
ROM Block
(reserved)
MUX
MUX
REG1
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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block diagram (continued)
LD31– LD0
LA23–LA0
LDE
LAE
LSTAT3– LSTAT0
LLOCK
LSTRB0, LSTRB1
LR/W0, LR/W1
LPAGE0, LPAGE1
LRDY0
, LRDY1
LCE0, LCE1
DMA Channel 1
DMA Channel 2
DMA Channel 4
DMA Channel 5
DMA Coprocessor
Six DMA Channels
3232
Global
Local
Port Control
Global-Control Register
Time-Period Register
Timer 1
Timer-Counter Register
TCLK1
Global-Control Register
Time-Period Register
Timer 0
Timer-Counter Register
TCLK0
Port-Control Registers
Output
FIFO
Input
FIFO
PAU
COM Port 1
CREQ1
CACK1
CSTRB1
CRDY1
C1D7–C1D0
Continued from previous page
Port-Control Registers
Output
FIFO
Input
FIFO
PAU
COM Port 5
CREQ5
CACK5
CSTRB5
CRDY5
C5D7–C5D0
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
PADDR Bus
PDATA Bus
COM Port 2
COM Port 4
Four
Communication
Ports
†
DMADATA Bus
DMAADDR Bus
MUX
MUX
Peripheral Data Bus
Peripheral Address Bus
DMA Channel 0
DMA Channel 3
CDIR1
CDIR5
†
Communication ports 0 and 3 are not connected.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
4
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functions
This section lists signal descriptions for the ’320C44 device: each signal, number of pins, operating mode(s)
(that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. The signals
are grouped according to function.
Pin Functions
SIGNAL NAME
NO. OF
PINS
TYPE
†
DESCRIPTION
GLOBAL-BUS EXTERNAL INTERFACE (73 pins)
D31–D0 32 I/O/Z 32-bit data port of the global-bus external interface
DE 1 I Data-bus-enable signal for the global-bus external interface
A23–A0 24 O/Z 24-bit address port of the global-bus external interface
AE 1 I Address-bus-enable signal for the global-bus external interface
STAT3–STAT0 4 O Status signals for the global-bus external interface
LOCK 1 O Lock signal for the global-bus external interface
STRB0
‡
1 O/Z Access strobe 0 for the global-bus external interface
R/W0
‡
1 O/Z Read/write signal for STRB0 accesses
PAGE0
‡
1 O/Z Page signal for STRB0 accesses
RDY0
‡
1 I Ready signal for STRB0 accesses
CE0
‡
1 I Control enable for the STRB0, PAGE0, and R/W0 signals
STRB1
‡
1 O/Z Access strobe 1 for the global-bus external interface
R/W1
‡
1 O/Z Read/write signal for STRB1 accesses
PAGE1
‡
1 O/Z Page signal for STRB1 accesses
RDY1
‡
1 I Ready signal for STRB1 accesses
CE1
‡
1 I Control enable for the STRB1, PAGE1, and R/W1 signals
LOCAL-BUS EXTERNAL INTERFACE (73 pins)
LD31–LD0 32 I/O/Z 32-bit data port of the local-bus external interface
LDE 1 I Data-bus-enable signal for the local-bus external interface
LA23–LA0 24 O/Z 24-bit address port of the local-bus external interface
LAE 1 I Address-bus-enable signal for the local-bus external interface
LSTAT3–LSTAT0 4 O Status signals for the local-bus external interface
LLOCK 1 O Lock signal for the local-bus external interface
LSTRB0
‡
1 O/Z Access strobe 0 for the local-bus external interface
LR/W0 1 O/Z Read/write signal for LSTRB0 accesses
LPAGE0 1 O/Z Page signal for LSTRB0 accesses
LRDY0 1 I Ready signal for LSTRB0 accesses
LCE0 1 I Control enable for the LSTRB0, LPAGE0, and LR/ W0 signals
LSTRB1
‡
1 O/Z Access strobe 1 for the local-bus external interface
LR/W1 1 O/Z Read/write signal for LSTRB1 accesses
LPAGE1 1 O/Z Page signal for LSTRB1 accesses
LRDY1 1 I Ready signal for LSTRB1 accesses
LCE1 1 I Control enable for the LSTRB1, LPAGE1, and LR/W1 signals
†
I = input, O = output, Z = high impedance
‡
The effective address range is defined by the local/global STRB
ACTIVE bits in the memory interface-control registers.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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Pin Functions (Continued)
SIGNAL NAME
NO. OF
PINS
TYPE
†
DESCRIPTION
COMMUNICATION PORT 1 INTERFACE (13 pins)
C1D7–C1D0 8 I/O Communication port 1 data bus
CREQ1 1 I/O Communication port 1 token-request signal
CACK1 1 I/O Communication port 1 token-request-acknowledge signal
CSTRB1 1 I/O Communication port 1 data-strobe signal
CRDY1 1 I/O Communication port 1 data-ready signal
CDIR1 1 O Communication port 1 direction signal
COMMUNICATION PORT 2 INTERFACE (13 pins)
C2D7–C2D0 8 I/O Communication port 2 data bus
CREQ2 1 I/O Communication port 2 token-request signal
CACK2 1 I/O Communication port 2 token-request-acknowledge signal
CSTRB2 1 I/O Communication port 2 data-strobe signal
CRDY2 1 I/O Communication port 2 data-ready signal
CDIR2 1 O Communication port 2 direction signal
COMMUNICATION PORT 4 INTERFACE (13 pins)
C4D7–C4D0 8 I/O Communication port 4 data bus
CREQ4 1 I/O Communication port 4 token-request signal
CACK4 1 I/O Communication port 4 token-request-acknowledge signal
CSTRB4 1 I/O Communication port 4 data-strobe signal
CRDY4 1 I/O Communication port 4 data-ready signal
CDIR4 1 O Communication port 4 direction signal
COMMUNICATION PORT 5 INTERFACE (13 pins)
C5D7–C5D0 8 I/O Communication port 5 data bus
CREQ5 1 I/O Communication port 5 token-request signal
CACK5 1 I/O Communication port 5 token-request-acknowledge signal
CSTRB5 1 I/O Communication port 5 data-strobe signal
CRDY5 1 I/O Communication port 5 data-ready signal
CDIR5 1 O Communication port 5 direction signal
INTERRUPTS, I/O FLAGS, RESET, TIMER (12 pins)
IIOF3–IIOF0 4 I/O Interrupt and I/O flags
NMI 1 I Nonmaskable interrupt. NMI is sensitive to a low-going edge.
IACK 1 O Interrupt acknowledge
RESET 1 I Reset signal
RESETLOC1
RESETLOC0
2 I Reset-vector location
ROMEN 1 I On-chip ROM enable (0 = disable, 1 = enable)
TCLK0 1 I/O Timer 0
TCLK1 1 I/O Timer 1
†
I = input, O = output, Z = high impedance
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Functions (Continued)
SIGNAL NAME
NO. OF
PINS
TYPE
†
DESCRIPTION
CLOCK (4 pins)
X1 1 O Crystal
X2 / CLKIN 1 I Crystal/oscillator
H1 1 O H1 clock
H3 1 O H3 clock
POWER (71 pins)
CV
SS
17 I Ground
DV
SS
17 I Ground
IV
SS
6 I Ground
DV
DD
22 I 5-VDC supply
VSUBS 1 I Substrate (tie to ground)
V
DDL
4 I 5-VDC supply
V
SSL
4 I Ground
EMULATION (7 pins)
TCK 1 I IEEE 1149.1 test port clock
TDI 1 I IEEE 1149.1 test port data in
TDO 1 O/Z IEEE 1149.1 test port data out
TMS 1 I IEEE 1149.1 test port mode select
TRST 1 I IEEE 1149.1 test port reset
EMU0 1 I/O Emulation pin 0
EMU1 1 I/O Emulation pin 1
†
I = input, O = output, Z = high impedance
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
7
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PDB Package Pin Assignments — Alphabetical Listing
PIN PIN PIN PIN
NAME NO. NAME NO. NAME NO. NAME NO.
A0 149 C2D7 34 CV
SS
134 D24 137
A1 150 C4D0 87 CV
SS
117 D25 138
A2 151 C4D1 88 CV
SS
102 D26 140
A3 152 C4D2 90 CV
SS
78 D27 141
A4 154 C4D3 92 CV
SS
62 D28 142
A5 155 C4D4 94 CV
SS
44 D29 143
A6 156 C4D5 97 CV
SS
25 D30 144
A7 157 C4D6 99 CV
SS
7 D31 145
A8 158 C4D7 100 CV
SS
282 DE 89
A9 159 C5D0 37 CV
SS
262 DV
DD
139
A10 160 C5D1 39 CV
SS
247 DV
DD
124
A11 162 C5D2 41 CV
SS
230 DV
DD
109
A12 165 C5D3 42 CV
SS
218 DV
DD
96
A13 166 C5D4 45 CV
SS
202 DV
DD
83
A14 167 C5D5 46 CV
SS
182 DV
DD
67
A15 168 C5D6 47 CV
SS
164 DV
DD
51
A16 169 C5D7 48 D0 104 DV
DD
40
A17 170 CACK1 13 D1 105 DV
DD
28
A18 171 CACK2 21 D2 106 DV
DD
17
A19 174 CACK4 73 D3 107 DV
DD
302
A20 175 CACK5 50 D4 108 DV
DD
288
A21 176 CDIR1 19 D5 110 DV
DD
272
A22 177 CDIR2 18 D6 111 DV
DD
256
A23 178 CDIR4 16 D7 112 DV
DD
244
AE 57 CDIR5 15 D8 113 DV
DD
236
C1D0 269 CE0 93 D9 114 DV
DD
223
C1D1 271 CE1 101 D10 115 DV
DD
207
C1D2 274 CRDY1 8 D11 118 DV
DD
188
C1D3 276 CRDY2 23 D12 120 DV
DD
172
C1D4 278 CRDY4 85 D13 122 DV
DD
161
C1D5 280 CRDY5 53 D14 123 DV
DD
153
C1D6 283 CREQ1 11 D15 125 DV
SS
147
C1D7 286 CREQ2 20 D16 127 DV
SS
133
C2D0 26 CREQ4 71 D17 128 DV
SS
116
C2D1 27 CREQ5 49 D18 129 DV
SS
103
C2D2 29 CSTRB1 14 D19 130 DV
SS
79
C2D3 30 CSTRB2 22 D20 131 DV
SS
63
C2D4 31 CSTRB4 84 D21 132 DV
SS
43
C2D5 32 CSTRB5 52 D22 135 DV
SS
24
C2D6 33 CV
SS
148 D23 136 DV
SS
6
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PDB Package Pin Assignments — Alphabetical Listing (Continued)
PIN PIN PIN PIN
NAME NO. NAME NO. NAME NO. NAME NO.
DV
SS
281 LA17 253 LD30 228 STAT0 68
DV
SS
261 LA18 254 LD31 229 STAT1 66
DV
SS
246 LA19 255 LDE 291 STAT2 64
DV
SS
231 LA20 257 LLOCK 284 STAT3 61
DV
SS
217 LA21 258 LOCK 95 STRB0 58
DV
SS
201 LA22 259 LPAGE0 299 STRB1 69
DV
SS
179 LA23 260 LPAGE1 294 TCK 86
DV
SS
163 LAE 287 LRDY0 298 TCLK0 290
EMU0 75 LCE0 297 LRDY1 293 TCLK1 289
EMU1 74 LCE1 292 LR/W0 300 TDI 76
H1 266 LD0 183 LR/W1 295 TDO 80
H3 268 LD1 184 LSTAT0 279 TMS 82
IACK 270 LD2 185 LSTAT1 277 TRST 81
IIOF0 10 LD3 186 LSTAT2 275 V
DDL
38
IIOF1 9 LD4 187 LSTAT3 273 V
DDL
121
IIOF2 5 LD5 192 LSTRB0 301 V
DDL
191
IIOF3 4 LD6 194 LSTRB1 296 V
DDL
267
IV
SS
126 LD7 195 NC 1 V
SSL
36
IV
SS
65 LD8 196 NC 77 V
SSL
119
IV
SS
35 LD9 197 NC 173 V
SSL
193
IV
SS
2 LD10 200 NC 180 V
SSL
265
IV
SS
285 LD11 203 NC 181 VSUBS 146
IV
SS
209 LD12 204 NC 189 X1 264
LA0 232 LD13 205 NC 190 X2/CLKIN 263
LA1 233 LD14 206 NC 198
LA2 234 LD15 208 NC 199
LA3 235 LD16 210 NC 214
LA4 237 LD17 211 NC 303
LA5 238 LD18 212 NC 304
LA6 239 LD19 213 NMI 3
LA7 240 LD20 215 PAGE0 60
LA8 241 LD21 216 PAGE1 72
LA9 242 LD22 219 RDY0 91
LA10 243 LD23 220 RDY1 98
LA11 245 LD24 221 RESET 54
LA12 248 LD25 222 RESETLOC0 55
LA13 249 LD26 224 RESETLOC1 56
LA14 250 LD27 225 ROMEN 12
LA15 251 LD28 226 R/W0 59
LA16 252 LD29 227 R/W1 70
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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PDB Package Pin Assignments — Numerical Listing
PIN PIN PIN PIN
NO. NAME NO. NAME NO. NAME NO. NAME
1 NC 41 C5D2 81 TRST 121 V
DDL
2 IV
SS
42 C5D3 82 TMS 122 D13
3 NMI 43 DV
SS
83 DV
DD
123 D14
4 IIOF3 44 CV
SS
84 CSTRB4 124 DV
DD
5 IIOF2 45 C5D4 85 CRDY4 125 D15
6 DV
SS
46 C5D5 86 TCK 126 IV
SS
7 CV
SS
47 C5D6 87 C4D0 127 D16
8 CRDY1 48 C5D7 88 C4D1 128 D17
9 IIOF1 49 CREQ5 89 DE 129 D18
10 IIOF0 50 CACK5 90 C4D2 130 D19
11 CREQ1 51 DV
DD
91 RDY0 131 D20
12 ROMEN 52 CSTRB5 92 C4D3 132 D21
13 CACK1 53 CRDY5 93 CE0 133 DV
SS
14 CSTRB1 54 RESET 94 C4D4 134 CV
SS
15 CDIR5 55 RESETLOC0 95 LOCK 135 D22
16 CDIR4 56 RESETLOC1 96 DV
DD
136 D23
17 DV
DD
57 AE 97 C4D5 137 D24
18 CDIR2 58 STRB0 98 RDY1 138 D25
19 CDIR1 59 R/W0 99 C4D6 139 DV
DD
20 CREQ2 60 PAGE0 100 C4D7 140 D26
21 CACK2 61 STAT3 101 CE1 141 D27
22 CSTRB2 62 CV
SS
102 CV
SS
142 D28
23 CRDY2 63 DV
SS
103 DV
SS
143 D29
24 DV
SS
64 STAT2 104 D0 144 D30
25 CV
SS
65 IV
SS
105 D1 145 D31
26 C2D0 66 STAT1 106 D2 146 VSUBS
27 C2D1 67 DV
DD
107 D3 147 DV
SS
28 DV
DD
68 STAT0 108 D4 148 CV
SS
29 C2D2 69 STRB1 109 DV
DD
149 A0
30 C2D3 70 R/W1 110 D5 150 A1
31 C2D4 71 CREQ4 111 D6 151 A2
32 C2D5 72 PAGE1 112 D7 152 A3
33 C2D6 73 CACK4 113 D8 153 DV
DD
34 C2D7 74 EMU1 114 D9 154 A4
35 IV
SS
75 EMU0 115 D10 155 A5
36 V
SSL
76 TDI 116 DV
SS
156 A6
37 C5D0 77 NC 117 CV
SS
157 A7
38 V
DDL
78 CV
SS
118 D11 158 A8
39 C5D1 79 DV
SS
119 V
SSL
159 A9
40 DV
DD
80 TDO 120 D12 160 A10
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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PDB Package Pin Assignments — Numerical Listing (Continued)
PIN PIN PIN PIN
NO. NAME NO. NAME NO. NAME NO. NAME
161 DV
DD
201 DV
SS
241 LA8 281 DV
SS
162 A11 202 CV
SS
242 LA9 282 CV
SS
163 DV
SS
203 LD11 243 LA10 283 C1D6
164 CV
SS
204 LD12 244 DV
DD
284 LLOCK
165 A12 205 LD13 245 LA11 285 IV
SS
166 A13 206 LD14 246 DV
SS
286 C1D7
167 A14 207 DV
DD
247 CV
SS
287 LAE
168 A15 208 LD15 248 LA12 288 DV
DD
169 A16 209 IV
SS
249 LA13 289 TCLK1
170 A17 210 LD16 250 LA14 290 TCLK0
171 A18 211 LD17 251 LA15 291 LDE
172 DV
DD
212 LD18 252 LA16 292 LCE1
173 NC 213 LD19 253 LA17 293 LRDY1
174 A19 214 NC 254 LA18 294 LPAGE1
175 A20 215 LD20 255 LA19 295 LR / W1
176 A21 216 LD21 256 DV
DD
296 LSTRB1
177 A22 217 DV
SS
257 LA20 297 LCE0
178 A23 218 CV
SS
258 LA21 298 LRDY0
179 DV
SS
219 LD22 259 LA22 299 LPAGE0
180 NC 220 LD23 260 LA23 300 LR / W0
181 NC 221 LD24 261 DV
SS
301 LSTRB0
182 CV
SS
222 LD25 262 CV
SS
302 DV
DD
183 LD0 223 DV
DD
263 X2 / CLKIN 303 NC
184 LD1 224 LD26 264 X1 304 NC
185 LD2 225 LD27 265 V
SSL
186 LD3 226 LD28 266 H1
187 LD4 227 LD29 267 V
DDL
188 DV
DD
228 LD30 268 H3
189 NC 229 LD31 269 C1D0
190 NC 230 CV
SS
270 IACK
191 V
DDL
231 DV
SS
271 C1D1
192 LD5 232 LA0 272 DV
DD
193 V
SSL
233 LA1 273 LSTAT3
194 LD6 234 LA2 274 C1D2
195 LD7 235 LA3 275 LSTAT2
196 LD8 236 DV
DD
276 C1D3
197 LD9 237 LA4 277 LSTAT1
198 NC 238 LA5 278 C1D4
199 NC 239 LA6 279 LSTAT0
200 LD10 240 LA7 280 C1D5
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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memory map
Figure 1 shows the memory map for the ’320C44. Refer to the
TMS320C4x User’s Guide
(literature number
SPRU063B) for a detailed description of this memory mapping.
1 M
1 M
1 M
13 M
2 G–16 M
2 G–16 M
000000000h
000000FFFh
000001000h
0000FFFFFh
000100000h
0001000FFh
000100100h
0001FFFFFh
000200000h
0002FF7FFh
0002FF800h
0002FFBFFh
0002FFC00h
0002FFFFFh
000300000h
000FFFFFFh
01000000h
7FFFFFFFh
80000000h
80FFFFFh
81000000
FFFFFFFFh
Accessible Local Bus
(External)
Peripherals (Internal)
Reserved
Reserved
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
Local Bus
(External)
Local Bus
(alias region, see Figure 2)
Global Bus
(External)
Global Bus
(alias region, see Figure 2)
(a) INTERNAL ROM DISABLED
(ROMEN = 0)
Microprocessor Mode
Reserved
Peripherals (Internal)
Reserved
Reserved
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
Local Bus
(External)
Local Bus
(alias region, see Figure 2)
Global Bus
(External)
Global Bus
(alias region, see Figure 2)
(b) INTERNAL ROM ENABLED
(ROMEN = 1)
Microcomputer Mode
Boot-Loader ROM (Internal)
Structure Depends Upon
Romen Bit
Structure Identical
16 M
Figure 1. Memory Map for the ’320C44
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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description
The TMS320C44 DSP is a 32-bit, floating-point processor manufactured in 0.72-µm double-level-metal CMOS
technology. The TMS320C44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The
on-chip parallel-processing capabilities of the ’C44 make the immense floating-point performance required by
many applications achievable.
operation
The ’320C44 has four on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity with no external-glue logic. The
communication ports remove input/output bottlenecks, and the independent smart 6-channel DMA
coprocessor is able to handle the CPU input/output burden.
T o fit the ’320C40 into a 304-pin PQFP package (thermally enhanced plastic quad flatpack), two communication
ports are removed and the external local and global address buses are reduced to 24 address lines each. In
this case, both the bond pads and driver circuits are removed, decreasing die size and power consumption.
Otherwise, functionality remains the same as the rest of the ’320C4x family.
The communication-port token and data-strobe control lines are internally connected to avoid spurious data,
boot-up, and power consumption problems.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory aliasing
The ’320C44 offers global and local addresses of A0–A23 and LA0–LA23, giving an external address reach
of (2 buses) × (224) = 225 words. Since the internal address span of the ’320C44 is 232 words, reading or writing
to memory outside of the base-address region causes memory aliasing. Figure 2 shows how the memory pages
overlap each other.
External Alias n
External Alias 1
External Alias 2
Local Bus
0x7F000000
0x02000000
0x02FFFFFF
0x01000000
0x7FFFFFFF
0x01FFFFFF
External Alias n
External Alias 1
External Alias 2
Global Bus
0xFF000000
0x82000000
0x82FFFFFF
0x81000000
0xFFFFFFFF
0x81FFFFFF
Base-Address
Region
0x00000000
0x00FFFFFF
Base-Address
Region
0x80000000
0x80FFFFFF
Figure 2. Memory Alias
central processing unit
The ’320C44 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:
D
Eight operations/cycle:
– 40-/32-bit floating-point/integer multiply
– 40-/32-bit floating-point/integer ALU operation
– Two data accesses
– Two address-register updates
D
Floating-point conversion
D
Divide and square-root support
D
’C3x and ’C4x assembly-language compatibility
D
Byte and halfword accessibility
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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DMA coprocessor
The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.
The key features of the DMA coprocessor are:
D
Link pointers to allow DMA channels to autoinitialize without CPU intervention
D
Parallel CPU operation and DMA transfers
D
Six DMA channels to support memory-to-memory data transfers
D
Split-mode operation which doubles the available channels to twelve when data transfers to and from a
communication port are required
communication ports
The ’320C44 contains four identical high-speed communication ports, each of which provides a
bidirectional-communication interface to other ’C4x devices and external peripherals. The key features of the
communication ports are:
D
Direct interprocessor communication and processor I/O
D
20M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface
D
Port direction pin (CDIR) to ease interfacing
D
Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O
D
Automatic arbitration and handshaking for direct processor-to-processor connection
communication-port direction pin
A port-direction pin (CDIR1, CDIR2, CDIR4, CDIR5) is available for each ’C44 communication port. When the
communication port is in the output mode, CDIRx is driven low. When the communication port is in the input
mode, CDIRx is driven high. The truth table for two ’320C44 devices is shown in Table 1. Communication
port 1 of CPUA is connected to communication port 4 of CPUB.
Table 1. Truth Table for Two ’320C44 Devices
CDIR1 CDIR4 DESCRIPTION
0 0 Token error
0 1 CPUA is configured to transmit to CPUB.
1 0 CPUB is configured to transmit to CPUA.
1 1 Token exchange overlap, if > 1H then token error
communication-port-software reset
The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port software-reset address as specified in T able 2. This software reset flushes any
word or byte already present in the FIFOs, but it does not affect the status of the communication-port pins.
T able 2. Communication-Port Software-Reset Address
COMMUNICATION PORT SOFTWARE-RESET ADDRESS
1 0x0100053
2 0x0100063
4 0x0100083
5 0x0100093
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
communication-port-software reset (continued)
When used in conjunction with the communication-port direction pins and NMI
bus-grant, an effective method
of error detection and correction can be achieved. A subroutine showing how to reset communication port 1 is
given in Figure 3.
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
; RESET1:Flushes FIFOs data for communication port 1;
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
RESET1 push AR0 ; Save registers
push R0 ;
push RC ;
ldhi 010h,AR0 ; Set AR0 to base address of COM 1
or 050h,AR0 ;
FLUSH: rpts 1 ; Flush FIFO data with back-to-back write
sti R0,*+AR0(3) ;
rpts 10 ; Wait
nop ;
ldi *+AR0(0),R0 ; Check for new data from other port
and 01FE0h,R0 ;
bnz FLUSH ;
pop RC ; Restore registers
pop R0 ;
pop AR0 ;
rets ; Return
Figure 3. Example of Communication-Port-Software Reset
NMI
with bus-grant feature
The ’320C44 devices have a software-configurable feature that allows forcing the internal-peripheral bus ready
when the NMI
signal is asserted. The NMI bus-grant feature is enabled when bits 19 and 18 of the status register
(ST) are set to 10b. When enabled, a peripheral bus-grant signal is generated on the falling edge of NMI. If NMI
is asserted and this feature is not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A
stall condition occurs when writing to a full output FIFO or reading an empty input FIFO. This feature is useful
in correcting communication-port errors when used in conjunction with the communication-port software-reset
feature.
IDLE2 clock-stop power-down mode
The ’320C44 has a clock-stop mode, or power-down mode (IDLE2) to achieve extremely low power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 held high. (Exiting IDLE2
requires asserting one of the IIOF3
–IIOF0 pins configured as an external interrupt.) A macro showing how to
generate the IDLE2 opcode is given in Figure 4. During this power-down mode:
D
No instructions are executed.
D
The CPU, peripherals, and internal memory retain their previous state.
D
The external-bus outputs are idle. The address lines remain in their previous state; the data lines are in the
high-impedance state; and the output-control signals are inactive.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IDLE2 clock-stop power-down mode (continued)
; ––––––––––––––––––––––––––––––––––––––––––––-–-–;
; IDLE2: Macro to generate idle2 opcode ;
; –––––––––––––––––––––––––––––––––––––––––––––-––;
IDLE2 .macro
.word 06000001h
.endm
Figure 4. Example Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3–IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180 degrees out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after a return opcode is executed.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.
boot-loader mode selection
Table 3. Boot-Loader Mode Selection Using Pins IIOF3
–IIOF0
EXTERNAL PIN
IIOF3 IIOF2 IIOF1 IIOF0
SOURCE PROGRAM LOCATION
1 1 0 1 Load source program from address 0030 0000h
1 0 1 1 Load source program from address 4000 0000h (see Note 1)
1 0 0 1 Load source program from address 80 0000h
0 1 1 1 Load source program from address 8000 0000h (see Note 2)
0 1 0 1 Load source program from address 8040 0000h (see Note 3)
0 0 1 1 Load source program from address 8080 0000h (see Note 4)
0 0 0 1 Reserved (boot-loader program terminates)
1 1 1 1 Load source program from communication port
NOTES: 1. This selection cause the ’C44 to drive 0 in the 24 external local address pins and activates the LSTRB0 signal.
2. This selection cause the ’C44 to drive 0 in the 24 external global address pins ando activates the STRB0
signal.
3. This selection cause the ’C44 to drive 0x40 0000 in the 24 external global address pins and activates the STRB0
signal.
4. This selection cause the ’C44 to drive 0x80 0000 in the 24 external global address pins and to activate the STRB0
signal.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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development tools
A key aspect to a parallel-processing implementation is the development tools available. The ’C44 is supported
by a host of parallel-processing tools for developing and simulating code easily and for debugging
parallel-processing systems. The code-generation tools include:
D
An optimizing ANSI C compiler with a runtime-support library that supports use of communication ports and
DMA
D
Third party support for C, C++, and Ada compilers
D
Several operating systems available for parallel-processing support as well as DMA and
communication-port drivers
D
Assembler and linker with support for mapping program and data to parallel processors
The simulation tools include a TI software-simulator with a high-level-language debugger interface for
simulating a single processor. The hardware development and verification tools consist of the XDS510
(parallel-processor in-circuit emulator and high-level-language debugger).
silicon revision identification
DSP
TMS320C44PDB
EAXXX
YYYYY
1991 TI T AIWAN
Device Type
Revision Number and Package Data Code
E XXXXX : Silicon rev 1.X
EA XXXXX : Silicon rev 2.X
Lot Number (May or may not exist)
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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absolute maximum ratings over specified temperature range (unless otherwise noted)
†
Supply voltage range, VDD (see Note 5) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC 0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
– 55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 5: All voltage values are with respect to VSS.
recommended operating conditions
MIN TYP
‡
MAX UNIT
V
DD
Supply voltage (DDVDD, etc.) 4.75 5 5.25 V
X2 / CLKIN 2.6 VDD + 0.3
§
V
IH
High-level input voltage
CSTRB
and CRDY pins 2.4 VDD + 0.3
§
V
All other pins 2 VDD + 0.3
§
V
IL
Low-level input voltage – 0.3
§
0.8 V
I
OH
High-level output current – 300 µA
I
OL
Low-level output current 2 mA
T
C
Operating case temperature 0 85 °C
‡
All typical values are at VDD = 5 V, TA (air temperature)= 25°C.
§
This parameter is characterized but not tested.
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS
¶
MIN TYP#MAX UNIT
V
OH
High-level output voltage VDD = MIN, IOH = MAX 2.4 3
V
V
OL
Low-level output voltage VDD = MIN, IOL = MAX 0.3 0.6
V
I
Z
High-impedance current VDD = MAX –20 20
µA
X2/CLKIN only –30 30
I
I
Input current
Inputs with internal pullups
(see Note 6)
VI = VSS to V
DD
–400 20
µA
All others –10 10
I
Supply current
TA = 25°C, VDD = MAX,
’320C44-40
’320C44-50
350 850
mA
CC
y
f
x
=
MAX (see Note 7)
’320C44-60 350 950
C
I
Input capacitance 15
||
pF
C
o
Output capacitance 15
||
pF
¶
For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
#
All typical values are at VDD = 3.3 V, TA (air temperature) = 25°C.
||
This parameter is specified by design but not tested.
NOTES: 6. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST
.
7. fx is the input clock frequency. The maximum value (max) for the ’320C44-40, ’320C44-50, and ’320C44-60 is 40, 50 and 60 MHz,
respectively.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
V
Load
I
OL
C
T
I
OH
Output
Under
Test
Where: I
OL
= 2 mA (all outputs)
I
OH
= 300 µA (all outputs)
V
LOAD
= 2.15 V
C
T
= 80 pF typical load-circuit capacitance
Figure 5. Test Load Circuit
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V .
Output transition times are specified as follows:
D
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
D
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
0.6 V
1 V
2 V
2.4 V
Figure 6. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
D
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.92 V (10%) and the level at which the input is said to be high is 1.88 V (90%).
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.88 V (90%) and the level at which the input is said to be low is 0.92 V (10%).
1.88 V (90%)
0.92 V (10%)
2 V
0.8 V
Figure 7. TTL-Level Inputs
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
20
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PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, pin names that have both global and local applications are generally represented with (L)
immediately preceding the basic signal name (for example, (L)RDY represents both the global term RDY and
local term LRDY). Other pin names and related terminology have been abbreviated as follows, unless otherwise
noted:
A (L)A23–(L)A0 or (L)Ax IACK IACK
AE (L)AE IF IIOF(3–0) or IIOFx
ASYNCH
Asynchronous reset signals in the
high-impedance state
IIOF IIOF(3–0)
or IIOFx
BYTE Byte transfer LOCK (L)LOCK
CA CACK(1,2,4,5) or CACKx Pt
c(H)
CD C(1,2,4,5)D7–C(1,2,4,5)D0 or CxDx PAGE (L)PAGE0 and (L)PAGE1 or (L)PAGEx
CDIR CDIR(1,2,4,5) or CDIRx RDY (L)RDY0
, (L)RDY1, or (L)RDYx
CE (L)CE0, (L)CE1, or (L)CEx RESET RESET
CI CLKIN RW (L)R/W0, (L)R/W1, or (L)R/Wx
COMM Asynchronous reset signals S (L)STRB0
, (L)STRB1, or (L)STRBx
CONTROL Control signals ST (L)STAT3–(L)STAT0 or (L)STATx
CRQ CREQ(1,2,4,5)
or CREQx TCK TCK
CRDY CRDY(1,2,4,5)
or CRDYx TCLK TCLK0, TCLK1, or TCLKx
CS CSTRB(1,2,4,5)
or CSTRBx TDO TDO
D (L)D31–(L)D0 or (L)Dx TMS TMS/TDI
DE (L)DE
WORD 32-bit word transfer
H H1, H3
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for X2/CLKIN, H1, H3 (see Figure 8 and Figure 9)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
f(CI)
Fall time, CLKIN 5
†
5
†
ns
2 t
w(CIL)
Pulse duration, CLKIN low, t
c(CI)
= MIN 7 5 ns
3 t
w(CIH)
Pulse duration, CLKIN high, t
c(CI)
= MIN 7 5 ns
4 t
r(CI)
Rise time, CLKIN 5
†
5
†
ns
5 t
c(CI)
Cycle time, CLKIN 20 242.5 16.67 242.5 ns
6 t
f(H)
Fall time, H1 and H3 3 3 ns
7 t
w(HL)
Pulse duration, H1 and H3 low t
c(CI)
–6 t
c(CI)
+6 t
c(CI)
–6 t
c(CI)
+6 ns
8 t
w(HH)
Pulse duration, H1 and H3 high t
c(CI)
–6 t
c(CI)
+6 t
c(CI)
–6 t
c(CI)
+6 ns
9 t
r(H)
Rise time, H1 and H3 4 4 ns
9.1 t
d(HL-HH)
Delay time from H1 low to H3 high or from H3 low to H1 high –1 4 –1 4 ns
10 t
c(H)
Cycle time, H1 and H3
‡
40 485 33.3 485 ns
†
This value is specified by design but not tested.
‡
Maximum cycle time is not limited during IDLE2 operation.
1
4
X2/CLKIN
5
2
3
Figure 8. X2/CLKIN Timing
H3
H1
6
9
9.1
9.1
6
9
10
8
7
7
8
10
Figure 9. H1 and H3 Timings
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 8, Figure 10, and
Figure 11)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-SL)
Delay time, H1 low to (L)STRBx low 0
†
9 0
†
8 ns
2 t
d(H1L-SH)
Delay time, H1 low to (L)STRBx high 0
†
9 0
†
8 ns
3 t
d(H1H-RWL)
Delay time, H1 high to (L)R/Wx low 0
†
9 0
†
8 ns
4 t
d(H1L-A)
Delay time, H1 low to (L)Ax valid 0
†
9 0
†
8 ns
5 t
su(D-H1L)R
Setup time, (L)Dx valid before H1 low (read) 10 9 ns
6 t
h(H1L-D)R
Hold time, (L)Dx after H1 low (read) 0 0 ns
7 t
su(RDY-H1L)
Setup time, (L)RDYx valid before H1 low 20
‡
18
†
ns
8 t
h(H1L-RDY)
Hold time, (L)RDYx after H1 low 0 0 ns
8.1 t
d(H1L-ST)
Delay time, H1 low to (L)STAT3–(L)STAT0 valid 8 8 ns
9 t
d(H1H-RWH)W
Delay time, H1 high to (L)R/Wx high (write) 0
†
9 0
†
8 ns
10 t
v(H1L-D)W
Valid time, (L)Dx after H1 low (write) 16 13 ns
11 t
h(H1H-D)W
Hold time, (L)Dx after H1 high (write) 0 0 ns
12 t
d(H1H-A)
Delay time, H1 high to address valid on back-to-back write cycles 9 8 ns
†
This value is specified by design but not tested.
‡
If this setup time is not met, the read/write operation is not assured.
NOTE 8: For consecutive reads, (L)R/W
x stays high and (L)STRBx stays low.
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)
6
H3
H1
(L)R/W
x
(L)Ax
(L)Dx
(L)RDYx
(L)STRBx
(L)STATx
5
3
1
2
4
8
7
8.1
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)
1
(L)RDYx
(L)Dx
(L)Ax
(L)R/W
x
(L)STRBx
H1
H3
9
11
12
8
10
4
(L)STATx
2
3
7
Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
(L)DE-, (L)AE-, and (L)CEx-enable timing (see Figure 12)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(DEH-DZ)
Delay time, (L)DE high to (L)D0–(L)D31 in the high-impedance
state
0
†
15
‡
0
†
15
‡
ns
2 t
d(DEL-DV)
Delay time, (L)DE low to (L)D0–(L)D31 valid 0
†
21 0
†
16 ns
3 t
d(AEH-AZ)
Delay time, (L)AE high to (L)A0–(L)A23 in the high-impedance
state
0
†
15
‡
0
†
15
‡
ns
4 t
d(AEL-AV)
Delay time, (L)AE low to (L)A0–(L)A23 valid 0
†
18 0
†
16 ns
5 t
d(CEH-RWZ)
Delay time, (L)CEx high to (L)R/W0, (L)R/W1 in the
high-impedance state
0
†
15
‡
0
†
15
‡
ns
6 t
d(CEL-RWV)
Delay time, (L)CEx low to (L)R/W0, (L)R/W1 valid 0
†
21 0
†
16 ns
7 t
d(CEH-SZ)
Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the
high-impedance state
0
†
15
‡
0
†
15
‡
ns
8 t
d(CEL-SV)
Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid 0
†
21 0
†
16 ns
9 t
d(CEH-PAGEZ)
Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the
high-impedance state
0
†
15
‡
0
†
15
‡
ns
10 t
d(CEL-PAGEV)
Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid 0
†
21 0
†
16 ns
†
This value is specified by design but not tested.
‡
This value is characterized but not tested.
(L)DE
(L)Dx
(L)AE
(L)Ax
(L)CEx
(L)R/Wx
(L)STRBx
(L)PAGEx
1
2
3
4
Hi-Z
5
6
Hi-Z
7 8
Hi-Z
9 10
Hi-Z
Hi-Z
Figure 12. (L)DE-, (L)AE -, and (L)CEx-Enable Timing
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for (L)LOCK when executing LDFI or LDII (see Figure 13)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-LOCKL)
Delay time, H1 low to (L)LOCK low 8 8 ns
H3
H1
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)LOCK
1
LDFI or LDII
External Access
Figure 13. Timing for (L)LOCK When Executing LDFI or LDII
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for (L)LOCK when executing STFI or STII (see Figure 14)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-LOCKH)
Delay time, H1 low to (L)LOCK high 8 8 ns
H3
H1
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)LOCK
1
STFI or STII
External Access
Figure 14. Timing for (L)LOCK When Executing STFI or STII
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for (L)LOCK when executing SIGI (see Figure 15)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-LOCKL)
Delay time, H1 low to (L)LOCK low 8 8 ns
2 t
d(H1L-LOCKH)
Delay time, H1 low to (L)LOCK high 8 8
1
H3
H1
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)LOCK
(L)STATx
2
Figure 15. Timing for (L)LOCK When Executing SIGI
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 16)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-PAGEH)
Delay time, H1 low to (L)PAGEx high for access to dif ferent page 0 9 0 8 ns
2 t
d(H1L-PAGEL)
Delay time, H1 low to (L)PAGEx low for access to different page 0 9 0 8 ns
(L)STRB1 read from a different page
(L)Ax
(L)Dx
(L)PAGEx
(L)RDYx
(L)STRBx
(L)R/Wx
H1
1122
(L)STRB1
write to a different page(L)STATx
Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for the IIOFx when configured as an output (see Figure 17)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
v(H1L-IIOF)
H1 low to IIOFx valid 14 14 ns
Fetch Load
Instruction
Decode Read Execute
H3
H1
FLAGx (IIF Register)
IIOFx
Pins
1 or 0
1
Figure 17. Timing for the IIOFx When Configured as an Output
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing of IIOFx changing from output to input mode (see Figure 18)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
h(H1L-IIOF)
Hold time, IIOFx after H1 low 14
†
14
†
ns
2 t
su(IIOF-H1L)
Setup time, IIOFx before H1 low 11 11 ns
3 t
h(H1L-IIOF)
Hold time, IIOFx after H1 low 0 0 ns
†
This value is specified by design but not tested.
Execute
Load of IIF
Register
Buffers Go
From Output
to Input
Synchronizer
Delay
Value on IIOF
Seen in IIF
H3
H1
IIOFx
FLAGx
(IIF Register)
TYPEx
(IIF Register)
1
2
3
Data
Sampled
Data
Seen
Output
Figure 18. Change of IIOFx From Output to Input Mode
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing of IIOFx changing from input to output mode (see Figure 19)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-IFIO)
Delay time, H1 low to IIOFx switching from input to output 14 14 ns
Execution of
Load of IIF
Register
1
H3
H1
TYPEx
(IIF Register)
IIOFx
Figure 19. Change of IIOFx From Input to Output Mode
RESET timing (see Figure 20)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
su(RESET-C1L)
Setup time for RESET before CLKIN low 11 t
c(CI)
11 t
c(CI)
ns
2.1 t
d(CIH-H1H)
Delay time, CLKIN high to H1 high 2 10 2 10 ns
2.2 t
d(CIH-H1L)
Delay time, CLKIN high to H1 low 2 10 2 10 ns
3 t
su(RESETH-H1L)
Setup time for RESET high before H1 low and after ten H1
clock cycles
13 13 ns
4.1 t
d(CIH-H3L)
Delay time, CLKIN high to H3 low 2 10 2 10 ns
4.2 t
d(CIH-H3H)
Delay time, CLKIN high to H3 high 2 10 2 10 ns
5 t
d(H1H-DZ)
Delay time, H1 high to (L)Dx in the high-impedance state 13
†
13
†
ns
6 t
d(H3H-AZ)
Delay time, H3 high to (L)Ax in the high-impedance state 9
†
9
†
ns
7 t
d(H3H-CONTROLH)
Delay time, H3 high to control signals high [low for (L)PAGE] 9
†
9
†
ns
8 t
d(H1H-IACKH)
Delay time, H1 high to IACK high 9
†
9
†
ns
9 t
d(RESETL-ASYNCH)
Delay time, RESET low to asynchronous reset signals in the
high-impedance state
21
†
21
†
ns
10 t
d(RESETH-COMMH)
Delay time, RESET high to asynchronous reset signals high 15
†
15
†
ns
11 t
d(H1H-CDIRL)
Delay time, 9 9 ns
12 t
d(H1H-CDIRH)
Delay time, 9 9 ns
†
This value is characterized but not tested.
(L)PAGEx
(see Note D)
Control Signals
(see Note D)
(L)Dx
(see Note C)
RESET
(see Notes A and B)
1
2.1
4.1
6
7
8
3
2.2
4.2
Control Signals
7
CLKIN
H1
H3
(L)Ax
see Note C)
IACK
Asynchronous Reset
Signals (see Note E)
Asynchronous Reset
Signals (see Note A)
Ten H1 Clock Cycles
5
9
9
10
CDIRx
(see Note F)
12
11
CDIRy
(see Note F)
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
• 33
NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy
(where x = 1 or 2 and y = 4 or 5).
B. RESET
is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise,
an additional delay of one clock cycle can occur.
C. For this diagram, (L)Dx includes D31– D0, LD31–LD0, and CxD7– CxD0; (L)Ax includes LA(23–0) and A(23– 0).
D. Control signals LSTRB0
, LSTRB1, STRB0, STRB1, (L)STAT3–(L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.
E. Asynchronous reset signals that go into the high-impedance state after RESET
goes low include TCLK0, TCLK1, IIOF3–IIOF0, and the communication-port control
signals CREQx
, CACKy, CSTRBy, and CRDYx (where x = 1 or 2, and y = 4 or 5). At reset, ports 1 and 2 become outputs, and ports 4 and 5 become inputs.
F. x = 1 or 2 and y = 4 or 5
Figure 20. RESET Timing
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for IIOFx interrupt response [P = t
c(H)
] (see Notes 9 and 10 and Figure 21)
TMS320C44-50 TMS320C44-60
NO
.
MIN TYP MAX MIN TYP MAX
UNIT
1 t
su(IIOF-H1L)
Setup time, IIOFx before H1 low 11
†
11
†
ns
2 t
w(INT)
Pulse duration, to assure one interrupt seen
(see Note 11)
P 1.5P < 2P
‡
P 1.5P < 2P
‡
ns
†
If this timing is not met, the interrupt is recognized in the next cycle.
‡
This value only applies to level-triggered interrupts and is specified by design but not tested.
NOTES: 9. IIOFx
is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.
10. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P . No maximum duration limit exists.
11. Level-triggered interrupts require interrupt-pulse duration of at least 1P wide (P = one H1 period) to assure it will be seen. It must
be less than 2P wide to assure it will be responded to only once. Recommended pulse duration is 1.5P.
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
IIOFx
FLAGx
(IIF Register)
Address
Data
Vector
Address
First
Instruction
Address
1
2
(see Note A)
NOTE A: The ’C44 can accept an interrupt from the same source every two H1 clock cycles.
Figure 21. IIOFx Interrupt-Response Timing [P = t
c(H)
]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for IACK (see Note 12 and Figure 22)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
d(H1L-IACKL)
Delay time, H1 low to IACK low 9 7 ns
2 t
d(H1L -IACKH)
Delay time, H1 low to IACK high during first cycle of IACK instruction
data read
9 7 ns
NOTE 12: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states.
H3
H1
IACK
Address
Data
12
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
Execute IACK
Instruction
Figure 22. IACK Timing
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
communication-port word-transfer-cycle timing† [P = t
c(H)
] (see Note 13 and Figure 23)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
c(WORD)
‡§
Cycle time, word transfer (4 bytes = 1 word) 1.5P+7 2.5P+170 1.5P+7 2.5P+170 ns
2 t
d(CRDYL-CSL)W
‡
Delay time, CRDYx low to CSTRBx low between
back-to-back write cycles
1.5P+7 2.5P + 28 1.5P+7 2.5P+28 ns
†
For these timing values, it is assumed that the ’C4x receiving data is ready to receive data. Line propagation delay is not considered.
‡
This value is characterized but not tested.
§
t
c(WORD)
max = 2.5P + 28 ns + the maximum summed values of 4 × t
d(CSL-CRDYL)R
, 3 × t
d(CRDYL-CSH),
3 × t
d(CSH-CRDYH)R
, and
3 × t
d(CRDYH-CSL)W
as seen in Figure 24. This timing assumes two ’C4xs are connected.
NOTE 13: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C44, timings can be longer. No
restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB
width restriction section of the
TMS320C4x User’s Guide
(literature number SPRU063B).
CREQx
CACKx
CSTRBx
CxDx
CRDYx
1
2
Undef.B0 B1 B2 B3 B0
¶
= When signal is an input (clear = when signal is an output).
¶
Begins byte 0 of the next word.
NOTE A: For correct operation during token exchange, the two communicating ’C4xs must have CLKIN frequencies within a factor of 2 of each
other (in other words, at most, one of the ’C4xs can be twice as fast as the other).
Figure 23. Communication-Port Word-Transfer-Cycle Timing [P = t
c(H)
]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
communication-port byte-cycle timing (write and read) (see Note 14 and Figure 24)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
su(CD-CSL)W
Setup time, CxDx valid before CSTRBx low (write) 2 2 ns
2 t
d(CRDYL-CSH)W
Delay time, CRDYx low to CSTRBx high (write) 0
†
12 0
†
12 ns
3 t
h(CRDYL-CD)W
Hold time, CxDx after CRDYx low (write) 2 2 ns
4 t
d(CRDYH-CSL)W
Delay time, CRDYx high to CSTRBx low for subsequent bytes
(write)
0
†
12 0
†
12 ns
5 t
c(BYTE)
‡
Cycle time, byte transfer 44
§
44
§
ns
6 t
d(CSL-CRDYL)R
Delay time, CSTRBx low to CRDYx low (read) 0
†
10 0
†
10 ns
7 t
su(CSL-CD)R
Setup time, CxDx valid after CSTRBx low (read) 0 0 ns
8 t
h(CRDYL-CD)R
Hold time, CxDx valid after CRDYx low (read) 2 2 ns
9 t
d(CSH-CRDYH)R
Delay time, CSTRBx high to CRDYx high (read) 0
†
10 0
†
10 ns
†
This value is specified by design but not tested.
‡
t
c(BYTE)
max = summed maximum values of t
d(CRDY-CSH)
, t
d(CSL-CRDYL)R
, t
d(CSH-CRDYH)R
, and t
d(CRDYH-CSL)W
. This assumes
two ’C4xs are connected.
§
This value is characterized but not tested.
NOTE 14: Communication port timing does not include line length delay.
CREQx
CACKx
CSTRBx
CxDx
CRDYx
(a) WRITE TIMING
(b) READ TIMING
Valid
Data
1
4
7
6
8
2
3
5
9
5
= When signal is an input (clear = when signal is an output).
Figure 24. Communication-Port Byte-Cycle Timing (Write and Read)
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for communication-token transfer sequence, input to an output port [P = t
c(H)
]
(see Figure 25)
†
NO. MIN MAX UNIT
1‡t
d(CAL-CS)T
Delay time, CACKx low to CSTRBx change from input to a high-level output 0.5P+ 6 1.5P+22 ns
2‡t
d(CAL-CRQH)T
Delay time, CACKx low to start of CREQx going high for token-request
acknowledge
P+5 2P+22 ns
3 t
d(CRQH-CRQ)T
Delay time, start of CREQx going high to CREQx change from output to an input 0.5P – 5 0.5P+13 ns
4 t
d(CRQH-CA)T
Delay time, start of CREQx going high to CACKx change from an input- to an
output-level high
0.5P – 5 0.5P+13 ns
4.1 t
d(CRQH-CD)T
Delay time, start of CREQx going high to CxDx change from input-driven to
output-driven
0.5P – 5 0.5P + 13 ns
4.2 t
d(CRQH-CRDY)T
Delay time, start of CREQx going high to CRDYx change from an output to an
input
0.5P – 5 0.5P+13 ns
5 t
d(CRQH-CSL)T
Delay time, start of CREQx going high to CSTRBx low for start of word-transfer
out
1.5P – 8 1.5P+9 ns
6 t
d(CRDYL-CSL)T
Delay time, CRDYx low at end of word-input to CSTRBx low for word-output 3.5P+12 5.5P+48 ns
7 t
d(CRQH-CDIRL)
Delay time, CREQx high to CDIRx low, change from input to output 0.5P – 5 0.5P+13 ns
†
These values are characterized but not tested.
‡
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
CREQx
CACKx
CSTRBx
CxDx
CRDYx
= When signal is an input (clear = when signal is an output).
6
3
4
1
4.1
4.2
Valid Data Out
2
5
CDIRx
7
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the ’320C44 receiving data. CACKx, CSTRBx, and
CxD7–CxD0 are input signals asserted by the device sending data to the ’C44; these are asynchronous with respect to the H1 clock
of the receiving ’320C44. After token exchange, CACKx
, CSTRBx, and CxD7–CxD0 become output signals, and CREQx and CRDYx
become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P = t
c(H)
]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing for communication-token transfer sequence, output to an input port [P = t
c(H)
]
(see Figure 26)
†
NO. MIN MAX UNIT
1‡t
d(CRQL-CAL)T
Delay time, CREQx low to start of CACKx going low for
token-request-acknowledge
P+5 2P+22 ns
2‡t
d(CRDYL-CAL)T
Delay time, CRDYx low at end of word-transfer out to start of CACKx going low P+6 2P+27 ns
3 t
d(CAL-CD)I
Delay time, start of CACKx going low to CxDx change from outputs to inputs 0.5P–8 0.5P+8 ns
4 t
d(CAL-CRDY)T
Delay time, start of CACKx going low to CRDYx change from an input to output,
high level
0.5P–8 0.5P+8 ns
5‡t
d(CRQH-CRQ)T
Delay time, CREQx high to CREQx change from an input to output, high level 4 22 ns
6‡t
d(CRQH-CA)T
Delay time, CREQx high to CACKx change from output to an input 4 22 ns
7‡t
d(CRQH-CS)T
Delay time, CREQx high to CSTRBx change from output to an input 4 22 ns
8‡t
d(CRQH-CRQL)T
Delay time, CREQx high to CREQx low for the next token-request P–4 2P+8 ns
9 t
d(CAL-CDIRH)
Delay time, CACKx low to CDIRx high, change from output to input 0.5P–8 0.5P+10 ns
†
These values are characterized but not tested.
‡
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
CREQx
CACKx
CSTRBx
CxDx
CRDYx
= When signal is an input (clear = when signal is an output).
Valid Data
1
5
6
7
8
3
4
2
Valid Data
CDIRx
9
NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7–CxD0 are asserted by the ’C44 sending data. CREQx and CRDYx are
input signals asserted by the ’C44 receiving data and are asynchronous with respect to the H1 clock of the sending ’C44. After token
exchange, CREQx
and CRDYx become outputs, and CSTRBx, CACKx, and CxD7–CxD0 become inputs.
Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P = t
c(H)
]
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer-pin timing (see Note 15 and Figure 27)
NO. MIN MAX UNIT
1 t
su(TCLK-H1L)
Setup time, TCLKx before H1 low 10 ns
2 t
h(H1L-TCLK)
Hold time, TCLKx after H1 low 0 ns
3 t
d(H1H-TCLK)
Delay time, TCLKx valid after H1 high 13 ns
NOTE 15: Period and polarity are specified by contents of internal control registers.
3
3
TCLKx
H1
H3
1
2
Figure 27. Timer-Pin Timing Cycle
timing for IEEE-1149.1 test access port (see Figure 28)
TMS320C44-50 TMS320C44-60
NO
.
MIN MAX MIN MAX
UNIT
1 t
su(TMS-TCKH)
Setup time, TMS/TDI to TCK high 10 10 ns
2 t
h(TCKH-TMS)
Hold time, TMS/TDI from TCK high 5 5 ns
3 t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid 0 15 0 12 ns
TCK
TMS/TDI
TDO
3
2
1
Figure 28. IEEE-1149.1 Test Access Port Timings
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PDB (S-PQFP-G304) PLASTIC QUAD FLATPACK (DIE-DOWN)
4040148/B 10/94
153
0,27
0,17
152
0,13 NOM
0,25
0,75
0,50
0,25 MIN
Seating Plane
76
77
Gage Plane
Heat slug
228
229
SQ
SQ
39,80
40,20
42,80
42,40
37,50 TYP
1
304
4,00
4,50 MAX
3,60
0,08
0,50
M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced molded plastic package with a heat slug (HSL)
D. Falls within JEDEC MO-143
Thermal Resistance Characteristics
Parameter °C/W Air Flow LFPM Parameter °C/W Air Flow LFPM
RΘ
JC
0.8 N/A RΘ
JA
12.1 250
RΘ
JA
16.0 0 RΘ
JA
10.0 500
RΘ
JA
14.2 100
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Copyright 1998, Texas Instruments Incorporated
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