Texas Instruments TMS320C40GFL60, TMS320C40GFL50, TMS320C40GFL40 Datasheet

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

D

Highest Performance Floating-Point Digital
Signal Processor (DSP)
– ’320C40-60:

33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 384M Bytes/s

– ’320C40-50:

40-ns Instruction Cycle Time

– ’320C40-40:

50-ns Instruction Cycle Time

D

Six Communications Ports

D

Six-Channel Direct Memory Access (DMA)
Coprocessor

D

Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format

D

Single Cycle, 1/x, 1/

D

Source-Code Compatible With TMS320C3x

D

Single-Cycle 40-Bit Floating-Point,

Ǹ

x

32-Bit Integer Multipliers

D

Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers, and Two
Timers

D

IEEE 1149.1† (JT AG) Boundary Scan
Compatible

D

Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
– High Port-Data Rate of 120M Bytes/s

(’C40-60) (Each Bus)

– 16G-Byte Continuous

Program/Data/Peripheral Address
Space

– Memory-Access Request for Fast,

Intelligent Bus Arbitration

– Separate Address-Bus, Data-Bus, and

Control-Enable Pins

– Four Sets of Memory-Control Signals

Support Different Speed Memories in
Hardware

D

325-Pin Ceramic Grid Array (GF Suffix)

D

Fabricated Using 0.72-µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)

D

Software-Communication-Port Reset

D

NMI With Bus-Grant Feature

325-PIN GF GRID ARRAY PACKAGE

AR

AP

AN

AM

AL

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

123456789

‡

Pin A1

See Pin Assignments table and Pin Functions table for location
and description of all pins.

D

Separate Internal Program, Data, and DMA

(BOTTOM VIEW)

10

14 1617181920212223242526 282730

11 131215

‡

29 3132333435

Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance

D

On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache

– 8K Bytes of Single-Cycle Dual-Access

Program or Data RAM

– ROM-Based Boot Loader Supports

Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports

D

IDLE2 Clock-Stop Power-Down Mode

D

5-V Operation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture

EPIC and TI are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1996, Texas Instruments Incorporated

1

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

block diagram

D(31–0)
A(30–0)

DE
AE

STAT(3–0)

LOCK

STRB0, STRB1

R/W0, R/W1

PAGE0, PAGE1

, RDY1

RDY0

CE0, CE1

X1

X2/CLKIN

ROMEN

RESET

RESETLOC0
RESETLOC1

NMI

IIOF(3–0)

IACK

H1

H3

CV

SS

DV

DD

DV

SS

IV

SS

LADV

DD

LDDV

DD

V

DDL

V

SSL

SUBS

M

U
X

IR

PC

Controller

Cache

(512 Bytes)

32 32

PDATA Bus

PADDR Bus
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus

RAM Block 0

(4K Bytes)

32

32 32

32

32

32

RAM Block 1

(4K Bytes)

32

C
P
U
1

MUX

32

R
E

G

1

R
E
G

2

32

40 40

Multiplier

40
40
32

ARAU0 ARAU1

32
32

32
32

32
32

ROM Block
(Reserved)

32

CPU1

CPU2

REG1

REG2

32-Bit Barrel

40

Extended
Precision
Registers

(R0–R11)

DISP, IR0, IR1

BK

Auxiliary
Registers
(AR0–AR7)

Other

Registers

(14)

32

40

Shifter

ALU

32

32

Continued on next page

40

40

40

40

32

32

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

block diagram (continued)

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

PDATA Bus

PADDR Bus
DDATA Bus

DADDR 1 Bus

DADDR 2 Bus

DMADATA Bus

Continued from previous page

DMAADDR Bus

3232

DMA Coprocessor
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5

Six DMA Channels

MUX

Peripheral Data Bus

Peripheral Address Bus

Global-Control Register

COM Port 0

Input

FIFO

Output

FIFO

Port-Control Registers

COM Port 5

Input

FIFO

Output

FIFO

Port-Control Registers

Timer 0

Time-Period Register

Timer-Counter Register

PAU

PAU

M
U
X

CREQ0
CACK0
CSTRB0
CRDY0

C0D7–C0D0

CREQ5
CACK5
CSTRB5

CRDY5
C5D7–C5D0

LD31–LD0
LA30–LA0
LDE
LAE
LSTAT3–LSTAT0
LLOCK
LSTRB0–LSTRB1
LR/W0–LR/W1
LPAGE0–LPAGE1

–LRDY1

LRDY0
LCE0,LCE1

Six Communication Ports

TCLK0

Timer 1

Global-Control Register

Time-Period Register

Timer-Counter Register

Port Control

Global

Local

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TCLK1

3

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

functions

This section lists signal descriptions for the ’320C40 device. The ’320C40 pin functions table lists each signal,
number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z,
respectively), and function. The signals are grouped according to function.

Pin Functions

NAME

D31–D0 32 I/O/Z 32-bit data port of the global-bus external interface
DE 1 I Data-bus-enable signal for the global-bus external interface
A30–A0 31 O/Z 31-bit address port of the global-bus external interface
AE 1 I Address-bus-enable signal for the global-bus external interface
STAT3–STAT0 4 O Status signals for the global-bus external interface
LOCK 1 O Lock signal for the global-bus external interface

‡

STRB0

‡

R/W0

‡

PAGE0

‡

RDY0

‡

CE0

‡

STRB1

‡

R/W1

‡

PAGE1

‡

RDY1

‡

CE1

LD31–LD0 32 I/O/Z 32-bit data port of the local-bus external interface
LDE 1 I Data-bus-enable signal for the local-bus external interface
LA30–LA0 31 O/Z 31-bit address port of the local-bus external interface
LAE 1 I Address-bus-enable signal for the local-bus external interface
LSTAT3–LSTAT0 4 O Status signals for the local-bus external interface
LLOCK 1 O Lock signal for the local-bus external interface

‡

LSTRB0
LR/W0 1 O/Z Read/write signal for LSTRB0 accesses
LPAGE0 1 O/Z Page signal for LSTRB0 accesses
LRDY0 1 I Ready signal for LSTRB0 accesses
LCE0 1 I Control enable for the LSTRB0, LPAGE0, and LR/W0 signals

‡

LSTRB1
LR/W1 1 O/Z Read/write signal for LSTRB1 accesses
LPAGE1 1 O/Z Page signal for LSTRB1 accesses
LRDY1 1 I Ready signal for LSTRB1 accesses
LCE1 1 I Control enable for the LSTRB1, LPAGE1, and LR/W1 signals

†

I = input, O = output, Z = high impedance

‡

Signal’s effective address range is defined by the local/global STRB ACTIVE bits.

NO. OF

PINS

1 O/Z Access strobe 0 for the global-bus external interface
1 O/Z Read/write signal for STRB0 accesses
1 O/Z Page signal for STRB0 accesses
1 I Ready signal for STRB0 accesses
1 I Control enable for the STRB0, PAGE0, and R/W0 signals
1 O/Z Access strobe 1 for the global-bus external interface
1 O/Z Read/write signal for STRB1 accesses
1 O/Z Page signal for STRB1 accesses
1 I Ready signal for STRB1 accesses
1 I Control enable for the STRB1, PAGE1, and R/W1 signals

1 O/Z Access strobe 0 for the local-bus external interface

1 O/Z Access strobe 1 for the local-bus external interface

TYPE

†

GLOBAL-BUS EXTERNAL INTERFACE (80 PINS)

LOCAL-BUS EXTERNAL INTERFACE (80 PINS)

DESCRIPTION

4

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DIGITAL SIGNAL PROCESSOR

Pin Functions (Continued)

NAME

C0D7–C0D0 8 I/O Communication port 0 data bus
CREQ0 1 I/O Communication port 0 token-request signal
CACK0 1 I/O Communication port 0 token-request-acknowledge signal
CSTRB0 1 I/O Communication port 0 data-strobe signal
CRDY0 1 I/O Communication port 0 data-ready signal

C1D7–C1D0 8 I/O Communication port 1 data bus
CREQ1 1 I/O Communication port 1 token-request signal
CACK1 1 I/O Communication port 1 token-request-acknowledge signal
CSTRB1 1 I/O Communication port 1 data-strobe signal
CRDY1 1 I/O Communication port 1 data-ready signal

C2D7–C2D0 8 I/O Communication port 2 data bus
CREQ2 1 I/O Communication port 2 token-request signal
CACK2 1 I/O Communication port 2 token-request-acknowledge signal
CSTRB2 1 I/O Communication port 2 data-strobe signal
CRDY2 1 I/O Communication port 2 data-ready signal

C3D7–C3D0 8 I/O Communication port 3 data bus
CREQ3 1 I/O Communication port 3 token-request signal
CACK3 1 I/O Communication port 3 token-request-acknowledge signal
CSTRB3 1 I/O Communication port 3 data-strobe signal
CRDY3 1 I/O Communication port 3 data-ready signal

C4D7–C4D0 8 I/O Communication port 4 data bus
CREQ4 1 I/O Communication port 4 token-request signal
CACK4 1 I/O Communication port 4 token-request-acknowledge signal
CSTRB4 1 I/O Communication port 4 data-strobe signal
CRDY4 1 I/O Communication port 4 data-ready signal

C5D7–C5D0 8 I/O Communication port 5 data bus
CREQ5 1 I/O Communication port 5 token-request signal
CACK5 1 I/O Communication port 5 token-request-acknowledge signal
CSTRB5 1 I/O Communication port 5 data-strobe signal
CRDY5 1 I/O Communication port 5 data-ready signal

†

I = input, O = output, Z = high impedance

NO. OF

PINS

TYPE

†

COMMUNICATION PORT 0 INTERFACE (12 PINS)

COMMUNICATION PORT 1 INTERFACE (12 PINS)

COMMUNICATION PORT 2 INTERFACE (12 PINS)

COMMUNICATION PORT 3 INTERFACE (12 PINS)

COMMUNICATION PORT 4 INTERFACE (12 PINS)

COMMUNICATION PORT 5 INTERFACE (12 PINS)

DESCRIPTION

TMS320C40

SPRS038 – JANUARY 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

Pin Functions (Continued)

NAME

IIOF3–IIOF0 4 I/O Interrupt and I/O flags
NMI 1 I Nonmaskable interrupt. NMI is sensitive to a low-going edge.
IACK 1 O Interrupt acknowledge
RESET 1 I Reset signal
RESETLOC1–

RESETLOC0
ROMEN 1 I On-chip ROM enable (0 = disable, 1 = enable)
TCLK0 1 I/O Timer 0 pin
TCLK1 1 I/O Timer 1 pin

X1 1 O Crystal pin
X2/CLKIN 1 I Crystal/oscillator pin
H1 1 O H1 clock
H3 1 O H3 clock

CV

SS

DV

SS

IV

SS

DV

DD

GADV

DD

GDDV

DD

LADV

DD

LDDV

DD

SUBS 1 I Substrate pin (tie to ground)
V

DDL

V

SSL

TCK 1 I IEEE 1149.1 test port clock
TDO 1 O/Z IEEE 1149.1 test port data out
TDI 1 I IEEE 1149.1 test port data in
TMS 1 I IEEE 1149.1 test port mode select
TRST 1 I IEEE 1149.1 test port reset
EMU0 1 I/O Emulation pin 0
EMU1 1 I/O Emulation pin 1

†

I = input, O = output, Z = high impedance

NO. OF

PINS

2 I Reset-vector location pins

15 I Ground pins
15 I Ground pins

6 I Ground pins

13 I 5-VDC supply pins

3 I 5-VDC supply pins
3 I 5-VDC supply pins
3 I 5-VDC supply pins
3 I 5-VDC supply pins

4 I 5-VDC supply pins
4 I Ground pins

†

TYPE

INTERRUPTS, I/O FLAGS, RESET, TIMER ( 12 PINS)

CLOCK (4 PINS)

POWER (70 PINS)

EMULATION (7 PINS)

DESCRIPTION

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

GF Package Pin Assignments — Alphabetical Listing

PIN PIN PIN PIN PIN

NAME NO. NAME NO. NAME NO. NAME NO. NAME NO.

A0 D32 C0D6 AN7 C5D4 AM30 CV
A1 B32 C0D7 AK8 C5D5 AP32 CV
A2 D30 C1D0 AL7 C5D6 AM32 CV
A3 C29 C1D1 AP8 C5D7 AL31 CV
A4 B30 C1D2 AM8 CACK0 AN11 CV
A5 F28 C1D3 AK12 CACK1 AN13 CV
A6 F24 C1D4 AK10 CACK2 AM14 CV
A7 E29 C1D5 AN9 CACK3 AM16 D0 U33 DV
A8 C27 C1D6 AL9 CACK4 AK32 D1 V32 DV

A9 D28 C1D7 AP10 CACK5 AJ31 D2 T34 DV
A10 B28 C2D0 AM18 CE0 AA33 D3 U31 DV
A11 F26 C2D1 AN19 CE1 V34 D4 R33 DV
A12 C25 C2D2 AL19 CRDY0 AP12 D5 P34 DV
A13 E27 C2D3 AP20 CRDY1 AP14 D6 T32 DV
A14 B26 C2D4 AM20 CRDY2 AL15 D7 N33 DV
A15 D26 C2D5 AN21 CRDY3 AL17 D8 R31 DV
A16 C23 C2D6 AL21 CRDY4 AH30 D9 M34 DV
A17 B24 C2D7 AP22 CRDY5 AH32 D10 P32 DV
A18 E25 C3D0 AM22 CREQ0 AM10 D11 L33 DV
A19 C21 C3D1 AN23 CREQ1 AM12 D12 N31 DV
A20 D24 C3D2 AL23 CREQ2 AN15 D13 K34 DV
A21 B22 C3D3 AP24 CREQ3 AN17 D14 M32 DV
A22 E23 C3D4 AM24 CREQ4 AN33 D15 J33 DV
A23 C19 C3D5 AN25 CREQ5 AL33 D16 L31 DV
A24 D22 C3D6 AL25 CSTRB0 AL11 D17 M30 DV
A25 B20 C3D7 AP26 CSTRB1 AL13 D18 K32 DV
A26 E21 C4D0 AN27 CSTRB2 AP16 D19 H34 DV
A27 B18 C4D1 AM26 CSTRB3 AP18 D20 J31 DV
A28 C17 C4D2 AK24 CSTRB4 AM34 D21 G33 DV
A29 D20 C4D3 AL27 CSTRB5 AK34 D22 K30 DV
A30 B16 C4D4 AP28 CV

AE AG31 C4D5 AK26 CV

C0D0 AP4 C4D6 AN29 CV
C0D1 AL5 C4D7 AM28 CV
C0D2 AN5 C5D0 AL29 CV
C0D3 AM4 C5D1 AP30 CV
C0D4 AP6 C5D2 AK28 CV
C0D5 AM6 C5D3 AN31 CV

SS
SS
SS
SS
SS
SS
SS
SS

AR19 D23 F34 EMU0 AA35

AR7 D24 H32 EMU1 AD34

N1 D25 E33 GADV

AL35 D26 D34 GADV

A27 D27 G31 GADV

A9 D28 C33 GDDV
E1 D29 H30 GDDV

J35 D30 E31 GDDV

SS
SS
SS
SS
SS
SS
SS

E35 D31 F32

AR25 DE AA31

AE1 DV

AR13 DV

A19 DV
R35 DV
AL1 DV

DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS

DD
DD
DD
DD
DD
DD

AR11
AR29

A13

A7
A17
L35

AR23

A29

L1

AC1

AR17

A23
AJ1

AJ35

A21
A25

G35

A11

AG1
AM2

R1

AR21
AR15

A15

AR27

G1

N35
AR9

B2

AR1
U35

V2
A35

A1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

7

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

GF Package Pin Assignments — Alphabetical Listing (Continued)

PIN PIN PIN PIN

NAME NO. NAME NO. NAME NO. NAME NO.

H1 AC3 LA25 R5 LD26 B4 STAT0 AD32

H3 AC5 LA26 T2 LD27 F8 STAT1 AE33
IACK W3 LA27 U3 LD28 D6 STAT2 AF34
IIOF0 AN3 LA28 T4 LD29 C3 STAT3 AE31
IIOF1 AL3 LA29 V4 LD30 E5 STRB0 AD30
IIOF2 AH6 LA30 U5 LD31 F6 STRB1 AC33
IIOF3 AK2 LADV
IV

SS

IV

SS

IV

SS

IV

SS

IV

SS

IV

SS

LA0 D2 LD1 C15 LPAGE1 AG3 TRST AE35
LA1 D4 LD2 D18 LRDY0 AF6 V
LA2 E3 LD3 B14 LRDY1 AE5 V
LA3 F4 LD4 E17 LR/W0 AH4 V
LA4 H6 LD5 D16 LR/W1 AF4 V
LA5 F2 LD6 C13 LSTAT0 AA3 V
LA6 G5 LD7 E15 LSTAT1 Y4 V
LA7 G3 LD8 B12 LSTAT2 Y2 V
LA8 H4 LD9 D14 LSTAT3 W5 V

LA9 H2 LD10 C11 LSTRB0 AJ3 X1 W1
LA10 K6 LD11 E13 LSTRB1 AD6 X2/CLKIN AA1
LA11 M6 LD12 B10 NMI AJ5
LA12 J5 LD13 D12 PAGE0 AG33
LA13 J3 LD14 C9 PAGE1 AB32
LA14 K4 LD15 E11 RDY0 Y32
LA15 K2 LD16 F12 RDY1 W31
LA16 L3 LD17 D10 RESETLOC0 AF30
LA17 L5 LD18 B8 RESETLOC1 AH34
LA18 M2 LD19 E9 RESET AJ33
LA19 M4 LD20 C7 ROMEN AK4
LA20 N3 LD21 F10 R/W0 AF32
LA21 N5 LD22 B6 R/W1 AC31
LA22 P2 LD23 D8
LA23 P4 LD24 C5
LA24 R3 LD25 E7

AR5 LADV
AR31 LADV
AG35 LAE AB4 LDE AD4 TCLK1 AD2

A31 LCE0 AG5 LLOCK AA5 TDO AB34

J1 LCE1 AF2 LOCK W33 TDI AC35

A5 LD0 E19 LPAGE0 AH2 TMS W35

DD
DD
DD

B34 LDDV
AB2 LDDV

AP34 LDDV

DD
DD
DD

AR35 SUBS C31

AP2 TCK Y34

U1 TCLK0 AE3

DDL
DDL
DDL
DDL
SSL
SSL
SSL
SSL

AN1

AN35

C35

C1
A3

AR3

AR33

A33

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

GF Package Pin Assignments — Numerical Listing

PIN PIN PIN PIN

NO. NAME NO. NAME NO. NAME NO. NAME

A1 GDDV
A3 V
A5 IV
A7 DV

A9 CV
A11 DV
A13 DV
A15 DV
A17 DV
A19 CV
A21 DV
A23 DV
A25 DV
A27 CV
A29 DV
A31 IV
A33 V
A35 GDDV
AA1 X2/CLKIN AG31 AE AL27 C4D3 AN31 C5D3
AA3 LSTAT0 AG33 PAGE0 AL29 C5D0 AN33 CREQ4
AA5 LLOCK AG35 IV

AA31 DE AH2 LPAGE0 AL33 CREQ5 AP2 LDDV
AA33 CE0 AH4 LR/W0 AL35 CV
AA35 EMU0 AH6 IIOF2 AM2 DV

AB2 LADV
AB4 LAE AH32 CRDY5 AM6 C0D5 AP10 C1D7

AB32 PAGE1 AH34 RESETLOC1 AM8 C1D2 AP12 CRDY0
AB34 TDO AJ1 DV

AC1 DV
AC3 H1 AJ5 NMI AM14 CACK2 AP18 CSTRB3
AC5 H3 AJ31 CACK5 AM16 CACK3 AP20 C2D3

AC31 R/W1 AJ33 RESET AM18 C2D0 AP22 C2D7
AC33 STRB1 AJ35 DV
AC35 TDI AK2 IIOF3 AM22 C3D0 AP26 C3D7

AD2 TCLK1 AK4 ROMEN AM24 C3D4 AP28 C4D4
AD4 LDE AK8 C0D7 AM26 C4D1 AP30 C5D1
AD6 LSTRB1 AK10 C1D4 AM28 C4D7 AP32 C5D5

DD

SSL

SS

DD
SS
SS
DD
SS
DD
SS
SS
DD
SS
SS
DD

SS

SSL

DD

DD

DD

AD30 STRB0 AK24 C4D2 AM30 C5D4
AD32 STAT0 AK26 C4D5 AM32 C5D6
AD34 EMU1 AK28 C5D2 AM34 CSTRB4

AE1 CV
AE3 TCLK0 AK34 CSTRB5 AN3 IIOF0

AE5 LRDY1 AL1 CV
AE31 STAT3 AL3 IIOF1 AN7 C0D6
AE33 STAT1 AL5 C0D1 AN9 C1D5
AE35 TRST AL7 C1D0 AN11 CACK0

AF2 LCE1 AL9 C1D6 AN13 CACK1

AF4 LR/W1 AL11 CSTRB0 AN15 CREQ2

AF6 LRDY0 AL13 CSTRB1 AN17 CREQ3
AF30 RESETLOC0 AL15 CRDY2 AN19 C2D1
AF32 R/W0 AL17 CRDY3 AN21 C2D5
AF34 STAT2 AL19 C2D2 AN23 C3D1

AG1 DV

AG3 LPAGE1 AL23 C3D2 AN27 C4D0

AG5 LCE0 AL25 C3D6 AN29 C4D6

AH30 CRDY4 AM4 C0D3 AP8 C1D1

AJ3 LSTRB0 AM12 CREQ1 AP16 CSTRB2

AK12 C1D3 AP34 LADV

SS

SS

SS

DD

SS

AK32 CACK4 AN1 V

SS

AL21 C2D6 AN25 C3D5

AL31 C5D7 AN35 V

SS
SS

AM10 CREQ0 AP14 CRDY1

AM20 C2D4 AP24 C3D3

AN5 C0D2

AP4 C0D0
AP6 C0D4

TMS320C40

DDL

DDL

DD

DD

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

9

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

GF Package Pin Assignments — Numerical Listing (Continued)

PIN PIN PIN PIN PIN

NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME

AR1 GADV
AR3 V
AR5 IV
AR7 CV

AR9 DV
AR11 DV
AR13 CV
AR15 DV
AR17 DV
AR19 CV
AR21 DV
AR23 DV
AR25 CV
AR27 DV
AR29 DV
AR31 IV
AR33 V
AR35 LDDV

B2 GADV
B4 LD26 D4 LA1 F4 LA3 L3 LA16 U35 GADV
B6 LD22 D6 LD28 F6 LD31 L5 LA17 V2 GDDV

B8 LD18 D8 LD23 F8 LD27 L31 D16 V4 LA29
B10 LD12 D10 LD17 F10 LD21 L33 D11 V32 D1
B12 LD8 D12 LD13 F12 LD16 L35 DV
B14 LD3 D14 LD9 F24 A6 M2 LA18 W1 X1
B16 A30 D16 LD5 F26 A11 M4 LA19 W3 IACK
B18 A27 D18 LD2 F28 A5 M6 LA11 W5 LSTAT3
B20 A25 D20 A29 F32 D31 M30 D17 W31 RDY1
B22 A21 D22 A24 F34 D23 M32 D14 W33 LOCK
B24 A17 D24 A20 G1 DV
B26 A14 D26 A15 G3 LA7 N1 CV
B28 A10 D28 A9 G5 LA6 N3 LA20 Y4 LSTAT1
B30 A4 D30 A2 G31 D27 N5 LA21 Y32 RDY0
B32 A1 D32 A0 G33 D21 N31 D12 Y34 TCK
B34 LADV

DD

SSL

SS

SS
SS
DD
SS
SS
DD
SS
SS
DD
SS
SS
DD

SS

SSL

DD

DD

DD

C1 V
C3 LD29 E3 LA2 H4 LA8 P4 LA23
C5 LD24 E5 LD30 H6 LA4 P32 D10
C7 LD20 E7 LD25 H30 D29 P34 D5

C9 LD14 E9 LD19 H32 D24 R1 DV
C11 LD10 E11 LD15 H34 D19 R3 LA24
C13 LD6 E13 LD11 J1 IV
C15 LD1 E15 LD7 J3 LA13 R31 D8
C17 A28 E17 LD4 J5 LA12 R33 D4
C19 A23 E19 LD0 J31 D20 R35 CV
C21 A19 E21 A26 J33 D15 T2 LA26
C23 A16 E23 A22 J35 CV
C25 A12 E25 A18 K2 LA15 T32 D6
C27 A8 E27 A13 K4 LA14 T34 D2
C29 A3 E29 A7 K6 LA10 U1 LDDV
C31 SUBS E31 D30 K30 D22 U3 LA27
C33 D28 E33 D25 K32 D18 U5 LA30
C35 V

D2 LA0 F2 LA5 L1 DV

D34 D26 G35 DV

DDL

DDL

E1 CV

E35 CV

SS

SS

SS

SS

H2 LA9 P2 LA22

SS

SS

K34 D13 U31 D3

DD

DD

M34 D9 W35 TMS

SS

N33 D7
N35 DV

SS

R5 LA25

T4 LA28

U33 D0

V34 CE1

Y2 LSTAT2

SS

SS

DD

DD
DD

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory map

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

Figure 1 shows the memory map for the ’320C40. Refer to the
SPRU063B) for a detailed description of this memory mapping.

Structure

Depends

Upon

ROMEN Bit

Structure

Identical

2G

1M

1M

1M

2G–3M

Accessible Local Bus

(External)

Peripherals (Internal)

Reserved

Reserved

1K RAM BLK 0 (Internal)

1K RAM BLK 1 (Internal)

Local Bus

(External)

TMS320C4x User’s Guide

000000000h
000000FFFh

000001000h

0000FFFFFh
000100000h

0001000FFh
000100100h

0001FFFFFh
000200000h

0002FF7FFh
0002FF800h

0002FFBFFh
0002FFC00h

0002FFFFFh
000300000h

Boot-Loader ROM

Peripherals (Internal)

1K RAM BLK 0 (Internal)

1K RAM BLK 1 (Internal)

(literature number

(Internal)

Reserved

Reserved

Reserved

Local Bus
(External)

2G

07FFFFFFFh
080000000h

Global Bus (External)

0FFFFFFFFh

(a) Internal ROM Disabled

(ROMEN = 0)

Microprocessor Mode

Figure 1. Memory Map for ’320C40

Global Bus (External)

(b) Internal ROM Enabled

(ROMEN = 1)

Microcomputer Mode

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11

TMS320C40
DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

description

The ’320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-µm,
double-level metal CMOS technology. The ’320C40 is a part of the fourth generation of DSPs from Texas
Instruments and is designed primarily for parallel processing.

operation

The ’320C40 has six on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity to other ’C4x processors with no
external-glue logic. The communication ports remove input / output bottlenecks, and the independent smart
DMA coprocessor is able to handle the CPU input/output burden.

central processing unit

The ’320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:

D

Eight operations/cycle:
– 40/32-bit floating-point/integer multiply
– 40/32-bit floating-point/integer ALU operation
– Two data accesses
– Two address register updates

D

IEEE floating-point conversion

D

Divide and square-root support

D

’C3x assembly language compatibility

D

Byte and halfword accessibility

DMA coprocessor

The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.
The key features of the DMA processor are:

D

Link pointers allow DMA channels to auto-initialize without CPU intervention.

D

Parallel CPU operation and DMA transfers

D

Six DMA channels support memory-to-memory data transfers.

D

Split-mode operation doubles the available DMA channel to 12 when data transfers to and from a
communication port are required.

communication ports

The ’320C40 is the first DSP with on-chip communication ports for processor-to-processor communication with
no external hardware and simple communication software. The features of the communication ports are:

D

Direct interprocessor communication and processor I/O

12

D

Six communication ports for direct interprocessor communication and processor I/O

D

20M-bytes/s bidirectional interface on each communication port for high-speed multiprocessor interface

D

Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O

D

Automatic arbitration and handshaking for direct processor-to-processor connection

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

communication-port software reset (’C40 silicon revision ≥ 5.0)

The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port-software reset address as specified in Table 1. This feature is not present in
’C40 silicon revision <5.0. This software reset flushes any word or byte already present in the FIFOs but it does
not affect the status of the communication-port pins. Figure 2 shows an example of
communication-port-software reset.

Table 1. Communication-Port Software-Reset Address

COMMUNICATION PORT SOFTWARE RESET ADDRESS

0 0x0100043
1 0x0100053
2 0x0100063
3 0x0100073
4 0x0100083
5 0x0100093

; –––––––––––––––––––––––––––––––––––––––––––––-–––;
; RESET1:Flush’s FIFO data for communication port 1;
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
RESET1 push AR0 ; Save registers

push R0 ;
push RC ;
ldhi 010h,AR0 ; Set AR0 to base address of COM 1
or 050h,AR0 ;

flush: rpts 1 ; Flush FIFO data with back-to-back write

sti R0,*+AR0(3) ;
rpts 10 ; Wait
nop ;
ldi *+AR0(0),R0 ; Check for new data from other port
and 01FE0h,R0 ;
bnz flush ;
pop RC ; Restore registers
pop R0 ;
pop AR0 ;
rets ; Return

Figure 2. Example of Communication-Port-Software Reset

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13