Texas Instruments TMS320C32PCMA50, TMS320C32PCMA40, TMS320C32PCM60, TMS320C32PCM50, TMS320C32PCM40 Datasheet
D
High-Performance Floating-Point DSP
– TMS320C32-60 (5 V)
33-ns Instruction Cycle Time
330 Million Operations Per Second
(MOPS), 60 Million Floating-Point
Operations Per Second (MFLOPS), 30
Million Instructions Per Second (MIPS)
– TMS320C32-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
– TMS320C32-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
D
32-Bit High-Performance CPU
D
16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
D
32-Bit Instruction Word, 24-Bit Addresses
D
Two 256 × 32-Bit Single-Cycle, Dual-Access
On-Chip RAM Blocks
D
Flexible Boot-Program Loader
D
On-Chip Memory-Mapped Peripherals:
– One Serial Port
– Two 32-Bit Timers
– Two-Channel Direct Memory Access
(DMA) Coprocessor With Configurable
Priorities
D
Enhanced External Memory Interface That
Supports 8-/16-/32-Bit-Wide External RAM
for Data Access and Program Execution
From 16-/32-Bit-Wide External RAM
D
TMS320C30 and TMS320C31 Object Code
Compatible
D
Fabricated using 0.7 µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
description
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
D
144-Pin Plastic Quad Flat Package
(PCM Suffix) 5 V
D
Eight Extended-Precision Registers
D
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
Two Low-Power Modes
D
Two- and Three-Operand Instructions
D
Parallel Arithmetic Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
D
Block-Repeat Capability
D
Zero-Overhead Loops With Single-Cycle
Branches
D
Conditional Calls and Returns
D
Interlocked Instructions for
Multiprocessing Support
D
One External Pin, PRGW, That Configures
the External-Program-Memory Width to
16 or 32 Bits
D
Two Sets of Memory Strobes (STRB0 and
STRB1
Allow Zero-Glue Logic Interface to Two
Banks of Memory and One Bank of External
Peripherals
D
Separate Bus-Control Registers for Each
Strobe-Control Wait-State Generation,
External Memory Width, and Data Type Size
D
STRB0 and STRB1 Memory Strobes Handle
8-, 16-, or 32-Bit External Data Accesses
(Reads and Writes)
D
Multiprocessor Support Through the HOLD
and HOLDA Signals Is Valid for All Strobes
) and One I/O Strobe (IOSTRB)
The TMS320C32 is the newest member of the TMS320C3x generation of digital signal processors (DSPs) from
Texas Instruments. The TMS320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-µm
triple-level-metal CMOS technology. The enhancements to the TMS320C3x architecture include a
variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA
coprocessor with configurable priorities, flexible boot loader, relocatable interrupt-vector table, and edge- or
level-triggered interrupts.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1996, Texas Instruments Incorporated
1
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
pin assignments
DR0
DV
DD
FSR0
CLKR0
CLKX0
FSX0
DX0
IV
SS
SHZ
TCLK0
TCLK1
DV
DD
EMU3
EMU0
V
DDL
V
DDL
EMU1
EMU2
V
SSL
MCBL/MP
CV
SS
DV
SS
A23
A22
A21
A20
A19
A18
DV
DD
A17
A16
A15
A14
A13
CV
SS
DV
SS
PCM PACKAGE
†
(TOP VIEW)
–2
–1
SS
SS
NC
INT3
INT2
INT1
INT0
IACK
XF1
XF0
144
143
142
141
140
139
138
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
373839404142434445464748495051525354555657585960616263646566676869
137DV136CV135
RESET
PRGW
134
133
R/W
STRB1_B0
132
131
DD
STRB1_B2/A
STRB1_B1
DV
130
129
128
SSL
V
127
STRB1_B3/A
126
DDL
V
125V124
DDL
STRB0_B0
STRB0_B1
123
122
–2
STRB0_B2/A
121
–1
STRB0_B3/A
120
SS
IOSTRB
119IV118
RDY
117DV116
DD
HOLD
HOLDA
115
114
SS
CLKIN
DV
113
112
SS
SUBS
CV
V
111
110
707172
NC
109
108
107
106
105
104
103
102
101
100
H3
H1
D0
D1
D2
D3
DV
DD
D4
D5
D6
99
D7
98
D8
97
D9
96
V
95
SSL
V
94
SSL
DV
93
SS
CV
92
SS
D10
91
DV
90
DD
D11
89
IV
88
SS
D12
87
V
86
DDL
V
85
DDL
D13
84
D14
83
D15
82
D16
81
D17
80
DV
79
DD
D18
78
D19
77
D20
76
D21
75
DV
74
SS
CV
73
SS
†
NC=No internal connection
2
NC
A12
DV
DD
A11
A9A8A7
A10
A6DDA5A4A3
DV
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DDL
V
DDL
V
A2
SS
CV
SS
DV
A1
SSL
V
SSL
V
A0
DV
DD
D31
D30
D29
D28
D27
D26SSD25DDD24
IV
DV
D23
D22
NC
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
Pin Assignments
PIN PIN PIN PIN PIN
NUMBER NAME NUMBER NAME NUMBER NAME NUMBER NAME NUMBER NAME
1 DR0 30 A17 59 DV
2 DV
3 FSR0 32 A15 61 D30 90 DV
4 CLKR0 33 A14 62 D29 91 D10 120 STRB0_B3/A
5 CLKX0 34 A13 63 D28 92 CV
6 FSX0 35 CV
7 DX0 36 DV
8 IV
9 SHZ 38 A12 67 D25 96 D9 125 V
10 TCLK0 39 DV
11 TCLK1 40 A11 69 D24 98 D7 127 V
12 DV
13 EMU3 42 A9 71 D22 100 D5 129 DV
14 EMU0 43 A8 72 NC 101 D4 130 STRB1_B1
15 V
16 V
17 EMU1 46 DV
18 EMU2 47 A5 76 D20 105 D1 134 RESET
19 V
20 MCBL/MP 49 A3 78 D18 107 H1 136 DV
21 CV
22 DV
23 A23 52 A2 81 D16 110 V
24 A22 53 CV
25 A21 54 DV
26 A20 55 A1 84 D13 113 CLKIN 142 INT2
27 A19 56 V
28 A18 57 V
29 DV
DD
SS
DD
DDL
DDL
SSL
SS
SS
DD
31 A16 60 D31 89 D11 118 IV
SS
SS
37 NC 66 IV
DD
41 A10 70 D23 99 D6 128 STRB1_B2/A
44 A7 73 CV
45 A6 74 DV
DD
48 A4 77 D19 106 D0 135 CV
50 V
51 V
58 A0 87 D12 116 DV
DDL
DDL
SS
SS
SSL
SSL
64 D27 93 DV
65 D26 94 V
68 DV
75 D21 104 D2 133 PRGW
79 DV
80 D17 109 NC 138 XF1
82 D15 111 CV
83 D14 112 DV
85 V
86 V
DD
SS
DD
SS
SS
DD
DDL
DDL
88 IV
95 V
97 D8 126 STRB1_B3/A
102 DV
103 D3 132 R/W
108 H3 137 XF0
114 HOLDA 143 INT3
115 HOLD 144 NC
SS
DD
SS
SS
SSL
SSL
DD
SUBS
SS
SS
DD
117 RDY
SS
119 IOSTRB
121 STRB0_B2/A
122 STRB0_B1
123 STRB0_B0
124 V
131 STRB1_B0
139 IACK
140 INT0
141 INT1
DDL
DDL
SSL
DD
SS
SS
–1
–2
–1
–2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS320C32
TYPE
†
DESCRIPTION
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
pin functions
This section provides signal descriptions for the TMS320C32 device. The following table lists each signal, the
number of pins, operating modes, and a brief signal description. The following table groups the signals
according to their function.
TMS320C32 Pin Functions
PIN
NAME NO.
EXTERNAL-BUS INTERFACE (70 PINS)
A23–A0 24 O/Z 24-bit address port of the external-bus interface S H R
D31–D0 32 I/O/Z 32-bit data port of the external-bus interface S H R
R/W 1 O/Z
IOSTRB 1 O/Z External-peripheral I/O strobe for the external-memory interface S H
STRB0_B3/A
STRB0_B2/A
STRB0_B1 1 O/Z
STRB0_B0 1 O/Z
STRB1_B3/A
STRB1_B2/A
STRB1_B1 1 O/Z
STRB1_B0 1 O/Z
RDY 1 I
HOLD 1 I
HOLDA 1 O/Z
PRGW 1 I
A23–A0 24 O/Z 24-bit address port of the external-bus interface S H R
†
I = input, O = output, Z = high-impedance state
‡
S = SHZ
–1
–2
–1
–2
active, H = HOLD active, R = RESET active
1 O/Z
1 O/Z
1 O/Z
1 O/Z
Read/write for external-memory interface. R/W is high when a read is performed
and low when a write is performed over the parallel interface.
External-memory access strobe 0, byte enable 3 for 32-bit external-memory
interface, and address pin for 8-bit and 16-bit external-memory interface
External-memory access strobe 0, byte enable 2 for 32-bit external-memory
interface, and address pin for 8-bit external-memory interface
External-memory access strobe 0, byte enable 1 for the external-memory
interface
External-memory access strobe 0, byte enable 0 for the external-memory
interface
External-memory access strobe 1, byte enable 3 for 32-bit external-memory
interface, and address pin for 8-bit and 16-bit external-memory interface
External-memory access strobe 1, byte enable 2 for 32-bit external-memory
interface, and address pin for 8-bit external-memory interface
External-memory access strobe 1, byte enable 1 for the external-memory
interface
External-memory access strobe 1, byte enable 0 for the external-memory
interface
Ready. RDY indicates that the external device is prepared for an externalmemory interface transaction to complete.
Hold signal for external-memory interface. When HOLD is a logic low, any
ongoing transaction is completed. A23 –A0, D31 –D0, IOSTRB
STRB1_Bx
transactions over the external-memory interface are held until HOLD
logic high or the NOHOLD bit of the STRB0 bus-control register is set.
Hold acknowledge for external-memory interface. HOLDA is generated in
response to a logic low on HOLD
IOSTRB
that all transactions over the memory are held. HOLDA
logic high of HOLD
is set.
Program memory width select. When PRGW is a logic low, program is fetched as
a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are
performed to fetch a single 32-bit instruction word. The status of PRGW at device
reset affects the reset value of the STRB0 and STRB1 bus-control register.
, and R/W are placed in the high-impedance state, and all
. HOLDA indicates that A23 – A0, D31 – D0,
, STRB0_Bx, STRB1_Bx, and R/W are in the high-impedance state and
is high in response to a
or when the NOHOLD bit of the external bus-control register
, STRB0_Bx,
becomes a
CONDITIONS
WHEN
SIGNAL IS
IN HIGH Z
S H
S H
S H
S H
S H
S H
S H
S H
S H
S
‡
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TYPE
†
DESCRIPTION
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
TMS320C32 Pin Functions (Continued)
PIN
NAME NO.
CONTROL SIGNALS (9 PINS)
Reset. When RESET is a logic low, the device is in the reset condition. When
RESET
RESET 1 I
INT3–INT0 4 I External interrupts
IACK 1 O/Z
MCBL/MP 1 I Microcomputer boot loader/microprocessor mode
XF1–XF0 2 I/O/Z
CLKX0 1 I/O/Z
DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R
FSX0 1 I/O/Z
CLKR0 1 I/O/Z
DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R
FSR0 1 I/O/Z
TCLK0 1 I/O/Z
TCLK1 1 I/O/Z
CLKIN 1 I Input to the internal oscillator from an external clock source
H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S
H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S
EMU0–EMU2 3 I Reserved for emulation. Use 18 kΩ–22 kΩ pullup resistors to 5 V.
EMU3 1 O/Z Reserved for emulation S
SHZ 1 I
†
I = input, O = output, Z = high-impedance state
‡
S = SHZ
active, H = HOLD active, R = RESET active
becomes a logic high, execution begins from the location specified by the
reset vector.
Interrupt acknowledge. IACK is generated by the IACK instruction. This signal can
be used to indicate the beginning or end of an interrupt-service routine.
External flags. XF1 and XF0 are used as general-purpose I/Os or used to support
interlocked-processor instructions.
SERIAL PORT SIGNALS (6 PINS)
Serial-port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the
transmit-data process over DX0.
Serial-port 0 receive clock. CLKR0 is the serial-shift clock for the serial-port 0
receiver.
Frame-synchronization pulse for receive. The FSR0 pulse initiates the
receive-data process over DR0.
TIMER SIGNALS (2 PINS)
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
an output, TCLK0 outputs pulses generated by timer 0.
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
an output, TCLK1 outputs pulses generated by timer 1.
CLOCK SIGNALS (3 PINS)
RESERVED (5 PINS)
Shutdown high impedance. When active, SHZ shuts down the ’C32 and places
all 3-state I/O pins in the high-impedance state. SHZ
to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ
’C32 memory and register contents. Reset the device with SHZ
to a known operating condition.
is used for board-level testing
corrupts
high to restore it
CONDITIONS
WHEN
SIGNAL IS
IN HIGH Z
S
S R
S R
S R
S R
S R
S R
S R
‡
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5
TMS320C32
TYPE
†
DESCRIPTION
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
TMS320C32 Pin Functions (Continued)
PIN
NAME NO.
CV
SS
DV
SS
IV
SS
DV
DD
V
DDL
V
SSL
V
SUBS
†
I = input, O = output, Z = high-impedance state
‡
S = SHZ
§
Recommended decoupling capacitor is 0.1 µF.
active, H = HOLD active, R = RESET active
7 I Ground
7 I Ground
4 I Ground
12 I + 5-V dc supply
8 I + 5-V dc supply
6 I Ground
1 I Substrate, tie to ground
POWER/GROUND
§
§
CONDITIONS
WHEN
SIGNAL IS
IN HIGH Z
‡
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
RESET
INT(3-0)
IACK
XF(1,0)
MCBL / MP
CLKIN
V
V
SHZ
EMU0–3
Program
Cache
(64 × 32)
32 24
32
24
Controller
PDATA Bus
PADDR Bus
DDATA Bus
DADDR1 Bus
Multiplexer
CPU1
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
REG1
IR
PC
H1
H3
DD
SS
RAM
Block 0
(256 × 32)
24
CPU1
CPU2
REG1
REG2
32 32 40 40
REG2
Multiplier
40
40
Extended-
40
Precision
Registers
32
(R0–R7)
DISP0, IR0, IR1
ARAU0 ARAU1
24
Auxiliary
24
Registers
32
(AR0 – AR7)
32
32
Other
32
Registers
RAM
Block 1
(256 × 32)
24 2432 32 32
DMA Controller
DMA Channel 0
Global-Contol Register
Source-AddressRegister
Destination-Address Reg.
Transfer-Counter Reg.
DMA Channel 1
Global-Control Register
Source-AddressRegister
Destination-Address Reg.
Transfer-Counter Reg.
40
40
40
24
24
32
32
BK
(12)
32-Bit
Barrel
Shifter
ALU
Boot
ROM
Multiplexer
Peripheral Data Bus
Peripheral Address Bus
Interface
Multiplexer
STRB0
STRB0 Control Reg.
STRB1
STRB1 Control Reg.
IOSTRB
IOSTRB Control Reg.
Serial Port
Serial Port-
Control Reg.
Receive/Transmit
(R/X)Timer Register
Data-Transmit
Register
Data-Receive
Register
Timer 0
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
Timer 1
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
External
Memory
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
TCLK0
TCLK1
A23 – A0
D31 – D0
R/W
RDY
HOLD
HOLDA
PRGW
STRB0_B3/A
STRB0_B2/A
STRB0_B1
STRB0_B0
STRB1_B3/A
STRB1_B2/A
STRB1_B1
STRB1_B0
IOSTRB
–1
–2
–1
–2
operation
Operation of the TMS320C32 is identical to the TMS320C30 and TMS320C31 digital signal processors, with
the exception of an enhanced external memory interface and the addition of two CPU power-management
modes.
external-memory interface
The TMS320C32 has a configurable external-memory interface with a 24-bit address bus, a 32-bit data bus,
and three independent multifunction strobes. The flexibility of this unique interface enables product designers
to minimize external-memory chip count.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
7
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
external memory interface (continued)
Up to three mutually exclusive memory areas (one program area and two data areas) can be implemented. Each
memory area configuration is independent of the physical memory width and independent of the configuration
of other memory areas. See Figure 1.
8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
32-Bit Program in 16-/32-Bit-
Wide Memory
8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
32-Bit Program in 16-/32-Bit-
Wide Memory
32-Bit Data in 32-Bit-Wide
Memory
32-Bit Program in 32-Bit-
Wide Memory
32-Bit
CPU
StrobeControl
Registers
’C32
PRGW Pin
Memory
Interface
STRB0
STRB1
IOSTRB
Figure 1. ’C32 External Memory Interface
The TMS320C32’s external-memory configuration is controlled by a combination of hardware configuration and
memory-mapped control registers and can be reconfigured dynamically. The signals that control
external-memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows:
D
The TMS320C32 is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The
external-memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit
half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high,
32 bits if the PRGW signal is low.
D
STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of
external-memory addresses. When an address within one of these ranges is accessed by a read or write
instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the
TMS320C32 memory map, showing the address ranges for which the strobe signals become active.
The behavior of the STRB0
and STRB1 control signals is determined by the contents of the STRB0 and STRB1
control registers.
The STRB0
and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or
32 bits) of the external-memory address ranges they control. Another field specifies the data width (8, 16, or
32 bits) of the data contained in those addresses. The values in these fields are not required to match. For
example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four
consecutive 8-bit locations, each having its own address.
Each control-signal set has two pins (STRBx_B2
/A–2 and STRBx_B3/A–1) that can act as either byte-enable
(chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and
STRBx_B1). The pin functions are determined by the physical memory width specified in the corresponding
control register.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
external memory interface (continued)
D
For 8-bit-wide physical memory, the STRBx_B2/A–2 and STRBx_B3/A–1 pins function as address pins
(least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin.
STRBx_B1 is unused. See Figure 2.
TMS320C32
8
Data
STRB0_B3
STRB0_B2/A
/A
STRB0_B1
STRB0_B0
8-Bit Data Bus
A14
A13
A12
.
.
A1
A0
–1
–2
NC
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
8
A14
.
.
A3
A2
A1
A0
Data
Memory
CS
Figure 2. ’C32 With 8-Bit-Wide External Memory
D
For 16-bit-wide physical memory, the STRBx_B3/A–1 pin functions as an address pin (least significant
address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins.
STRBx_B2/A
is unused. See Figure 3.
–2
16
Data
A14
A13
TMS320C32
STRB0_B3/A
STRB0_B2/ A
STRB0_B1
STRB0_B0
A2
A1
A0
–1
–2
16-Bit Data Bus
8
A14
.
.
NC
.
A2
A1
A0
Data
Memory
CS
A14
.
..
A3A3
A2
A1
A0
8
Data
Memory
CS
Figure 3. ’C32 With 16-Bit-Wide External Memory
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
9
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
external memory interface (continued)
D
For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins.
See Figure 4.
32
32-Bit Data Bus
Data
A14
A13
.
.
A2
A1
A0
Data
CS
Memory
A14
A13
.
.
A2
A1
A0
TMS320C32
STRB0_B3/A
STRB0_B2/A
STRB0_B1
STRB0_B0
A14
A13
A2
A1
A0
–1
–2
Data
A14
A13
A2
A1
A0
.
.
Memory
CS
.
.
A14
A13
.
.
A2
A1
A0
Data
Memory
CS
Figure 4. ’C32 With 32-Bit-Wide External Memory
For more detailed information and examples see
(literature number SPRU132) and
Interfacing Memory to the TMS320C32 DSP Application Report
TMS320C32 Addendum to the TMS320C3x User’s Guide
number SPRA040).
D
The IOSTRB control signal, like STRB0 and STRB1, also is mapped to a specific range of addresses but
it is a single signal that can access only 32-bit data from 32-bit-wide memory . Its range of addresses appears
in the TMS320C32 memory map, shown in Figure 8. The IOSTRB
bus timing is different from the STRB0
and STRB1 bus timings to accommodate slower I/O peripherals.
8888
Data
Memory
CS
(literature
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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
external memory interface (continued)
examples
Figure 5 and Figure 6 show examples of external memory configurations that can be implemented using the
TMS320C32 external memory interface. The first example has a 32-bit-wide external memory with 8- and 16-bit
data areas and a 32-bit program area.
32-Bit-Wide Memory
8-Bit Data 8-Bit Data8-Bit Data
32-Bit Program
16-Bit Data16-Bit Data
8 8 8
320C32
32
8-Bit Data
8
32-Bit-Wide Data Bus
Figure 5. 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit Program
Memory
Figure 6 shows a configuration that can be implemented with 16-bit external memory. The 32-bit data and
program words can be stored and retrieved as half-words.
16-Bit-Wide Memory
8-Bit Data
320C32
8-Bit Data
32-Bit Program
16-Bit Data
16
16-Bit-Wide Data Bus
88
Figure 6. 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit Program
Area
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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
external memory interface (continued)
Figure 7 shows one possible configuration that can be implemented with 8-bit external memory. Program words,
which are 32-bit, cannot be executed from 8-bit-wide memory.
8-Bit-Wide Memory
8-Bit Data
320C32
16-Bit Data
8
8-Bit-Wide Data Bus
8
Figure 7. 8-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas
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ИИИИИИИИИИ
ИИИИИИИИИИ
ИИИИИИИИИИ
memory map
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
Figure 8 depicts the memory map for the TMS320C32. Refer to theTMS320C32 Addendum to the
User’s Guide
(literature number SPRU132) for a detailed description of this memory mapping, with shading to
indicate external memory.
0h
7FFFFFh
800000h
807FFFh
808000h
8097FFh
809800h
80FFFFh
810000h
Reset-Vector Location
External Memory
Memory-Mapped Registers
(6K-Word Internal)
Active
STRB0
(8.192M Words)
Reserved
(32K Words)
Peripheral-Bus
Reserved
(26K Words)
0h
FFFh
1000h
1001h
7FFFFFh
800000h
807FFFh
808000h
8097FFh
809800h
80FFFFh
810000h
810001h
Reserved for
Boot-Loader Operations
Boot 1
External Memory
STRB0
Active
(8.188M Words)
Reserved
(32K Words)
Peripheral-Bus
Memory-Mapped Registers
(6K-Word Internal)
Reserved
(26K Words)
Boot 2
TMS320C3x
82FFFFh
830000h
87FDFFh
87FE00h
87FEFFh
87FF00h
87FFFFh
880000h
8FFFFFh
900000h
FFFFFFh
External Memory
(314.5K Words)
(256-Word Internal)
(256-Word Internal)
External Memory
External Memory
STRB1
(7.168M Words)
Microprocessor Mode Microcomputer/Boot-LoaderMode
Active
IOSTRB
(128K Words)
Reserved
RAM Block 0
RAM Block 1
STRB0 Active
(512K Words)
Active
82FFFFh
830000h
87FDFFh
87FE00h
87FEFFh
87FF00h
87FFFFh
880000h
8FFFFFh
900000h
900001h
FFFFFFh
RAM Block 0 (256-Word Internal)
RAM Block 1 (256-Word Internal)
External Memory
IOSTRB
(319.5K Words)
External Memory
External Memory
(7.168M Words)
Active
(128K Words)
Reserved
Active
STRB0
(512K Words)
Boot 3
STRB1
Active
Figure 8. TMS320C32 Memory Map
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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
power management
The TMS320C32 CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2
mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the
external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal
is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to
execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN
frequency divided by 16 (that is, TMS320C32 with a 32-MHz CLKIN frequency performs the same as a 2-MHz
TMS320C32 with an instruction cycle time of 1000 ns (1 MHz).
boot loader
The TMS320C32 flexible boot loader loads programs from the serial port, EPROM, or other standard
non-volatile memory device. The boot-loader functionality of the TMS320C32 is equivalent to that of the
TMS320C31, and has added modes to handle the data-type sizes and memory widths supported by the external
memory interface. The memory-boot load supports data transfers with and without handshaking. The
handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and
data-ready signals.
peripherals
The TMS320C32 peripherals are composed of one serial port, two timers, and two DMA channels. The serial
port and timers are the functional equivalent of those in the TMS320C31 peripherals. The TMS320C32
two-channel DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA.
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