Texas instruments TMS320C28341, TMS320C28345, TMS320C28344, TMS320C28346, TMS320C28342 Data Manual

...

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

Delfino Microcontrollers

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS516B

March 2009–Revised July 2010

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Contents

1 TMS320C2834x ( Delfino™) MCUs ....................................................................................... 11

1.1 Overview .................................................................................................................... 11

1.2 Features .................................................................................................................... 11

1.3 Getting Started ............................................................................................................. 12

2 Introduction ...................................................................................................................... 13

2.1 Pin Assignments ........................................................................................................... 16

2.2 Signal Descriptions ........................................................................................................ 24

3 Functional Overview .......................................................................................................... 35

3.1 Memory Maps .............................................................................................................. 36

3.2 Brief Descriptions .......................................................................................................... 41

3.2.1 C28x CPU ....................................................................................................... 41

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 41

3.2.3 Peripheral Bus .................................................................................................. 41

3.2.4 Real-Time JTAG and Analysis ................................................................................ 42

3.2.5 External Interface (XINTF) .................................................................................... 42

3.2.6 M0, M1 SARAMs ............................................................................................... 42

3.2.7 L0, L1, L2, L3, L4, L5, L6, L7 , H0, H1, H2, H3, H4, H5 SARAMs ....................................... 42

3.2.8 Boot ROM ....................................................................................................... 43

3.2.9 Security .......................................................................................................... 43

3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 44

3.2.11 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 44

3.2.12 Oscillator and PLL .............................................................................................. 44

3.2.13 Watchdog ........................................................................................................ 44

3.2.14 Peripheral Clocking ............................................................................................. 44

3.2.15 Low-Power Modes .............................................................................................. 44

3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 45

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 45

3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 45

3.2.19 Control Peripherals ............................................................................................. 46

3.2.20 Serial Port Peripherals ......................................................................................... 46

3.3 Register Map ............................................................................................................... 47

3.4 Device Emulation Registers .............................................................................................. 48

3.5 Interrupts .................................................................................................................... 49

3.5.1 External Interrupts .............................................................................................. 53

3.6 System Control ............................................................................................................ 54

3.6.1 OSC and PLL Block ............................................................................................ 55

3.6.1.1 External Reference Oscillator Clock Option .................................................... 57

3.6.1.2 PLL-Based Clock Module ......................................................................... 58

3.6.1.3 Loss of Input Clock ................................................................................ 59

3.6.2 Watchdog Block ................................................................................................. 60

3.7 Low-Power Modes Block ................................................................................................. 61

4 Peripherals ....................................................................................................................... 62

4.1 DMA Overview ............................................................................................................. 62

4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 64

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 /7/8/9) ................................................................. 66

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

4.4 High-Resolution PWM (HRPWM) ....................................................................................... 70

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 71

4.6 Enhanced QEP Modules (eQEP1/2 /3) ................................................................................. 73

4.7 External ADC Interface ................................................................................................... 75

4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 76

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 79

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 85

4.11 Serial Peripheral Interface (SPI) Module (SPI-A , SPI-D) ............................................................ 89

4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 92

4.13 GPIO MUX ................................................................................................................. 93

4.14 External Interface (XINTF) .............................................................................................. 100

SPRS516B–MARCH 2009–REVISED JULY 2010

5 Device Support ................................................................................................................ 102

5.1 Device and Development Support Tool Nomenclature ............................................................. 102

5.2 Documentation Support ................................................................................................. 104

6 Electrical Specifications ................................................................................................... 108

6.1 Absolute Maximum Ratings ............................................................................................. 108

6.2 Recommended Operating Conditions ................................................................................. 109

6.3 Electrical Characteristics ................................................................................................ 109

6.4 Current Consumption .................................................................................................... 110

6.4.1 Reducing Current Consumption ............................................................................. 112

6.5 Thermal Design Considerations ........................................................................................ 114

6.6 Emulator Connection Without Signal Buffering for the MCU ....................................................... 114

6.7 Timing Parameter Symbology .......................................................................................... 115

6.7.1 General Notes on Timing Parameters ...................................................................... 115

6.7.2 Test Load Circuit .............................................................................................. 115

6.7.3 Device Clock Table ........................................................................................... 116

6.8 Clock Requirements and Characteristics ............................................................................. 118

6.9 Power Sequencing ....................................................................................................... 119

6.9.1 Power Management and Supervisory Circuit Solutions .................................................. 120

6.10 General-Purpose Input/Output (GPIO) ................................................................................ 123

6.10.1 GPIO - Output Timing ........................................................................................ 123

6.10.2 GPIO - Input Timing .......................................................................................... 124

6.10.3 Sampling Window Width for Input Signals ................................................................. 125

6.10.4 Low-Power Mode Wakeup Timing .......................................................................... 126

6.11 Enhanced Control Peripherals ......................................................................................... 129

6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 129

6.11.2 Trip-Zone Input Timing ....................................................................................... 129

6.11.3 Enhanced Capture (eCAP) Timing ......................................................................... 130

6.11.4 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 130

6.11.5 ADC Start-of-Conversion Timing ............................................................................ 131

6.12 External Interrupt Timing ................................................................................................ 131

6.13 I2C Electrical Specification and Timing ............................................................................... 132

6.14 Serial Peripheral Interface (SPI) Timing .............................................................................. 132

6.14.1 Master Mode Timing .......................................................................................... 132

6.14.2 SPI Slave Mode Timing ...................................................................................... 137

6.15 External Interface (XINTF) Timing ..................................................................................... 140

6.15.1 USEREADY = 0 ............................................................................................... 140

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 141

6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 142

6.15.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 144

6.15.5 External Interface Read Timing ............................................................................. 145

6.15.6 External Interface Write Timing ............................................................................. 147

6.15.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 149

6.15.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 152

6.15.9 XHOLD and XHOLDA Timing ............................................................................... 155

6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 157

6.16.1 McBSP Transmit and Receive Timing ...................................................................... 157

6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 160

www.ti.com

7 Revision History .............................................................................................................. 164

8 Thermal/Mechanical Data .................................................................................................. 165

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

List of Figures

2-1 C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew) .......................................... 17

2-2 C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View)......................................... 18

2-3 C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View)........................................... 19

2-4 C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View)......................................... 20

2-5 C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View) ................................................. 21

2-6 C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View) ............................................... 22

2-7 C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View) ................................................. 23

2-8 C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View) ............................................... 23

3-1 Functional Block Diagram ...................................................................................................... 36

3-2 C28346/C28345 Memory Map ................................................................................................. 38

3-3 C28344/C28343 Memory Map ................................................................................................. 39

3-4 C28342, C28341 Memory Map ................................................................................................ 40

3-5 External and PIE Interrupt Sources............................................................................................ 50

3-6 External Interrupts................................................................................................................ 50

3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 51

3-8 Clock and Reset Domains ...................................................................................................... 54

3-9 OSC and PLL Block Diagram................................................................................................... 55

3-10 Using a 3.3-V External Oscillator............................................................................................... 56

3-11 Using a 1. 8-V External Oscillator.............................................................................................. 56

3-12 Using the Internal Oscillator .................................................................................................... 56

3-13 Watchdog Module................................................................................................................ 60

4-1 DMA Functional Block Diagram ................................................................................................ 63

4-2 CPU-Timers....................................................................................................................... 64

4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 64

4-4 Generation of SOC Pulses to the External ADC Module ................................................................... 66

4-5 ePWM Submodules Showing Critical Internal Signal Interconnections................................................... 69

4-6 eCAP Functional Block Diagram ............................................................................................... 71

4-7 eQEP Functional Block Diagram............................................................................................... 73

4-8 External ADC Interface .......................................................................................................... 75

4-9 McBSP Module .................................................................................................................. 77

4-10 eCAN Block Diagram and Interface Circuit ................................................................................... 80

4-11 eCAN-A Memory Map ........................................................................................................... 82

4-12 eCAN-B Memory Map ........................................................................................................... 83

4-13 Serial Communications Interface (SCI) Module Block Diagram............................................................ 88

4-14 SPI Module Block Diagram (Slave Mode) .................................................................................... 91

4-15 I2C Peripheral Module Interfaces .............................................................................................. 92

4-16 GPIO MUX Block Diagram...................................................................................................... 94

4-17 Qualification Using Sampling Window......................................................................................... 99

4-18 External Interface Block Diagram............................................................................................. 100

4-19 Typical 16-bit Data Bus XINTF Connections................................................................................ 101

4-20 Typical 32-bit Data Bus XINTF Connections................................................................................ 101

5-1 Example of C2834x Device Nomenclature.................................................................................. 103

6-1 Temperature Versus Leakage Current (Typical)............................................................................ 112

6-2 Emulator Connection Without Signal Buffering for the MCU ............................................................. 114

6-3 3.3-V Test Load Circuit......................................................................................................... 115

6-4 Clock Timing..................................................................................................................... 118

6-5 Power-on Reset ................................................................................................................. 121

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

6-6 Warm Reset ..................................................................................................................... 122

6-7 Example of Effect of Writing Into PLLCR Register ......................................................................... 123

6-8 General-Purpose Output Timing.............................................................................................. 124

6-9 Sampling Mode ................................................................................................................. 124

6-10 General-Purpose Input Timing................................................................................................ 125

6-11 IDLE Entry and Exit Timing.................................................................................................... 126

6-12 STANDBY Entry and Exit Timing Diagram.................................................................................. 127

6-13 HALT Wake-Up Using GPIOn................................................................................................. 128

6-14 PWM Hi-Z Characteristics..................................................................................................... 129

6-15 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 131

6-16 External Interrupt Timing....................................................................................................... 131

6-17 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 134

6-18 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 136

6-19 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 138

6-20 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 139

6-21 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 143

6-22 Example Read Access......................................................................................................... 146

6-23 Example Write Access......................................................................................................... 148

6-24 Example Read With Synchronous XREADY Access ...................................................................... 150

6-25 Example Read With Asynchronous XREADY Access..................................................................... 151

6-26 Write With Synchronous XREADY Access.................................................................................. 153

6-27 Write With Asynchronous XREADY Access ................................................................................ 154

6-28 External Interface Hold Waveform............................................................................................ 156

6-29 McBSP Receive Timing........................................................................................................ 159

6-30 McBSP Transmit Timing....................................................................................................... 159

6-31 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 160

6-32 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 161

6-33 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 162

6-34 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 163

www.ti.com

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

List of Tables

2-1 C2834x Hardware Features .................................................................................................... 14

2-2 Signal Descriptions............................................................................................................... 24

3-1 Wait-states ........................................................................................................................ 40

3-2 Boot Mode Selection............................................................................................................. 43

3-3 Peripheral Frame 0 Registers .................................................................................................. 47

3-4 Peripheral Frame 1 Registers .................................................................................................. 47

3-5 Peripheral Frame 2 Registers .................................................................................................. 48

3-6 Peripheral Frame 3 Registers .................................................................................................. 48

3-7 Device Emulation Registers..................................................................................................... 48

3-8 PIE Peripheral Interrupts ....................................................................................................... 51

3-9 PIE Configuration and Control Registers...................................................................................... 52

3-10 External Interrupt Registers..................................................................................................... 53

3-11 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 55

3-12 PLL Settings ...................................................................................................................... 58

3-13 CLKIN Divide Options ........................................................................................................... 58

3-14 Possible PLL Configuration Modes ............................................................................................ 59

3-15 Low-Power Modes ............................................................................................................... 61

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 65

4-2 ePWM1-4 Control and Status Registers ...................................................................................... 67

4-3 ePWM5-9 Control and Status Registers ...................................................................................... 68

4-4 eCAP Control and Status Registers ........................................................................................... 72

4-5 eQEP Control and Status Registers ........................................................................................... 74

4-6 External ADC Interface Registers ............................................................................................. 75

4-7 McBSP Register Summary...................................................................................................... 78

4-8 3.3-V eCAN Transceivers ...................................................................................................... 81

4-9 CAN Register Map .............................................................................................................. 84

4-10 SCI-A Registers .................................................................................................................. 86

4-11 SCI-B Registers .................................................................................................................. 86

4-12 SCI-C Registers ................................................................................................................. 87

4-13 SPI-A Registers................................................................................................................... 90

4-14 SPI-D Registers .................................................................................................................. 90

4-15 I2C-A Registers................................................................................................................... 93

4-16 GPIO Registers .................................................................................................................. 95

4-17 GPIO-A Mux Peripheral Selection Matrix .................................................................................... 96

4-18 GPIO-B Mux Peripheral Selection Matrix .................................................................................... 97

4-19 GPIO-C Mux Peripheral Selection Matrix .................................................................................... 98

4-20 XINTF Configuration and Control Register Mapping....................................................................... 101

5-1 TMS320x2834x Delfino Peripheral Selection Guide ....................................................................... 104

6-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT................. 110

6-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT................. 111

6-3 Typical Current Consumption by Various Peripherals .................................................................... 113

6-4 Clocking and Nomenclature (300-MHz Devices) ........................................................................... 116

6-5 Clocking and Nomenclature (200-MHz Devices) ........................................................................... 117

6-6 XCLKIN/X1 Timing Requirements – PLL Enabled ......................................................................... 118

6-7 XCLKIN/X1 Timing Requirements – PLL Disabled ........................................................................ 118

6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 118

6-9 Power Management and Supervisory Circuit Solutions ................................................................... 120

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

6-10 Reset (XRS) Timing Requirements .......................................................................................... 122

6-11 General-Purpose Output Switching Characteristics........................................................................ 123

6-12 General-Purpose Input Timing Requirements .............................................................................. 124

6-13 IDLE Mode Timing Requirements ........................................................................................... 126

6-14 IDLE Mode Switching Characteristics ....................................................................................... 126

6-15 STANDBY Mode Timing Requirements ..................................................................................... 127

6-16 STANDBY Mode Switching Characteristics ................................................................................ 127

6-17 HALT Mode Timing Requirements ........................................................................................... 128

6-18 HALT Mode Switching Characteristics ...................................................................................... 128

6-19 ePWM Timing Requirements ................................................................................................. 129

6-20 ePWM Switching Characteristics ............................................................................................ 129

6-21 Trip-Zone Input Timing Requirements ...................................................................................... 129

6-22 High-Resolution PWM Characteristics at SYSCLKOUT = ( 150– 300 MHz) ........................................... 130

6-23 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 130

6-24 eCAP Switching Characteristics ............................................................................................. 130

6-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 130

6-26 eQEP Switching Characteristics ............................................................................................. 130

6-27 External ADC Start-of-Conversion Switching Characteristics............................................................. 131

6-28 External Interrupt Timing Requirements .................................................................................... 131

6-29 External Interrupt Switching Characteristics ................................................................................ 131

6-30 I2C Timing ...................................................................................................................... 132

6-31 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 133

6-32 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 135

6-33 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 137

6-34 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 139

6-35 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 140

6-36 XINTF Clock Configurations for SYSCLKOUT = 300 MHz ............................................................... 143

6-37 External Interface Read Timing Requirements ............................................................................. 145

6-38 External Interface Read Switching Characteristics......................................................................... 145

6-39 External Interface Write Switching Characteristics......................................................................... 147

6-40 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 149

6-41 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 149

6-42 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 149

6-43 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 149

6-44 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 152

6-45 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 152

6-46 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 152

6-47 XHOLD/XHOLDA Timing Requirements .................................................................................... 155

6-48 McBSP Timing Requirements ................................................................................................ 157

6-49 McBSP Switching Characteristics ........................................................................................... 158

6-50 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 160

6-51 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................ 160

6-52 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 161

6-53 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................ 161

6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 162

6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................ 162

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 163

6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 163

www.ti.com

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

8-1 Thermal Model 179-Ball ZHH Results ....................................................................................... 165

8-2 Thermal Model 256-Ball ZFE Results ....................................................................................... 165

SPRS516B–MARCH 2009–REVISED JULY 2010

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Delfino Microcontrollers

Check for Samples: TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, TMS320C28341

1 TMS320C2834x ( Delfino™) MCUs

1.1 Overview

The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x high-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance, and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the C28x™ core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency core make the C2834x an excellent solution for performance-hungry real-time control applications.

1.2 Features

1234

• High-Performance Static CMOS Technology – Up to 300 MHz (3.33-ns Cycle Time) – 1.1-V/1.2-V Core, 3.3-V I/O , 1.8-V

PLL/Oscillator Design

• High-Performance 32-Bit CPU (TMS320C28x) – IEEE-754 Single-Precision Floating-Point

Unit (FPU) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Fast Interrupt Response and Processing – Code-Efficient (in C/C++ and Assembly)

• Six-Channel DMA Controller (for McBSP, XINTF, and SARAM)

• 16-Bit or 32-Bit External Interface (XINTF) – Over 2M x 16 Address Reach

• On-Chip Memory – Up to 258K x 16 SARAM – 8K x 16 Boot ROM

• Clock and System Control – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• Peripheral Interrupt Expansion (PIE) Block That Supports All 64 Peripheral Interrupts

• Enhanced Control Peripherals – Eighteen Enhanced Pulse Width Modulator

(ePWM) Outputs

• Dedicated 16-Bit Time-Based Counter With Period and Frequency Control

• Single-Edge, Dual-Edge Symmetric, or Dual-Edge Asymmetric Outputs

• Dead-Band Generation

• PWM Chopping by High-Frequency Carrier

• Trip Zone Input

• Up to 9 HRPWM Outputs With 55-ps MEP Resolution at VDD= 1.1 V (65 ps at 1.2 V)

– Six 32-Bit Enhanced Capture (eCAP)

Modules

• Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator Outputs

• Single-Shot Capture of up to Four Event Time-Stamps

– Three 32-Bit Quadrature Encoder Pulse

(QEP) Modules

– Six 32-Bit Timers/Nine 16-Bit Timers

• Three 32-Bit CPU Timers

• Serial Port Peripherals – Up to 2 CAN Modules – Up to 3 SCI (UART) Modules – Up to 2 McBSP Modules (Configurable as

SPI) – Up to 2 SPI Module s – One Inter-Integrated-Circuit (I2C) Bus

• External ADC Interface

• Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Delfino, MicroStar BGA, C28x, TMS320C54x, TMS320C55x, Code Composer Studio, TMS320C28x are trademarks of Texas Instruments. 31-Wire is a registered trademark of Maxim Integrated Products, Inc. 4All other trademarks are the property of their respective owners.

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

• 2834x Package Options: • Community Resources – MicroStar BGA™ (ZHH) – TI E2E Community – Plastic BGA (ZFE) – TI Embedded Processors Wiki

1.3 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following:

• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

• TMS320F28x Development and Experimenter's Kits (http://www.ti.com/f28xkits)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

2 Introduction

The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and C28341, respectively. Table 2-1 provides a summary of features for each device.

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 2-1. C2834x Hardware Features

FEATURE TYPE

Package Type – Instruction cycle – 3.33 ns 5 ns 3.33 ns 5 ns 3.33 ns 5 ns

Floating-point unit – Yes Yes Yes Yes Yes Yes Single-access RAM (SARAM) (16-bit word) – 258K 258K 130K 130K 98K 98K Code security for on-chip SARAM blocks – No Boot ROM (8K x 16) – Yes Yes Yes Yes Yes Yes 16-/32-bit External Interface (XINTF) 1 Yes Yes Yes Yes Yes Yes 6-channel Direct Memory Access (DMA) 0 Yes Yes Yes Yes Yes Yes

PWM outputs 0

HRPWM channels 0 3A/4A/5A/6A/ 3A/4A/5A/6A/ 3A/4A/5A/6A/ 3A/4A/5A/6A/

32-bit Capture inputs or auxiliary PWM outputs 0 6 6 6 6 4 4 32-bit QEP channels (four inputs/channel) 0 3 3 3 3 2 2 Watchdog timer – Yes Yes Yes Yes Yes Yes External ADC Interface – Yes Yes Yes Yes Yes Yes 32-bit CPU timers – 3 3 3 3 3 3 Multichannel Buffered Serial Port (McBSP)/SPI 1 2 2 2 2 1 1 Serial Peripheral Interface (SPI) 0 2 2 2 2 2 2 Serial Communications Interface (SCI) 0 3 3 3 3 3 3 Enhanced Controller Area Network (eCAN) 0 2 2 2 2 2 2 Inter-Integrated Circuit (I2C) 0 1 1 1 1 1 1 General-Purpose Input/Output (GPIO) pins

(shared) External interrupts – 8 8 8 8 8 8

(1)

– 88 88 88 88 88 88

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the

peripheral reference guides. (2) TMX samples will come with the ZEP designator. The designator will change to ZFE after TMS. (3) Custom secure versions of these devices are available. See Section 3.2.9, Security, for more details.

C28346 C28345 C28344 C28343 C28342 C28341

(300 MHz) (200 MHz) (300 MHz) (200 MHz) (300 MHz) (200 MHz)

256-Ball ZFE 256-Ball ZFE 179-Ball ZHH 256-Ball ZFE 256-Ball ZFE 179-Ball ZHH 256-Ball ZFE 256-Ball ZFE 179-Ball ZHH

(2)

PBGA

(3)

ePWM1/2/3/ ePWM1/2/3/ ePWM1/2/3/ ePWM1/2/3/ ePWM1/2/3/ ePWM1/2/3/

4/5/6/7/8/9 4/5/6/7/8/9 4/5/6/7/8/9 4/5/6/7/8/9 4/5/6 4/5/6

ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/

7A/8A/9A 7A/8A/9A 7A/8A/9A 7A/8A/9A

PBGA

(2)

BGA PBGA

(3)

(2)

(3)

PBGA

(2)

BGA PBGA

(3)

(2)

(3)

ePWM1A/2A/ ePWM1A/2A/

3A/4A/5A/6A 3A/4A/5A/6A

PBGA

(2)

(3)

BGA

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-1. C2834x Hardware Features (continued)

FEATURE TYPE

T: –40°C to 105°C – ZFE ZFE ZHH ZFE ZFE ZHH ZFE ZFE ZHH

Temperature S: –40°C to 125°C – ZFE ZFE – ZFE ZFE – ZFE ZFE – options

Product status

Q: –40°C to 125°C (Q100 qualification)

(1)

– ZFE ZFE – ZFE ZFE – ZFE ZFE – – TMS TMS TMS TMS TMS TMS

(1) See Section 5.1 for descriptions of device stages.

C28346 C28345 C28344 C28343 C28342 C28341

(300 MHz) (200 MHz) (300 MHz) (200 MHz) (300 MHz) (200 MHz)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

EXTSOC3B

GPIO19/

SCIRXDB/

CANTXA

SPISTEA

GPIO23/ EQEP1I/

MFSXA/

SCIRXDB

GPIO24/

ECAP1/

EQEP2A/

MDXB

EXTSOC1A

EXTSOC2A EXTSOC1B

GPIO21/

EQEP1B/

MDRA/

CANRXB

GPIO20/

EQEP1A/

MDXA/

CANTXB

P P

N N

M M

L L

GPIO18/ SPICLKA/ SCITXDB/

CANRXA

TDI

GPIO16/

SPISIMOA/

CANTXB/

TZ5

GPIO12/

CANTXB/

MDXB

TZ1

EXTSOC3A

K K

J J

H H

1 2 3 4 5

6 7

TDO

1 2

5 6

EXTSOC2B

TRST

GPIO17/

SPISOMIA/

CANRXB/

TZ6

GPIO13/

CANRXB/

MDRB

TZ2

GPIO15/

/ /

SCIRXDB/

MFSXB

TZ4XHOLDA

GPIO25/

ECAP2/

EQEP2B/

MDRB

GPIO22/ EQEP1S/ MCLKXA/ SCITXDB

EXTADCCLK

DDIO

GPIO11/ EPWM6B/ SCIRXDB/

ECAP4

DDIO

GPIO14/

/ /

SCITXDB/

MCLKXB

TZ3XHOLD

DDIO

GPIO26/

ECAP3/

EQEP2I/

MCLKXB

GPIO27/

ECAP4/

EQEP2S/

MFSXB

GPIO33/

SCLA/

EPWMSYNCO/

ADCSOCBO

GPIO32/

SDAA/

EPWMSYNCI/

ADCSOCAO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

2.1 Pin Assignments

The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-1 through Figure 2-4. The 256-ball ZFE plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-5 through

Figure 2-8. Table 2-2 describes the function(s) of each pin.

www.ti.com

Figure 2-1. C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

GPIO49/

ECAP6/

XD30/

SPISOMID

DDIO

GPIO54/

SPISIMOA/

XD25/

EQEP3A

GPIO59/ MFSRA/

XD20/

EPWM7B

GPIO55/

SPISOMIA/

XD24/

EQEP3B

GPIO60/

MCLKRB/

XD19/

EPWM8A

EMU1

GPIO / MFSRB/

XD18/

EPWM8B

GPIO70/

XD9

TCK

EMU0

8 9

10 11 12 13 14

GPIO63/

SCITXDC/

XD16/

EPWM9B

GPIO68/

XD11

XRSIO

GPIO65/

XD14

8 9 10

11 12

XRS

TMS

GPIO67/

XD12

GPIO66/

XD13

GPIO62/

SCIRXDC/

XD17/

EPWM9A

GPIO57/

XD22/

EQEP3I

SPISTEA

GPIO50/

EQEP1A/

XD29/

SPICLKD

GPIO51/

EQEP1B/

XD28/

SPISTED

DDIO

GPIO64/

XD15

GPIO48/

ECAP5/

XD31/

SPISIMOD

GPIO52/

EQEP1S/

XD27

GPIO53/ EQEP1I/

XD26

GPIO56/

SPICLKA/

XD23/

EQEP3S

GPIO58/

MCLKRA/

XD21/

EPWM7A

DDIO

GPIO69/

XD10

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 2-2. C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

GPIO9/ EPWM5B/ SCITXDB/

ECAP3

GPIO10/ EPWM6A/ CANRXB/

ADCSOCBO

GPIO8/

EPWM5A/

CANTXB/

ADCSOCAO

GPIO80/

XA8

GPIO7/

EPWM4B/

MCLKRA/

ECAP2

GPIO4/

EPWM3A

GPIO5/

EPWM3B/

MFSRA/

ECAP1

GPIO3/

EPWM2B/

ECAP5/

MCLKRB

GPIO46/

XA6

DDIO

GPIO85/

XA13

GPIO84/

XA12

GPIO1/

EPWM1B/

ECAP6/

MFSRB

GPIO30/

CANRXA/

XA18

GPIO29/ SCITXDA/

XA19

GPIO81/

XA9

GPIO0/

EPWM1A

GPIO31/

CANTXA/

XA17

GPIO87/

XA15

DDIO

GPIO83/

XA11

GPIO39/

XA16

GPIO86/

XA14

1 2 3 4 5 6 7

DD18

DDIO

GPIO82/

XA10

1 2 3 4 5

6 7

DDIO

GPIO6/

EPWM4A/

EPWMSYNCI/ EPWMSYNCO

GPIO2/

EPWM2A

GPIO47/

XA7

DDIO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Figure 2-3. C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

GPIO71/

XD8

GPIO72/

XD7

GPIO73/

XD6

GPIO35/

SCITXDA/

XR/W

GPIO34/

ECAP1

XREADY

GPIO75/

XD4

GPIO77/

XD2

XCLKIN

GPIO41/

XA1

GPIO38/

XWE0

GPIO36/

SCIRXDA/

XZCS0

GPIO40/

XA0

GPIO44/

XA4

GPIO78/

XD1

8 9 10 11 12 13 14

XCLKOUT

XRD

DDIO

8 9

10 11 12 13 14

DD18

GPIO79/

XD0

SSK

DDIO

GPIO45/

XA5

GPIO42/

XA2

GPIO43/

XA3

GPIO28/

SCIRXDA/

XZCS6

GPIO74/

XD5

XWE1

GPIO76/

XD3

DDIO

GPIO37/

ECAP2/

XZCS7

DDIO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 2-4. C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

DDIO

3 4 5 6 7 8

DDIO

GPIO19/

SCIRXDB/

CANTXA

SPISTEA

GPIO33/

SCLA/

EPWMSYNCO/

ADCSOCBO

GPIO21/

EQEP1B/

MDRA/

CANRXB

GPIO23/ EQEP1I/

MFSXA/

SCIRXDB

GPIO22/ EQEP1S/ MCLKXA/ SCITXDB

GPIO20/

EQEP1A/

MDXA/

CANTXB

GPIO32/

SDAA/

EPWMSYNCI/

ADCSOCAO

GPIO27/

ECAP4/

EQEP2S/

MFSXB

GPIO26/

ECAP3/ EQEP2I/ MCLKXB

GPIO25/

ECAP2/

EQEP2B/

MDRB

GPIO24/

ECAP1/

EQEP2A/

MDXB

TDI

EXTSOC3A

EXTADCCLK

EXTSOC2B

TRST

EXTSOC3B

EXTSOC2A

TDO

GPIO17/

SPISOMIA/

CANRXB/

TZ6

GPIO15/

/ /

SCIRXDB/

MFSXB

TZ4XHOLDA

DDIO

GPIO14/

/ /

SCITXDB/

MCLKXB

TZ3XHOLD

GPIO13/

CANRXB/

MDRB

TZ2

GPIO16/

SPISIMOA/

CANTXB/

TZ5

GPIO18/ SPICLKA/ SCITXDB/

CANRXA

EXTSOC1A EXTSOC1B

DDIO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Figure 2-5. C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

DDIO

11 12

GPIO58/

MCLKRA/

XD21/

EPWM7A

13 14 15 16

GPIO64/

XD15

GPIO59/

MFSRA/

XD20/

EPWM7B

GPIO57/

XD22/

EQEP3I

SPISTEA

GPIO56/

SPICLKA/

XD23/

EQEP3S

DDIO

TCK

GPIO63/

SCITXDC/

XD16/

EPWM9B

GPIO60/

MCLKRB/

XD19/

EPWM8A

GPIO68/

XD11

GPIO66/

XD13

GPIO61/

MFSRB/

XD18/

EPWM8B

GPIO65/

XD14

GPIO69/

XD10

GPIO67/

XD12

GPIO62/

SCIRXDC/

XD17/

EPWM9A

DDIO

GPIO53/ EQEP1I/

XD26

GPIO55/

SPISOMIA/

XD24/

EQEP3B

GPIO54/

SPISIMOA/

XD25/

EQEP3A

DDIO

GPIO50/

EQEP1A/

XD29/

SPICLKD

GPIO52/

EQEP1S/

XD27

GPIO51/

EQEP1B/

XD28/

SPISTED

GPIO49/

ECAP6/

XD30/

SPISOMID

GPIO48/

ECAP5/

XD31/

SPISIMOD

XRS

EMU0

EMU1

TMS

DDIO

XRSIO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 2-6. C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

SSK

DD18

3 4 5 6 7 8

GPIO81/

XA9

GPIO82/

XA10

GPIO84/

XA12

GPIO85/

XA13

GPIO39/

XA16

DDIO

GPIO31/

CANTXA/

XA17

GPIO30/

CANRXA/

XA18

GPIO46/

XA6

GPIO47/

XA7

DDIO

GPIO80/

XA8

GPIO83/

XA11

DDIO

GPIO86/

XA14

DDIO

GPIO87/

XA15

DDIO

GPIO6/

EPWM4A/ EPWMSYNCI/ EPWMSYNCO

GPIO3/

EPWM2B/

ECAP5/

MCLKRB

GPIO12/

CANTXB/

MDXB

TZ1

GPIO9/ EPWM5B/ SCITXDB/

ECAP3

GPIO0/

EPWM1A

GPIO2/

EPWM2A

GPIO5/

EPWM3B/

MFSRA/

ECAP1

GPIO8/

EPWM5A/

CANTXB/

ADCSOCAO

GPIO11/

EPWM6B/

SCIRXDB/

ECAP4

GPIO29/

SCITXDA/

XA19

GPIO1/

EPWM1B/

ECAP6/ MFSRB

GPIO4/

EPWM3A

GPIO7/

EPWM4B/

MCLKRA/

ECAP2

GPIO10/

EPWM6A/

CANRXB/

ADCSOCBO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Figure 2-7. C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

11 12 13 14 15 16

DDIO

DD18

DDIO

GPIO36/

SCIRXDA/

XZCS0

GPIO38/

XWE0

XRD

GPIO77/

XD2

GPIO74/

XD5

GPIO71/

XD8

GPIO34/

ECAP1/

XREADY

GPIO78/

XD1

GPIO75/

XD4

GPIO72/

XD7

GPIO28/

SCIRXDA/

XZCS6

GPIO37/

ECAP2/

XZCS7

GPIO41/

XA1

GPIO43/

XA3

GPIO35/

SCITXDA/

XR/W

XCLKIN

GPIO40/

XA0

GPIO42/

XA2

GPIO44/

XA4

GPIO45/

XA5

XCLKOUT

GPIO79/

XD0

GPIO76/

XD3

GPIO73/

XD6

GPIO70/

XD9

XWE1

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 2-8. C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

2.2 Signal Descriptions

Table 2-2 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral

signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA (typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–GPIO87 are enabled upon reset.

Table 2-2. Signal Descriptions

NAME DESCRIPTION

TRST

TCK

TMS

TDI

TDO

EMU0

EMU1

XCLKOUT

XCLKIN the X1 pin must be tied to V

ZHH ZFE

BALL # BALL #

JTAG

M7 R8 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of

P9 T11 JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers

M8 P9 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP

L6 T8 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction

N7 P8 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)

N9 P10 Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator

L9 R10 Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator

B14 D16 Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the

D9 A12 External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,

C8 A7 Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected

A8 A9 Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it

the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓)

adequate protection.(I)

controller on the rising edge of TCK. (I, ↑)

or data) on a rising edge of TCK. (I, ↑)

are shifted out of TDO on the falling edge of TCK.

system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Clock

frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset.

. If a crystal/resonator is used (or if an external 1.8-V oscillator is

used to feed clock to X1 pin), this pin must be tied to VSS. (I)

across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to V

must be left unconnected. (O)

SSK

www.ti.com

. (I)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

XRS P8 T10

XRSIO N8 T9 low (reset), the level detected on this pin puts all output buffers on the device in high-impedance

EXTSOC1A N1 M2 External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of

EXTSOC1B M3 M3 External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of

EXTSOC2A M2 N1 External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of

EXTSOC2B P1 N2 External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of

EXTSOC3A N2 N3 External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of

EXTSOC3B P2 P2 External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of

EXTADCCLK N3 R3 External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O) ECAP6 Enhanced Capture 6 input/output (I/O) MFSRB McBSP-B receive frame synch (I/O)

GPIO2 General purpose input/output 2 (I/O/Z) EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O) ECAP5 Enhanced Capture 5 input/output (I/O) MCLKRB McBSP-B receive clock (I/O)

GPIO4 General purpose input/output 4 (I/O/Z) EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O) MFSRA McBSP-A receive frame synch (I/O) ECAP1 Enhanced Capture input/output 1 (I/O)

GPIO6 General purpose input/output 6 (I/O/Z) EPWM4A Enhanced PWM4 output A and HRPWM channel (O) EPWMSYNCI External ePWM sync pulse input (I) EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) EPWM4B Enhanced PWM4 output B (O) MCLKRA McBSP-A receive clock (I/O) ECAP2 Enhanced capture input/output 2 (I/O)

ZHH ZFE

BALL # BALL #

Reset

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑) The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.

XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is mode.

External ADC Interface Signals

ePWM1/2/3 SOCA internal signals (O)

ePWM1/2/3 SOCB internal signals (O)

ePWM4/5/6 SOCA internal signals (O)

ePWM4/5/6 SOCB internal signals (O)

ePWM7/8/9 SOCA internal signals (O)

ePWM7/8/9 SOCB internal signals (O)

GPIO and Peripheral Signals

B1 D2

C1 E1

F5 E2

E4 E3

E2 F1

E3 F2

F3 F3

F2 G1

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO8 General Purpose Input/Output 8 (I/O/Z) EPWM5A Enhanced PWM5 output A and HRPWM channel (O) CANTXB Enhanced CAN-B transmit (O) ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) EPWM5B Enhanced PWM5 output B (O) SCITXDB SCI-B transmit data(O) ECAP3 Enhanced capture input/output 3 (I/O)

GPIO10 General purpose input/output 10 (I/O/Z) EPWM6A Enhanced PWM6 output A and HRPWM channel (O) CANRXB Enhanced CAN-B receive (I) ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) EPWM6B Enhanced PWM6 output B (O) SCIRXDB SCI-B receive data (I) ECAP4 Enhanced CAP Input/Output 4 (I/O)

GPIO12 General purpose input/output 12 (I/O/Z) TZ1 Trip Zone input 1 (I) CANTXB Enhanced CAN-B transmit (O) MDXB McBSP-B transmit serial data (O)

GPIO13 General purpose input/output 13 (I/O/Z) TZ2 Trip Zone input 2 (I) CANRXB Enhanced CAN-B receive (I) MDRB McBSP-B receive serial data (I)

GPIO14 General purpose input/output 14 (I/O/Z)

TZ3/XHOLD XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3

SCITXDB SCI-B Transmit (O) MCLKXB McBSP-B transmit clock (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

TZ4/XHOLDA

SCIRXDB SCI-B receive (I) MFSXB McBSP-B transmit frame synch (I/O)

GPIO16 General purpose input/output 16 (I/O/Z) SPISIMOA SPI slave in, master out (I/O) CANTXB Enhanced CAN-B transmit (O) TZ5 Trip Zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) CANRXB Enhanced CAN-B receive (I) TZ6 Trip zone input 6 (I)

GPIO18 General purpose input/output 18 (I/O/Z) SPICLKA SPI-A clock input/output (I/O) SCITXDB SCI-B transmit (O) CANRXA Enhanced CAN-A receive (I)

GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/O) SCIRXDB SCI-B receive (I) CANTXA Enhanced CAN-A transmit (O)

ZHH ZFE

BALL # BALL #

G4 G2

G2 G3

G3 H1

H3 H2

H2 H3

H4 J2

Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing

H5 J3

K2 K2 active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals

K4 L1

J5 L2

L1 M1

P3 T4

goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)

Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven

will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/O)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO20 General purpose input/output 20 (I/O/Z) EQEP1A Enhanced QEP1 input A (I) MDXA McBSP-A transmit serial data (O) CANTXB Enhanced CAN-B transmit (O)

GPIO21 General purpose input/output 21 (I/O/Z) EQEP1B Enhanced QEP1 input B (I) MDRA McBSP-A receive serial data (I) CANRXB Enhanced CAN-B receive (I)

GPIO22 General purpose input/output 22 (I/O/Z) EQEP1S Enhanced QEP1 strobe (I/O) MCLKXA McBSP-A transmit clock (I/O) SCITXDB SCI-B transmit (O)

GPIO23 General purpose input/output 23 (I/O/Z) EQEP1I Enhanced QEP1 index (I/O) MFSXA McBSP-A transmit frame synch (I/O) SCIRXDB SCI-B receive (I)

GPIO24 General purpose input/output 24 (I/O/Z) ECAP1 Enhanced capture 1 (I/O) EQEP2A Enhanced QEP2 input A (I) MDXB McBSP-B transmit serial data (O)

GPIO25 General purpose input/output 25 (I/O/Z) ECAP2 Enhanced capture 2 (I/O) EQEP2B Enhanced QEP2 input B (I) MDRB McBSP-B receive serial data (I)

GPIO26 General purpose input/output 26 (I/O/Z) ECAP3 Enhanced capture 3 (I/O) EQEP2I Enhanced QEP2 index (I/O) MCLKXB McBSP-B transmit clock (I/O)

GPIO27 General purpose input/output 27 (I/O/Z) ECAP4 Enhanced capture 4 (I/O) EQEP2S Enhanced QEP2 strobe (I/O) MFSXB McBSP-B transmit frame synch (I/O)

GPIO28 General purpose input/output 28 (I/O/Z) SCIRXDA A12 B13 SCI receive data (I) XZCS6 External Interface zone 6 chip select (O)

GPIO29 General purpose input/output 29. (I/O/Z) SCITXDA C3 D1 SCI transmit data (O) XA19 External Interface Address Line 19 (O)

GPIO30 General purpose input/output 30 (I/O/Z) CANRXA C2 C2 Enhanced CAN-A receive (I) XA18 External Interface Address Line 18 (O)

GPIO31 General purpose input/output 31 (I/O/Z) CANTXA B2 B3 Enhanced CAN-A transmit (O) XA17 External Interface Address Line 17 (O)

GPIO32 General purpose input/output 32 (I/O/Z) SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I) ADCSOCAO ADC start-of-conversion A (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion B (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z) ECAP1 A13 B14 Enhanced Capture input/output 1 (I/O) XREADY External Interface Ready signal

GPIO35 General-Purpose Input/Output 35 (I/O/Z) SCITXDA B13 C15 SCI-A transmit data (O) XR/W External Interface read, not write strobe

GPIO36 General-Purpose Input/Output 36 (I/O/Z) SCIRXDA B12 A13 SCI-A receive data (I) XZCS0 External Interface zone 0 chip select (O)

ZHH ZFE

BALL # BALL #

L4 R4

M4 T5

N4 R5

P4 P5

P5 T6

M5 R6

K6 P6

M6 T7

P6 R7

N6 P7

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO37 General-Purpose Input/Output 37 (I/O/Z) ECAP2 D11 B12 Enhanced Capture input/output 2 (I/O) XZCS7 External Interface zone 7 chip select (O)

GPIO38 General-Purpose Input/Output 38 (I/O/Z)

- C12 E15 XWE0 External Interface Write Enable 0 (O)

GPIO39 General-Purpose Input/Output 39 (I/O/Z)

- A2 B4 XA16 External Interface Address Line 16 (O)

GPIO40 General-Purpose Input/Output 40 (I/O/Z)

- E10 C12 XA0 External Interface Address Line 0

GPIO41 General-Purpose Input/Output 41 (I/O/Z)

- D10 B11 XA1 External Interface Address Line 1 (O)

GPIO42 General-Purpose Input/Output 42 (I/O/Z)

- B10 C11 XA2 External Interface Address Line 2 (O)

GPIO43 General-Purpose Input/Output 43 (I/O/Z)

- A10 B10 XA3 External Interface Address Line 3 (O)

GPIO44 General-Purpose Input/Output 44 (I/O/Z)

- A9 C10 XA4 External Interface Address Line 4 (O)

GPIO45 General-Purpose Input/Output 45 (I/O/Z)

- B9 C9 XA5 External Interface Address Line 5 (O)

GPIO46 General-Purpose Input/Output 46 (I/O/Z)

- E7 B8 XA6 External Interface Address Line 6 (O)

GPIO47 General-Purpose Input/Output 47 (I/O/Z)

- D6 C8 XA7 External Interface Address Line 7 (O)

GPIO48 General-Purpose Input/Output 48 (I/O/Z) ECAP5 Enhanced Capture input/output 5 (I/O) XD31 External Interface Data Line 31 (O) SPISIMOD SPI-D slave in, master out (I/O)

GPIO49 General-Purpose Input/Output 49 (I/O/Z) ECAP6 Enhanced Capture input/output 6 (I/O) XD30 External Interface Data Line 30 (O) SPISOMID SPI-D slave out, master in (I/O)

GPIO50 General-Purpose Input/Output 50 (I/O/Z) EQEP1A Enhanced QEP 1input A (I) XD29 External Interface Data Line 29 (O) SPICLKD SPI-D Clock input/output (I/O)

GPIO51 General-Purpose Input/Output 51 (I/O/Z) EQEP1B Enhanced QEP 1input B (I) XD28 External Interface Data Line 28 (O) SPISTED SPI-D slave transmit enable input/output (I/O)

GPIO52 General-Purpose Input/Output 52 (I/O/Z) EQEP1S M11 P12 Enhanced QEP 1Strobe (I/O) XD27 External Interface Data Line 27 (O)

GPIO53 General-Purpose Input/Output 53 (I/O/Z) EQEP1I L11 T13 Enhanced QEP1 lndex (I/O) XD26 External Interface Data Line 26 (O)

GPIO54 General-Purpose Input/Output 54 (I/O/Z) SPISIMOA SPI-A slave in, master out (I/O) XD25 External Interface Data Line 25 (O) EQEP3A Enhanced QEP3 input A (I)

ZHH ZFE

BALL # BALL #

M10 R11

P10 P11

N10 T12

N11 R12

P12 R13

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO55 General-Purpose Input/Output 55 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) XD24 External Interface Data Line 24 (O) EQEP3B Enhanced QEP3 input B (I)

GPIO56 General-Purpose Input/Output 56 (I/O/Z) SPICLKA SPI-A clock (I/O) XD23 External Interface Data Line 23 (O) EQEP3S Enhanced QEP3 strobe (I/O)

GPIO57 General-Purpose Input/Output 57 (I/O/Z) SPISTEA SPI-A slave transmit enable (I/O) XD22 External Interface Data Line 22 (O) EQEP3I Enhanced QEP3 index (I/O)

GPIO58 General-Purpose Input/Output 58 (I/O/Z) MCLKRA McBSP-A receive clock (I/O) XD21 External Interface Data Line 21 (O) EPWM7A Enhanced PWM 7 output A and HRPWM channel (O)

GPIO59 General-Purpose Input/Output 59 (I/O/Z) MFSRA McBSP-A receive frame synch (I/O) XD20 External Interface Data Line 20 (O) EPWM7B Enhanced PWM 7 output B (O)

GPIO60 General-Purpose Input/Output 60 (I/O/Z) MCLKRB McBSP-B receive clock (I/O) XD19 External Interface Data Line 19 (O) EPWM8A Enhanced PWM 8 output A and HRPWM channel (O)

GPIO61 General-Purpose Input/Output 61 (I/O/Z) MFSRB McBSP-B receive frame synch (I/O) XD18 External Interface Data Line 18 (O) EPWM8B Enhanced PWM8 output B (O)

GPIO62 General-Purpose Input/Output 62 (I/O/Z) SCIRXDC SCI-C receive data (I) XD17 External Interface Data Line 17 (O) EPWM9A Enhanced PWM9 output A and HRPWM channel (O)

GPIO63 General-Purpose Input/Output 63 (I/O/Z) SCITXDC SCI-C transmit data (O) XD16 External Interface Data Line 16 (O) EPWM9B Enhanced PWM9 output B (O)

GPIO64 General-Purpose Input/Output 64 (I/O/Z)

- K12 L15 XD15 External Interface Data Line 15 (O)

GPIO65 General-Purpose Input/Output 65 (I/O/Z)

- K14 L14 XD14 External Interface Data Line 14 (O)

GPIO66 General-Purpose Input/Output 66 (I/O/Z)

- J11 K15 XD13 External Interface Data Line 13 (O)

GPIO67 General-Purpose Input/Output 67 (I/O/Z)

- J12 K14 XD12 External Interface Data Line 12 (O)

GPIO68 General-Purpose Input/Output 68 (I/O/Z)

- J13 J15 XD11 External Interface Data Line 11 (O)

GPIO69 General-Purpose Input/Output 69 (I/O/Z)

- H13 J14 XD10 External Interface Data Line 10 (O)

GPIO70 General-Purpose Input/Output 70 (I/O/Z)

- H12 H16 XD9 External Interface Data Line 9 (O)

GPIO71 General-Purpose Input/Output 71 (I/O/Z)

- G12 H15 XD8 External Interface Data Line 8 (O)

ZHH ZFE

BALL # BALL #

N12 P13

P13 R14

N13 P15

P14 N16

M13 N15

M14 M16

L12 M15

L13 M14

K13 L16

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO72 General-Purpose Input/Output 72 (I/O/Z)

- G13 H14 XD7 External Interface Data Line 7 (O)

GPIO73 General-Purpose Input/Output 73 (I/O/Z)

- F14 G16 XD6 External Interface Data Line 6 (O)

GPIO74 General-Purpose Input/Output 74 (I/O/Z)

- F13 G15 XD5 External Interface Data Line 5 (O)

GPIO75 General-Purpose Input/Output 75 (I/O/Z)

- F12 G14 XD4 External Interface Data Line 4 (O)

GPIO76 General-Purpose Input/Output 76 (I/O/Z)

- E13 F16 XD3 External Interface Data Line 3 (O)

GPIO77 General-Purpose Input/Output 77 (I/O/Z)

- E11 F15 XD2 External Interface Data Line 2 (O)

GPIO78 General-Purpose Input/Output 78 (I/O/Z)

- F10 F14 XD1 External Interface Data Line 1 (O)

GPIO79 General-Purpose Input/Output 79 (I/O/Z)

- C14 E16 XD0 External Interface Data Line 0 (O)

GPIO80 General-Purpose Input/Output 80 (I/O/Z)

- E6 B7 XA8 External Interface Address Line 8 (O)

GPIO81 General-Purpose Input/Output 81 (I/O/Z)

- C5 C7 XA9 External Interface Address Line 9 (O)

GPIO82 General-Purpose Input/Output 82 (I/O/Z)

- A5 B6 XA10 External Interface Address Line 10 (O)

GPIO83 General-Purpose Input/Output 83 (I/O/Z)

- B5 C6 XA11 External Interface Address Line 11 (O)

GPIO84 General-Purpose Input/Output 84 (I/O/Z)

- D5 A5 XA12 External Interface Address Line 12 (O)

GPIO85 General-Purpose Input/Output 85 (I/O/Z)

- D4 B5 XA13 External Interface Address Line 13 (O)

GPIO86 General-Purpose Input/Output 86 (I/O/Z)

- A3 C5 XA14 External Interface Address Line 14 (O)

GPIO87 General-Purpose Input/Output 87 (I/O/Z)

- B3 A4 XA15 External Interface Address Line 15 (O)

XRD A14 D15 External Interface Read Enable (O) XWE1 C13 E14 External Memory Interface Write Enable for Upper 16-bits (O)

ZHH ZFE

BALL # BALL #

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

DD18

SSK

DDIO

ZHH ZFE

BALL # BALL #

CPU and I/O Power Pins

E8 A6

C7 A11

Oscillator and PLL Power Pin (1.8 V)

B8 A8 Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 3-10

through Figure 3-12 for proper application board connections.

D1 C1

E1 C16

G1 E6

K3 E7 M1 E8 N5 E9

P7 E10

J3 E11

J4 F5

K9 F12

L10 G5 N14 G12 K11 H5 H11 H12 H14 J5

G10 J12

CPU and logic digital power pins (1.1 V/1.2 V)

E12 K3 D12 K5 C11 K12 C10 L3

B7 L5 C6 L12

E5 M6 C4 M7

M9 M10 M11

P16

D3 A3

F1 A14 J1 B9 L2 D5 K5 D6 Digital I/O power pins (3.3 V) K7 D8

K8 D11 P11 D12 L14 E4

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

DDIO

ZHH ZFE

BALL # BALL #

J14 E13 F11 F4 D14 F13 A11 J1

C9 J4 D7 J13

B6 J16

B4 L4

L13

M4 Digital I/O power pins

M13

N5 N6

N8 N11 N12

T14

D2 A1

F4 A2 G5 A10 H1 A15

J2 A16

K1 B1

L3 B2

L5 B15

L7 B16

L8 C3 M9 C4

K10 C13

M12 C14

J10 D3 Digital ground pins

H10 D4 G14 D7 G11 D9

E14 D10

D13 D13

B11 D14

E9 E5

D8 E12

A7 F6 A6 F7 A4 F8

F10

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

ZHH ZFE

BALL # BALL #

F11

G4 G6 G7 G8

G9 G10 G11 G13

H9 H10 H11 H13

J6 J7 J8

J9 J10 J11

K1 K4 K6 K7 K8

K9 K10 K11 K13 K16

L6 L7 L8

L9 L10 L11

M12

N4 N7

N9 N10 N13

Digital ground pins

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 2-2. Signal Descriptions (continued)

NAME DESCRIPTION

ZHH ZFE

BALL # BALL #

N14

P4 P14

R2 R15 R16

T2 T15 T16

Digital ground pins

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

L0SARAM8Kx16

(0-Wait)

L1SARAM8Kx16

(0-Wait)

L2SARAM8Kx16

(0-Wait)

L3SARAM8Kx16

(0-Wait)

L4SARAM8Kx16

(0-Wait)

L5SARAM8Kx16

(0-Wait)

BootROM

8Kx16

DMA Bus

XINTF

XWE0

XZCS6

XZCS7

XZCS0

XR/W

XREADY

XHOLD

XHOLDA

XD31:0

XA19:1

GPIO

MUX

MemoryBus

XCLKOUT

XRD

GPIO

MUX

88GPIOs

8ExternalInterrupts

88GPIOs

ADC

SoC

EXTADCCLK

EXTSOC

CPUTimer0

CPUTimer1

CPUTimer2

OSC,

PLL,

LPM,

DMA 6Ch

PIE

(Interrupts)

32-bitCPU (300MHz@1.2V 200MHz@1.1V)

EMU1

EMU0

TRST

TDO

TMS

TDI

TCK

XRS

XCLKIN

FPU

DMA Bus

MemoryBus

FIFO

(16Levels)

SCI-A/B/C

FIFO

(16Levels)

SPI-A/D

FIFO

(16Levels)

I2C

16-bitperipheralbus

SPISOMIx

SPISIMOx

SPICLKx

SPISTEx

SCIRXDx

SCITXDx

SDAx

SCLx

McBSP-A/B

MRXx

MDXx

MCLKXx

MCLKRx

MFSXx

MFSRx

32-bitperipheralbus

(DMA accessible)

ePWM-1/../9

HRPWM-1/../9

eCAP-1/../6

eQEP-1/2/3

EPWMxA

EPWMxB

ESYNCI

ESYNCO

TZx

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

CAN-A/B

(32-mbox)

CANRXx

CANTXx

M0SARAM1Kx16

(0-Wait)

M1SARAM1Kx16

(0-Wait)

MemoryBus

32-bitperipheralbus

GPIOMUX

88GPIOs

XWE1

H0SARAM32Kx16

(1Wait,Prefetch)

H1SARAM32Kx16

(1Wait,Prefetch)

H2SARAM32Kx16

(1Wait,Prefetch)

H3SARAM32Kx16

(1Wait,Prefetch)

H4SARAM32Kx16

(1Wait,Prefetch)

H5SARAM32Kx16

(1Wait,Prefetch)

L6SARAM8Kx16

(1-Wait)

L7SARAM8Kx16

(1-Wait)

DMA Bus

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3 Functional Overview

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 3-1. Functional Block Diagram

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.1 Memory Maps

In Figure 3-2 through Figure 3-4, the following apply:

• Memory blocks are not to scale.

• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.

• Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more details.

• Certain memory ranges are EALLOW protected against spurious writes after configuration.

• If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

Reserved

L0SARAM(8Kx16,DMA Accessible)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(8Kx16, DMA Accessible)

H0SARAM

(32Kx16Prefetch)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x00 A000

0x300000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone0(4Kx16, )XZCS0

(Protected)DMA Accessible

Reserved

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps-M0vector,PIEvector,BROMvector-shouldbeenabledatatime.

LEGEND:

L2SARAM(8Kx16, DMA Accessible)

L3SARAM(8Kx16, DMA Accessible)

L4SARAM(8Kx16,DMA Accessible)

L5SARAM(8Kx16,DMA Accessible)

0x00C000

0x00E000

0x010000

0x012000

0x014000

Reserved

0x004000

0x005000

PeripheralFrame3

(Protected)DMA Accessible

0x308000

0x310000

0x328000

0x33FFF8

0x33FFFF

0x3FE000

PeripheralFrame0

XINTFZone6(1Mx16, )(DMA Accessible)XZCS6

0x100000

0x200000

0x300000

XINTFZone7(1Mx16, )XZCS7 (DMAAccessible)

0x318000

0x330000

0x320000

H1SARAM

(32Kx16Prefetch)

H2SARAM

(32Kx16Prefetch)

H3SARAM

(32Kx16Prefetch)

H4SARAM

(32Kx16Prefetch)

H5SARAM

(32Kx16Prefetch)

128-BitPassword

(A)

Reserved

L6SARAM(8Kx16,DMA Accessible)

L7SARAM(8Kx16,DMA Accessible)

0x016000

0x018000

Reserved

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.

Figure 3-2. C28346/C28345 Memory Map

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

Reserved

L0SARAM(8Kx16, )DMA Accessible

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(8Kx16, )

DMA Accessible

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x00 A000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone0(4Kx16, )

(Protected)DMA Accessible

XZCS0

Reserved

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps-M0vector,PIEvector,BROMvector-shouldbeenabledatatime.

LEGEND:

L2SARAM(8Kx16, )DMA Accessible

L3SARAM(8Kx16, )DMA Accessible

L4SARAM(8Kx16,DMA Accessible)

L5SARAM(8Kx16,DMA Accessible)

0x00C000

0x00E000

0x010000

0x012000

0x014000

Reserved

0x004000

0x005000

PeripheralFrame3

(Protected)DMA Accessible

0x33FFF8

0x33FFFF

0x3FE000

PeripheralFrame0

XINTFZone6(1Mx16, )(DMA Accessible)XZCS6

0x100000

0x200000

0x300000

XINTFZone7(1Mx16, )XZCS7 (DMAAccessible)

H0SARAM

(32Kx16Prefetch)

0x300000

0x308000

0x310000

H1SARAM

(32Kx16Prefetch)

128-BitPassword

(A)

Reserved

L6SARAM(8Kx16,DMA Accessible)

L7SARAM(8Kx16,DMA Accessible)

0x016000

0x018000

Reserved

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.

Figure 3-3. C28344/C28343 Memory Map

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

Reserved

L0SARAM(8Kx16, )DMA Accessible

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(8Kx16, )

DMA Accessible

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x00 A000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone0(4Kx16, )

(Protected)

XZCS0

DMA Accessible

Reserved

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps-M0vector,PIEvector,BROMvector-shouldbeenabledatatime.

LEGEND:

L2SARAM(8Kx16, )DMA Accessible

L3SARAM(8Kx16, )DMA Accessible

0x00C000

0x00E000

0x010000

Reserved

0x004000

0x005000

PeripheralFrame3

(Protected)DMA Accessible

0x33FFF8

0x33FFFF

0x3FE000

PeripheralFrame0

XINTFZone6(1Mx16, )(DMA Accessible)XZCS6

0x100000

0x200000

0x300000

XINTFZone7(1Mx16, )XZCS7 (DMAAccessible)

H0SARAM

(32Kx16Prefetch)

0x300000

0x308000

0x310000

H1SARAM

(32Kx16Prefetch)

128-BitPassword

(A)

Reserved

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.

Figure 3-4. C28342, C28341 Memory Map

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-1 .

Table 3-1. Wait-states

AREA COMMENTS

M0 and M1 SARAMs 0-wait No access Fixed

Peripheral Frame 0 0-wait (writes) No access (writes)

Peripheral Frame 3 0-wait (writes) 0-wait (writes) Assumes no conflicts between CPU and DMA.

Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.

Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.

L0 SARAM 0-wait data and Assumes no CPU conflicts L1 SARAM L2 SARAM L3 SARAM L4 SARAM 1-wait Assumes no conflicts between CPU and DMA L5 SARAM L6 SARAM 1-wait L7 SARAM

XINTF Programmable Programmed via the XTIMING registers or extendable via

H0 SARAM 1-wait A program-access prefetch mechanism is enabled on these H1 SARAM H2 SARAM H3 SARAM H4 SARAM H5 SARAM

Boot-ROM 1-wait No access

(1) The DMA has a base of 4 cycles/word.

WAIT-STATES WAIT-STATES

(CPU) (DMA)

1-wait (reads) 0-wait (reads)

2-wait (reads) 1-wait (reads)

2-wait (reads) Consecutive writes to the CAN will experience a 1-cycle

2-wait (reads)

program

1-wait minimum 1-wait is minimum wait states allowed on external waveforms

0-wait minimum writes 0-wait data (write) 0-wait minimum for writes assumes write buffer enabled and

with write buffer 0-wait data (read) not full.

enabled Assumes no conflicts between CPU and DMA. When DMA

(1)

No access

pipeline hit.

No access

external XREADY signal.

for both reads and writes on XINTF.

and CPU attempt simultaneous conflict, 1-cycle delay is added for arbitration.

memories to improve instruction fetch performance for linear code execution.

No access

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3.2 Brief Descriptions

3.2.1 C28x CPU

The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. It also enables math algorithms to be developed using C/C++. The device is as efficient at DSP math tasks as it is at system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many MCU type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

SPRS516B–MARCH 2009–REVISED JULY 2010

Highest: Data Writes (Simultaneous data and program writes cannot occur on the

Program Writes (Simultaneous data and program writes cannot occur on the

Data Reads Program (Simultaneous program reads and fetches cannot occur on the

Reads memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the C2834x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).

memory bus.)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.2.4 Real-Time JTAG and Analysis

The C2834x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to the C2834x device, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generate various user-selectable break events when a match occurs.

3.2.5 External Interface (XINTF)

This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals.

3.2.6 M0, M1 SARAMs

All C2834x devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages.

www.ti.com

3.2.7 L0, L1, L2, L3, L4, L5, L6, L7 , H0, H1, H2, H3, H4, H5 SARAMs

The 2834x has up to 256K × 16 single-access RAM (SARAM) divided up into the following categories:

L0/1/2/3/4/5 SARAM Blocks Up to 48K × 16 of SARAM at all frequencies. Each block is

8K × 16.

L6/L7 SARAM Blocks These 8K × 16 SARAM blocks are single-wait state at all

frequencies.

H0/1/2/3/4/5 SARAM Blocks H0–H5 are each 32K × 16 and 1-wait state at all

frequencies. A program-access prefetch buffer is used to improve performance of linear code.

All SARAM blocks are mapped to both program and data space. L0–L7 are accessible by both the CPU and the DMA (1 wait state).

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

3.2.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.

Table 3-2. Boot Mode Selection

MODE GPIO87/XA15 GPIO86/XA14 GPIO85/XA13 GPIO84/XA12 MODE

F 1 1 1 1 Secure boot

E 1 1 1 0 SCI-A boot D 1 1 0 1 SPI-A boot C 1 1 0 0 I2C-A boot Timing 1

B 1 0 1 1 eCAN-A boot Timing 1

A 1 0 1 0 McBSP-A boot

9 1 0 0 1 Jump to XINTF x16

8 1 0 0 0 Reserved

7 0 1 1 1 eCAN-A boot Timing 2

6 0 1 1 0 Parallel GPIO I/O boot

5 0 1 0 1 Parallel XINTF boot

4 0 1 0 0 Jump to SARAM

3 0 0 1 1 Branch to check boot mode

2 0 0 1 0 I2C-A boot Timing 2

1 0 0 0 1 Reserved

0 0 0 0 0 TI Test Only

(1) All four GPIO pins have an internal pullup. (2) This mode is available on secure devices only. See Section 3.2.9, Security.

(2)

(1)

3.2.9 Security

The 128-bit password locations on these devices will always read back 0xFFFF. To preserve compatibility with other C28x designs with code security, the password locations at 0x33FFF8–0x33FFFF must be read after a device reset; otherwise, certain memory locations will be inaccessible. The Boot ROM code performs this read during startup. If during debug the Boot ROM is bypassed, then it is the responsibility of the application software to read the password locations after a reset.

Custom Encryption: Activating the Code Security Module (CSM) and Emulation Code Security Logic (ECSL)

Custom secure versions of these devices are available which enable the CSM and ECSL logic on these devices. In the custom version, the 128-bit password locations are set to a customer-chosen value, activating the Code Security Module (CSM), which protects the Hx RAM memories from unauthorized access. Additionally, a TI-generated AES decryption routine is embedded into an on-chip secure ROM, providing a method to secure application code that is stored externally. Contact TI at support@ti.com for more details.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.2.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the C2834x, 64 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.11 External Interrupts (XINT1–XINT7, XNMI)

The devices support eight masked external interrupts (XINT1–XINT7, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1, XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0–GPIO31 pins. XINT3–XINT7 interrupts can accept inputs from GPIO32–GPIO63 pins.

3.2.12 Oscillator and PLL

www.ti.com

The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 31 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.13 Watchdog

The devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be disabled if necessary.

3.2.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.15 Low-Power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event

HALT: Turns off the internal oscillator. This mode basically shuts down the device and

places it in the lowest possible power consumption mode. A reset or external signal can wake the device from this mode.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn)

The device segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

XINTF: External Interface Registers DMA DMA Registers Timers: CPU-Timers 0, 1, 2 Registers

PF1: eCAN: eCAN Mailbox and Control Registers

GPIO: GPIO MUX Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: External ADC Interface I2C: Inter-Integrated Circuit Module and Registers XINT External Interrupt Registers

PF3: McBSP Multichannel Buffered Serial Port Registers

SPRS516B–MARCH 2009–REVISED JULY 2010

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes.

3.2.18 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.2.19 Control Peripherals

The C2834x devices support the following peripherals which are used for embedded control and communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM features.

eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal.

eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed

measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals.

3.2.20 Serial Port Peripherals

The devices support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines,

phone-quality codecs for modem applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be configured as an SPI as required.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. The SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU and

other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module. The I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

3.3 Register Map

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 3-3.

Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus.

See Table 3-4.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus.

See Table 3-5.

Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible

peripheral bus. See Table 3-6.

Table 3-3. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Device Emulation Registers 0x00 0880 – 0x00 09FF 384 EALLOW protected Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 EALLOW protected XINTF Registers 0x00 0B20 – 0x00 0B3F 32 Not EALLOW protected CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 Not EALLOW protected PIE Registers 0x00 0CE0 – 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 EALLOW protected DMA Registers 0x00 1000 – 0x00 11FF 512 EALLOW protected

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(1)

(2)

Table 3-4. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (x16)

eCAN-A Registers 0x00 6000 – 0x00 61FF 512 eCAN-B Registers 0x00 6200 – 0x00 63FF 512 ePWM1 + HRPWM1 registers 0x00 6800 – 0x00 683F 64 ePWM2 + HRPWM2 registers 0x00 6840 – 0x00 687F 64 ePWM3 + HRPWM3 registers 0x00 6880 – 0x00 68BF 64 ePWM4 + HRPWM4 registers 0x00 68C0 – 0x00 68FF 64 ePWM5 + HRPWM5 registers 0x00 6900 – 0x00 693F 64 ePWM6 + HRPWM6 registers 0x00 6940 – 0x00 697F 64 ePWM7 + HRPWM7 registers 0x00 6980 – 0x00 69BF 64 ePWM8 + HRPWM8 registers 0x00 69C0 – 0x00 69FF 64 ePWM9 + HRPWM9 registers 0x00 6600 – 0x00 663F 64 eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 eCAP2 registers 0x00 6A20 – 0x00 6A3F 32 eCAP3 registers 0x00 6A40 – 0x00 6A5F 32 eCAP4 registers 0x00 6A60 – 0x00 6A7F 32 eCAP5 registers 0x00 6A80 – 0x00 6A9F 32 eCAP6 registers 0x00 6AA0 – 0x00 6ABF 32 eQEP1 registers 0x00 6B00 – 0x00 6B3F 64 eQEP2 registers 0x00 6B40 – 0x00 6B7F 64 eQEP3 registers 0x00 6B80 – 0x00 6BBF 64 GPIO registers 0x00 6F80 – 0x00 6FFF 128

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 3-5. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (x16)

System Control Registers 0x00 7010 – 0x00 702F 32 SPI-A Registers 0x00 7040 – 0x00 704F 16 SCI-A Registers 0x00 7050 – 0x00 705F 16 External Interrupt Registers 0x00 7070 – 0x00 707F 16 SCI-B Registers 0x00 7750 – 0x00 775F 16 SCI-C Registers 0x00 7770 – 0x00 777F 16 SPI-D Registers 0x00 7780 – 0x00 778F 16 I2C-A Registers 0x00 7900 – 0x00 793F 64

Table 3-6. Peripheral Frame 3 Registers

NAME ADDRESS RANGE SIZE (x16)

McBSP-A Registers 0x00 5000 – 0x00 503F 64 McBSP-B Registers 0x00 5040 – 0x00 507F 64

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-7.

www.ti.com

Table 3-7. Device Emulation Registers

NAME SIZE (x16) DESCRIPTION

DEVICECNF 2 Device Configuration Register PARTID 0x0882 1 Part ID Register TMS320C28346 0xFFD0

REVID 0x0883 1 Revision ID

PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register

ADDRESS

RANGE

0x0880 0x0881

TMS320C28345 0xFFD1 TMS320C28344 0xFFD2 TMS320C28343 0xFFD3 TMS320C28342 0xFFD4 TMS320C28341 0xFFD5

0x0000 - Silicon Rev. 0 - TMS

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

WDINT

LPMINT

Watchdog

LowPowerModels

Sync

SYSCLKOUT

WAKEINT

DMA

Clear

Peripherals

(SPI,SCI,I2C,CAN,McBSP

)

(A),

EPWM,ECAP,EQEP

DMA

XINT1

InterruptControl

XINT1CR(15:0)

XINT1CTR(15:0)

XINT1

Latch

MUX

GPIOXINT1SEL(4:0)

DMA

XINT2

InterruptControl

XINT2CR(15:0)

XINT2CTR(15:0)

XINT2

Latch

MUX

GPIOXINT2SEL(4:0)

DMA

TINT0

CPUTimer0

DMA

TINT2

CPUTimer2

CPUTimer1

MUX

TINT1

InterruptControl

XNMICR(15:0)

XNMICTR(15:0)

MUX

DMA

NMI

INT13

INT14

INT1

INT12

C28

Core

96Interrupts

PIE

XNMI_

XINT13

Latch

MUX

GPIOXNMISEL(4:0)

GPIO

Mux

GPIO0.int

GPIO31.int

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3.5 Interrupts

Figure 3-5 shows how the various interrupt sources are multiplexed.

SPRS516B–MARCH 2009–REVISED JULY 2010

A. DMA-accessible

Figure 3-5. External and PIE Interrupt Sources

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

InterruptControl

XINT3CR(15:0)

Latch

Mux

GPIOXINT3SEL(4:0)

DMA

XINT3

InterruptControl

XINT4CR(15:0)

Latch

Mux

GPIOXINT4SEL(4:0)

XINT4

InterruptControl

XINT5CR(15:0)

Mux

GPIOXINT5SEL(4:0)

XINT5

InterruptControl

XINT6CR(15:0)

Mux

GPIOXINT6SEL(4:0)

XINT6

InterruptControl

XINT7CR(15:0)

Mux

GPIOXINT7SEL(4:0)

XINT7

DMA

96Interrupts

PIE

INT1

INT12

C28

Core

GPIO32.int

GPIO63.int

GPIO

Mux

Latch

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with

Figure 3-6. External Interrupts

8 interrupts per group equals 96 possible interrupts. On the C2834x devices, 64 of these are used by peripherals as shown in Table 3-8.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx(8:1) PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals

External

Interrupts

(Enable) (Flag)

IER(12:1)IFR(12:1)

Global

Enable

INTM

PIEACKx

(Enable/Flag)

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 3-7. Multiplexing of Interrupts Using the PIE Block

Table 3-8. PIE Peripheral Interrupts

CPU INTERRUPTS

INT1 Reserved XINT2 XINT1 Reserved Reserved Reserved

INT2

INT3

INT4 Reserved Reserved

INT5 Reserved Reserved Reserved Reserved Reserved

INT6

INT7 Reserved Reserved

INT8 Reserved Reserved Reserved Reserved

INT9

INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT12 Reserved XINT7 XINT6 XINT5 XINT4 XINT3

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 (LPM/WD) (TIMER 0)

EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

ECAP6_INT ECAP5_INT ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT

(eCAP6) (eCAP5) (eCAP4) (eCAP3) (eCAP2) (eCAP1)

SPITXINTD SPIRXINTD MXINTA MRINTA MXINTB MRINTB SPITXINTA SPIRXINTA

(SPI-D) (SPI-D) (McBSP-A) (McBSP-A) (McBSP-B) (McBSP-B) (SPI-A) (SPI-A)

DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1

(DMA) (DMA) (DMA) (DMA) (DMA) (DMA)

SCITXINTC SCIRXINTC I2CINT2A I2CINT1A

(SCI-C) (SCI-C) (I2C-A) (I2C-A)

ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

LUF LVF

(FPU) (FPU)

(1) Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there is one sage case when the reserved interrupts could be used as software interrupts:

1) No peripheral within the group is asserting interrupts.

PIE INTERRUPTS

(1)

EQEP3_INT EQEP2_INT EQEP1_INT

(eQEP3) (eQEP2) (eQEP1)

EPWM9_TZINT

(ePWM9)

EPWM9_INT

(ePWM9)

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 3-9. PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA – 0x0CFF 6 Reserved

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

www.ti.com

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3.5.1 External Interrupts

NAME ADDRESS SIZE (x16) DESCRIPTION

XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT4CR 0x00 7073 1 XINT4 configuration register XINT5CR 0x00 7074 1 XINT5 configuration register XINT6CR 0x00 7075 1 XINT6 configuration register XINT7CR 0x00 7076 1 XINT7 configuration register XNMICR 0x00 7077 1 XNMI configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register Reserved 0x707A – 0x707E 5 XNMICTR 0x00 707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1).

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 3-10. External Interrupt Registers

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

ePWM1/../9,HRPWM1/../9,

eCAP1/../6,eQEP1/../3

Peripheral

registers

Bridge

Clockenables

I/O

Peripheral

registers

Clockenables

I/O

eCAN-A/B

Peripheral

registers

Clockenables

I/O

SPI-A/D,SCI-A/B/C

LOSPCP

LSPCLK

System

control

Bridge

SYSCLKOUT

Memorybus

C28xCore

GPIO

Mux

Clockenable

Peripheral

registers

I/O

McBSP-A/B

LOSPCP

LSPCLK

Clockenables

Bridge

HISPCP

DMA

bus

Bridge

ADCSOC

EXTSOC

DMA

ClockEnables

Peripheralbus

CPUtimer

registers

CPUtimer0/1/2

Clockenable

Peripheral

registers

I2C-A

EXTADCCLK

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.6 System Control

This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. shows the various clock and reset domains that will be discussed.

www.ti.com

There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be taken into account before attempting to access the peripheral configuration registers.

Figure 3-8. Clock and Reset Domains

NOTE

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

XCLKIN

(3.3-Vclockinput

fromexternal

oscillator)

On-chip

oscillator

PLLSTS[OSCOFF]

OSCCLK

PLL

VCOCLK

5-bitmultiplierPLLCR[DIV]

OSCCLKor

VCOCLK

CLKIN

OSCCLK

PLLSTS[PLLOFF]

n ≠ 0

PLLSTS[DIVSEL]

External

Crystalor

Resonator

CPU

/2 /4

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-11.

Table 3-11. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

PLLSTS 0x00 7011 1 PLL Status Register Reserved 0x00 7012 – 0x00 7018 7 Reserved PCLKCR2 0x00 7019 1 Peripheral Clock Control Register 2 HISPCP 0x00 701A 1 High-Speed Peripheral Clock Pre-Scaler Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Pre-Scaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 Reserved 0x00 701F 1 Reserved PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register Reserved 0x00 7024 1 Reserved WDKEY 0x00 7025 1 Watchdog Reset Key Register Reserved 0x00 7026 – 0x00 7028 3 Reserved WDCR 0x00 7029 1 Watchdog Control Register Reserved 0x00 702A – 0x00 702 C 3 Reserved EXTSOCCFG 0x00 702D 1 External ADC SOC Configuration Register Reserved 0x00 702E 1 Reserved

3.6.1 OSC and PLL Block

Figure 3-9 shows the OSC and PLL block.

Figure 3-9. OSC and PLL Block Diagram

The on-chip oscillator circuit enables a crystal/resonator to be attached to the C2834x devices using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following configurations:

unconnected and the X1 pin tied to V

2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left

1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left

unconnected and the XCLKIN pin tied to VSS. The logic-high level in this case should not exceed V

DD18

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

SSK

Submit Documentation Feedback

TMS320C28341

. The logic-high level in this case should not exceed V

DDIO

ExternalClockSignal

(Toggling0-V

DDIO

)

XCLKIN

SSK

External Clock Signal

(Toggling 0-V )

XCLKIN

X1 X2

C1 C2

Crystal

SSK

DD18

1.8V

XCLKIN

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

The three possible input-clock configurations are shown in Figure 3-10 through Figure 3-12.

Figure 3-10. Using a 3.3-V External Oscillator

Figure 3-11. Using a 1. 8-V External Oscillator

www.ti.com

Figure 3-12. Using the Internal Oscillator

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

C1C

(C1) C2)

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

3.6.1.1 External Reference Oscillator Clock Option

The on-chip oscillator requires an external crystal to be connected across the X1 and X2 pins. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in

Figure 3-12. The load capacitors, C1and C2, must be chosen such that the equation below is satisfied

(typical values are on the order of C1 = C2 = 10 pF). CLin the equation is the load specified for the crystal. All discrete components used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (X1, X2, and V

The external crystal load capacitors must be connected only to the oscillator ground pin (V

). Do not connect to board ground (VSS).

SSK

Where: CLequals the crystal load capacitance. TI recommends that customers have the crystal vendor characterize the operation of their device with the

MCU chip. The crystal vendor has the equipment and expertise to tune the crystal circuit. The vendor can also advise the customer regarding the proper component values that will produce proper start up and stability over the entire operating range.

NOTE

SSK

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

3.6.1.2 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) falls between 400 MHz and 600 MHz. The PLLSTS[DIVSEL] bit should be selected such that SYSCLKOUT(CLKIN) does not exceed the maximum operating frequency allowed for the device (300 MHz or 200 MHz). For example, suppose it is desired to operate a 300-MHz device at 100 MHz using a 20-MHz OSCCLK input (i.e., for power savings). The PLL should be configured for OSCCLK * 20, which produces VCOCLK = 400 MHz. PLLSTS[DIVSEL] should then be configured for /4 mode, resulting in the desired 100-MHz CLKIN to the CPU. The PLL should not be configured for OSCCLK * 10 with PLLSTS[DIVSEL] set for /2 mode. This combination would produce VCOCLK = 200 MHz, which does not fall within the required 400 MHz to 600 MHz range.

Table 3-12. PLL Settings

PLLCR[DIV]

(2) (3)

VALUE

00000 (PLL bypass) OSCCLK/8 (Default) OSCCLK/4 OSCCLK/2 OSCCLK

00001 (OSCCLK * 2)/8 (OSCCLK * 2)/4 (OSCCLK * 2)/2 – 00010 (OSCCLK * 3)/8 (OSCCLK * 3)/4 (OSCCLK * 3)/2 – 00011 (OSCCLK * 4)/8 (OSCCLK * 4)/4 (OSCCLK * 4)/2 – 00100 (OSCCLK * 5)/8 (OSCCLK * 5)/4 (OSCCLK * 5)/2 – 00101 (OSCCLK * 6)/8 (OSCCLK * 6)/4 (OSCCLK * 6)/2 – 00110 (OSCCLK * 7)/8 (OSCCLK * 7)/4 (OSCCLK * 7)/2 – 00111 (OSCCLK * 8)/8 (OSCCLK * 8)/4 (OSCCLK * 8)/2 – 01000 (OSCCLK * 9)/8 (OSCCLK * 9)/4 (OSCCLK * 9)/2 – 01001 (OSCCLK * 10)/8 (OSCCLK * 10)/4 (OSCCLK * 10)/2 – 01010 (OSCCLK * 11)/8 (OSCCLK * 11)/4 (OSCCLK * 11)/2 –

01011 – 11111 (OSCCLK * 12)/8 – (OSCCLK * 12)/4 – (OSCCLK * 12)/2 – –

(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set only to 1 or 2 after PLLSTS[PLLLOCKS] = 1. At reset,

PLLSTS[DIVSEL] is configured for /8. The boot ROM changes this to /2 or /1, depending on the boot option.

(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic have no effect.

(3) This register is EALLOW protected. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number

SPRUFN1) for more information.

(4) PLLSTS[DIVSEL] = 3 should be used only when the PLL is bypassed or off.

PLLSTS[DIVSEL] = 0 PLLSTS[DIVSEL] = 1

(OSCCLK * 32)/8 (OSCCLK * 32)/4 (OSCCLK * 32)/2

(1)

SYSCLKOUT (CLKIN)

PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3

(4)

Table 3-13. CLKIN Divide Options

PLLSTS [DIVSEL] CLKIN DIVIDE

0 /8 1 /4 2 /2 3 /1

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 3-14. Possible PLL Configuration Modes

CLKIN AND

PLL MODE REMARKS PLLSTS[DIVSEL]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

PLL Bypass

PLL Enable

(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set to 1 or 2 only after PLLSTS[PLLLOCKS] = 1. See the

TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more information.

(2) PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled and not bypassed.

is disabled in this mode. This can be useful to reduce system noise and for low before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external 0 OSCCLK/8

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or 1 OSCCLK/4 while the PLL locks to a new frequency after the PLLCR register has been 2 OSCCLK/2 modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. 3 OSCCLK/1

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 1 OSCCLK*n/4 PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK*n/2

0 OSCCLK/8 1 OSCCLK/4 2 OSCCLK/2 3 OSCCLK/1

0 OSCCLK*n/8

3 –

(1)

SYSCLKOUT

3.6.1.3 Loss of Input Clock

Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged.

(2)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

/512

OSCCLK

WDCR (WDPS[2:0])

WDCLK

WDCNTR[7:0]

WDKEY[7:0]

Good Key

WDCR (WDCHK[2:0])

Bad

WDCHK

Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

3.6.2 Watchdog Block

The watchdog block on the C2834x device is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-13 shows the various functional blocks within the watchdog module.

www.ti.com

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-13. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7, Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

3.7 Low-Power Modes Block

The low-power modes on the C2834x devices are similar to the 240x devices. Table 3-15 summarizes the various modes.

Table 3-15. Low-Power Modes

(3)

, XNMI

(1)

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

IDLE 00 On On On

STANDBY 01 Off Off

HALT 1X (oscillator and PLL turned off, Off Off

(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will

exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(watchdog still running) signal, debugger

watchdog not functional)

On XRS, Watchdog interrupt, GPIO Port A

Off

(2)

XRS, Watchdog interrupt, any enabled interrupt, XNMI

XRS, GPIO Port A signal, XNMI, debugger

(3)

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized

by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the

device from HALT mode. The user selects the signal in the GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more details.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4 Peripherals

The integrated peripherals are described in the following subsections:

• 6-channel Direct Memory Access (DMA)

• Three 32-bit CPU-Timers

• Up to nine enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7, ePWM8, ePWM9)

• Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)

• Up to three enhanced QEP modules (eQEP1, eQEP2, eQEP3)

• External analog-to-digital converter (ADC) Interface

• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)

• Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)

• Up to two serial peripheral interface (SPI) modules (SPI-A, SPI-D)

• Inter-integrated circuit module (I2C)

• Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules

• Digital I/O and shared pin functions

• External Interface (XINTF)

4.1 DMA Overview

Features:

• 6 Channels with independent PIE interrupts

• Trigger Sources: – McBSP-A and McBSP-B transmit and receive logic – XINT1–7 and XINT13 – CPU Timers – Software

• Data Sources/Destinations: – L0–L7 64K × 16 SARAM – All XINTF zones – McBSP-A and McBSP-B transmit and receive buffers

• Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)

• Throughput: 4 cycles/word (5 cycles/word for McBSP reads)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

PF3

I/F

McBSP A

McBSP B

Event

triggers

DMA

6-ch

External

interrupts

CPU

timers

CPUbus

DMA bus

PIE

INT7

DINT[CH1:CH6]

CPU

XINTFzonesinterface

XINTFmemoryzones

I/F

L0RAM

I/F

L1RAM

I/F

L2RAM

I/F

L3RAM

I/F

L4RAM

I/F

L5RAM

I/F

L6RAM

I/F

L7RAM

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 4-1. DMA Functional Block Diagram

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

INT1

INT12

INT14

28x

CPU

TINT2

TINT0

PIE

CPU-TIMER0

CPU-TIMER2

(ReservedforDSP/BIOS)

INT13

TINT1

CPU-TIMER1

XINT13

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.2 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2). Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.

These timers are different from the timers that are present in the ePWM modules.

NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

www.ti.com

NOTE

Figure 4-2. CPU-Timers

The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.

A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-3. CPU-Timer Interrupt Signals and Output Signal

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1).

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register Reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register Reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register Reserved 0x0C15 1 TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High Reserved 0x0C18 – 0x0C3F 40

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

EXTSOC1A

POLSEL

EXTSOC1A

EXTSOC3A

EXTSOC2A

EXTSOC1B

EXTSOC2B

EXTSOC3B

PulseStretcher,

32HSPCLKCyclesWideandThentoChipPins

ePWM2

ePWM2SOCA

ePWM2SOCB

ePWM1

ePWM1SOCA

ePWM1SOCB

ePWM3

ePWM3SOCA

ePWM3SOCB

ePWM4

ePWM4SOCA

ePWM4SOCB

EXTSOC2A

POLSEL

ePWM6

ePWM6SOCA

ePWM6SOCB

ePWM5

ePWM5SOCA

ePWM5SOCB

ePWM7

ePWM7SOCA

ePWM7SOCB

ePWM8

ePWM8SOCA

ePWM8SOCB

EXTSOC1B

POLSEL

EXTSOC2B

POLSEL

ePWM9

ePWM9SOCA

ePWM9SOCB

EXTSOC3A

POLSEL

EXTSOC3B

POLSEL

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 /7/8/9)

The devices contain up to nine enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.

Table 4-2 and Table 4-3 show the complete ePWM register set per module.

www.ti.com

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Figure 4-4. Generation of SOC Pulses to the External ADC Module

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 4-2. ePWM1-4 Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION

TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register

(1) Registers that are EALLOW protected.

SIZE (x16) /

#SHADOW

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 4-3. ePWM5-9 Control and Status Registers

NAME ePWM5 ePWM6 ePWM7 ePWM8 ePWM9 DESCRIPTION

TBCTL 0x6900 0x6940 0x6980 0x69C0 0x6600 1 / 0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 0x69C1 0x6601 1 / 0 Time Base Status Register TBPHSHR 0x6902 0x6942 0x6982 0x69C2 0x6602 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6903 0x6943 0x6983 0x69C3 0x6603 1 / 0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 0x69C4 0x6604 1 / 0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 0x69C5 0x6605 1 / 1 Time Base Period Register Set CMPCTL 0x6907 0x6947 0x6987 0x69C7 0x6607 1 / 0 Counter Compare Control Register CMPAHR 0x6908 0x6948 0x6988 0x69C8 0x6608 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6909 0x6949 0x6989 0x69C9 0x6609 1 / 1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 0x69CA 0x660A 1 / 1 Counter Compare B Register Set AQCTLA 0x690B 0x694B 0x698B 0x69CB 0x660B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 0x69CC 0x660C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 0x69CD 0x660D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 0x69CE 0x660E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 0x69CF 0x660F 1 / 1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 0x69D0 0x6610 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 0x69D1 0x6611 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 0x69D2 0x6612 1 / 0 Trip Zone Select Register TZCTL 0x6914 0x6954 0x6994 0x69D4 0x6614 1 / 0 Trip Zone Control Register TZEINT 0x6915 0x6955 0x6995 0x69D5 0x6615 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6916 0x6956 0x6996 0x69D6 0x6616 1 / 0 Trip Zone Flag Register TZCLR 0x6917 0x6957 0x6997 0x69D7 0x6617 1 / 0 Trip Zone Clear Register TZFRC 0x6918 0x6958 0x6998 0x69D8 0x6618 1 / 0 Trip Zone Force Register ETSEL 0x6919 0x6959 0x6999 0x69D9 0x6619 1 / 0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 0x69DA 0x661A 1 / 0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 0x69DB 0x661B 1 / 0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 0x69DC 0x661C 1 / 0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 0x69DD 0x661D 1 / 0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 0x69DE 0x661E 1 / 0 PWM Chopper Control Register HRCNFG 0x6920 0x6960 0x69A0 0x69E0 0x6620 1 / 0 HRPWM Configuration Register

(1) Registers that are EALLOW protected.

SIZE (x16) / #SHADOW

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

CTR=PRD

TBPRD shadow (16)

TBPRD active (16)

Counter

up/down

(16 bit)

TBCTR

active (16)

TBCTL[PHSEN]

TBCTL[SWFSYNC] (software forced sync)

EPWMxSYNCI

CTR=ZERO

CTR_Dir

CTR=CMPB

Disabled

Sync in/out select

Mux

TBCTL[SYNCOSEL]

EPWMxSYNCO

TBPHS active (24)

TBPHSHR (8)

Phase control

Time−base (TB)

CTR=CMPA

CMPA active (24)

CMPA shadow (24)

Action

qualifier

(AQ)

Counter compare (CC)

CMPB active (16)

CTR=CMPB

CMPB shadow (16)

CMPAHR (8)

EPWMA

EPWMB

Dead band

(DB) (PC)

chopper

PWM

zone

(TZ)

Trip

CTR = ZERO

EPWMxAO

EPWMxBO

EPWMxTZINT

TZ1 to TZ6

HiRes PWM (HRPWM)

CTR = PRD

CTR = ZERO

CTR = CMPB

CTR = CMPA

CTR_Dir

Event

trigger

and

interrupt

(ET)

EPWMxINT

EPWMxSOCA

EPWMxSOCB

CTR=ZERO

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections

SPRS516B–MARCH 2009–REVISED JULY 2010

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.4 High-Resolution PWM (HRPWM)

The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM

• Typically used when effective PWM resolution falls below ~ 9–10 bits. This occurs at PWM frequencies greater than ~500 kHz when using a CPU/System clock of 300 MHz or ~375 kHz when using a CPU/system clock of 200 MHz.

• This capability can be utilized in both duty cycle and phase-shift control methods.

• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module.

• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TSCTR

(Counter - 32-bit)

RST

CAP1

(APRD Active)

CAP2

(ACMP Active)

CAP3

(APRD Shadow)

CAP4

(ACMP Shadow)

Continuous/

One-Shot

Capture Control

LD1

LD2

LD3

LD4

PRD [0-31]

CTR [0-31]

eCAPx

MODE SELECT

Interrupt

Trigger

and

Flag

Control

to PIE

CTR=CMP

ACMP

Shadow

Event

Prescale

CTRPHS

(Phase Register - 32-bit)

SYNCOut

SYNCIn

SYNC

Event

Qualifier

Polarity

Select

Polarity

Select

Polarity

Select

Polarity

Select

CTR=PRD

CTR_OVF

PWM

Compare

Logic

CTR [0-31]

PRD [0-31]

CMP [0-31]

CTR=CMP

CTR=PRD

CTR_OVF

OVF

APWM Mode

Delta Mode

Capture Events

CEVT[1:4]

APRD

Shadow

CMP [0-31]

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)

The device contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module.

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 4-6. eCAP Functional Block Diagram

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

The eCAP modules are clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP

modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low, indicating that the peripheral clock is off.

Table 4-4. eCAP Control and Status Registers

NAME eCAP1 eCAP2 eCAP3 eCAP4 eCAP5 eCAP6 DESCRIPTION

TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 0x6A80 0x6AA0 2 Time-Stamp Counter

CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 0x6A82 0x6AA2 2 Counter Phase Offset Value

CAP1 0x6A04 0x6A24 0x6A44 0x6A64 0x6A84 0x6AA4 2 Capture 1 Register CAP2 0x6A06 0x6A26 0x6A46 0x6A66 0x6A86 0x6AA6 2 Capture 2 Register CAP3 0x6A08 0x6A28 0x6A48 0x6A68 0x6A88 0x6AA8 2 Capture 3 Register CAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 0x6A8A 0x6AAA 2 Capture 4 Register

Reserved 0x6A0C- 0x6A2C- 0x6A4C- 0x6A6C- 0x6A8C- 0x6AAC- 8 Reserved

0x6A12 0x6A32 0x6A52 0x6A72 0x6A92 0x6AB2 ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 0x6A94 0x6AB4 1 Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 0x6A95 0x6AB5 1 Capture Control Register 2

ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 0x6A96 0x6AB6 1 Capture Interrupt Enable Register

ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 0x6A97 0x6AB7 1 Capture Interrupt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 0x6A98 0x6AB8 1 Capture Interrupt Clear Register ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 0x6A99 0x6AB9 1 Capture Interrupt Force Register

Reserved 0x6A1A- 0x6A3A- 0x6A5A- 0x6A7A- 0x6A9A- 0x6ABA- 6 Reserved

0x6A1F 0x6A3F 0x6A5F 0x6A7F 0x6A9F 0x6ABF

SIZE (x16)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

QWDTMR

QWDPRD

QWDOG

UTIME

QUPRD

QUTMR

UTOUT

WDTOUT

Quadrature

Capture

Unit

(QCAP)

QCPRDLAT

QCTMRLAT

QFLG

QEPSTS

QEPCTL

Registers

Used by

Multiple Units

QCLK

QDIR

PHE

PCSOUT

Quadrature

Decoder

(QDU)

QDECCTL

Position Counter/

Control Unit

(PCCU)

QPOSLAT

QPOSSLAT

QPOSILAT

EQEPxAIN

EQEPxBIN

EQEPxIIN

EQEPxIOUT

EQEPxIOE

EQEPxSIN

EQEPxSOUT

EQEPxSOE

GPIO

MUX

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxS

EQEPxI

QPOSCMP

QEINT

QFRC

QCLR

QPOSCTL

1632

QPOSCNT

QPOSMAX

QPOSINIT

PIE

EQEPxINT

Enhanced QEP (eQEP) Peripheral

System Control

Registers

QCTMR

QCPRD

1616

QCAPCTL

EQEPxENCLK

SYSCLKOUT

To CPU

Data Bus

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

4.6 Enhanced QEP Modules (eQEP1/2 /3)

The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution.

Figure 4-7 shows the block diagram of the eQEP module.

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 4-7. eQEP Functional Block Diagram

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 4-5 provides a summary of the eQEP registers.

Table 4-5. eQEP Control and Status Registers

NAME SIZE(x16)/ REGISTER DESCRIPTION

QPOSCNT 0x6B00 0x6B40 0x6B80 2/0 eQEP Position Counter QPOSINIT 0x6B02 0x6B42 0x6B82 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 0x6B44 0x6B84 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 0x6B46 0x6B86 2/1 eQEP Position-compare QPOSILAT 0x6B08 0x6B48 0x6B88 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 0x6B4A 0x6B8A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4C 0x6B8C 2/0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 0x6B8E 2/0 eQEP Unit Timer QUPRD 0x6B10 0x6B50 0x6B90 2/0 eQEP Unit Period Register QWDTMR 0x6B12 0x6B52 0x6B92 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 0x6B53 0x6B93 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 0x6B54 0x6B94 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 0x6B55 0x6B95 1/0 eQEP Control Register QCAPCTL 0x6B16 0x6B56 0x6B96 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 0x6B97 1/0 eQEP Position-compare Control

QEINT 0x6B18 0x6B58 0x6B98 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 0x6B59 0x6B99 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 0x6B5A 0x6B9A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 0x6B5B 0x6B9B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 0x6B5C 0x6B9C 1/0 eQEP Status Register QCTMR 0x6B1D 0x6B5D 0x6B9D 1/0 eQEP Capture Timer QCPRD 0x6B1E 0x6B5E 0x6B9E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 0x6B5F 0x6B9F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 0x6B60 0x6BA0 1/0 eQEP Capture Period Latch Reserved 0x6B21 - 0x6B3F 0x6B61 - 0x6B7F 0x6BBA1 - 0x6BBF 31/0

eQEP1 eQEP2 eQEP3

ADDRESS ADDRESS ADDRESS

eQEPx

#SHADOW

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

EXTSOC1A

POLSEL

EXTSOC1A

EXTSOC3A

EXTSOC2A

EXTSOC1B

EXTSOC2B

EXTSOC3B

PulseStretcher,

32HSPCLKCyclesWideandThentoChipPins

ePWM2

ePWM2SOCA

ePWM2SOCB

ePWM1

ePWM1SOCA

ePWM1SOCB

ePWM3

ePWM3SOCA

ePWM3SOCB

ePWM4

ePWM4SOCA

ePWM4SOCB

EXTSOC2A

POLSEL

ePWM6

ePWM6SOCA

ePWM6SOCB

ePWM5

ePWM5SOCA

ePWM5SOCB

ePWM7

ePWM7SOCA

ePWM7SOCB

ePWM8

ePWM8SOCA

ePWM8SOCB

EXTSOC1B

POLSEL

EXTSOC2B

POLSEL

ePWM9

ePWM9SOCA

ePWM9SOCB

EXTSOC3A

POLSEL

EXTSOC3B

POLSEL

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

4.7 External ADC Interface

The external ADC interface operation is configured, controlled, and monitored by the External SoC Configuration Register (EXTSOCCFG) at address 0x702E.

Figure 4-8. External ADC Interface

SPRS516B–MARCH 2009–REVISED JULY 2010

NAME DESCRIPTION ADDRESS

EXTSOCCFG External SoC Configuration Register 0x00 702E

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Table 4-6. External ADC Interface Registers

Submit Documentation Feedback

TMS320C28341

( )

CLKSRG

CLKG =

1 + CLKGDV

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.8 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices

• Full-duplex communication

• Double-buffered data registers that allow a continuous data stream

• Independent framing and clocking for receive and transmit

• External shift clock generation or an internal programmable frequency shift clock

• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits

• 8-bit data transfers with LSB or MSB first

• Programmable polarity for both frame synchronization and data clocks

• Highly programmable internal clock and frame generation

• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices

• Works with SPI-compatible devices

• The following application interfaces can be supported on the McBSP: – T1/E1 framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) – IIS-compliant devices – SPI

• McBSP clock rate,

www.ti.com

where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit.

NOTE

See Section 6 for maximum I/O pin toggling speed.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

McBSP Receive

InterruptSelectLogic

MDXx

MDRx

ExpandLogic

DRR1ReceiveBuffer

Interrupt

DRR2ReceiveBuffer

RBR1RegisterRBR2Register

MCLKXx

MFSXx

MCLKRx

MFSRx

CompandLogic

DXR2 TransmitBuffer

RSR1

XSR2

XSR1

PeripheralReadBus

RSR2

DXR1 TransmitBuffer

LSPCLK

MRINT

ToCPU

RXInterruptLogic

McBSP Transmit

InterruptSelectLogic

Interrupt

MXINT

ToCPU

TXInterruptLogic

16 16

Bridge

DMA Bus

PeripheralBus

PeripheralWriteBus

CPU

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Figure 4-9 shows the block diagram of the McBSP module.

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 4-9. McBSP Module

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 4-7 provides a summary of the McBSP registers.

Table 4-7. McBSP Register Summary

NAME TYPE RESET VALUE DESCRIPTION

DRR2 0x5000 0x5040 R 0x0000 McBSP Data Receive Register 2 DRR1 0x5001 0x5041 R 0x0000 McBSP Data Receive Register 1 DXR2 0x5002 0x5042 W 0x0000 McBSP Data Transmit Register 2 DXR1 0x5003 0x5043 W 0x0000 McBSP Data Transmit Register 1

SPCR2 0x5004 0x5044 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 0x5005 0x5045 R/W 0x0000 McBSP Serial Port Control Register 1 RCR2 0x5006 0x5046 R/W 0x0000 McBSP Receive Control Register 2 RCR1 0x5007 0x5047 R/W 0x0000 McBSP Receive Control Register 1 XCR2 0x5008 0x5048 R/W 0x0000 McBSP Transmit Control Register 2 XCR1 0x5009 0x5049 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0x500A 0x504A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0x500B 0x504B R/W 0x0000 McBSP Sample Rate Generator Register 1

MCR2 0x500C 0x504C R/W 0x0000 McBSP Multichannel Register 2 MCR1 0x500D 0x504D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0x500E 0x504E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0x500F 0x504F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 0x5010 0x5050 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 0x5011 0x5051 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 0x5012 0x5052 R/W 0x0000 McBSP Pin Control Register RCERC 0x5013 0x5053 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 0x5014 0x5054 R/W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 0x5015 0x5055 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 0x5016 0x5056 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 0x5017 0x5057 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 0x5018 0x5058 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 0x5019 0x5059 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 0x501A 0x505A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 0x501B 0x505B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 0x501C 0x505C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 0x501D 0x505D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 0x501E 0x505E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H MFFINT 0x5023 0x5063 R/W 0x0000 McBSP Interrupt Enable Register MFFST 0x5024 0x5064 R/W 0x0000 McBSP Pin Status Register

McBSP-A McBSP-B

ADDRESS ADDRESS

Data Registers, Receive, Transmit

McBSP Control Registers

Multichannel Control Registers

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)

• Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

NOTE

For a SYSCLKOUT of 300 MHz, the smallest bit rate possible is 11.719 kbps. For a SYSCLKOUT of 200 MHz, the smallest bit rate possible is 7.8125 kbps.

The CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 x 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and

Message Objects Control

Message Controller

32 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

Controls

Address Data

eCAN1INTeCAN0INT

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Figure 4-10. eCAN Block Diagram and Interface Circuit

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 4-8. 3.3-V eCAN Transceivers

PART NUMBER VREF OTHER T

SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C

SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C

ISO1050 3–5.5 V None None None –55°C to 105°C

SUPPLY LOW-POWER SLOPE

VOLTAGE MODE CONTROL

• Built-in isolation

• Low-prop delay

• Thermal shutdown

• Failsafe operation

• Dominant time-out

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

Master Control - CANMC

Bit-Timing Configuration - CANBTC

Error and Status - CANES

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Global Interrupt Flag 1 - CANGIF1

Time-Out Control - CANTOC

Time-Out Status - CANTOS

Reserved

eCAN-A Control and Status Registers

Message Identifier - MSGID

61E8h-61E9h

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h

603Fh

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

6040h

607Fh 6080h

60BFh 60C0h

60FFh

eCAN-A Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Mailbox 06100h-6107h

Mailbox 1

6108h-610Fh

Mailbox 2

6110h-6117h

Mailbox 3

6118h-611Fh

eCAN-A Memory RAM (512 Bytes)

Mailbox 4

6120h-6127h

Mailbox 28

61E0h-61E7h

Mailbox 2961E8h-61EFh

Mailbox 3061F0h-61F7h

Mailbox 31

61F8h-61FFh

61EAh-61EBh

61ECh-61EDh

61EEh-61EFh

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

Figure 4-11. eCAN-A Memory Map

NOTE

www.ti.com

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

Master Control - CANMC

Bit-Timing Configuration - CANBTC

Error and Status - CANES

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Global Interrupt Flag 1 - CANGIF1

Time-Out Control - CANTOC

Time-Out Status - CANTOS

Reserved

eCAN-B Control and Status Registers

Message Identifier - MSGID

63E8h-63E9h

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6200h

623Fh

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

6240h

627Fh 6280h

62BFh 62C0h

62FFh

eCAN-B Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Mailbox 06300h-6307h

Mailbox 1

6308h-630Fh

Mailbox 2

6310h-6317h

Mailbox 3

6318h-631Fh

eCAN-B Memory RAM (512 Bytes)

Mailbox 4

6320h-6327h

Mailbox 28

63E0h-63E7h

Mailbox 2963E8h-63EFh

Mailbox 3063F0h-63F7h

Mailbox 31

63F8h-63FFh

63EAh-63EBh

63ECh-63EDh

63EEh-63EFh

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Figure 4-12. eCAN-B Memory Map

SPRS516B–MARCH 2009–REVISED JULY 2010

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Table 4-9. CAN Register Map

CANME 0x6000 0x6200 1 Mailbox enable

CANMD 0x6002 0x6202 1 Mailbox direction CANTRS 0x6004 0x6204 1 Transmit request set CANTRR 0x6006 0x6206 1 Transmit request reset

CANTA 0x6008 0x6208 1 Transmission acknowledge CANAA 0x600A 0x620A 1 Abort acknowledge

CANRMP 0x600C 0x620C 1 Receive message pending

CANRML 0x600E 0x620E 1 Receive message lost CANRFP 0x6010 0x6210 1 Remote frame pending

CANGAM 0x6012 0x6212 1 Global acceptance mask

CANMC 0x6014 0x6214 1 Master control CANBTC 0x6016 0x6216 1 Bit-timing configuration

CANES 0x6018 0x6218 1 Error and status CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter

CANGIF0 0x601E 0x621E 1 Global interrupt flag 0

CANGIM 0x6020 0x6220 1 Global interrupt mask

CANGIF1 0x6022 0x6222 1 Global interrupt flag 1

CANMIM 0x6024 0x6224 1 Mailbox interrupt mask

CANMIL 0x6026 0x6226 1 Mailbox interrupt level

CANOPC 0x6028 0x6228 1 Overwrite protection control

CANTIOC 0x602A 0x622A 1 TX I/O control CANRIOC 0x602C 0x622C 1 RX I/O control

CANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

eCAN-A eCAN-B SIZE

ADDRESS ADDRESS (x32)

(1)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

8*1)(BRR

LSPCLK

rateBaud

0BRRwhen ¹

LSPCLK

rateBaud =

0BRRwhen =

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

The devices include three serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

NOTE

See Section 6 for maximum I/O pin toggling speed.

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

• NRZ (non-return-to-zero) format

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and

Table 4-12.

Table 4-10. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x7050 1 SCI-A Communications Control Register

SCICTL1A 0x7051 1 SCI-A Control Register 1

SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x7054 1 SCI-A Control Register 2

SCIRXSTA 0x7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register SCIFFTXA SCIFFRXA SCIFFCTA

SCIPRIA 0x705F 1 SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2)

0x705A 1 SCI-A FIFO Transmit Register 0x705B 1 SCI-A FIFO Receive Register

0x705C 1 SCI-A FIFO Control Register

(1)

Table 4-11. SCI-B Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRB 0x7750 1 SCI-B Communications Control Register

SCICTL1B 0x7751 1 SCI-B Control Register 1

SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits

SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits

SCICTL2B 0x7754 1 SCI-B Control Register 2

SCIRXSTB 0x7755 1 SCI-B Receive Status Register

SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register

SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register SCIFFTXB SCIFFRXB SCIFFCTB

SCIPRIB 0x775F 1 SCI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2)

0x775A 1 SCI-B FIFO Transmit Register 0x775B 1 SCI-B FIFO Receive Register

0x775C 1 SCI-B FIFO Control Register

(1) (2)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Table 4-12. SCI-C Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRC 0x7770 1 SCI-C Communications Control Register

SCICTL1C 0x7771 1 SCI-C Control Register 1

SCIHBAUDC 0x7772 1 SCI-C Baud Register, High Bits

SCILBAUDC 0x7773 1 SCI-C Baud Register, Low Bits

SCICTL2C 0x7774 1 SCI-C Control Register 2 SCIRXSTC 0x7775 1 SCI-C Receive Status Register

SCIRXEMUC 0x7776 1 SCI-C Receive Emulation Data Buffer Register

SCIRXBUFC 0x7777 1 SCI-C Receive Data Buffer Register

SCITXBUFC 0x7779 1 SCI-C Transmit Data Buffer Register SCIFFTXC SCIFFRXC SCIFFCTC

SCIPRC 0x777F 1 SCI-C Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2)

(2) (2)

0x777A 1 SCI-C FIFO Transmit Register 0x777B 1 SCI-C FIFO Receive Register

0x777C 1 SCI-C FIFO Control Register

(1) (2)

SPRS516B–MARCH 2009–REVISED JULY 2010

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

LSPCLK

Frame Format and Mode

Even/Odd

Enable

Parity

SCIRXD

SCIRXST.1

TXENA

RXWAKE

SCITXD

SCICCR.6 SCICCR.5

RXSHF Register

SCITXD

TXSHF

WUT

SCICTL1.3

TXWAKE

Baud Rate

MSbyte

Baud Rate

LSbyte

SCIHBAUD. 15 - 8

SCILBAUD. 7 - 0

FIFO

Interrupts

RXENA

SCICTL1.0

FIFO

Interrupts

SCICTL1.1

SCIRXD

RX ERR INT ENA

SCICTL1.6

RX Error

PEFE OE

RX Error

SCIRXST.7 SCIRXST.4 - 2

SCITXBUF.7-0

TX FIFO Registers

Transmitter-Data

Buffer Register

SCIFFENA

TX FIFO _15

- - - - -

TX FIFO _1

TX FIFO _0

SCIFFTX.14

SCIRXBUF.7-0

RX FIFO Registers

Receive-Data

Buffer Register

SCIRXBUF.7-0

SCIFFRX.15

RXFFOVF

RX FIFO _0

- - - - -

RX FIFO _1

RX FIFO _15

SCI TX Interrupt Select Logic

TX EMPTY

SCICTL2.6

TXINT

TXRDY

SCICTL2.0

TX INT ENA

SCICTL2.7

To CPU

AutoBaud Detect Logic

TX Interrupt Logic

RX Interrupt Logic

SCI RX Interrupt Select Logic

RXRDY

SCIRXST.6

BRKDT

SCIRXST.5

RX/BK INT ENA

SCICTL2.1

RXINT

To CPU

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Figure 4-13 shows the SCI module block diagram.

www.ti.com

Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

1)(SPIBRR

LSPCLK

rateBaud

127to3SPIBRRwhen =

LSPCLK

rateBaud =

21,0,SPIBRRwhen =

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

4.11 Serial Peripheral Interface (SPI) Module (SPI-A , SPI-D)

The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO if the SPI module is not used.

• Two operational modes: master and slave Baud rate: 125 different programmable rates.

SPRS516B–MARCH 2009–REVISED JULY 2010

NOTE

See Section 6 for maximum I/O pin toggling speed.

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Enhanced features:

• 16-level transmit/receive FIFO

• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 4-13 and Table 4-14 .

Table 4-13. SPI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7040 1 SPI-A Configuration Control Register

SPICTL 0x7041 1 SPI-A Operation Control Register SPISTS 0x7042 1 SPI-A Status Register SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register

SPIFFRX 0x704B 1 SPI-A FIFO Receive Register

SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Table 4-14. SPI-D Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x7780 1 SPI-D Configuration Control Register

SPICTL 0x7781 1 SPI-D Operation Control Register SPISTS 0x7782 1 SPI-D Status Register SPIBRR 0x7784 1 SPI-D Baud Rate Register

SPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer Register

SPIRXBUF 0x7787 1 SPI-D Serial Input Buffer Register SPITXBUF 0x7788 1 SPI-D Serial Output Buffer Register

SPIDAT 0x7789 1 SPI-D Serial Data Register

SPIFFTX 0x778A 1 SPI-D FIFO Transmit Register

SPIFFRX 0x778B 1 SPI-D FIFO Receive Register

SPIFFCT 0x778C 1 SPI-D FIFO Control Register

SPIPRI 0x778F 1 SPI-D Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

SPICTL.0

SPIINTFLAG

SPIINT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

456 123 0

0123

SPIBitRate

StateControl

SPIRXBUF

BufferRegister

Clock Phase

Receiver

OverrunFlag

SPICTL.4

Overrun INTENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6 SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

DataRegister

SPICTL.2

SPIChar

SPISIMO

SPISOMI

SPICLK

SW2

SW3

ToCPU

SW1

SPITXBUF

BufferRegister

RXFIFO_0 RXFIFO_1

−−−−−

RXFIFO_15

TXFIFOregisters

TXFIFO_0

TXFIFO_1

−−−−−

TXFIFO_15

RXFIFOregisters

TXInterrupt

Logic

RXInterrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVFFLAG

SPIFFRX.15

TXFIFOInterrupt

RXFIFOInterrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

(A)

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

Figure 4-14 is a block diagram of the SPI in slave mode.

SPRS516B–MARCH 2009–REVISED JULY 2010

A. SPISTE is driven low by the master for a slave device.

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Figure 4-14. SPI Module Block Diagram (Slave Mode)

Submit Documentation Feedback

TMS320C28341

SYSRS

SYSCLKOUT

Control

I2CINT1A

I2CINT2A

C28x CPU

GPIO

MUX

Peripheral Bus

I C-A

System Control Block

I2CAENCLK

PIE

Block

SDAA

SCLA

Data[16]

Addr[16]

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.12 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces within the device.

www.ti.com

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-15. I2C Peripheral Module Interfaces

The I2C module has the following features:

• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)

• One 16-word receive FIFO and one 16-word transmit FIFO

• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions:

– Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

• An additional interrupt that can be used by the CPU when in FIFO mode

• Module enable/disable capability

• Free data format mode

The registers in Table 4-15 configure and control the I2C port operation.

SPRS516B–MARCH 2009–REVISED JULY 2010

– Arbitration lost – Stop condition detected – Addressed as slave

Table 4-15. I2C-A Registers

NAME ADDRESS DESCRIPTION

I2COAR 0x7900 I2C own address register

I2CIER 0x7901 I2C interrupt enable register

I2CSTR 0x7902 I2C status register I2CCLKL 0x7903 I2C clock low-time divider register I2CCLKH 0x7904 I2C clock high-time divider register

I2CCNT 0x7905 I2C data count register

I2CDRR 0x7906 I2C data receive register

I2CSAR 0x7907 I2C slave address register

I2CDXR 0x7908 I2C data transmit register

I2CMDR 0x7909 I2C mode register I2CISRC 0x790A I2C interrupt source register

I2CPSC 0x790C I2C prescaler register I2CFFTX 0x7920 I2C FIFO transmit register I2CFFRX 0x7921 I2C FIFO receive register

I2CRSR – I2C receive shift register (not accessible to the CPU)

I2CXSR – I2C transmit shift register (not accessible to the CPU)

4.13 GPIO MUX

On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram per pin is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1 ) for details.

NOTE

There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

GPxDAT (read)

Input

Qualification

GPxMUX1/2

High-Impedance

Output Control

GPIOx pin

XRS

0 = Input, 1 = Output

Low-Power

Modes Block

GPxPUD

Internal

Pullup

= Default at Reset

External Interrupt

MUX

Peripheral 3 Input

Peripheral 3 Output Enable

Peripheral 2 Output Enable

Peripheral 1 Output Enable

Peripheral 3 Output

Peripheral 2 Output

Peripheral 1 Output

Peripheral 2 Input

Peripheral 1 Input

N/C

GPxDIR (latch)

GPxDAT (latch)

Asynchronous

path

Asynchronous path

LPMCR0

GPIOLMPSEL

GPxCTRL

GPxQSEL1/2

GPIOXNMISEL

GPIOXINT7SEL

GPIOXINT3SEL

GPIOXINT2SEL

GPIOXINT1SEL

GPxSET

GPxCLEAR

GPxTOGGLE

PIE

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected. B. GPxDAT latch/read are accessed at the same memory location. C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the

TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1 ) for

pin-specific variations.

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Figure 4-16. GPIO MUX Block Diagram

Submit Documentation Feedback

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-16 shows the GPIO register mapping.

Table 4-16. GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)

GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)

Reserved 0x6F8E – 0x6F8F 2

GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 63) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 47) GPBQSEL2 0x6F94 2 GPIOB Qualifier Select 2 Register (GPIO48 to 63)

GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 47) GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48 to 63)

GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 63)

GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 63)

Reserved 0x6F9E – 0x6FA5 8 GPCMUX1 0x6FA6 2 GPIO C MUX1 Register (GPIO64 to 79) GPCMUX2 0x6FA8 2 GPIO C MUX2 Register (GPIO80 to 87)

GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64 to 87) GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64 to 87) Reserved 0x6FAE – 0x6FBF 18

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)

GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)

GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)

GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 63) GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 63)

GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 63)

GPBTOGGLE 0x6FCE 2 GPIOB Data Toggle Register (GPIO32 to 63)

GPCDAT 0x6FD0 2 GPIO C Data Register (GPIO64 to 87) GPCSET 0x6FD2 2 GPIO C Data Set Register (GPIO64 to 87)

GPCCLEAR 0x6FD4 2 GPIO C Data Clear Register (GPIO64 to 87)

GPCTOGGLE 0x6FD6 2 GPIO C Data Toggle Register (GPIO64 to 87)

Reserved 0x6FD8 – 0x6FDF 8

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE3 1 XINT3 GPIO Input Select Register (GPIO32 to 63) GPIOXINT4SEL 0x6FE4 1 XINT4 GPIO Input Select Register (GPIO32 to 63) GPIOXINT5SEL 0x6FE5 1 XINT5 GPIO Input Select Register (GPIO32 to 63)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

www.ti.com

Table 4-16. GPIO Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to 63)

GPIOINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to 63)

GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

Reserved 0x6FEA – 0x6FFF 22

Table 4-17. GPIO-A Mux Peripheral Selection Matrix

GPADIR GPADAT GPASET GPACLR

GPATOGGLE

QUALPRD0 0 1, 0 GPIO0 (I/O) EPWM1A (O) Reserved Reserved

1 3, 2 GPIO1 (I/O) EPWM1B (O) ECAP6 (I/O) MFSRB (I/O) 2 5, 4 GPIO2 (I/O) EPWM2A (O) Reserved Reserved 3 7, 6 GPIO3 (I/O) EPWM2B (O) ECAP5 (I/O) MCLKRB (I/O) 4 9, 8 GPIO4 (I/O) EPWM3A (O) Reserved Reserved 5 11, 10 GPIO5 (I/O) EPWM3B (O) MFSRA (I/O) ECAP1 (I/O) 6 13, 12 GPIO6 (I/O) EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 7 15, 14 GPIO7 (I/O) EPWM4B (O) MCLKRA (I/O) ECAP2 (I/O)

QUALPRD1 8 17, 16 GPIO8 (I/O) EPWM5A (O) CANTXB (O) ADCSOCAO (O)

9 19, 18 GPIO9 (I/O) EPWM5B (O) SCITXDB (O) ECAP3 (I/O) 10 21, 20 GPIO10 (I/O) EPWM6A (O) CANRXB (I) ADCSOCBO (O) 11 23, 22 GPIO11 (I/O) EPWM6B (O) SCIRXDB (I) ECAP4 (I/O) 12 25, 24 GPIO12 (I/O) TZ1 (I) CANTXB (O) MDXB (O) 13 27, 26 GPIO13 (I/O) TZ2 (I) CANRXB (I) MDRB (I) 14 29, 28 GPIO14 (I/O) TZ3 (I)/XHOLD (I) SCITXDB (O) MCLKXB (I/O) 15 31, 30 GPIO15 (I/O) TZ4 (I)/XHOLDA (O) SCIRXDB (I) MFSXB (I/O)

QUALPRD2 16 1, 0 GPIO16 (I/O) SPISIMOA (I/O) CANTXB (O) TZ5 (I)

17 3, 2 GPIO17 (I/O) SPISOMIA (I/O) CANRXB (I) TZ6 (I) 18 5, 4 GPIO18 (I/O) SPICLKA (I/O) SCITXDB (O) CANRXA (I) 19 7, 6 GPIO19 (I/O) SPISTEA (I/O) SCIRXDB (I) CANTXA (O) 20 9, 8 GPIO20 (I/O) EQEP1A (I) MDXA (O) CANTXB (O) 21 11, 10 GPIO21 (I/O) EQEP1B (I) MDRA (I) CANRXB (I) 22 13, 12 GPIO22 (I/O) EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) 23 15, 14 GPIO23 (I/O) EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)

QUALPRD3 24 17, 16 GPIO24 (I/O) ECAP1 (I/O) EQEP2A (I) MDXB (O)

25 19, 18 GPIO25 (I/O) ECAP2 (I/O) EQEP2B (I) MDRB (I) 26 21, 20 GPIO26 (I/O) ECAP3 (I/O) EQEP2I (I/O) MCLKXB (I/O) 27 23, 22 GPIO27 (I/O) ECAP4 (I/O) EQEP2S (I/O) MFSXB (I/O) 28 25, 24 GPIO28 (I/O) SCIRXDA (I) XZCS6 (O) 29 27, 26 GPIO29 (I/O) SCITXDA (O) XA19 (O) 30 29, 28 GPIO30 (I/O) CANRXA (I) XA18 (O) 31 31, 30 GPIO31 (I/O) CANTXA (O) XA17 (O)

GPAMUX1 GPIOx PER1 PER2 PER3

GPAQSEL1 GPAMUX1 = 0,0 GPAMUX1 = 0, 1 GPAMUX1 = 1, 0 GPAMUX1 = 1, 1

GPAMUX2

GPAQSEL2

GPAMUX2 = 0, 0 GPAMUX2 = 0, 1 GPAMUX2 = 1, 0 GPAMUX2 = 1, 1

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 4-18. GPIO-B Mux Peripheral Selection Matrix

GPBDIR

GPBDAT

GPBSET

GPBCLR

GPBTOGGLE

QUALPRD0 0 1, 0 GPIO32 (I/O) SDAA (I/OC)

1 3, 2 GPIO33 (I/O) SCLA (I/OC) 2 5, 4 GPIO34 (I/O) ECAP1 (I/O) XREADY (I) 3 7, 6 GPIO35 (I/O) SCITXDA (O) XR/W (O) 4 9, 8 GPIO36 (I/O) SCIRXDA (I) XZCS0 (O) 5 11, 10 GPIO37 (I/O) ECAP2 (I/O) XZCS7 (O) 6 13, 12 GPIO38 (I/O) XWE0(O) 7 15, 14 GPIO39 (I/O) XA16 (O)

QUALPRD1 8 17, 16 GPIO40 (I/O) XA0 (O)

9 19, 18 GPIO41 (I/O) XA1 (O) 10 21, 20 GPIO42 (I/O) XA2 (O) 11 23, 22 GPIO43 (I/O) XA3 (O) 12 25, 24 GPIO44 (I/O) XA4 (O) 13 27, 26 GPIO45 (I/O) XA5 (O) 14 29, 28 GPIO46 (I/O) XA6 (O) 15 31, 30 GPIO47 (I/O) XA7 (O)

QUALPRD2 16 1, 0 GPIO48 (I/O) ECAP5 (I/O) XD31 (I/O) SPISIMOD (I/O)

17 3, 2 GPIO49 (I/O) ECAP6 (I/O) XD30 (I/O) SPISOMID (I/O) 18 5, 4 GPIO50 (I/O) EQEP1A (I) XD29 (I/O) SPICLKD (I/O) 19 7, 6 GPIO51 (I/O) EQEP1B (I) XD28 (I/O) SPISTED (I/O) 20 9, 8 GPIO52 (I/O) EQEP1S (I/O) XD27 (I/O) Reserved 21 11, 10 GPIO53 (I/O) EQEP1I (I/O) XD26 (I/O) Reserved 22 13, 12 GPIO54 (I/O) SPISIMOA (I/O) XD25 (I/O) EQEP3A (I) 23 15, 14 GPIO55 (I/O) SPISOMIA (I/O) XD24 (I/O) EQEP3B (I)

QUALPRD3 24 17, 16 GPIO56 (I/O) SPICLKA (I/O) XD23 (I/O) EQEP3S (I/O)

25 19, 18 GPIO57 (I/O) SPISTEA (I/O) XD22 (I/O) EQEP3I (I/O) 26 21, 20 GPIO58 (I/O) MCLKRA (I/O) XD21 (I/O) EPWM7A (O) 27 23, 22 GPIO59 (I/O) MFSRA (I/O) XD20 (I/O) EPWM7B (O) 28 25, 24 GPIO60 (I/O) MCLKRB (I/O) XD19 (I/O) EPWM8A (O) 29 27, 26 GPIO61 (I/O) MFSRB (I/O) XD18 (I/O) EPWM8B (O) 30 29, 28 GPIO62 (I/O) SCIRXDC (I) XD17 (I/O) EPWM9A (O) 31 31, 30 GPIO63 (I/O) SCITXDC (O) XD16 (I/O) EPWM9B (O)

(1) Open drain

GPBMUX1 GPIOx PER1 PER2 PER3

GPBQSEL1 GPBMUX1 = 0, 0 GPBMUX1 = 0, 1 GPBMUX1 = 1, 0 GPBMUX1 = 1, 1

GPBMUX2

GPBQSEL2

(1)

Reserved

GPBMUX2 = 0, 0 GPBMUX2 = 0, 1 GPBMUX2 = 1, 0 GPBMUX2 = 1, 1

EPWMSYNCI (I) ADCSOCAO (O)

EPWMSYNCO (O) ADCSOCBO (O)

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

Table 4-19. GPIO-C Mux Peripheral Selection Matrix

GPCDIR

GPCDAT

GPCSET GPCMUX1

GPCCLR

GPCTOGGLE

no qual 0 1, 0 GPIO64 (I/O) XD15 (I/O)

1 3, 2 GPIO65 (I/O) XD14 (I/O) 2 5, 4 GPIO66 (I/O) XD13 (I/O) 3 7, 6 GPIO67 (I/O) XD12 (I/O) 4 9, 8 GPIO68 (I/O) XD11 (I/O) 5 11, 10 GPIO69 (I/O) XD10 (I/O) 6 13, 12 GPIO70 (I/O) XD9 (I/O) 7 15, 14 GPIO71 (I/O) XD8 (I/O)

no qual 8 17, 16 GPIO72 (I/O) XD7 (I/O)

9 19, 18 GPIO73 (I/O) XD6 (I/O) 10 21, 20 GPIO74 (I/O) XD5 (I/O) 11 23, 22 GPIO75 (I/O) XD4 (I/O) 12 25, 24 GPIO76 (I/O) XD3 (I/O) 13 27, 26 GPIO77 (I/O) XD2 (I/O) 14 29, 28 GPIO78 (I/O) XD1 (I/O) 15 31, 30 GPIO79 (I/O) XD0 (I/O)

GPCMUX2 GPCMUX2 = 0, 0 or 0, 1 GPCMUX2 = 1, 0 or 1, 1

no qual 16 1, 0 GPIO80 (I/O) XA8 (O)

17 3, 2 GPIO81 (I/O) XA9 (O) 18 5, 4 GPIO82 (I/O) XA10 (O) 19 7, 6 GPIO83 (I/O) XA11 (O) 20 9, 8 GPIO84 (I/O) XA12 (O) 21 11, 10 GPIO85 (I/O) XA13 (O) 22 13, 12 GPIO86 (I/O) XA14 (O) 23 15, 14 GPIO87 (I/O) XA15 (O)

GPIOx or PER1 PER2 or PER3

GPCMUX1 = 0, 0 or 0, 1 GPCMUX1 = 1, 0 or 1, 1

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

TMS320C28341

GPyCTRL Reg

SYNC

SYSCLKOUT

Qualification

Input Signal Qualified by

3 or 6 Samples

GPIOx

Time Between Samples

GPxQSEL

Number of Samples

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

www.ti.com

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices:

• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins

• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,

SPRS516B–MARCH 2009–REVISED JULY 2010

at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.

Figure 4-17. Qualification Using Sampling Window

• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-17 (for 6-sample mode).

• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

XD(31:0)

XA(19:0)

XZCS0

XZCS6

XZCS7

XWE0

XR/W

XREADY

XHOLD

XHOLDA

XCLKOUT

XRD

XINTFZone0

(8Kx16)

XINTFZone7

(1Mx16)

0x0030−0000

0x0020−0000

0x0010−0000

0x0000−5000

0x0000−4000

0x0000−0000

DataSpace ProgSpace

XINTFZone6

(1Mx16)

XWE1

A(19:0)

D(15:0)

16-bits

External wait-state generator

XREADY

XCLKOUT

XZCS0/6/7

XA(19:0)

XWE1

XRD

XWE0

XD(15:0)

XINTF

TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341

SPRS516B–MARCH 2009–REVISED JULY 2010

4.14 External Interface (XINTF)

This section gives a top-level view of the external interface (XINTF) that is implemented on the C2834x devices.

The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three fixed zones shown in Figure 4-18.

www.ti.com

Figure 4-18. External Interface Block Diagram

Figure 4-19 and Figure 4-20 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how

the functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 4-20 defines XINTF configuration and control registers.

Figure 4-19. Typical 16-bit Data Bus XINTF Connections

Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342,

Submit Documentation Feedback

TMS320C28341

Texas instruments TMS320C28341, TMS320C28345, TMS320C28344, TMS320C28346, TMS320C28342 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Overview

1.2 Features

1.3 Getting Started

2 Introduction

2.1 Pin Assignments

2.2 Signal Descriptions

3 Functional Overview

3.1 Memory Maps

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 External Interface (XINTF)

3.2.6 M0, M1 SARAMs

3.2.7 L0, L1, L2, L3, L4, L5, L6, L7 , H0, H1, H2, H3, H4, H5 SARAMs

3.2.8 Boot ROM

3.2.9 Security

3.2.10 Peripheral Interrupt Expansion (PIE) Block

3.2.11 External Interrupts (XINT1–XINT7, XNMI)

3.2.12 Oscillator and PLL

3.2.13 Watchdog

3.2.14 Peripheral Clocking

3.2.15 Low-Power Modes

3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn)

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

3.2.18 32-Bit CPU-Timers (0, 1, 2)

3.2.19 Control Peripherals

3.2.20 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 Interrupts

3.5.1 External Interrupts

3.6 System Control

3.6.1 OSC and PLL Block

3.6.1.1 External Reference Oscillator Clock Option

3.6.1.2 PLL-Based Clock Module

3.6.1.3 Loss of Input Clock

3.6.2 Watchdog Block

3.7 Low-Power Modes Block

4 Peripherals

4.1 DMA Overview

4.2 32-Bit CPU-Timers 0/1/2

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 /7/8/9)

4.4 High-Resolution PWM (HRPWM)

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)

4.6 Enhanced QEP Modules (eQEP1/2 /3)

4.7 External ADC Interface

4.8 Multichannel Buffered Serial Port (McBSP) Module

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

4.11 Serial Peripheral Interface (SPI) Module (SPI-A , SPI-D)

4.12 Inter-Integrated Circuit (I2C)

4.13 GPIO MUX

4.14 External Interface (XINTF)