TEXAS INSTRUMENTS TMS27C256 Technical data

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D

Organization...32768 by 8 Bits

D

Single 5-V Power Supply

D

Pin Compatible With Existing 256K MOS
ROMs, PROMs, and EPROMs

D

All Inputs /Outputs Fully TTL Compatible

D

Max Access/Min Cycle Time

± 10%

V

CC

’27C/PC256-10 100 ns
’27C/PC256-12 120 ns
’27C/PC256-15 150 ns
’27C/PC256-17 170 ns
’27C/PC256-20 200 ns
’27C/PC256-25 250 ns

D

Power Saving CMOS Technology

D

Very High-Speed SNAP! Pulse
Programming

D

3-State Output Buffers

D

400-mV Minimum DC Noise Immunity With
Standard TTL Loads

D

Latchup Immunity of 250 mA on All Input
and Output Lines

D

Low Power Dissipation (VCC = 5.5 V)
– Active...165 mW Worst Case
– Standby...1.4 mW Worst Case

(CMOS Input Levels)

D

Temperature Range Options

D

256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)

description

The TMS27C256 series are 32768 by 8-bit
(262144-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).

The TMS27PC256 series are 32768 by 8-bit
(262144-bit), one-time programmmable (OTP)
electrically programmable read-only memories
(PROMs).

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

J PACKAGE
(TOP VIEW)

V

1

PP

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

DQ0

11

DQ1

12

DQ2

13

GND

5

A6

6

A5

7

A4

8

A3
A2

9

A1

10

A0

11

NC

12

DQ0

13

A0–A14 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
E
G
GND Ground
NC No Internal Connection
NU Make No External Connection
V

CC

V

PP

†

Only in program mode

14

FM PACKAGE

(TOP VIEW)

PP

A7

A12VNUVA14

3213231

430

14

15 16 17 18 19

DQ1

DQ2NUDQ3

GND

PIN NOMENCLATURE

Chip Enable/Powerdown
Output Enable

5-V Power Supply
13-V Power Supply

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

V

CC

A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3

20

DQ4

†

A13

29
28
27
26
25
24
23
22
21

DQ5

A8
A9
A1 1
NC
G
A10
E
DQ7
DQ6

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1997, Texas Instruments Incorporated

1

TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

description (continued)

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.

The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.

The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is supplied in a 32-lead
plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).

The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffixes) and – 40°C to 85°C (JE and FME suffixes). See Table 1.

All package styles conform to JEDEC standards.

Table 1. Temperature Range Suffixes

EPROM

AND

OTP PROM

TMS27C512-xxx JL JE
TMS27PC512-xxx FML FME

SUFFIX FOR OPERATING

FREE-AIR TEMPERATURE RANGES

0°C TO 70°C –40°C TO 85°C

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming . All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a V

of 13 V and a VCC of 6.5 V for a nominal programming time of four seconds.

PP

For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

operation

The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V

FUNCTION

E V
G V

V

PP

V

CC

A9 X X X X X X VH‡ VH‡
A0 X X X X X X V

DQ0–DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z

†

X can be VIL or VIH.

‡

VH = 12 V ± 0.5 V.

READ

IL
IL

V

CC

V

CC

during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.

PP

Table 2. Operation Modes

†

MODE

OUTPUT

DISABLE

V

IL

V

IH

V

CC

V

CC

STANDBY PROGRAMMING VERIFY

V

IH

X V

V

CC

V

CC

V

IL

IH

V

PP

V

CC

V

IH

V

IL

V

PP

V

CC

PROGRAM

INHIBIT

V

IH

X V

V

PP

V

CC

SIGNATURE

MODE

V
V

IL

CODE

MFG DEVICE

97 04

V

IL

IL
CC
CC

V

IH

read/output disable

When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E

and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.

power down

Active I
inputs) by applying a high TTL or CMOS signal to the E

supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level

CC

pin. In this mode all outputs are in the high-impedance

state.

erasure (TMS27C256)

Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity × exposure time) is 15-W•s/cm

2

. A typical 12-mW/ cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

3

TMS27C256 32768 BY 8-BIT UV ERASABLE

IDENTIFIER

†

TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

initializing (TMS27PC256)

The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

SNAP! Pulse programming

The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte

verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.

The programming mode is achieved when V

= 13 V , VCC = 6.5 V , G = VIH, and E = VIL. More than one device

PP

can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAP! Pulse programming routine is complete, all bits are verified with V

= VPP = 5 V.

CC

program inhibit

Programming can be inhibited by maintaining a high level input on the E

pin.

program verify

Programmed bits can be verified with V

= 13 V when G = VIL and E = VIH.

PP

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V . T wo identifier bytes are accessed by toggling A0. All other addresses must
be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 04, as shown in Table 3.

Table 3. Signature Mode

PINS

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

MANUFACTURER CODE V

DEVICE CODE V

†

E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, VPP = VCC, PGM = VIH or VIL.

1 0 0 1 0 1 1 1 97

IL

0 0 0 0 0 1 0 0 04

IH

is pulsed.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

Start

Address = First Location

Increment

Address

VCC = 6.5 V, VPP = 13 V

Program One Pulse = tw = 100 µs

Last

Address?

Yes

Address = First Location

X = 0

Verify

One Byte

Pass

No

Fail

Increment Address

Program One Pulse = tw = 100 µs

No

X = 10?X = X + 1

Program

Mode

Interactive

Mode

No

VCC = VPP = 5 V ±10%

Last

Address?

Yes Yes

Compare
All Bytes

To Original

Data

Pass

Device Passed

Fail

Device Failed

Figure 1. SNAP! Pulse Programming Flowchart

Final

Verification

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5

TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

logic symbol

10

A0

9

A1

8

A2

7

A3

6

A4

5

A5

4

A6

3

A7

25

A8

24

A9

21

A10

23

A11

2

A12

26

A13

27

A14

20

E

22

G

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J package.

†

0

14
[PWR DWN]

&

EPROM

32 768 × 8

0

A

32 767

EN

&

OTP PROM

32 768 × 8

0

A

32 767

EN

A
A
A
A
A
A
A
A

11
12
13
15
16
17
18
19

10

A0

9

A1

8

A2

7

A3

6

11

A
A
A
A
A
A
A
A

12
13
15
16
17
18
19

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14

5
4

3
25
24
21
23

2
26
27

20

E

22

G

0

14
[PWR DWN]

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Supply voltage range, V
Input voltage range (see Note 1): All inputs except A9 : –0.6 V to V

Output voltage range (see Note 1) : –0.6 V to V
Operating free-air temperature range (’27C256-_ _JL, ’27PC256-_ _FML) T
Operating free-air temperature range (’27C5256-_ _JE, ’27PC256-_ _FME) T
Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

(see Note 1) : –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

: –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PP

A9 : –0.6 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

:0°C to 70°C. . . . . . . . . . . . . .

A

: –40°C to 85°C. . . . . . . . . . .

: –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

A

CC

CC

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

‡

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

VCCSuppl

oltage

V

VPPSuppl

oltage

V

VIHHigh-level dc input voltage

V

VILLow-level dc input voltage

V

VOHHigh-level dc output voltage

V

VOLLow-level dc output voltage

V

I

CC

y

A

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

pp

y v

p

p

T

Operating free-air temperature

A

T

Operating free-air temperature

A

NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted

into or removed from the board when VPP or VCC is applied.

electrical characteristics over recommended ranges of operating conditions

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

p

p

I

Input current (leakage) VI = 0 V to 5.5 V ±1 µA

I

I

Output current (leakage) VO = 0 V to V

O

I

PP1VPP

I

PP2VPP

CC1

I

CC2VCC

supply current VPP = VCC = 5.5 V 1 10 µA
supply current (during program pulse) VPP = 13 V 35 50 mA

V

supply current

(standby)

supply current (active)

TTL-input level VCC = 5.5 V, E = V
CMOS-input level

Read mode (see Note 2) 4.5 5 5.5
SNAP! Pulse programming algorithm 6.25 6.5 6.75
Read mode VCC–0.6 VCC+0.6
SNAP! Pulse programming algorithm 12.75 13 13.25

TTL 2 VCC+1
CMOS VCC– 0.2 VCC+1
TTL – 0.5 0.8
CMOS – 0.5 0.2
’27C256-_ _JL

’27PC256-_ _FML
’27C256-_ _JE

’27PC256-_ _FME

IOH = – 2.5 mA 3.5
IOH = – 20 µA VCC– 0.1
IOL = 2.1 mA 0.4
IOL = 20 µA 0.1

CC

IH

VCC = 5.5 V, E = V
VCC = 5.5 V, E = VIL,

t

= minimum cycle time,

cycle

outputs open

CC

0 70 °C

–40 85 °C

±1 µA

250 500
100 250

15 30 mA

µ

capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz

C

i

C

o

†

Capacitance measurements are made on a sample basis only.

‡

Typical values are at TA = 25°C and nominal voltages.

†

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

Input capacitance VI = 0, f = 1 MHz 6 10 pF
Output capacitance VO = 0, f = 1 MHz 10 14 pF

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

7

TMS27C256 32768 BY 8-BIT UV ERASABLE

(SEE NOTES 3 AND 4)

1 Series 74 TTL Load

f

(SEE NOTES 3 AND 4)

1 Series 74 TTL Load

f

TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

switching characteristics over recommended range of operating conditions

t

a(A)

t

a(E)

t

en(G)

t

dis

t

v(A)

PARAMETER

Access time from address 100 120 150 ns
Access time from chip enable 100 120 150 ns
Output enable time from G
Output disable time from G or E, whichever

occurs first
Output data valid time after change of

address, E

†

, or G, whichever occurs first

†

TEST CONDITIONS

CL = 100 pF,

Input tr ≤ 20 ns,

Input t

≤ 20 ns

’27C256-10
’27PC256-10

MIN MAX MIN MAX MIN MAX

,

0 45 0 45 0 60 ns

0 0 0 ns

’27C256-12
’27PC256-12

55 55 75 ns

’27C256-15
’27PC256-15

UNIT

PARAMETER

t
t
t

t

t

†
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

Access time from address 170 200 250 ns

a(A)

Access time from chip enable 170 200 250 ns

a(E)

Output enable time from G

en(G)

Output disable time from G or E, whichever

dis

occurs first
Output data valid time after change of

v(A)

address, E

Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.

4. Common test conditions apply for the t

†

, or G, whichever occurs first

0.8 V for logic low) (see Figure 2).

†

TEST CONDITIONS

CL = 100 pF,

Input tr ≤ 20 ns,

Input t

≤ 20 ns

except during programming.

dis

’27C256-17
’27PC256-17

MIN MAX MIN MAX MIN MAX

,

0 60 0 60 0 60 ns

0 0 0 ns

’27C256-20
’27PC256-20

75 75 100 ns

’27C256-25
’27PC256-25

UNIT

switching characteristics for programming: VCC = 6.50 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)

PARAMETER MIN MAX UNIT

t

dis(G)

t

en(G)

NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

Output disable time from G 0 130 ns
Output enable time from G 150 ns

0.8 V for logic low).

timing requirements for programming

MIN NOM MAX UNIT

t

h(A)

t

h(D)

t

w(IPGM)

t

su(A)

t

su(G)

t

su(E)

t

su(D)

t

su(VPP)

t

su(VCC)

Hold time, address 0 µs
Hold time, data 2 µs
Pulse duration, initial program 95 100 105 µs
Setup time, address 2 µs
Setup time, G 2 µs
Setup time, E 2 µs
Setup time, data 2 µs
Setup time, V
Setup time, V

PP
CC

2 µs
2 µs

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

Output

Under Test

NOTE A: CL includes probe and fixture capacitance.

ac testing input/output wave forms

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

2.08 V

RL = 800 Ω

CL = 100 pF
(see Note A)

2.4 V

0.4 V

2 V 2 V

0.8 V 0.8 V

AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.

Figure 2. AC Testing Output Load Circuit

V

A0–A14

DQ0–DQ7

Addresses Valid

E

t

a(E)

G

t

dis

Hi-Z

Hi-Z

t

a(A)

t

en(G)

t

v(A)

Output Valid

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

Figure 3. Read-Cycle Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

9

TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Program

A0–A14

t

su(A)

DQ0–DQ7

V

PP

V

CC

E

t

w(IPGM)

G

†

t

and t

dis(G)

‡

13-V VPP and 6.5-V VCC for SNAP! Pulse programming

are characteristics of the device but must be accommodated by the programmer

en(G)

Data-In Stable Data-Out Valid

t

su(D)

t

su(VPP)

t

su(VCC)

t

su(E)

Address Stable

Hi-Z

t

h(D)

t

su(G)

Verify

t

dis(G)

t

en(G)

V

Address

N+1

t

h(A)

†

†

IH

V

IL

VIH/V

VIL/V

VPP‡

V

CC

VCC‡

V

CC

V

IH

V

IL

V

IH

V

IL

OH

OH

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C256 32768 BY 8-BIT UV ERASABLE

TMS27PC256 32768 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER

Seating Plane

0.140 (3,56)

0.495 (12,57)

0.485 (12,32)

0.453 (11,51)

0.447 (11,35)

4

301

0.129 (3,28)

0.123 (3,12)

0.049 (1,24)

0.043 (1,09)

0.008 (0,20) NOM

0.132 (3,35)

0.004 (0,10)

13

5

14

0.050 (1,27)

20

29

0.020 (0,51)

0.015 (0,38)

0.595 (15,11)

0.585 (14,86)

0.553 (14,05)

0.547 (13,89)

0.030 (0,76)
TYP

21

4040201-4/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-016

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

11

TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997

J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

B

24

1

0.090 (2,29)

0.060 (1,53)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

13

12

0.018 (0,46) MIN

0.022 (0,56)

0.014 (0,36)

C

0.175 (4,45)

0.140 (3,56)

Seating Plane

0.125 (3,18) MIN

Lens Protrusion

0.010 (0,25) MAX

A

0°–10°

0.012 (0,30)

0.008 (0,20)

DIM

NOTES: A. All linear dimensions are in inches (millimeters).

PINS**

MAX

A

MIN
MAX

B

MIN
MAX

C

MIN

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13)

1.235(31,37) 1.235(31,37)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

24

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.465(37,21) 1.465(37,21)

1.435(36,45) 1.435(36,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

28

WIDE WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.668(42,37) 1.668(42,37)

1.632(41,45) 1.632(41,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

32

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

2.068(52,53) 2.068(52,53)

2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

4040084/B 04/95

40

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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