TEXAS INSTRUMENTS TMS27C256 Technical data
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D
Organization...32768 by 8 Bits
D
Single 5-V Power Supply
D
Pin Compatible With Existing 256K MOS
ROMs, PROMs, and EPROMs
D
All Inputs /Outputs Fully TTL Compatible
D
Max Access/Min Cycle Time
± 10%
V
CC
’27C/PC256-10 100 ns
’27C/PC256-12 120 ns
’27C/PC256-15 150 ns
’27C/PC256-17 170 ns
’27C/PC256-20 200 ns
’27C/PC256-25 250 ns
D
Power Saving CMOS Technology
D
Very High-Speed SNAP! Pulse
Programming
D
3-State Output Buffers
D
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Lines
D
Low Power Dissipation (VCC = 5.5 V)
– Active...165 mW Worst Case
– Standby...1.4 mW Worst Case
(CMOS Input Levels)
D
Temperature Range Options
D
256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
description
The TMS27C256 series are 32768 by 8-bit
(262144-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
The TMS27PC256 series are 32768 by 8-bit
(262144-bit), one-time programmmable (OTP)
electrically programmable read-only memories
(PROMs).
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
J PACKAGE
(TOP VIEW)
V
1
PP
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
DQ0
11
DQ1
12
DQ2
13
GND
5
A6
6
A5
7
A4
8
A3
A2
9
A1
10
A0
11
NC
12
DQ0
13
A0–A14 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
E
G
GND Ground
NC No Internal Connection
NU Make No External Connection
V
CC
V
PP
†
Only in program mode
14
FM PACKAGE
(TOP VIEW)
PP
A7
A12VNUVA14
3213231
430
14
15 16 17 18 19
DQ1
DQ2NUDQ3
GND
PIN NOMENCLATURE
Chip Enable/Powerdown
Output Enable
5-V Power Supply
13-V Power Supply
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
V
CC
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
20
DQ4
†
A13
29
28
27
26
25
24
23
22
21
DQ5
A8
A9
A1 1
NC
G
A10
E
DQ7
DQ6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1997, Texas Instruments Incorporated
1
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is supplied in a 32-lead
plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffixes) and – 40°C to 85°C (JE and FME suffixes). See Table 1.
All package styles conform to JEDEC standards.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
TMS27C512-xxx JL JE
TMS27PC512-xxx FML FME
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE RANGES
0°C TO 70°C –40°C TO 85°C
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming . All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a V
of 13 V and a VCC of 6.5 V for a nominal programming time of four seconds.
PP
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V
FUNCTION
E V
G V
V
PP
V
CC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X V
DQ0–DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z
†
X can be VIL or VIH.
‡
VH = 12 V ± 0.5 V.
READ
IL
IL
V
CC
V
CC
during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
PP
Table 2. Operation Modes
†
MODE
OUTPUT
DISABLE
V
IL
V
IH
V
CC
V
CC
STANDBY PROGRAMMING VERIFY
V
IH
X V
V
CC
V
CC
V
IL
IH
V
PP
V
CC
V
IH
V
IL
V
PP
V
CC
PROGRAM
INHIBIT
V
IH
X V
V
PP
V
CC
SIGNATURE
MODE
V
V
IL
CODE
MFG DEVICE
97 04
V
IL
IL
CC
CC
V
IH
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E
and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
inputs) by applying a high TTL or CMOS signal to the E
supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level
CC
pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity × exposure time) is 15-W•s/cm
2
. A typical 12-mW/ cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS27C256 32768 BY 8-BIT UV ERASABLE
IDENTIFIER
†
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
initializing (TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V
= 13 V , VCC = 6.5 V , G = VIH, and E = VIL. More than one device
PP
can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAP! Pulse programming routine is complete, all bits are verified with V
= VPP = 5 V.
CC
program inhibit
Programming can be inhibited by maintaining a high level input on the E
pin.
program verify
Programmed bits can be verified with V
= 13 V when G = VIL and E = VIH.
PP
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V . T wo identifier bytes are accessed by toggling A0. All other addresses must
be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 04, as shown in Table 3.
Table 3. Signature Mode
PINS
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
MANUFACTURER CODE V
DEVICE CODE V
†
E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, VPP = VCC, PGM = VIH or VIL.
1 0 0 1 0 1 1 1 97
IL
0 0 0 0 0 1 0 0 04
IH
is pulsed.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
Start
Address = First Location
Increment
Address
VCC = 6.5 V, VPP = 13 V
Program One Pulse = tw = 100 µs
Last
Address?
Yes
Address = First Location
X = 0
Verify
One Byte
Pass
No
Fail
Increment Address
Program One Pulse = tw = 100 µs
No
X = 10?X = X + 1
Program
Mode
Interactive
Mode
No
VCC = VPP = 5 V ±10%
Last
Address?
Yes Yes
Compare
All Bytes
To Original
Data
Pass
Device Passed
Fail
Device Failed
Figure 1. SNAP! Pulse Programming Flowchart
Final
Verification
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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