TEXAS INSTRUMENTS TMS27C240 Technical data

查询TMS27C240供应商

TMS27C240 262144 BY 16-BIT UV ERASABLE

TMS27PC240 262144 BY 16-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997

D

Organization . . . 262144 by 16 Bits

D

Single 5-V Power Supply

D

All Inputs/Outputs Fully TTL Compatible

D

Static Operations (No Clocks, No Refresh)

D

Max Access/Min Cycle Time

± 10%

V

CC

’27C/PC240-10 100 ns
’27C/PC240-12 120 ns
’27C/PC240-15 150 ns

D

16-Bit Output For Use in
Microprocessor-Based Systems

D

Very High Speed SNAP! Pulse
Programming

D

Power-Saving CMOS Technology

D

3-State Output Buffers

D

400-mV Minimum DC Noise Immunity With
Standard TTL Loads

D

Latchup Immunity of 250 mA on All Input
and Output Lines

D

No Pullup Resistors Required

D

Low Power Dissipation (VCC = 5.5 V)
– Active . . . 275 mW Worst Case
– Standby...0.55 mW Worst Case

(CMOS-Input Levels)

D

Temperature Range Options

TMS27PC240 FN PACKAGE

(TOP VIEW)

DQ13

DQ14

5 43 26

DQ12
DQ11
DQ10

GND

7
8
9

DQ9

10

DQ8

11

†

12

NC

13

DQ7

14

DQ6

15

DQ5

16

DQ4

17

18 19

20 21 22 23

DQ3

DQ2

PIN NOMENCLATURE

A0–A17 Address Inputs
DQ0–DQ15 Inputs (programming)/Outputs
E
G
GND Ground
NC No Connection
V

CC

V

PP

†

Pins 11 and 30 (J package) and pins 12 and 34
(FN package) must be connected externally to
ground.

‡

Only in program mode

PPVCC

DQ15EV

G

DQ1

DQ0

Chip Enable
Output Enable

5-V Supply
13-V Power Supply

A17

NC

1

42 41 40

44 43

24 25 26 27 28

A0

A1A2A3

NC

A16

‡

A15

A14

39
38
37
36
35
34
33
32
31
30
29

A4

A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5

†

description

The TMS27C240 series are 262144 by 16-bit (4194304-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).

The TMS27PC240 series are 262 144 by 16-bit (4 194 304-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.

The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C240 is offered with two choices of temperature
ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

1

TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997

TMS27C240 J PACKAGE

(TOP VIEW)

V

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8

GND

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

PP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

CC

A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0

†

1

E

2
3
4
5
6
7
8
9
10

†

11
12
13
14
15
16
17
18
19

G

20

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C240 262144 BY 16-BIT UV ERASABLE

TMS27PC240 262144 BY 16-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997

description (continued)

The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC240 is offered with two choices of temperature ranges of 0°C
to 70°C (FNL suffix) and –40°C to 85°C (FNE suffix). See Table 1.

Table 1. Temperature Range Suffixes

SUFFIX FOR OPERATING FREE-

AIR TEMPERATURE RANGES

0°C TO 70°C –40°C TO 85°C

TMS27C240-XXX JL JE
TMS27PC240-XXX FNL FNE

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming . All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.

operation

The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in Table 2. The read mode
requires a single 5-V supply . All inputs are TTL level except for V

during programming (13 V for SNAP! Pulse),

PP

and 12 V on A9 for the signature mode.

Table 2. Operation Modes

CC

CC
CC

CC
CC
CC
CC

CC

CC

†

A9 A0 I/O

X X
X X Hi-Z

X X Hi-Z
X X Data In
X X Data Out
X X Hi-Z

‡

V

H

‡

V

H

V

IL

V

IH

Manufacturer’s

Read V
Output Disable V

Standby V
Programming V
Verify V
Program Inhibit V

Signature Mode (Mfg) V

Signature Mode (Device) V

†

X can be VIL or VIH.

‡

VH = 12 V ±0.5 V.

E G V

IL
IL

IH

IL
IH
IH

IL

IL

V

IL

V

IH

X V

V

IH

V

IL

V

IH

V

IL

V

IL

FUNCTION

PP

V

CC

V

CC
CC

V

PP

V

PP

V

PP

V

CC

V

CC

V

V
V

V
V
V
V

V

V

read/output disable

DQ0–DQ7

DQ8–DQ15

Code

0097

Device Code

0030

When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E

and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

3

TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES

SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997

latchup immunity

Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.

power down

Active I
100 µA by applying a high CMOS input on E

supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to

CC

. In this mode all outputs are in the high-impedance state.

erasure (TMS27C240)

Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s/cm

2

. A 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.

initializing (TMS27PC240)

The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

SNAP! Pulse programming

The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart, shown in Figure 1.

The initial setup is V

= 13 V , VCC = 6.5 V , E = VIH, and G = VIH. Once the initial location is selected, the data

PP

is presented in parallel (eight bits) on pins DQ0 through DQ15. Once addresses and data are stable, the
programming mode is achieved when E

is pulsed low (VIL) with a pulse duration of t

w(PGM)

. Every location is

programmed only once before going to interactive mode.
In the interactive mode, the word is verified at V

is not read, the programming is performed by pulling E

= 13 V , VCC = 6.5 V , E = VIH, and G = VIL. If the correct data

PP

low with a pulse duration of t

w(PGM)

. This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with V

= VPP = 5 V ± 10%.

CC

program inhibit

Programming can be inhibited by maintaining a high level input on the E

program verify

Programmed bits can be verified with V

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

= 13 V when G = VIL and E = VIH.

PP

and G pins.

IDENTIFIER

†

TMS27C240 262144 BY 16-BIT UV ERASABLE

TMS27PC240 262144 BY 16-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by toggling
A0. DQ0–DQ7 contain the valid codes. All other addresses must be held low. The signature code for these
devices is 9730. A0 low selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 30
(Hex), as shown in Table 3.

Table 3. Signature Mode

PINS

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

MANUFACTURER CODE V
DEVICE CODE V

†

E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A17 = VIL, VPP = VCC, PGM = VIH or VIL.

IL

IH

1 0 0 1 0 1 1 1 97
0 0 1 1 0 0 0 0 30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5