查询TMS27C240供应商
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
D
Organization . . . 262144 by 16 Bits
D
Single 5-V Power Supply
D
All Inputs/Outputs Fully TTL Compatible
D
Static Operations (No Clocks, No Refresh)
D
Max Access/Min Cycle Time
± 10%
V
CC
’27C/PC240-10 100 ns
’27C/PC240-12 120 ns
’27C/PC240-15 150 ns
D
16-Bit Output For Use in
Microprocessor-Based Systems
D
Very High Speed SNAP! Pulse
Programming
D
Power-Saving CMOS Technology
D
3-State Output Buffers
D
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Lines
D
No Pullup Resistors Required
D
Low Power Dissipation (VCC = 5.5 V)
– Active . . . 275 mW Worst Case
– Standby...0.55 mW Worst Case
(CMOS-Input Levels)
D
Temperature Range Options
TMS27PC240 FN PACKAGE
(TOP VIEW)
DQ13
DQ14
5 43 26
DQ12
DQ11
DQ10
GND
7
8
9
DQ9
10
DQ8
11
†
12
NC
13
DQ7
14
DQ6
15
DQ5
16
DQ4
17
18 19
20 21 22 23
DQ3
DQ2
PIN NOMENCLATURE
A0–A17 Address Inputs
DQ0–DQ15 Inputs (programming)/Outputs
E
G
GND Ground
NC No Connection
V
CC
V
PP
†
Pins 11 and 30 (J package) and pins 12 and 34
(FN package) must be connected externally to
ground.
‡
Only in program mode
PPVCC
DQ15EV
G
DQ1
DQ0
Chip Enable
Output Enable
5-V Supply
13-V Power Supply
A17
NC
1
42 41 40
44 43
24 25 26 27 28
A0
A1A2A3
NC
A16
‡
A15
A14
39
38
37
36
35
34
33
32
31
30
29
A4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
†
description
The TMS27C240 series are 262144 by 16-bit (4194304-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC240 series are 262 144 by 16-bit (4 194 304-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C240 is offered with two choices of temperature
ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
1
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
TMS27C240 J PACKAGE
(TOP VIEW)
V
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
GND
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
PP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
†
1
E
2
3
4
5
6
7
8
9
10
†
11
12
13
14
15
16
17
18
19
G
20
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC240 is offered with two choices of temperature ranges of 0°C
to 70°C (FNL suffix) and –40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING FREE-
AIR TEMPERATURE RANGES
0°C TO 70°C –40°C TO 85°C
TMS27C240-XXX JL JE
TMS27PC240-XXX FNL FNE
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming . All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in Table 2. The read mode
requires a single 5-V supply . All inputs are TTL level except for V
during programming (13 V for SNAP! Pulse),
PP
and 12 V on A9 for the signature mode.
Table 2. Operation Modes
CC
CC
CC
CC
CC
CC
CC
CC
CC
†
A9 A0 I/O
X X
X X Hi-Z
X X Hi-Z
X X Data In
X X Data Out
X X Hi-Z
‡
V
H
‡
V
H
V
IL
V
IH
Manufacturer’s
Read V
Output Disable V
Standby V
Programming V
Verify V
Program Inhibit V
Signature Mode (Mfg) V
Signature Mode (Device) V
†
X can be VIL or VIH.
‡
VH = 12 V ±0.5 V.
E G V
IL
IL
IH
IL
IH
IH
IL
IL
V
IL
V
IH
X V
V
IH
V
IL
V
IH
V
IL
V
IL
FUNCTION
PP
V
CC
V
CC
CC
V
PP
V
PP
V
PP
V
CC
V
CC
V
V
V
V
V
V
V
V
V
read/output disable
DQ0–DQ7
DQ8–DQ15
Code
0097
Device Code
0030
When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E
and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
latchup immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
100 µA by applying a high CMOS input on E
supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
CC
. In this mode all outputs are in the high-impedance state.
erasure (TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s/cm
2
. A 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.
initializing (TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart, shown in Figure 1.
The initial setup is V
= 13 V , VCC = 6.5 V , E = VIH, and G = VIH. Once the initial location is selected, the data
PP
is presented in parallel (eight bits) on pins DQ0 through DQ15. Once addresses and data are stable, the
programming mode is achieved when E
is pulsed low (VIL) with a pulse duration of t
w(PGM)
. Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at V
is not read, the programming is performed by pulling E
= 13 V , VCC = 6.5 V , E = VIH, and G = VIL. If the correct data
PP
low with a pulse duration of t
w(PGM)
. This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with V
= VPP = 5 V ± 10%.
CC
program inhibit
Programming can be inhibited by maintaining a high level input on the E
program verify
Programmed bits can be verified with V
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
= 13 V when G = VIL and E = VIH.
PP
and G pins.
IDENTIFIER
†
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by toggling
A0. DQ0–DQ7 contain the valid codes. All other addresses must be held low. The signature code for these
devices is 9730. A0 low selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 30
(Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
MANUFACTURER CODE V
DEVICE CODE V
†
E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A17 = VIL, VPP = VCC, PGM = VIH or VIL.
IL
IH
1 0 0 1 0 1 1 1 97
0 0 1 1 0 0 0 0 30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
Increment
Address
VCC = 6.5 V, VPP = 13 V
Program One Pulse = tw = 100 µs
Last
Address?
Yes
Address = First Location
X = 0
Verify
One Byte
Pass
No
Fail
Increment Address
Program One Pulse = tw = 100 µs
No
X = 10?X = X + 1
Program
Mode
Interactive
Mode
No
VCC = VPP = 5 V ±10%
Last
Address?
Yes Yes
Compare
All Bytes
To Original
Data
Pass
Device Passed
Fail
Device Failed
Figure 1. SNAP! Pulse Programming Flow Chart
Final
Verification
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
logic symbol
†
EPROM 256K × 16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
2
E
0
A
262 143
17
[PWR DWN]
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
0
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
19
18
17
16
15
14
13
12
10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
9
DQ9
8
DQ10
7
DQ11
6
DQ12
5
DQ13
4
DQ14
3
DQ15
&
20
G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the J package.
EN
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
7
TMS27C240 262144 BY 16-BIT UV ERASABLE
VCCSuppl
oltage
V
VPPSuppl
oltage
V
VIHHigh-level dc input voltage
V
VILLow-level dc input voltage
V
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC (see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, V
Input voltage range (see Note 1): All inputs except A9 –0.6 V to V
–0.6 V to 13 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PP
CC
+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A9 –0.6 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (see Note 1) –0.6 V to V
CC
+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range (’27C240-_ _JL; ’27PC240-_ _ FNL) 0° C to 70° C. . . . . . . . . . . . . . . .
Operating free-air temperature range (’27C240-_ _JE, ’27PC240-_ _FNE) – 40° C to 85° C. . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
MIN NOM MAX UNIT
pp
y v
pp
y v
p
p
T
A
T
A
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
Operating free-air temperature
Operating free-air temperature
into or removed from the board when VPP or VCC is applied.
Read mode (see Note 2) 4.5 5 5.5
SNAP! Pulse programming algorithm 6.25 6.5 6.75
Read mode VCC–0.6 VCC+0.6
SNAP! Pulse programming algorithm 12.75 13 13.25
TTL 2 VCC+0.5
CMOS VCC– 0.2 VCC+0.5
TTL – 0.5 0.8
CMOS – 0.5 0.2
’27C240-_ _JL
’27PC240-_ _ FNL
’27PC240-_ _FNE
’27C240-_ _JE
0 70 °C
–40 85 °C
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
VOHHigh-level dc output voltage
V
VOLLow-level dc output voltage
V
I
VCC supply current (standby)
,
C
L
100 F,
In ut t
f
ns
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER TEST CONDITIONS MIN MAX UNIT
p
p
I
Input current (leakage) VI = 0 V to 5.5 V ±1 µA
I
I
Output current (leakage) VO = 0 V to V
O
I
PP1VPP
I
PP2VPP
CC1
I
CC2VCC
supply current VPP = VCC = 5.5 V 10 µA
supply current (during program pulse) VPP = 13 V 50 mA
pp
supply current (active)
IOH = – 400 µA 2.4
IOH = – 20 µA VCC– 0.1
IOL = 2.1 mA 0.4
IOL = 20 µA 0.1
CC
VCC = 5.5 V, E = V
VCC = 5.5 V, E = V
VCC = 5.5 V, E = VIL,
t
= minimum cycle time,
cycle
outputs open
IH
CC
±1 µA
100 µA
50 mA
1 mA
capacitance over recommended ranges of supply voltage and operating free-air
temperature, f = 1 MHz
C
i
C
o
†
Capacitance measurements are made on a sample basis only.
‡
Typical values are at TA = 25°C and nominal voltages.
Input capacitance VI = 0 V 4 8 pF
Output capacitance VO = 0 V 8 12 pF
†
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
’27C240-10
PARAMETER TEST CONDITIONS
t
a(A)
t
a(E)
t
en(G)
t
dis
t
v(A)
§
Value calculated from 0.5 V delta to measured level.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V . T iming measurements are made at 2 V for logic high and
Access time from address 100 120 150 ns
Access time from chip enable
Output enable time from G
Output disable time from G or E, whichever
occurs first
Output data valid time after change of
address, E
4. Common test conditions apply for t
†
, or G, whichever occurs first
0.8 V for logic low (see Figure 2).
§
dis
except during programming.
C
= 100 pF
1 Series 74
TTL load,
Input tr ≤ 20 ns,
≤ 20
p
’27PC240-10
MIN MAX MIN MAX MIN MAX
0 50 0 50 0 50 ns
0 0 0 ns
’27C240-12
’27PC240-12
100 120 150 ns
50 50 50 ns
’27C240-15
’27PC240-15
UNIT
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
9
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER MIN MAX UNIT
t
dis(G)
t
en(G)
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
timing requirements for programming
t
w(PGM)
t
su(A)
t
su(E)
t
su(G)
t
su(D)
t
su(VPP)
t
su(VCC)
t
h(A)
t
h(D)
Output disable time from G 0 100 ns
Output enable time from G 150 ns
0.8 V for logic low. (See Figure 2)
MIN NOM MAX UNIT
Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs
Setup time, address 2 µs
Setup time, E 2 µs
Setup time, G 2 µs
Setup time, data 2 µs
Setup time, V
Setup time, V
Hold time, address 0 µs
Hold time, data 2 µs
PP
CC
2 µs
2 µs
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
2.4 V
0.40 V
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
2 V
0.8 V
Figure 2. The ac Testing Output Load Circuit and Waveform
E
G
DQ0–DQ15
Hi-Z Hi-Z
2 V
0.8 V
Address ValidA0–A17
t
a(E)
t
en(G)
t
a(A)
Output
Valid
t
dis
t
v(A)
Figure 3. Read-Cycle Timing
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Program
Verify
A0–A17
t
su(A)
DQ0–DQ15
V
PP
V
CC
E
G
†
13-V VPP and 6.5-V VCC for SNAP! Pulse programming
t
w(PGM)
Data-In Stable
t
su(D)
t
su(VPP)
t
su(E)
t
su(VCC)
Figure 4. Programming-Cycle Timing (SNAP! Pulse Programming)
Address Stable
Hi-Z
t
en(G)
t
h(D)
t
su(G)
Data-Out
Stable
t
h(A)
t
dis(G)
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
D
D1
13
4
E1E
8
9
NO. OF
PINS
**
D/E
19
13
18
14
0.032 (0,81)
0.026 (0,66)
0.050 (1,27)
0.008 (0,20) NOM
D1/E1
MINMAXMIN
MAX
D2/E2
MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN
D2/E2
D2/E2
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
MAX
M
20
28
44
52
68
84
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
0.785 (19,94)
0.985 (25,02)
1.185 (30,10)
0.395 (10,03)
0.495 (12,57)
0.695 (17,65)
0.795 (20,19)
0.995 (25,27)
1.195 (30,35)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
0.350 (8,89)
0.450 (11,43)
0.650 (16,51)
0.750 (19,05)
0.950 (24,13)
1.150 (29,21)
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.756 (19,20)
0.958 (24,33)
1.158 (29,41)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.441 (11,20)
0.541 (13,74)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
0.469 (11,91)
0.569 (14,45)
4040005/B 03/95
13
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
24
1
0.090 (2,29)
0.060 (1,53)
0.100 (2,54)
0.065 (1,65)
0.045 (1,14)
13
12
0.018 (0,46) MIN
0.022 (0,56)
0.014 (0,36)
C
0.175 (4,45)
0.140 (3,56)
Seating Plane
0.125 (3,18) MIN
Lens Protrusion
0.010 (0,25) MAX
A
0°–10°
0.012 (0,30)
0.008 (0,20)
DIM
NOTES: A. All linear dimensions are in inches (millimeters).
PINS**
MAX
A
MIN
MAX
B
MIN
MAX
C
MIN
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13)
1.235(31,37) 1.235(31,37)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
24
WIDE
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
1.465(37,21) 1.465(37,21)
1.435(36,45) 1.435(36,45)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
28
WIDE WIDE
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
1.668(42,37) 1.668(42,37)
1.632(41,45) 1.632(41,45)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
32
WIDE
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
2.068(52,53) 2.068(52,53)
2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
4040084/B 04/95
40
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...