TEXAS INSTRUMENTS TMS27C210A Technical data
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TMS27C210A 65536 BY 16-BIT UV ERASABLE
TMS27PC210A 65536 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS310D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
D
Organization...65536 by 16 Bits
D
Single 5-V Power Supply
D
Operationally Compatible With Existing
Megabit EPROMs
D
40-Pin Dual-In-Line Package and 44-Lead
Plastic Leaded Chip Carrier
D
All Inputs/Outputs Fully TTL Compatible
D
±10% VCC Tolerance
D
Maximum Access/Minimum Cycle Time
’27C/PC210A-10 100 ns
’27C/PC210A-12 120 ns
’27C/PC210A-15 150 ns
’27C/PC210A-20 200 ns
’27C/PC210A-25 250 ns
D
16-Bit Output For Use in
Microprocessor-Based Systems
D
Very High-Speed SNAP! Pulse
Programming
D
Power-Saving CMOS Technology
D
3-State Output Buffers
D
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Pins
D
No Pullup Resistors Required
D
Low Power Dissipation
– Active...275 mW Worst Case
– Standby...0.55 mW Worst Case
(CMOS-Input Levels)
D
Temperature Range Options
PIN NOMENCLATURE
A0–A15 Address Inputs
DQ0–DQ15 Inputs (programming)/Outputs
E
G Output Enable
GND Ground
NC No Internal Connection
PGM Program
V
CC
V
PP
Chip Enable
5-V Power Supply
13-V Power Supply
‡
DQ12
DQ11
DQ10
DQ9
DQ8
GND
NC
DQ7
DQ6
DQ5
DQ4
J PACKAGE
(TOP VIEW)
V
1
PP
E
2
DQ15
3
DQ14
4
DQ13
5
DQ12
6
7
DQ11
8
DQ10
9
DQ9
10
DQ8
†
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
FN PACKAGE
(TOP VIEW)
DQ14
DQ15ENC
5 43 26
20 21 22 23
DQ2
DQ1
11
12
13
14
15
16
17
18
19
20
V
DQ0
GND
DQ13
7
8
9
10
11
†
12
13
14
15
16
17
18 19
DQ3
V
40
PGM
39
NC
38
A15
37
A14
36
A13
35
34
A12
33
A11
32
A10
31
A9
30
GND
29
A8
28
A7
27
A6
26
A5
25
A4
24
A3
23
A2
22
A1
21
A0
CC
PP
V
1
44 43
24 25 26 27 28
G
A0
NC
CC
†
PGMNCA15
42 41 40
A1A2A3
A14
39
38
37
36
35
34
33
32
31
30
29
A4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
†
†
Pins 11 and 30 (J package) and pins 12 and 34 (FN
package) must be connected externally to ground.
‡
Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1997, Texas Instruments Incorporated
1
TMS27C210A 65536 BY 16-BIT UV ERASABLE
TMS27PC210A 65536 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS310D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
description
The TMS27C210A series are 65536 by 16-bit (1048576-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC210A series are 65 536 by 16-bit (1 048576-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of
temperature ranges, 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FN suffix). The TMS27PC210A is offered with two choices of temperature ranges,
0°C to 70°C (FNL suffix) and –40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
TMS27C210A-xx JL JE
TMS27PC210A-xx FNL FNE
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE
RANGES
0°C to 70°C – 40°C to 85°C
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in T able 2. The read mode
requires a single 5-V supply . All inputs are TTL level except for V
A9 for signature mode.
during programming (13 V), and 12 V on
PP
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C210A 65536 BY 16-BIT UV ERASABLE
TMS27PC210A 65536 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS310D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
Table 2. Operation Modes
†
MODE
FUNCTION
E V
G V
PGM X X X V
V
PP
V
CC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X V
DQ0–DQ15 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z
†
X can be VIL or VIH.
‡
VH = 12 V ±0.5 V.
READ
IL
IL
V
CC
V
CC
OUTPUT
DISABLE
V
IL
V
IH
V
CC
V
CC
STANDBY PROGRAMMING VERIFY
V
IH
X V
V
CC
V
CC
V
IL
IH
IL
V
PP
V
CC
V
IL
V
IL
V
IH
V
PP
V
CC
PROGRAM
INHIBIT
V
IH
X V
X X
V
PP
V
CC
SIGNATURE MODE
IL
MFG DEVICE
97 AB
V
IL
IL
V
CC
V
CC
CODE
V
IH
read/output disable
When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E
and G pins. All other
devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, “
HVCMOS EPROM Family
”, available through TI Sales Offices.
Design Considerations; Latchup Immunity of the
power down
Active ICC supply current can be reduced from 50 mA to 500 µA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E
. In this mode all outputs are in the high-impedance state.
erasure (TMS27C210A)
Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W•s/cm
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the
window should be covered with an opaque label.
2
. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The
initializing (TMS27PC210A)
The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed
into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS27C210A 65536 BY 16-BIT UV ERASABLE
IDENTIFIER
†
TMS27PC210A 65536 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS310D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
SNAP! Pulse programming
The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm
(shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V
(16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM
= 13 V , VCC = 6.5 V , E = VIL, G = VIH. Data is presented in parallel
PP
is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V
= VPP = 5 V ± 10%.
CC
program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = V
IH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0–DQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects
the manufacturer’s code 97 (Hex), and A0 high selects the device code AB (Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
Manufacturer Code V
Device Code V
†
E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, VPP = VCC, PGM = VIH or VIL.
1 0 0 1 0 1 1 1 97
IL
1 0 1 0 1 0 1 1 AB
IH
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C210A 65536 BY 16-BIT UV ERASABLE
TMS27PC210A 65536 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS310D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V
Program One Pulse = tw = 100 µs
Last
Address?
Yes
Address = First Location
X = 0
Increment
Address
Verify
One Byte
Pass
Fail
No
Increment Address
Program One Pulse = tw = 100 µs
No
X = 10?X = X + 1
Program
Mode
Interactive
Mode
No
VCC = VPP = 5 V ± 0.5 V
Last
Address?
Yes Yes
Compare
All Bytes
to Original
Data
Pass
Device Passed
Fail
Device Failed
Figure 1. SNAP! Pulse Programming Flowchart
Final
Verification
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5
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