TEXAS INSTRUMENTS TMS27C040 Technical data

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TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

D

Organization...524288 by 8 Bits

D

Single 5-V Power Supply

D

Industry Standard 32-Pin Dual In-Line
Package and 32-Lead Plastic Leaded Chip
Carrier

D

All Inputs/Outputs Fully TTL Compatible

D

Static Operation (No Clocks, No Refresh)

D

Max Access/Min Cycle Time

± 10%

V

CC

’27C/PC040-10 100 ns
’27C/PC040-12 120 ns
’27C/PC040-15 150 ns

D

8-Bit Output For Use in
Microprocessor-Based Systems

D

Power-Saving CMOS Technology

D

3-State Output Buffers

D

400-mV Assured DC Noise Immunity With
Standard TTL Loads

D

Latchup Immunity of 250 mA on All Input
and Output Pins

D

No Pullup Resistors Required

D

Low Power Dissipation (VCC = 5.5 V)
– Active...275 mW Worst Case
– Standby...0.55 mW Worst Cas E

(CMOS-Input Levels)

D

Temperature Range Options

description

The TMS27C040 devices are 524288 by 8-bit
(4194304-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).

The TMS27PC040 devices are 524 288 by 8-bit
(4194304-bit), one-time programmable (OTP)
electrically programmable read-only memories
(PROMs).

These devices are fabricated using CMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs (including
program data inputs) can be driven by the Series
74 TTL circuits. Each output can drive one Series
74 TTL circuit without external resistors.

TMS27C040
J PACKAGE
(TOP VIEW)

V

1

PP

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

DQ0

13

DQ1

14

DQ2

15

GND

5

A7

6

A6

7

A5

8

A4
A3

9

A2

10

A1

11

A0

12

DQ0

13

A0–A18 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
E
G
GND Ground
V

CC

V

PP

†

Only in program mode.

16

TMS27PC040

FM PACKAGE

(TOP VIEW)

A12

A15

A16

3213231

430

14

15 16 17 18 19

DQ1

DQ2

GND

PIN NOMENCLATURE

Chip Enable
Output Enable

5-V Supply
13-V Power Supply

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PP

V

DQ3

CC

V

DQ4

V

CC

A18
A17
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3

A18

20

DQ5

A17

29
28
27
26
25
24
23
22
21

DQ6

†

A14
A13
A8
A9
A1 1
G
A10
E
DQ7

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1997, Texas Instruments Incorporated

1

TMS27C040 524288 BY 8-BIT UV ERASABLE

MODE

Signature Mode

VILVILVCCV

V

‡

TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

description (continued)

The data outputs are 3-state for connecting multiple devices to a common bus
The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with

two choices of temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). (See Table 1.)
The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package (FM suffix). The TMS27PC040

is offered with two choices of temperature ranges of 0°C to 70°C (JL suffix) and –40°C to 85° C (JE suffix).

Table 1. Temperature Range Suffixes

SUFFIX FOR OPERATING

FUNCTION

TMS27C040-XXX JL JE

TMS27PC040-XXX FML FME

These EPROMs and PROMS operate from a single 5-V supply (in the read mode), and they are ideal for use
in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.

FREE-AIR TEMPERATURE

RANGES

0°C to 70°C – 40°C to 85°C

operation

The seven modes of operation are listed in T able 2. The read mode requires a single 5-V supply . All inputs are
TTL level except for V

Read V

Output Disable V

Standby V

Programming V

Program Inhibit V

Verify V

†

X can be VIL or V

‡

VH = 12 V ± 0.5 V

IH

read/output disable

When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.

during programming (13 V), and VH (12 V) on A9 for the signature mode.

PP

Table 2. Operation Modes

†

A9 A0 DQ0–DQ7

X X Data Out
X X Hi-Z
X X Hi-Z
X X Data In
X X Hi-Z
X X Data Out

V

H

IL

V

IH

E G V

IL
IL

IH

IL
IH
IH

V

IL

V

IH

X V

V

IH

V

IH

V

IL

PP

X V

V

CC
CC

V

PP

V

PP

V

PP

FUNCTION

V

CC

CC

V

CC

V

CC

V

CC

V

CC

V

CC

CC

MFG Code 97

Device Code 50

and G pins. All other

latchup immunity

2

Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IDENTIFIER

†

TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

power down

Active I
100 µA by applying a high CMOS input on E

erasure (TMS27C040)

Before programming, the TMS27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity UV-light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s/cm
lamp must be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C040, the
window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are
programmed into the desired locations. A programmed low can be erased only by UV light.

initializing (TMS27PC040)

The OTP TMS27PC040 PROM is provided with all bits in logic high state, then logic lows are programmed into
the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

SNAP! Pulse programming

The TMS27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart shown in Figure 1.

supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to

CC

. In this mode all outputs are in the high-impedance state.

2

. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The

The initial setup is V

= 13 V , VCC = 6.5 V , E = VIH, and G = VIH. Once the initial location is selected, the data

PP

is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, the
programming mode is achieved when E

is pulsed low (VIL) with a pulse duration of t

w(PGM)

. Every location is

programmed only once before going to interactive mode.
In the interactive mode, the word is verified at V

is not read, the programming is performed by pulling E

= 13 V , VCC = 6.5 V , E = VIH, and G = VIL. If the correct data

PP

low with a pulse duration of t

w(PGM)

. This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with V

= VPP = 5 V ± 10%.

CC

program inhibit

Programming can be inhibited by maintaining high level inputs on the E

and G pins.

program verify

Programmed bits can be verified with V

= 13 V when G = VIL, and E = VIH.

PP

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for the TMS27C040 is 9750. A0 low selects the manufacturer’s
code 97 (Hex), and A0 high selects the device code 50 (Hex), as shown in Table 3.

Table 3. Signature Mode

PINS

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

MANUFACTURER CODE V

DEVICE CODE V

†

E

= G = VIL, A1-A8 = VIL, A9 = VH, A10-A18 = VIL, VPP = VCC.

IL

IH

1 0 0 1 0 1 1 1 97
0 1 0 1 0 0 0 0 50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

3

TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

Start

Address = First Location

VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V

Program One Pulse = tw = 100 µs

Last

Address?

Yes

Address = First Location

X = 0

Increment

Address

Verify

One Byte

Pass

Fail

No

Increment Address

Program One Pulse = tw = 100 µs

No

X = 10?X = X + 1

Program

Mode

Interactive

Mode

No

VCC = VPP = 5 V ± 0.5 V

Last

Address?

Yes Yes

Compare
All Bytes

to Original

Data

Pass

Device Passed

Fail

Device Failed

Figure 1. SNAP! Pulse Programming Flow Chart

Final

Verification

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443