TEXAS INSTRUMENTS TMS27C040 Technical data

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TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

Organization...524288 by 8 Bits

Single 5-V Power Supply

Industry Standard 32-Pin Dual In-Line Package and 32-Lead Plastic Leaded Chip Carrier

All Inputs/Outputs Fully TTL Compatible

Static Operation (No Clocks, No Refresh)

Max Access/Min Cycle Time

± 10%

’27C/PC040-10 100 ns ’27C/PC040-12 120 ns ’27C/PC040-15 150 ns

8-Bit Output For Use in Microprocessor-Based Systems

Power-Saving CMOS Technology

3-State Output Buffers

400-mV Assured DC Noise Immunity With Standard TTL Loads

Latchup Immunity of 250 mA on All Input and Output Pins

No Pullup Resistors Required

Low Power Dissipation (VCC = 5.5 V) – Active...275 mW Worst Case – Standby...0.55 mW Worst Cas E

(CMOS-Input Levels)

Temperature Range Options

description

The TMS27C040 devices are 524288 by 8-bit (4194304-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs).

The TMS27PC040 devices are 524 288 by 8-bit (4194304-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs).

These devices are fabricated using CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by the Series 74 TTL circuits. Each output can drive one Series 74 TTL circuit without external resistors.

TMS27C040 J PACKAGE (TOP VIEW)

A16

A15

A12

DQ0

DQ1

DQ2

GND

A4 A3

DQ0

A0–A18 Address Inputs DQ0–DQ7 Inputs (programming)/Outputs E G GND Ground V

†

Only in program mode.

TMS27PC040

FM PACKAGE

(TOP VIEW)

A12

A15

A16

3213231

430

15 16 17 18 19

DQ1

DQ2

GND

PIN NOMENCLATURE

Chip Enable Output Enable

5-V Supply 13-V Power Supply

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

DQ3

DQ4

A18 A17 A14 A13 A8 A9 A1 1 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3

A18

DQ5

A17

29 28 27 26 25 24 23 22 21

DQ6

†

A14 A13 A8 A9 A1 1 G A10 E DQ7

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS27C040 524288 BY 8-BIT UV ERASABLE

MODE

Signature Mode

VILVILVCCV

‡

TMS27PC040 524288 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

description (continued)

The data outputs are 3-state for connecting multiple devices to a common bus The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with

two choices of temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). (See Table 1.) The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package (FM suffix). The TMS27PC040

is offered with two choices of temperature ranges of 0°C to 70°C (JL suffix) and –40°C to 85° C (JE suffix).

Table 1. Temperature Range Suffixes

SUFFIX FOR OPERATING

FUNCTION

TMS27C040-XXX JL JE

TMS27PC040-XXX FML FME

These EPROMs and PROMS operate from a single 5-V supply (in the read mode), and they are ideal for use in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used.

FREE-AIR TEMPERATURE

RANGES

0°C to 70°C – 40°C to 85°C

operation

The seven modes of operation are listed in T able 2. The read mode requires a single 5-V supply . All inputs are TTL level except for V

Read V

Output Disable V

Standby V

Programming V

Program Inhibit V

Verify V

†

X can be VIL or V

‡

VH = 12 V ± 0.5 V

read/output disable

When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of a single device, a low level signal is applied to the E devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.

during programming (13 V), and VH (12 V) on A9 for the signature mode.

Table 2. Operation Modes

†

A9 A0 DQ0–DQ7

X X Data Out X X Hi-Z X X Hi-Z X X Data In X X Hi-Z X X Data Out

E G V

IL IL

IL IH IH

X V

CC CC

FUNCTION

MFG Code 97

Device Code 50

and G pins. All other

latchup immunity

Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P .C. board level when the EPROM is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup without compromising performance or packing density.

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IDENTIFIER

†

TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

power down

Active I 100 µA by applying a high CMOS input on E

erasure (TMS27C040)

Before programming, the TMS27C040 EPROM is erased by exposing the chip through the transparent lid to a high intensity UV-light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity × exposure time) is 15-W⋅s/cm lamp must be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C040, the window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased only by UV light.

initializing (TMS27PC040)

The OTP TMS27PC040 PROM is provided with all bits in logic high state, then logic lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

SNAP! Pulse programming

The TMS27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The programming sequence is shown in the SNAP! Pulse programming flow chart shown in Figure 1.

supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to

. In this mode all outputs are in the high-impedance state.

. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The

The initial setup is V

= 13 V , VCC = 6.5 V , E = VIH, and G = VIH. Once the initial location is selected, the data

is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, the programming mode is achieved when E

is pulsed low (VIL) with a pulse duration of t

w(PGM)

. Every location is

programmed only once before going to interactive mode. In the interactive mode, the word is verified at V

is not read, the programming is performed by pulling E

= 13 V , VCC = 6.5 V , E = VIH, and G = VIL. If the correct data

low with a pulse duration of t

w(PGM)

. This sequence of verification and programming is performed up to a maximum of 10 times. When the device is fully programmed, all bytes are verified with V

= VPP = 5 V ± 10%.

program inhibit

Programming can be inhibited by maintaining high level inputs on the E

and G pins.

program verify

Programmed bits can be verified with V

= 13 V when G = VIL, and E = VIH.

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. The signature code for the TMS27C040 is 9750. A0 low selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 50 (Hex), as shown in Table 3.

Table 3. Signature Mode

PINS

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

MANUFACTURER CODE V

DEVICE CODE V

†

= G = VIL, A1-A8 = VIL, A9 = VH, A10-A18 = VIL, VPP = VCC.

1 0 0 1 0 1 1 1 97 0 1 0 1 0 0 0 0 50

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TMS27C040 524288 BY 8-BIT UV ERASABLE TMS27PC040 524288 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

Start

Address = First Location

VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V

Program One Pulse = tw = 100 µs

Last

Address?

Yes

Address = First Location

X = 0

Increment

Address

Verify

One Byte

Pass

Fail

Increment Address

Program One Pulse = tw = 100 µs

X = 10?X = X + 1

Program

Mode

Interactive

Mode

VCC = VPP = 5 V ± 0.5 V

Last

Address?

Yes Yes

Compare All Bytes

to Original

Data

Pass

Device Passed

Fail

Device Failed

Figure 1. SNAP! Pulse Programming Flow Chart

Final

Verification

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TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers are for the J package.

†

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

A10

A11 A12 A13 A14 A15 A16 A17

A18

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 22

EPROM 524 288 × 8

524 287

[PWR DWN]

A A A A A A A A

13 14 15 17 18 19 20 21

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Supply voltage range, V Input voltage range (see Note 1), All inputs except A9 –0.6 V to V

Output voltage range, with respect to V

Operating free-air temperature range (’27C040-_ _JL and ’27PC040-_ _FML) 0°C to 70°C. . . . . . . . . . . . . .

Operating free-air temperature range (’27C040-_ _JE and ’27PC040 _ _ FME) – 40°C to 85°C. . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A9 –0.6 V to 13 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.6 V to VCC + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

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TMS27C040 524288 BY 8-BIT UV ERASABLE

VCCSuppl

oltage

VPPSuppl

oltage

VIHHigh-level dc input voltage

VILLow-level dc input voltage

VOHHigh-level dc output voltage

VOLLow-level dc output voltage

supply current (standby)

TMS27PC040 524288 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

recommended operating conditions

MIN NOM MAX UNIT

y v

Operating free-air temperature

Operating free-air temperature ’27C040-_ _JE –40 85 °C

NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted

into or removed from the board when VPP or VCC is applied.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER TEST CONDITIONS MIN MAX UNIT

PP1

PP2

CC1

CC2

†

Minimum cycle time = maximum access time.

Input current (leakage) VI = 0 V to 5.5 V ±1 µA Output current (leakage) VO = 0 V to V VPP supply current VPP = VCC = 5.5 V 10 µA VPP supply current (during program pulse) VPP = 12.75 V 50 mA

VCC supply current (active)

Read mode (see Note 2) 4.5 5 5.5 V SNAP! Pulse programming algorithm 6.25 6.5 6.75 V Read mode VCC– 0.6 VCC+ 0.6 V SNAP! Pulse programming algorithm 12.75 13 13.25 V

TTL 2 VCC + 0.5 V CMOS VCC– 0.2 VCC+ 0.5 V TTL – 0.5 0.8 V CMOS – 0.5 0.2 V

’27C040-_ _JL ’27PC040-_ _FML

IOH = – 400 µA 2.4 IOH = – 20 µA VCC – 0.1 IOL = 2.1 mA 0.4 IOL = 20 µA 0.1

TTL-Input level VCC = 5.5 V, E = V CMOS-Input level VCC = 5.5 V, E = V

E = VIL,V t

= minimum cycle time,

cycle

outputs open

†

IH CC

= 5.5 V

0 70 °C

±1 µA

1 mA

100 µA

50 mA

capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz

‡

All typical values are at TA = 25°C and nominal voltages.

Capacitance measurements are made on sample basis only.

‡

Input capacitance VI = 0 V 4 8 pF Output capacitance VO = 0 V 8 12 pF

PARAMETER

TEST CONDITIONS MIN TYP§MAX UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

100 F

Input t

TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

switching characteristics over recommended ranges of operating conditions (see Notes 3 and 4)

’27C040-10

PARAMETER TEST CONDITIONS

t t t

† NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

Access time from address 100 120 150 ns

a(A)

Access time from chip enable

a(E)

Output enable time from G

en(G)

Output disable time from G or E, whichever

dis

occurs first Output data valid time after change of

v(A)

address, E

Value calculated from 0.5-V delta to measured output level.

4. Common test conditions apply for t

, or G, whichever occurs first

0.8 V for logic low. (See Figure 2)

†

except during programming.

dis

= 1 Series 74 TTL load, Input tr ≤ 20 ns,

≤ 20

’27PC040-10

MIN MAX MIN MAX MIN MAX

0 50 0 50 0 50 ns

0 0 0 ns

switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3)

PARAMETER MIN MAX UNIT

dis(G)

en(G)

NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

Output disable time from G 0 100 ns Output enable time from G 150 ns

0.8 V for logic low. (See Figure 2)

’27C040-12 ’27PC040-12

100 120 150 ns

50 50 50 ns

’27C040-15 ’27PC040-15

UNIT

timing requirements for programming

w(PGM)

su(A)

su(E)

su(G)

su(D)

su(VPP)

su(VCC)

h(A)

h(D)

Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs Setup time, address 2 µs Setup time, E 2 µs Setup time, G 2 µs Setup time, data 2 µs Setup time, V Setup time, V Hold time, address 0 µs Hold time, data 2 µs

PP CC

MIN NOM MAX UNIT

2 µs 2 µs

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C040 524288 BY 8-BIT UV ERASABLE TMS27PC040 524288 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Output

Under Test

2.08 V

RL = 800 Ω

CL = 100 pF (see Note A)

2.4 V

0.4 V

NOTES: A. CL includes probe and fixture capacitance.

B. AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low . Timing measurements are made at 2 V for logic high and

0.8 V for logic low for both inputs and outputs.

2 V

0.8 V

Figure 2. AC Testing Output Load Circuit and Waveform

A0–A18

DQ0–DQ7

Hi-Z

Addresses Valid

a(A)

a(E)

en(G)

2 V

0.8 V

v(A)

Output Valid

dis

Hi-Z

Figure 3. Read-Cycle Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

Program

A0–A18

su(A)

DQ0–DQ7

†

13-V VPP and 6.5-V VCC for SNAP! Pulse programming

w(PGM)

Data-In Stable

su(D)

su(VPP)

su(E)

su(VCC)

Address Stable

Hi-Z

en(G)

h(D)

TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

Verify

h(A)

†

su(G)

Data-Out

Stable

dis(G)

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

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TMS27C040 524288 BY 8-BIT UV ERASABLE TMS27PC040 524288 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER

Seating Plane

0.140 (3,56)

0.495 (12,57)

0.485 (12,32)

0.453 (11,51)

0.447 (11,35)

301

0.129 (3,28)

0.123 (3,12)

0.049 (1,24)

0.043 (1,09)

0.008 (0,20) NOM

0.132 (3,35)

0.004 (0,10)

0.050 (1,27)

0.020 (0,51)

0.015 (0,38)

0.595 (15,11)

0.585 (14,86)

0.553 (14,05)

0.547 (13,89)

0.030 (0,76) TYP

4040201-4/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-016

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.090 (2,29)

0.060 (1,53)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

0.018 (0,46) MIN

0.022 (0,56)

0.014 (0,36)

0.175 (4,45)

0.140 (3,56)

Seating Plane

0.125 (3,18) MIN

Lens Protrusion

0.010 (0,25) MAX

0°–10°

0.012 (0,30)

0.008 (0,20)

DIM

NOTES: A. All linear dimensions are in inches (millimeters).

PINS**

MAX

MIN MAX

MIN

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13)

1.235(31,37) 1.235(31,37)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.465(37,21) 1.465(37,21)

1.435(36,45) 1.435(36,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.668(42,37) 1.668(42,37)

1.632(41,45) 1.632(41,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

2.068(52,53) 2.068(52,53)

2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

4040084/B 04/95

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TEXAS INSTRUMENTS TMS27C040 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual