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TLV1562
User Manual
99 pgs318.85 Kb0

Texas Instruments TLV1562 User Manual

Interfacing the TLV1562 Parallel ADĆConverter to the TMS320C54x DSP
Application Report
July 1999 Advanced Analog Products
SLAA040
IMPORTANT NOTICE
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 The Board 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 TMS320C54x Starter Kit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 TLV1562EVM 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 ADC TLV1562 Overview 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Suggestions for the ’C54x to TLV1562 Interface 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Recyclic Architecture 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Note on the Interface, Using an External ADC Clock Drive 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Onboard Components 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 TLC5618 – Serial DAC 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 TLV5651 – Parallel DAC 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Operational Overview 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Reference Voltage Inputs 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Input Data Bits 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Connections Between the DSP and the EVM 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Jumpers Used on the TLV1562EVM 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 The Serial DAC/DSP System 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 The DSP Serial Port 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Other DSP/TLV1562 Signals 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 DSP Internal Serial Port Operation 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Conversation Between the TLV1562 and the DSP 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Writing to the ADC 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Mono Interrupt Driven Mode Using RD
7.3 Mono Interrupt Driven Mode Using CSTART
7.4 Dual Interrupt Driven Mode 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Mono Continuous Mode 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Dual Continuous Mode 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Software Overview 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Software Development tools 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 DSP Memory Map 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Programming Strategies for the ’C54x, Explanations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Optimizing CPU Resources for Maximum Data Rates 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2 Address and Data Bus for I/O Tasks 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 Timer Output 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.4 Data Page Pointer 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.5 Generating the Chip Select Signal and the CSTART
8.3.6 Interfacing the Serial DAC 5618 to the DSP 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.7 Interrupt Latency 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.8 Branch Optimization (goto/dgoto, call/dcall, ...) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.9 Enabling Software Modules (.if/.elseif/.endif) 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Software Code Explanation 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1 Software Principals of the Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 Flow Charts and Comments for All Software Modes 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.1 The Mono Interrupt Driven Mode Using RD
8.5.2 Mono Interrupt Driven Mode Using CSTART
8.5.3 Dual Interrupt Driven Mode 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.4 Mono Continuous Mode 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
to Start Conversion 27. . . . . . . . . . . . . . . . . . . . . . . .
to Start Conversion 30. . . . . . . . . . . . . . . . . . . . . . .
Signal 21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfacing the TLV1562 Parallel AD-Converter to the TMS320C54x DSP
iii
Contents
8.5.5 Dual Continuous Mode 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.6 C-Callable With Mono Interrupt Driven Mode Using CSTART
to Start Conversion 40. . . . . . . . .
8.6 Source Code 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1 Common Software for all Modes (except C-Callable) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.2 Mono Mode Interrupt Driven Software Using RD
to Start Conversion 46. . . . . . . . . . . . . . . . . . . .
8.6.3 Calibration of the ADC 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.4 Mono Mode Interrupt Driven Software Using CSTART
to Start Conversion 58. . . . . . . . . . . . . . .
8.6.5 Dual Interrupt Driven Mode 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.6 Mono Continuous Mode 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.7 Dual Continuous Mode 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.8 C-Callable 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Summary 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 References 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
SLAA040
Figures
List of Figures
1 TLV1562 – DSP Interface of the EVM, Using RD or the CSTART Signal to Start Conversion 2. . . . . . . . . . . . . . .
2 TLV1562 – DSP Interface of the EVM, Using RD
3 TLC5618 – DSP Interface 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 TLC5651 – DSP Interface 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Memory Map 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Software Flow of the Mono Interrupt Driven Solution 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Flow Chart Mono Interrupt Driven Mode Using CSTART
8 Time Optimization (monocst1) Maximum Performance at 12 MSPS with Internal Clock 33. . . . . . . . . . . . . . . . . . .
9 Flow Chart Dual Interrupt Driven Mode (Using CSTART
10 Flow Chart Mono Continuous Mode 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Flow Chart Dual Continuous Mode 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or the CSTART Signal to Start Conversion 3. . . . . . . . . . . . . . .
to Start Conversion 31. . . . . . . . . . . . . . . . . . . . . . . . . . . .
) to Start Conversion 35. . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
1 Signal Connections 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 3-Position Jumpers 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 2-Position Jumpers 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 DSP/DAC Interconnection 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 DSP Serial Port Signals and Registers 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 DSP Algorithm for Writing to the ADC 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 DSP Algorithm for Mono Interrupt Driven Mode Using RD 8 DSP Algorithm for Mono Interrupt Driven Mode Using CSTART
9 DSP Algorithm for Dual Interrupt Driven Mode 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 DSP Algorithm for Mono Continuous Mode 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 DSP Algorithm for Dual Continuous Mode 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Switch Settings 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Instruction in the Program Header (Step 1) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 Instruction in the Program Header (Step 1) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfacing the TLV1562 Parallel AD-Converter to the TMS320C54x DSP
v
vi
SLAA040
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
Falk Alicke and Perry Miller
ABSTRACT
In this application report we discuss the hardware and software interface of the TL V1562, 10-bit parallel-output analog-to-digital converter (ADC) to the TMS320C54x digital signal processor (DSP).
consists of the TLV1562 10-bit ADC, a THS5651 10-bit parallel output communication digital-to-analog converter (CommsDAC) and a TLC5618A serial-output digital-to-analog converter (DAC).
Following the discussion of the ADC we explain the need for both the THS5651 CommsDAC and the TLC5618A serial DAC.
The application report concludes with several software application examples and recommendations for simplifying the software through modifications of the DSP hardware interface circuit.
1 Introduction
The analog-to-digital (A/D) interface can present a significant design problem because hardware and software must work together across the interface to produce a usable, complete design. This application report provides a design solution for the interface between the TLV1562 10-bit parallel-output analog-to-digital converter (ADC) and the TMS320C54x digital signal processor (DSP).
The report describes the hardware and software needed to interface the ’C54x DSP to the TL V1562 ADC, which is intended for applications, such as industrial control and signal intelligence in which large amounts of data must be processed quickly. The first sections describe the basic operation of the TLV1562. For additional information see the References section at the end of this report.
The hardware interface board, or evaluation module (EVM)
2 The Board
The TL V1562 evaluation module (EVM) is a four-layer printed circuit board (PCB) constructed from FR4 material. The PCB dimensions are 180 mm × 112 mm × 12 mm. Ribbon cables are used to interface the TLV1562EVM to the TMS320C54x DSK plus starter kit.
2.1 TMS320C54x Starter Kit
The starter kit simplifies the task of interfacing to the ’C54x processor. It comes with an ADC for voice bandwidth, and GoDSP code explorer as the software tool. A 10-MHz oscillator provides the clock signal to allow 40-MHz internal DSP clock cycles generated by the internal DSP PLL. Therefore, the board provides 40 MIPS of processing power.
Ribbon cables are used to connect the DSP with the EVM. Detailed descriptions of all connections are given later in this report.
CommsDAC is a trademark of Texas Instruments.
1
The Board
2.2 TLV1562EVM
The TLV1562EVM gives customers an easy start with employing many of the features of this converter. A serial DAC (TLC5618A), a parallel DAC (THS5651), and the ADC (TL V1562) make this EVM flexible enough to test the features of the TLV1562. It also helps show how this ADC can be implemented.
2.3 ADC TLV1562 Overview
The TL V1562 is a CMOS 10-bit high-speed programmable resolution analog-to­digital converter, using a low-power recyclic architecture.
The converter provides two differential or four single-ended inputs to interface the analog input signals.
On the digital side, the device has a chip-select (CS sample/conversion start signal (CSTART input (WR
), and 10 parallel data I/O lines (D9:0).
The converter integrates the CSTART
), read signal input (RD), write signal
signal to coordinate sampling and conversion timing without using the parallel bus. Since the TMS320C542 DSP has no second general-purpose output, this signal is generated with the signal (CSTART
) from the address decoder.
2.3.1 Suggestions for the ’C54x to TLV1562 Interface
The following paragraphs describe two suggested interfaces between the ’C54x and the TLV1562.
2.3.1.1 The Universal Interface
The schematic in Figure 1 shows the pin-to-pin connections between the TL V1562 and ’C54x, realized on the EVM. This routing can test the converter in each mode. One I/O-wait state is required for write operations to the ADC. The read sequence from the ADC does not require any wait states because the RD signal is generated with XF.
TLV1562 TMS320C54x
INT
CSTART
CS
01 10 11
Address Decoder
), input clock (CLKIN),
INT
A0 A1
2 SLAA040
RD
WR
CLKIN
D(0–9) D(0–9)
≥ 1
1: x
Divider
XF
IOSTRB R/W
CLOCKOUT
Figure 1. TLV1562 to ’C54x DSP Interface of the EVM,
Using RD or the CSTART Signal to Start Conversion
2.3.1.2 Simplification of Software Requirements Through Modified Interface
Of all the TL V1562 modes of operation, only the mono interrupt driven mode uses the RD
signal to start the conversion. This requires a very flexible handling of the read signal and therefore has to be performed by a general-purpose output signal. If the application excludes using the RD (using CSTART
instead). The TLV1562 RD input signal can be generated with
an OR gate, whose inputs are driven by IOSTRB
signal to start the conversion
and R/W signals from the DSP
(see Figure 2). Using these connections saves the programming steps of setting/resetting RD
with the XF signal. Another advantage is having XF available to control the CSTART
signal. This saves busy times on the address bus (in Figure 1, CST ART
was generated through A0/A1.) and simplifies the software code.
CAUTION:
The time t
EN(DATAOUT)
between the RD high-to-low transition (generated by the DSP) and the arrival of valid ADC output data on the data bus is related to the capacitive load of the bus. In most cases, the ADC come out of the 3-state mode and supplies the correct voltage levels onto the bus lines in less than 50 ns. Thus, the minimum number of I/O-wait states becomes two (for t
TLV1562 TMS320C54x
INT
CSTART
CS
EN(DATAOUT)
01 10 11
≤50 ns).
Address Decoder
INT XF
A0 A1
The Board
CLKIN
D(0–9) D(0–9)
Figure 2. TLV1562 to ’C54x DSP Interface of the EVM,
Using RD
2.3.2 Recyclic Architecture
One specialty of this ADC is its recyclic architecture. Instead of limiting the device power by the highest possible resolution at the fastest speed, this converter is able to work at three maximum speeds for three resolutions. The highest resolution runs at 2MSPS maximum throughput rate; 8-bit resolution corresponds to 3MSPS, and 4-bit resolution to 7MSPS.
RD
WR
≥ 1
&
≥ 1
1: x
Divider
IOSTRB R/W
CLOCKOUT
or the CSTART Signal to Start Conversion
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
3
The Board
This feature fits well into monitoring application. For example, the ADC may have to trigger on one event out of some channels inside an extremely small time window and then sample the correct channel with a higher resolution, but lower throughput to analyze this process. This feature also fits well into home security applications or applications that must monitor several inputs simultaneously.
2.3.3 Note on the Interface, Using an External ADC Clock Drive
The TL V1562data sheet (Figure 9) shows that RD has to fall as close as possible to the falling edge of the clock signal. The user must adhere to this timing, otherwise the conversion result may be wrong. The user may not recognize the erroneous result, since the ADC will signal that the conversion has finished during the logic low transition of the INT interface behavior of the ADC whether the timing is correct or not. The following figure shows what happens when the RD RD
falls nearly 1/2 of one cycle too late, the conversion result is valid on the 5
clock cycle.
signal. The following timing diagram shows the
falling edge is timed wrong. Although
th
12345678910
CLK
RD
INT
Conversion Starts
Next Sampling Starts
2.4 Onboard Components
These sections describe the EVM onboard components.
2.4.1 TLC5618A – Serial DAC
This 12-bit DAC has a serial interface that can run at 20-MHz clock; therefore, it can update the output at 1.21 MSPS. Two outputs are available on the 8-pin package. The buffered SPI of the DSP provides the DSP interface. Using the auto-buffer mode, updating the data on the DAC requires only four CPU instructions/samples.
1
Conversion Finished
4 SLAA040
The Board
Serial DAC
SCLK
CS
TLC5618A
DIN
TLV1562 EVM Pin Connector
Figure 3. TLC5618A to ’C542 DSP Interface
2.4.2 THS5651 – Parallel Output CommsDAC
This 10-bit data converter has a parallel interface and is able to update its output with 100 MSPS. The two outputs on the 28-pin package can each drive a current between 2 mA and 20 mA with an output resistance >100 kΩ (ideal current source: output impedance → ∞). The data bus and the address decoder provide the interface to the DSP.
Parallel DAC
DSP
BCLKX
BCLKR
BFSX
TMS320C542
BFSR
BDX
BDR
DSP
CLK
THS5651
D(0–9)
Buffer
CLKOUT
TMS320C542
A(0–1) = 11
D(0–9)
b
Figure 4. THS5651 to C542 DSP Interface
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
5
Operational Overview
3 Operational Overview
This chapter discusses the software and hardware interface for the TLV1562. Plus the overall operational sequence of the A/D interface is described.
3.1 Reference Voltage Inputs
The voltage difference between the VREFP and VREFM terminals determines the analog input range, i.e., the upper and lower limits of the analog inputs that produce the full-scale (output data all 1s) and zero-scale (output data all 0s) readings, respectively.
For design reasons, this high-speed sampling ADC does not have a ground­referenced input voltage range. Hence, level shifting is required unless the application allows the signal to be ac coupled. Level shifting could be done with single-supply op amps.
The absolute voltage values applied to VREFP, VREFM, and the analog input should not be greater than the A V input restrictions apply so consult the TL V1562 data sheet for further information. The digital output is full scale when the analog input is equal to or greater than the voltage on VREFP , and is zero scale when the input signal is equal to or lower than VREFM.
supply minus 1 V , or lower than 0.8 V . Other
DD
3.2 Input Data Bits
The ADC contains the two user-accessible registers, CR0 and CR1. All user defined features such as conversion mode, data output format or sample size are programmed in CR0 and CR1. The data acquisition process must be started by writing to these two registers. After this initialization, the converter processes data in the same configuration until these registers are overwritten.
6 SLAA040
3.3 Connections Between the DSP and the EVM
The following connections provide the interface between the DSP and the EVM:
Table 1. Signal Connections
Operational Overview
DSP Signal Connector/Pin on the DSKplus cir-
cuit board
General
GND Connector JP4: Pin 1, 10, 1 1, 12, 14,
15, 19, 20, 21, 27, 34, 35 Connector JP5: Pin 6, 10, 1 1, 12
VCC JP1/32  N/A VCC
Parallel Interface
CLKOUT JP3/2  J11/11 CLKIN INT0 XF JP4/8  J11/3 RD R/W JP4/30  J11/9 decoded to the WR line IOSTRB JP4/36  J11/7 decoded to the WR line A0 JP5/34  J11/2 addr. decoder for CS and CSTART A1 JP5/35  J11/1 addr. decoder for CS and CSTART D0 JP3/35  J10/13 D0 D1 JP3/34  J10/15 D1 D2 JP3/8  J10/17 D2 D3 JP3/12  J10/19 D3 D4 JP3/11  J10/21 D4 D5 JP3/15  J10/23 D5 D6 JP3/14  J10/25 D6 D7 JP3/18  J10/27 D7 D8 JP3/17  J10/29 D8 D9 JP3/21  J10/31 D9
Serial Interface to the DAC TLC5618A
BCLKR JP1/14  J11/25 SCLK BCLKX JP1/17  J11/23 SCLK BFSR JP1/20  J11/21 CS BFSX JP1/23  J11/19 CS BDR JP1/26  J11/17 DIN BDX JP1/29  J11/15 DIN
JP5/1  J11/5 INT

Connector/Pin on the TLV1562EVM
J10/2,J10/4,...,J10/34 J11/4,J11/6,...,J11/26
ADC Signal
GND
Signals D[9–0] of the TLV1562 and D[9–0] of the DSP are tied together in this application to simplify hardware debugging during the development phase. However, if the 2s complement feature of the DAC is to be used, it is easier to connect D[15-6] of the DSP with D[9–0] of the ADC. A simple right shift of the result then evaluates the result when sign extension mode (SXM) is enabled.
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
7
Operational Overview
3.3.1 Jumpers Used on the TLV1562EVM
Table 2. 3-Position Jumpers
JUMPER GENERAL DESCRIPTION PIN 1-2 PIN 2-3
W1 Connects BP/CH3 (ADC) to R45 or GND; Input not in use, grounded to reduce noise Use as single input channel3 or
W2 Connects BM/CH4 (ADC) to R44 or GND; Input not in use, grounded to reduce noise Use as single input channel4 or
W3 Connects RD to XF or /RD1 Logic generator is connected to the ADC DSP is connected to the ADC W4 WR + WR1 is connected with DSP_WR or
W5 W6 W7
W8 MCB_CLK is connected to BUFCLK (U14) or
W9 CLK input of the Counter (U2) is connected with
W10 ADC CLKIN is connected to CLK/2 or CLK/4 The ADC clock runs at a quarter of the
W11 Connects AP/CH1 (ADC) to R48 or GND; Input not in use, grounded to reduce
W12 Connects AM/CH2 (ADC) to R47 or GND; Input not in use, grounded to reduce
W13 Connects REFLO (TL V5651) to Vcc or GND Disable internal reference Enable internal reference W14 Connects SCLK (TLC5618AA) to BCLKX or J8
W15 Connects CLK (TLV5651) to CLKOUT (DSP) or
W23 Connects CSTAR T to A0, A1, or XF A0 and A1 used to generate ADC
W24 Connects DSP_RD to XF or IOSTRB, ORed with
U12-J9/3 The three Jumpers define the prescaling of the
CLKOUT signal to the MCB_CLK Pin, if W8 is set to Counter-Mode
(U11)
RD1
CLKOUT or CLKOUT/2
(BNC)
J7 (BNC)
/W from the DSP
R
Logic generator is connected to the ADC DSP is connected to the ADC
Counter-Mode (MCB_CLK signal is divided by the counter, set-up with Jumper W(5-7)
The counter is toggled by the DSP system clock (signal BUFF_CLK)
DSP clock frequency (10 MHz)
noise
noise
Normal DSP mode An external clock source drives the
Normal DSP mode An external clock source drives the CLK
signal
CSTART XF signal connected to ADC RD pin RD pin driven by IOSTRB ORed with R/W
differential input positive channel B
differential input negative channel B
Counter-Mode disabled (MCB_CLK is synchronize with the CLKOUT signal)
The counter’s clock is prescaled by two (toggled by half the DSP system clock (CLKOUT2))
The ADC clock runs at half the DSP clock frequency (20 MHz)
Use as single input channel 1 or differential input positive channel A
Use as single input channel 2 or differential input negative channel A
SCLK pin instead of the DSP
pin instead of the DSP XF signal connects to CSTAR T pin
Table 3. 2-Position Jumpers
JUMPER GENERAL DESCRIPTION PINS SHORTED PINS OPEN
W16 Connects Mode input (TLV 5651) to GND MODE 0 is chosen (binary data input) MODE 1 is chosen (2s complement
W17 Connects REFIO (TLV5651) to VREF1 or leaves
the REFIO pin decoupled to GND via a 0.1 µF capacitor
W18 Connects DIR (U19) to GND or leaves the DIR
pin connected to WR
W19 Connects OE (U19) to GND or leaves the OE pin
connected to CS
W20 Connects BDX to BDR or leaves BDR open DSP BDR pin gets a shortcuted feedback
W21 Connects BSFX to BSFR or leaves BCLKR open DSP BSFR pin gets a shortcuted feedback
W22 Connects BCLKX backwards with BCLKR or
leaves it open
W28 Connect Sleep input (TLV5651/5 GND Normal mode of operation Sleep mode seleted
Use as external reference voltage input Use as internal reference voltage
ADC can only write but not read to the data bus
Output driver is isolated and disabled (no signal can bus trough the data bus)
from the BDX (transmit) pin; normal mode
from the BSFX (transmit) pin; normal mode DSP BCLKR pin gets a shortcuted feedback
from the BCLKX (transmit) pin; normal mode
8 SLAA040
data input)
output with this pin terminated into GND in series with 0.1 pF
Normal operation mode
Normal operation mode
BDR remains open
BSFR remains open
BCLKR remains open
4 The Serial DAC/DSP System
The software configures the buffered DSP serial port to the 16-bit master mode so that the DSP generates the frame sync signal at BFSX and the data clock at BCLKX serial port terminals. Table 4 shows the connections between the DSP and the DAC TLC5618A.
Table 4. DSP/DAC Interconnection
FROM DSP TO DSP TO DAC
BFSX BFSR CS
BCLKX CLKR I/O CLK
BDX BDR DATA IN
The following statements describe the generation and application of the configuration and control signals.
• The DSP BCLKX output provides a 20-MHz data clock, which is a divide-by-2
of the DSP master clock.
• The DSP BDX output supplies the 16-bit control and data move to the
TLC5618A at DATA IN.
• The DSP BFSX frame synchronization signal, connected to CS, triggers the
start of a new frame of data.
The Serial DAC/DSP System
After the falling edge of FSX, the next 16 data clocks transfer data into the DSP DR terminal and out of the DX terminal. Since this DSP/DAC interface is synchronous, the FSX signal is sent to the FSR terminal, and the CLKX is sent to the CLKR terminal.
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
9
The DSP Serial Port
5 The DSP Serial Port
The buffered serial port provides direct communication with serial I/O devices and consists of six basic signals and five registers. The DSP internal serial port operation section discusses the registers.
The six signals are:
• BCLKX - The serial transmit clock. This signal clocks the transmitted data
from the BDX terminal to the DIN terminal of the TLC5618A.
• BCLKR - The serial receive clock. This signal clocks data into the DSP BDR
terminal. Since the DAC does not send any information back to the DSP, this signal is not important.
• BDX - Data transmit. From this terminal the DSP transmits 16-bit data to the
DIN terminal of the TLC5618A.
• BDR - Data receive – not in use
• BFSX - Frame sync transmit. This signal frames the transmit data. The DSP
begins to transmit data from BDX on the falling edge of BFSX and continues to transmit data for the next 16 clock cycles from the BCLKX terminal. The BFSX signal is applied to the TLC5618A CS
• BFSR - Frame sync receive. This signal frames the receive data. The DSP
begins to receive data on the falling edge of BFSR and continues to recognize valid data for the following 16 clocks from BCLKR. This signal is not important for this application.
terminal.
Table 5 lists the serial port pins and registers.
Table 5. DSP Serial Port Signals and Registers
PINS DESCRIPTION REGISTERS DESCRIPTION
BCLKX Transmit clock signal BSPC Serial port control register BCLKR Receive clock signal BSPCE extended BSPC
BDX Transmitted serial data signal BDXR Data transmit register
BDR Received serial data signal BDRR Data receive register BFSX Transmit frame synchronization signal BXSR Transmit shift register BFSR Receive frame synchronization signal BRSR Receive shift register
AXR Buffer start location BKX Buffer size
For this application the DSP buffered serial port is programmed as the master, so the BCLKX output is fed to the BCLKR terminal and the BFSX output is fed to the BFSR terminal.
10 SLAA040
6 Other DSP/TLV1562 Signals
These paragraphs describe other DSP and TLV1562 signals.
6.1 DSP Internal Serial Port Operation
Three signals are necessary to connect the transmit pins of the transmitting device with the receive pins of the receiving device for data transmission. The transmitted serial data signal (BDX) sends the actual data. BFSX initiates the transfer (at the beginning of the packet), and BCLKX clocks the bit transfer. The corresponding pins on the receive device are BDR, BFSR and BCLKR, respectively.
The transmit is executed by the autobuffer mode. This means there is no need to write to the serial port output buffer . Instead, the DSP continuously sends the data, located in the memory beginning on AXR. When all data are sent (defined by the buffer length in BXR), the first word (pointed to by AXR) is sent again. Therefore, the program has only to store the samples into this memory location. The rest of the task is handled in the background, using no CPU power.
Other DSP/TLV1562 Signals
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
11
Conversation Between the TLV1562 and the DSP
7 Conversation Between the TLV1562 and the DSP
The complexity of the TLV1562 ADC may be confusing because of the number of possible modes to drive the protocol between DSP and ADC. The following paragraphs explain more about the data sheet descriptions for interfacing the ’C54x to the ADC.
7.1 Writing to the ADC
Registers CR0 and CR1 must be set to choose any of the modes the TLV1562 offers. Therefore, a write sequence must be performed from the DSP to the ADC.
After selecting the ADC (CS
low), a high-low transition of the WR line tells the
converter that something is to be written to the data port.
Table 6. DSP Algorithm for Writing to the ADC
STEPS TIMING, NOTES
1. Set one DSP I/O waitstate Make timing between 40 MHz C54x CPU compatible with the TLV1562
2. Clear CS Select ADC
3. Send out data on the bus The signal WR is automatically handled by the DSP
4. Set CS Deselect ADC
7.2 Mono Interrupt Driven Mode Using RD
This mode is used when the application needs to sample one channel at a time and performs the sampling, conversion, and serial transmission steps only once. Although this mode produces continuous sampling data, the use of other modes is recommended. One reason is the CS sampling/conversion time. An interesting advantage of this mode is its ability to control the start-sample time.
The RD stops the sampling process (disconnects the capacitor from the input signal) and starts the signal conversion. After two ADCSYSSCLKs, the sampling capacitor gets connected back to the input signal to do the next sampling. The conversion time needs five ADCSYSCLKs to finish the conversion before it gets written to the data port.
signal controls the sampling and converting. Every falling edge of RD
signal has to stay low during the whole
During configuration, the rising edge of WR Also, when conversion is finished, the ADC clears the INT signal purposes. Next
the ADC writes the conversion result to the data port. The rising edge of RD this status; in other words, the INT conversion result on the data port becomes invalid (the ADC data port gets 3-stated).
The configuration data needs to be written only once to the ADC. After this, toggling the RD the RD
12 SLAA040
starts the sampling.
resets
signal goes back to logic high and the
signal runs the ADC in a sampling/conversion/sending mode and
signal releases every new cycle.
Table 7. DSP Algorithm for Mono Interrupt Driven Mode Using RD
STEPS TIMING, NOTES
0. Initialization Write all configuration data to the
ADC
1. set CS deselect ADC (optional with APD=0)
2. clear CS Select ADC
3. Wait for t
D(CSL-sample)
+1ADCSYSCLK
activate the mono interrupt-driven mode in CR0(2;3)
(Note: if Hardware Auto power down is enabled, Chip select has to be used, otherwise CS can be left high)
t
D(CSL-sample)
t
D(CSL-sample)
= 5ns (APD=0) = 500ns (APD=1)
Conversation Between the TLV1562 and the DSP
Wait cycles for the DSP internally (40 MHz DSPCLK):
APD=0
ADCSYCLK
= 7.5 MHz
≥6 ≥5 ≥26 ≥25
APD=0
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
4. Clear RD ADC goes over from sampling into
conversion
5. Wait until INT goes low alternative: ignore the INT signal, wait 49
ns+5(6) ADCSYSCLK and goto step number 7
6. Wait the time t
EN(DATAOUT)
t
EN(DATAOUT)
= 41 ns ≥2 ≥2 ≥2 ≥2
7. Read sample out from the data port; Reset RD
signal
8. Goto step 1 or step 3 (if APD=0) for more samples
≥34 ≥22 ≥34 ≥22
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
13
Conversation Between the TLV1562 and the DSP
7.3 Mono Interrupt Driven Mode Using CSTART
Use the CSTART signal when two or more ADCs must sample/convert signals at the same time. Instead of the RD is started with the edges of the CST ART get the data out of the ADC and onto the bus.
Table 8. DSP Algorithm for Mono Interrupt Driven Mode Using CSTART
STEPS TIMING, NOTES
1. Set CS Deselect ADC
2. Clear CSTART tTis starts sampling
3. Wait for t
4. Set CSTART This starts the conversion
5. Wait until INT goes low Alternative: ignore the INT signal,
6. Wait the time t
7. Clear CS Select the ADC
8. Clear RD Start communication
9. Wait the time t
10. Read sample out from the data port; Reset RD
11. Set CS Deselect ADC
12. Go to step 2 for the next samples
W(CSTARTL)
D(INTL-CSI)
EN(DATAOUT)
signal
t
W(CSTARTL)
t
W(CSTARTL)
wait 14ns+5 ADCSYSCLK and goto step number 7
t
D(INTL-CSI)
t
EN(DATAOUT)
signal, the timing for sampling and converting
signal. The RD signal is still required to
= 100 ns (APD=0) = 600 ns (APD=1)
= 10 ns ≥1 ≥1 ≥1 ≥1
= 41 ns ≥2 ≥2 ≥2 ≥2
Wait cycles for the DSP internally (40MHz DSPCLK):
APD=0
ADCSYCLK
= 7.5 MHz
≥4 ≥4 ≥24 ≥24
≥33 ≥21 ≥33 ≥21
APD=0
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
14 SLAA040
7.4 Dual Interrupt Driven Mode
Using techniques similar to those described in the first two modes for sampling/converting/sending tasks, the dual mode samples two channels at the same time and sends out the results in series to the data port. The CST AR T is used to start sampling and converting.
Table 9. DSP Algorithm for Dual Interrupt Driven Mode
STEPS TIMING, NOTES
1. Set CS Deselect ADC
2. Clear CSTART This starts sampling
3. Wait for t
4. Set CSTART This starts the conversion
5. Wait until INT goes low Alternative: ignore the INT signal,
6. Wait the time t
7. Clear CS Select the ADC
8. Clear RD Start communication
9. Wait the time t
10. Read sample out from the data port; reset RD
11. Wait t
12. Clear RD- Start communication
13. Wait the time t
14. Read sample out from the data port; reset RD
15. Set CS Deselect ADC
16. Goto step 2 for the next samples
W(CSTARTL)
D(INTL-CSL)
EN(DATAOUT)
signal
W(CSH)
EN(DATAOUT)
signal
t
W(CSTARTL)
t
W(CSTARTL)
wait 210ns+10 ADCSYSCLK and go to step number 7
t
D(INTL-CSI)
t
EN(DATAOUT)
t
W(CSH)
t
EN(DATAOUT)
= 100ns (APD=0) = 600ns (APD=1)
= 10 ns ≥1 ≥1 ≥1 ≥1
= 41 ns ≥2 ≥2 ≥2 ≥2
= 50 ns ≥2 ≥2 ≥2 ≥2
= 41 ns ≥2 ≥2 ≥2 ≥2
Conversation Between the TLV1562 and the DSP
pin
Wait cycles for the DSP internally (40MHz DSPCLK):
APD=0
ADCSYCLK
= 7.5MHz
≥4 ≥4 ≥24 ≥24
≥62 ≥48 ≥62 ≥48
APD=0
ADCSYCLK
= 10MHz
APD=1
ADCSYCLK
= 10MHz
APD=1
ADCSYCLK
= 10MHz
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
15
Conversation Between the TLV1562 and the DSP
7.5 Mono Continuous Mode
This mode simplifies data acquisition, since there is no need to generate a signal to sample or convert data. Instead, initializing this mode once, the ADC sends out the data continuously and will be read by the DSP with the RD
CAUTION: In this mode, the sampling result sent out by the ADC is the value of the sample from the last cycle. Therefore, the first sample after initialization is trash.
Table 10. DSP Algorithm for Mono Continuous Mode
Wait cycles for the DSP internally (40MHz DSPCLK):
STEPS TIMING, NOTES
0. Initialization N/A N/A
Write all configuration data to the ADC
1. Set CS Deselect ADC N/A N/A
2. wait for t
3. Clear CS Select ADC N/A N/A
4. Clear RD Start conversion N/A N/A
5. Wait the time t
6. Read sample out from the data port; reset RD
7. Wait for the time t step 7 and 8 to ensure 5(6) ADC­SYSCLk
8. Go to step 4 for more samples N/A N/A
(SAMPLE1)
EN(DATAOUT)
signal
(CONV1)
minus
Activate the mono continuous mode in CR0(2;3)
t
(SAMPLE1)
t
EN(DATAOUT)
(Caution: the first result after initialization is trash)
t
(CONV1)
7 and 8 take at least 4 DSPSYSCLK, the calculation are 5(6) ADCSYSCLK minus 100 ns
= 100 ns ≥4 ≥4 N/A N/A
= 41 ns ≥2 ≥2 N/A N/A
= 5(6) ADCSYSCLK; since step
APD=0
ADCSYCLK
= 7.5 MHz
≥23 ≥16 N/A N/A
signal.
APD=0
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
N/A N/A
N/A N/A
APD=1
ADCSYCLK
= 10 MHz
16 SLAA040
Conversation Between the TLV1562 and the DSP
7.6 Dual Continuous Mode
The dual continuous mode provides a data stream of two input signals. The characteristic of the data protocol is similar to the mono continuous mode but with the use of two RD
In this mode, the sampling result sent out by the ADC is the value of the sample from the last cycle. Therefore, the first sample after initialization is trash.
Table 11. DSP Algorithm for Dual Continuous Mode
STEPS TIMING, NOTES
0. Initialization N/A N/A
Write all configuration data to the ADC
1. Set CS deselect ADC N/A N/A
2. Wait for t
3. Clear CS Select ADC N/A N/A
4. Clear RD Start conversion
5. Wait the time t
6. Read first sample out from the data port; reset RD
7. Wait for the time t step 7 and 8 to ensure 5(6) ADC­SYSCLk
8. Clear RD Start conversion
9. Wait the time t
10. Read second sample out from the data port; reset RD
11. Wait for the time t step 7 and 8 to ensure 5(6) ADC­SYSCLk
12. Go to step 4 for more samples N/A N/A
(SAMPLE1)
EN(DATAOUT)
EN(DATAOUT)
signal
(CONV1)
signal
(CONV1)
minus
minus
cycles for one sample/hold cycle.
CAUTION:
Wait cycles for the DSP internally (40MHz DSPCLK):
ADCSYCLK
Activate the dual continuous mode in CR0(2;3)
t
(SAMPLE1)
t
EN(DATAOUT)
(Caution: the first result after initialization is trash)
t
(CONV1)
and 8 take at least 4 DSPSYSCLK, the calculation are 5(6)ADCSYSCLK minus 100 ns
t
EN(DATAOUT)
(Caution: the first result after initialization is trash)
t
(CONV1)
and 8 take at least 4 DSPSYSCLK, the calculation are 5(6)ADCSYSCLK minus 100ns
= 100 ns ≥4 ≥4 N/A N/A
= 41 ns ≥2 ≥2 N/A N/A
= 5(6) ADCSysclk; since step 7
= 41 ns ≥2 ≥2 N/A N/A
= 5(6) ADCSysclk; since step 7
APD=0
= 7.5 MHz
≥23 ≥16 N/A N/A
≥23 ≥16 N/A N/A
APD=0
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
N/A N/A
N/A N/A
N/A N/A
APD=1
ADCSYCLK
= 10 MHz
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
17
Software Overview
8 Software Overview
The software in this report shows how to use all modes of the TL V1562 and useful variations for each mode. It also includes a C program to start data acquisition from a C level. To limit the number of programs, the report supplies five files for running the ADC in five modes; a sixth program shows the C-callable function. Each program can enable different software blocks to give the user a large choice for generating the data acquisition. For more details, see paragraph 8.3.9.
Instead of using numbers for memory addresses or constants, very often symbols replace the numbers. For that, the symbol (name) is assigned with the real value (number) in the file header. The advantage of doing this is the higher flexibility. Instead of changing a variable memory location in every related instruction, the value for this location is changed only once in the program header. This prevents software bugs from appearing through a forgotten correction of a related instruction.
BSPC_BUFFER_START set 00800h ; memory location (800h) for the
@AXR = #(BSPC_BUFFER_START) ; assign the starting address of auto
8.1 Software Development tools
The DSKplus Starter Kit of the TMS320C54x comes with a free compiler to generate an absolute object file from assembler code (DSKPLASM.EXE in the TMS320C54x DSKplus development tools). The object code is then loaded into the GoDSP software to run it on the kit.
An advanced version of this kit is the TMS320C54x Optimizing C Compiler/ Assembler/Linker (for example: TMDS324L855-02). These tools allow generation of object code from C and assembler files. Furthermore, they also link the code to an executable COFF file. The software in this report was created with these tools.
For more information visit TI’s Internet page at: http://www.ti.com/sc/docs/dsps/tools/c5000/c54x/index.htm
8.2 DSP Memory Map
Figure 6 shows the memory map assigned to the application. PROGRAM MEMORY (on-chip DARAM 10k words (OVLY=1) from 0080h to 27FFh):
; start address of the SPC buffer
; buffer
.
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0000h
007Fh 0080h
00FFh
0100h
017Fh
0180h
07FFh
0800h
0FFFh
1000h 1009h
100Ah 17FFh
1800h
27FFh
2800h
EFFFh
F000h F7FFh
F800h
FF7Fh FF80h
FFFFh
(OVLY = 1)
Original Interrupts DSKplus
Starter Kit
Communication Kernel
Starter Kit
RAM
BSP RAM Block or Program RAM
Kernel Buffer (10 Words)
HPI RAM Block or Porgram RAM
Program
External
On-Chip ROM
ROM (Bootloader)
ROM Interrupts
01FFh
0200h
027Fh
0280h
02FFh
0300h
Software Overview
Unused
Software Interrupt Table
Unused
Linked Program Memory Code
0000h
005Fh
0060h
007Fh
0080h
27FFh
1800h
1FFFh
2000h
27FFh
2800h
FFFFh
Reserved Memory by The DSKplus Board
Memory-Mapped Register
Scratch-Pad RAM
DRAM See Program Memory
Software Data Memory
(All Variables)
Tables to Store Data Samples
External
Figure 5. Memory Map
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
data_log_A
data_loc_A + num_data_A
data_loc_B
data_loc_B + num_data_B
data_loc_C
data_loc_C + num_data_C
data_loc_D
data_loc_D + num_data_D
Table 1
Table 2
Table 3
Table 4
19
Software Overview
8.3 Programming Strategies for the ’C54x, Explanations
Before listing the program code, this chapter introduces some basic instructions (strategies) to provide the ’C54x user with some ideas for dealing with the DSP architecture.
8.3.1 Optimizing CPU Resources for Maximum Data Rates
The ’C54x processor on the DSKplus starter kit runs at an internal clock frequency of 40 MHz. Since the pipeline architecture allows most instructions to be executed in one cycle, the DSP provides up to 40 MIPS. However, some instructions, especially branch instructions, are not single cycle instructions; therefore, they lower the available CPU power. Because of the high transfer rate of the TLV1562 ADC, performance. Since correct signal timing between DSP and ADC requires some instructions per sample, the CPU power required between two samples is very small.
The optimum case is to read a new sample, store it into memory, execute a customized task as it could be data filtering (FFT, FIR, IIR), and send a digital result to one of the DACs. Unfortunately, this task is impossible at the ADC’s maximum throughput of 40 MIPS. Therefore, this software only stores the samples and optionally moves them out to the DACs. Enabling all options at the same time prevents the application from running at maximum throughput.
the software code must be optimized to test the full ADC
The following switches enable/disable these actions:
SAVE_INTO_MEMORY .set 00001h; set 1 to store the samples into memory SEND_OUT_SERIAL .set 00001h; set 1 to send last sample to the serial DAC SEND_OUT_PARALLEL .set 00001h; set 1 to send last sample out to the parallel DAC
8.3.2 Address and Data Bus for I/O Tasks
8.3.2.1 Writing
PORT(PA) = Smem
Writing something to the I/O bus uses the port instruction. PA sets the ADDRESS bus permanently to that value. Smem is a value from memory , transferred for one clock cycle to the DATA bus.
@send = #01234h ; set the content of memory address send to 1234h port(0FFFFh) = @send ; set address bus to FFFFh and write 1234h for one cycle
; on the DATA bus
8.3.2.2 Reading
Smem = PORT(PA)
Reading from the I/O bus. P A sets the ADDRESS bus. Smem is a memory cell, PA the address on the bus.
8.3.3 Timer Output
@TCR = #00010h ; deactivate timer @PRD = #00000h ; @TCR = #00C01h ; set timer output toggling frequency to ½ CLKOUT
; frequency ; and start toggling
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The timer output pin TOUT can be used to generate an output function with a prescale from half the CLK frequency down to 1FFFF . The problem: the high-time is always one clock cycle and only the low time of the TOUT signal changes with the timer.
8.3.4 Data Page Pointer
DP = #0 ; load DP with 0 DP = #variable ; point with DP to the page, where variable is stored DP ≠ #register ; error, this won’t work, the DP gets not loaded with
; register page, instead load DP with zero
If a register has to be written (example: IFR), the DP has to be loaded with zero since DP=#register will not work.
8.3.5 Generating the Chip Select Signal and the CSTART Signal
port(CSTART) = @ZERO ; clear CSTART- (CSTARTlow) port(ADC) = @CR0_SEND ; clear CS- (CSlow) port(DEACTIVE) = @ZERO ; set CS or CSTART back (CS high or CSTARThigh)
The chip select signal and the CST ART signal can be accessed using the address bus (decoder on A0/A1). The basic idea of having CSTART triggering for sampling/conversion purposes without having to use CS always blocks the address bus). Since the ’C542 DSP does not have enough general purpose outputs, this application still uses the address bus to activate CSTART.
was to allow ADC
Software Overview
(which
8.3.6 Interfacing the Serial DAC 5618A to the DSP
A buffered serial port on the ’C542 board interfaces the TLC5618A DAC. The advantage of using a buffered serial port compared to the standard port is the auto buffer mode. This allows the programmer to save CPU power . A background process takes the data from a defined memory location (table) and moves it out to the serial port. (An interrupt can be generated after sending out half or the full table content. However, disabling this interrupt and writing the new ADC samples into the same memory location where the SPI takes the send value from, allows continuous transmission of the data stream to the DAC. When debugging the EVM it is preferable to compare the analog output signal of the DAC with the analog input signal applied to the ADC.
The TLC5618A is very easy to use. The sample size is limited to 10 bits and the first six MSBs are set so that the converter outputs the value on the right pin in the right mode.
The next lines of code show the initialization. The only requirement is to initialize the buffered serial port, since the DAC does not need an initialization procedure.
@BSPC = #00000h ; reset SPI @IFR = #00020h ; clear any pending SPI IRQ @IMR = #00020h ; allow BXINT0 @BSPCE = #00521h ; set Auto buffer mode @AXR = #(BSPC_BUFFER_START); set the starting address of the auto buffer @BKX = #(BSPC_BUFFER_SIZE) ; buffer size @BSPC = #0C07Ch ; start serial port, FSX in Burst (every word)
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
21
Software Overview
8.3.7 Interrupt Latency
The time required to execute an interrupt depends on the handling of the IRQ at the four-word vector address or jumping further with a GOTO instruction. Using the fast return from IRQ instruction, and branching from the IRQ vector to a separate routine memory location, produces an IRQ overhead of:
3 sysclk (goto IRQ vector) + 4sysclk (goto/dgoto) + 1 sysclk (fast return) = 8 instruction cycles
The time between when the IRQ occurs and the routine executes its first instruction depends on the instruction in the CPU pipeline when the interrupt occurs. Running a repeat command delays the IRQ until the full number of repetitions is finished.
NOTE: Using a delayed branch instruction (dgoto) and putting two useful words of instruction behind this instruction saves the CPU calculation power.(See the explanations about delayed branches Section 8.3.8).
8.3.8 Branch Optimization (goto/dgoto, call/dcall, ...)
The easiest solution for a branch is to use the goto instruction. Since the ’C54x has a pipeline to allow execution of one instruction in one clock cycle, a simple branch instruction will take four cycles for execution. Example:
GOTO MARK
...
MARK: DP = #1;
ARP = #5; ...
The program counter (PC) points after the last instruction (ARP=#5) past 6 sysclk cycles. However, this can be optimized, using a delayed branch.
DGOTO MARK DP = #1; ARP = #5; ...
MARK: ...
The time to execute the same number of instructions is now only four CPU clock cycles. (After four instructions, the PC points to the address MARK. The reason for this is the processor’s pipeline finishes the instructions after dgoto and does not just trash the already-processed fetch when the branch is in the pipeline’s decoding state.
Conclusion: The goto and dgoto instructions both execute the branch in less than four SYSCLCKs, but the dgoto instruction can execute the next two instructions following dgoto in the same amount of time.
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CAUTION:
Use the delayed branches carefully , since it looks confusing when an instruction has been executed after a call instruction. A solution is to first use the normal branches when writing the code, and when all tasks have been finished, optimize the code with the delayed algorithms.
8.3.9 Enabling Software Modules (.if/.elseif/.endif)
To test different software solutions while keeping the number of files small requires integrating all the modules in the same file. Furthermore, a switch is needed to enable any of the software modules. Setting the constant SWITCH in the program header to either one or zero enables/disables the instructions inside an .IF-.ENDIF loop. Example:
SWITCH1 .set 00001h SWITCH2 .set 00000h
...
.if SWITCH1
instruction_X ; the instructions on this line will be assembled
.elseif SWITCH2
instruction_Y ; the instructions on this line will be ignored
.endif
In this example, instruction_X is executed (linked into object code) while instruction_Y is ignored. Setting SWITCH2 instead of SWITCH1 to 1 enables instruction_Y and makes the compiler link it to object code. If both switches are one, only instruction_X is compiled.
8.4 Software Code Explanation
Software Overview
The next capture describes the software solution to interface the TLV1562 and the two DACs on the EVM board. Although the code looks very large and complicated at first, it is a simple solution with only a little knowledge of the code required to verify/customize the settings. The TLV1562 (ADC) offers a wide choice of settings. First, choose the conversation mode. This application report provides one file for each mode. Many settings (2s complement, channels, etc.) must be selected. This software allows a variation of those parameters in the program header. A simple switch enables or disables each component. After recompiling the code with a special setting of all switches, the code becomes much smaller and easier to understand. The .if/.elsif/.endif instruction allows the program to use or ignore blocks of instruction between the statements.
If, for example, one does not want to use the serial DAC and disables the switch SEND_OUT_SERIAL, all the source code for the serial conversation between DSP and DAC is ignored. The compiler will not implement any code related to the serial DAC.
8.4.1 Software Principals of the Interface
Controlling the status of signals can be done in different ways. One of the challenges in this interface is controlling signal status when the ADC conversion is finished and the digital result is ready to be transferred from the ADC to DSP. A high/low transition on the INT has completed the conversion. Optionally, the DSP can ignore the INT initialize the conversion instead, wait for a defined time, and directly read the result out of the ADC. This solution requires knowing the precise time for conversion/data ready on the bus for each converter/mode.
line of the TL V1562 informs the DSP that the ADC
signal,
Three options are given for each mode to match different custom needs; they are listed in the next three sections.
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
23
Software Overview
8.4.1.1 Software Polling
The status of the input pin is tested in a loop until the valid transition occurs. After this transition, the program branches to the next instruction (reads data sample).
Advantage:
• Relatively fast program response after high-to-low transition of INT
• The software compensates for variations of timing given in data sheets for
conversion and the real time until the flag goes high.
• Not critical for any software changes (e.g. adding new features)
• Even when the program reaches the polling loop later than the transition
occurred, it steps ahead properly.
Disadvantage:
• Time inside the polling loop is not usable for other software features (wasted
CPU power)
• A hang up (ADC does not respond) will not be recognized without a watchdog
algorithm
• The polling algorithm requires five instruction cycles. Depending on when the
conversion finishes during these five instructions (when the INT low), the time response after the falling edge can vary up to the five instruction cycles. As experiments confirmed, this can result in a variation in the length of the sampling window. So, a filter algorithm (eg. FFT) on the samples might result in slightly different results for a steady (stable) input function, related to the sampling time variations. The only way to prevent this is to control the conversion with the on-chip timer of the DSP. Unfortunately, the maximum throughput falls off with increased requirements for CPU power.
signal goes
8.4.1.2 Timed Solution
How
long the ADC requires for conversion must be factored into the software flow. In other words, the DSP has to wait a certain time between initializing the conversion and reading the conversion result on the data bus from the ADC. This timing is critical to the sampling device. If the conversion time of a data converter changes (data sheet), the timing must be verified again.
Advantage:
• Fastest solution (with a fine tune, the maximum performance can be
extracted from the converter)
• Saves CPU power of the DSP (no time wasted for polling)
• Program can not hang up in an endless loop
• Less hardware required (input pin on the DSP and INT connection are left out)
Disadvantage:
• Every software variation changes timing and therefore, requires fine tuning
again. This can be avoided by using the DSP timer module, but since the TLV1562 is an extremely fast device (2 MSPS at 10 bit), a timer module solution becomes too slow.
• If the conversion time of the ADC varies for some reasons, this algorithm is
not able to respond; instead, the maximum conversion time is used.
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