Texas Instruments TLV0838IN, TLV0838IDWR, TLV0838CN, TLV0838IDW, TLV0838CDWR Datasheet
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TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 – SEPTEMBER 1996
D
8-Bit Resolution
D
2.7 V to 3.6 V V
D
Easy Microprocessor Interface or
CC
Standalone Operation
D
Operates Ratiometrically or With V
Reference
D
4- or 8-Channel Multiplexer Options With
Address Logic
D
Input Range 0 V to VCC With VCC Reference
D
Remote Operation With Serial Data Link
D
Inputs and Outputs Are Compatible With
TTL and MOS
D
Conversion Time of 32 µs at
f
D
Functionally Equivalent to the ADC0834
(CLK)
= 250 kHz
and ADC0838 at 3-V Supply Without the
Internal Zener Regulator Network
D
Total Unadjusted Error...±1 LSB
description
These devices are 8-bit successive-approximation
analog-to-digital converters, each with an
input-configurable multichannel multiplexer and
serial input/output. The serial input/output is
configured to interface with standard shift registers
or microprocessors. Detailed information on
interfacing with most popular microprocessors is
readily available from the factory.
CC
TLV0834...D OR N PACKAGE
DGTL GND
TLV0838...DW OR N PACKAGE
COM
DGTL GND
NC
CS
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
7
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
9
8
20
19
18
17
16
15
14
13
12
11
V
CC
DI
CLK
SARS
DO
REF
ANLG GND
V
CC
NC
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TL V0834C and TL V0838C are characterized for operation from 0°C to 70°C. The TL V0834I and TL V0838I
are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TLV0834CD TLV0838CDW TLV0834CN TLV0838CN
–40°C to 85°C TLV0834ID TLV0838IDW TLV0834IN TLV0838IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OUTLINE
SMALL
(D)
SMALL
OUTLINE
(DW)
PLASTIC DIP
(N)
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
SLAS147 – SEPTEMBER 1996
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
functional block diagram
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834
TLC0838
CLK
CS
TLC0838
Only
SE
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DI
(see Note A)
To Internal
Circuits
D
CLK
SELECT0
REF
R
5-Bit Shift Register
ODD\
SELECT1
EVEN
Analog
MUX
EN
EN
Ladder
and
Decoder
DIF
SGL\
Comparator
Bits 0–7
START
One
Shot
CS
R
SAR
Logic
and
Latch
MSB
First
Bits 0–7
Bit 1
LSB
First
Time
Delay
CS
R
CLK
9-Bit
Shift
Register
EOC
Start
Flip-Flop
CLK
S
R
CLK
S
R
CS
CS
R
CLK
D
CS
SARS
CS
DO
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 – SEPTEMBER 1996
functional description
The TL V0834 and TL V0838 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. Operation of both devices is similar with the exception of SE
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity . When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs . For example, channel 0 and channel 1 may be selected as a differential pair . These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
, an analog
The common input on the TL V0838 can be used for a pseudo-differential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TL V0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE
high on the TLV0838, the value of the LSB remains on the data line. When SE
clocked out as LSB-first data. (To output LSB first, SE
register outputs LSB first.) When CS
go to the high-impedance state. If another conversion is desired, CS
by address information.
low, which enables all logic circuits. CS must be held low for the complete
is held
is forced low, the data is then
must first go low, then the data stored in the 9-bit shift
goes high, all internal registers are cleared. At this time, the output circuits
must make a high-to-low transition followed
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 – SEPTEMBER 1996
sequence of operation
TLV0834
157
CLK
t
conv
CS
t
su
+Sign
SELECT
Start
Bit
ODD
SGLBit
Bit 1
21201918141312123456 1011
DI
SARS
DO
DIF
Hi-Z
MUX Settling Time
Hi-Z
Don’t Care
EVEN
1
MSB-First Data
MSB
LSB-First Data
176201267
TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS CHANNEL NUMBER
SGL/DIF
L
L
L
L
H
H
H
H
H = high level, L = low level, – or + = terminal polarity for the selected input channel
ODD/EVEN
L
L
H
H
L
L
H
H
SELECT BIT 1
L
H
L
H
L
H
L
H
CH0 CH1
+––
+
+
+
CH2 CH3
+––
+
+
+
MSBLSB
Hi-Z
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
sequence of operation
1
CLK
TLV0834C, TLV0834I, TLV0838C, TLV0838I
SLAS147 – SEPTEMBER 1996
TLV0838
8765432
2726252423222120191817161514131211
ARS
SE
DO
CS
DI
Hi-Z
SE
Hi-Z
Start
Bit
t
su
MUX
Addressing
t
su
+
Sign
Bit
MUX Settling
Bit
1SGL ODD
1EVENDIF
Time
t
conv
SELSEL
Bit
0
Don’t Care
0
Hi-Z
LSB Held LSB-First DataMSB-First Data
LSB-First Data
MSB
Hi-Z
765432101267
MSB
MSB-First Data
LSB
Used to Control LSB-First Data
SE
DO
MSB
LSB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSB
765432101267
5
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