Texas Instruments TLK1501 User Manual
TLK1501 Serdes EVM Kit
Setup and Usage
User’s Guide
June 2000 Mixed Signal Products
SLLU008
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
About This Manual
This manual should be used to determine how to set up and use the TLK1501
evaluation module in order to evaluate the TLK1501 device.
How to Use This Manual
This document contains the following chapters:
Notational Conventions
Preface
Read This First
-
-
-
-
-
Notational Conventions
This document uses the following conventions.
-
Chapter 1 — Introduction
Chapter 2 — TLK1501 EVM Board Configuration
Chapter 3 — PCB Construction and Characteristics
Appendix A — Schematics, Board Layouts, and Suggested Optics and
Cable Assembly Specifications
Appendix B — NetLight 1417K4A 1300 nm Laser 2.5 Gbits/s
SpeedBlaster Transceiver data sheet
Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities
Read This First
iii
Trademarks
-
In syntax descriptions, the instruction, command, or directive is in a bold
typeface font and parameters are in an
italic typeface
. Portions of a syntax
that are in bold should be entered as shown; portions of a syntax that are
italics
in
describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect ”
section name
”,
address
.asect is the directive. This directive has two parameters, indicated by
tion name
and
address
. When you use .asect, the first parameter must be
an actual section name, enclosed in double quotes; the second parameter
must be an address.
-
Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK
The LALK instruction has two parameters. The first parameter,
stant
16–bit constant [, shift]
, is required. The second parameter,
16-bit con-
shift
, is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with
a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
-
Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here’s an example of a list:
sec-
Trademarks
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
-
Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this directive is:
.byte
value1 [, ... , valuen]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
TI is a trademark of Texas Instruments Incorporated.
NetLight and SpeedBlaster are trademarks of Lucent Technologies Inc.
iv
Running Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 TLK1501 EVM Kit Contents 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 TLK1501 EVM Board Configuration 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Typical Test and Setup Configurations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Optical Interfacing and Configuration 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 PCB Construction and Characteristics 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Schematics, Board Layouts, and Suggested Optics and Cable
Assembly Specifications A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B NetLight 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlaster Transceiver B-1. . . . . . . . . .
Chapter Title—Attribute Reference
v
Running Title—Attribute Reference
Figures
2–1 TLK1501 Serial Loop-Back Test Configuration 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 TLK1501 Serial Loop-Back Test Configuration 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 TLK1501 Serial PRBS BERT Test Configuration 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 TLK1501 Serial PRBS BERT Test Configuration 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Optical Interface Configuration 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 TLK1501EVM to Laser Module Configuration 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 TLK1501 EVM Layer Construction 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 TLK1501 EVM Transceiver Schematic A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Optical Transceiver Schematic A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Top Layer 1 A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 GND Layers 2 and 5 A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Power Plane 1 A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 Bottom Layer 6 A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 Bottom Layer 7 A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 Top Layer 1 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 Detail of Top Layer 1 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–10 GND Layers 2 and 5 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–11 Detail of GND Layers 2 and 5 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–12 Power Plane 1 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13 Detail of Power Plane 1 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14 Bottom Layer 6 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–15 Detail of Bottom Layer 6 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–16 Bottom Layer 6 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–17 Detail of Bottom Layer 6 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T ables
2–1 Default Transceiver Board Configuration as Shipped 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Configuration Changes Necessary for DC-Coupling of the High-Speed Signals 2-2. . . . . . . .
3–1 TLK1501 EVM TTL Bus PCB Transmission Line Characteristics 3-2. . . . . . . . . . . . . . . . . . . .
3–2 TLK1501 Differential Pair PCB Transmission Line Characteristics 3-2. . . . . . . . . . . . . . . . . . .
A–1 TLK1501 EVM Transceiver Bill of Materials A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Chapter 1
Introduction
The Texas Instruments (TI) TLK1501 serdes evaluation module (EVM) board
is used to evaluate the TLK1501 device(VQFP) and associated optical interface (NetLight) for point-to-point data transmission applications.
The board enables the designer to connect 50 Ω parallel buses to both
transmitter and receiver connectors. The TLK1501, using high speed PLL
technology, serializes, encodes (8b/10b) and transmits data along one
differential pair. The receiver part of the device deserializes, decodes and
presents data on the parallel bus. The high speed (up to 1.6 Gbps) data lines
interface to four 50-Ω controlled-impedance SMA connectors. The designer
can either use this copper interface directly or loop back to the laser module
section for an optical interface(not provided).
Topic Page
1.1 Introduction 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction
1-1
Introduction
1.1 Introduction
The board can be used to evaluate device parameters while acting as a guide
for high-speed board layout. The evaluation board can be used as daughter
boards that are plugged into new or existing designs. Since the TLK1501
operates over a wide range of frequencies, the designers will need to optimize
their design for the frequency of interest. Additionally , the designers may wish
to use buried transmission lines and provide additional noise attenuation and
EMI suppression to optimize their end product.
As the frequency of operation increases, the board designer must take special
care to ensure that the highest signal integrity is maintained. To achieve this,
the board’s impedance is controlled to 50 Ω for both the high-speed differential
serial and parallel data connections. In addition, impedance mismatches are
reduced by designing the component pad size to be as close as possible to
the width of the connecting transmission lines. Vias are minimized and, when
necessary , placed as close as possible to the device drivers. Since the board
contains both serial and parallel transmission lines, care was taken to control
both impedance and trace length mismatch (board skew).
Overall, the board layout is designed and optimized to support high-speed
operation. Thus, understanding impedance control and transmission line
effects are crucial when designing high-speed boards.
Some of the advanced features offered by this board include:
-
PCB (printed-circuit board) is designed for high-speed signal integrity.
-
Flexibility–The PCB can be configured for copper or optical interfaces.
-
SMA and parallel fixtures are easily connected to test equipment.
-
All input/output signals are accessible for rapid prototyping.
-
Analog and digital power planes can be supplied through separate banana
jacks for isolation or can be combined using ferrite bridging networks.
-
Series termination resistors provide parallel RD outputs.
-
Onboard capacitors provide ac-coupling of high-speed signals.
1.2 TLK1501 EVM Kit Contents
-
TLK1501 EVM board
-
TLK1501 EVM kit documentation (This document)
1-2
Chapter 2
TLK1501 EVM Board Configuration
The TLK1501 EVM board gives the developer various options for operation,
many of which are jumper selectable. Other options can be either soldered into
the EVM or connected through input connectors.
The TX and RX parallel connectors, J1–J4 of Figures 8 and 10 in Appendix A,
provide a connection for both transmitted and received data. The reference
clock is supplied through SMA connector J8 and jumper J5 must be installed
between pins 1 and 2. A direct clock connection can also be made to J5 pins
1 and 3. The high-speed serial data is transmitted through J13 and J14 SMA
connectors. The received recovered clock (RX_CLK) is output through J15
header. Received data connects through SMA connectors J17 and J23 on the
RX side of the board. Header J7 provides static signals (normally pulled high)
to configure the device for different modes of operation. The J20 header
indicates the optical transmitter has detected a signal and J21 allows the
operator to disable the optical transceiver.
The power planes are split three ways to provide power for different parts of
the board. This prevents coupling of switching noise between the analog and
digital sections of the TLK1501 and provides voltage isolation for the laser
section. The laser section of the board requires 3.3 volts and is energized
through the VCC connector. The VDD and VDDA connectors require 2.5 volts
and are joined together by a removable ferrite bead L3 that is installed in the
default configuration. Thus, only the VDD connection is necessary to energize
the TLK1501 device in the default configuration. In all sections of the board,
the ground planes are common and each ground plane is tied together at every
component ground connection. For a detailed schematic and layout see
TLK1501EVM Schematic, Optical Transceiver Schematic
Stack-up
in Appendix A.
and
Board Layer
Topic Page
2.1 Typical Test and Setup Configurations 2–3. . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Optical Interfacing and Configuration 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . .
TLK1501 EVM Board Configuration
2-1
The board is normally delivered in a default configuration that requires external
clock and data inputs. The TLK1501 is shipped with jumpers for default
operation. Table 2–1 shows the default configuration for sending data.
Table 2–1.Default Transceiver Board Configuration as Shipped
Designator Function Condition
J5 GTX CLK SEL Jumper installed – Provides a method of supplying an input clock to
the board
J7 TESTEN Jumper installed (Logic 0)
Disables the TLK1501 test mode
J7 PRBSEN Jumper installed (Logic 0)
Disables the TLK1501 PRBS internal production test mode
J7 LCKREFN Jumper not installed (Logical 1)
Locks to received clock
J7 ENABLE Jumper not installed (Logical 1)
Enables the device for normal operation
J7 TXER Jumper installed (Logic 0)
Puts the TLK1501 in a state to transmit TX bus data
J7 LOOPEN Jumper installed (Logic 0)
Disables the TLK1501 internal loop back mode
J7 TXEN Jumper not installed (Logical 1)
Puts the TLK1501 in a state to transmit TX bus data
L3 VDD– bridge –VDDA Joins VDD and VDDA power planes
C24, C25 TX ac-coupling
capacitors
C22, C23 RX ac-coupling
capacitors
Note: For details, see TLK1501 data sheet
These capacitors (normally installed) are provided to ac-couple the
transmitted signal.
These capacitors (normally installed) are provided to ac-couple the
received signal
Table 2–2.Configuration Changes Necessary for DC Coupling of the High Speed Signals
Designator Function Condition or Changes Necessary for DC Coupling
C24, C25 TX ac-coupling
capacitors
C22, C23 TX ac-coupling
capacitors
R34 RX bias resistor Install zero ohm resistor.
R33 RX bias resistor Uninstall resistor (open circuit)
Install zero ohm resistors
Install zero ohm resistors.
R37, R38 TX termination
network
2-2
Uninstall resistors (open circuit) – Termination and pullup is achieved
at the receiver. Dif ferential swing is increased.
2.1 Typical Test and Setup Configurations
The following configurations are used to evaluate and test the TLK1501
transceiver. The first configuration is a serial loopback of the high-speed
signals shown in Figure 2–1. The serial loopback allows the designer to
evaluate most of the functions of both transmitter and receiver sections of the
TLK1501 device. To test a system, a parallel bit error rate tester (BERT)
generates a predefined parallel bit pattern. The pattern is connected to the
transmitter through parallel connectors TD0–TD15. Additionally, two control
pins TX_ER and TX_EN are configured by the BERT for valid data
transmission (TX_ER low and TX_EN high). The TLK1501 device encodes,
serializes, and presents the data on the high-speed serial pair. The serial TX
data is then looped back to the receiver side and the device deserializes,
decodes, and presents the data on the receive side RD0–RD15. The data and
indication bits (RX_DV and RX_ER) are received by the BERT and compared
against the transmitted pattern and monitored for valid data and errors. If any
bit errors are received, a bit error rate is evaluated at the parallel receive BERT .
Figure 2–1.TLK1501 Serial Loop-Back Test Configuration
Jumper Selection
GND
TESTEN
PRBSEN
LCKREFN
J7
ENABLE
TX_ER
Pulse Generator
(Asynchronous to BERT)
EXT INPUT
T ypical Test and Setup Configurations
HP8133A
Channel 1
O/P
LOOPEN
TX_EN
GND
Parallel BERT
Frequency = 30-80 MHz
CLK OUT
TX Data Out 0-17
CLK IN
RX Data In 0-17
Receiver BERT
18 bits
18 bits
GTX_CLK
TD 0-15
TX_EN
TX_ER
RX CLK
RX_ER
RX_DV
RD 0-15
TLK1501EVM
Evaluation Board
TX+
TX–
RX+
RX–
TLK1501 EVM Board Configuration
2-3
T ypical Test and Setup Configurations
If a parallel BERT is not available, the designer can take advantage of the
built-in test mode of the device, see Figure 2–2. If the designer asserts the
PRBSEN pin high this results in a pseudorandom bit pattern to be transmitted.
This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid
pattern is indicated by the PRBSPASS pin indicating high. This test only
validates the high-speed serial portion of the device and system interconnects.
The PRBS pattern is compatible with most serial BERT test equipment. This
function allows the operator to isolate and test the transmitter and receiver
independently. A typical configuration is shown in Figure 2–3. The dashed
lines represent optional connections that can be made monitoring eye patterns
and measuring jitter.
Figure 2–2.TLK1501 Serial Loop-Back Test Configuration
Jumper Selection
GND
TESTEN
PRBSEN
LCKREFN
ENABLE
TX_ER
LOOPEN
TX_EN
J7
Channel 1
GND
HP8133A
Pulse Generator
TRIGGER
O/P
EXT
INPUT
OUT
HP83480 or
Tek 11801
Digital
Oscilloscope
CH1
CH2
Trigger
Channel 1
TDS820 Digital
Oscilloscope
GTX_CLK
PRBS
2^7-1
PRBS_PASS
RD 0-15
TLK1501EVM
Evaluation Board
TX–
TX+
RX+
RX–
PRBS 2^7-1
2-4
Figure 2–3.TLK1501 Serial PRBS BERT Test Configuration
Jumper Selection
GND
TESTEN
PRBSEN
LCKREFN
ENABLE
TX_ER
LOOPEN
TX_EN
GND
Channel 1
J7
Pulse Generator
Channel 1
O/P
PRBS
2^7-1
HP8133A
EXT
INPUT
TRIGGER
OUT
GTX_CLK
TX–
TX+
CLK/20
T ypical Test and Setup Configurations
HP83480 or
Tek 11801
Digital
Oscilloscope
CH1
CH2
Trigger
Serial BERT
HP7004A 3 Gbps
Receiver BERT
Data In
TDS820 Digital
Oscilloscope
Transmitter BERT
PRBS_PASS
RD 0-15
TLK1501EVM
Evaluation Board
RX+
RX–
PRBS 2^7-1
Data Out
Data Out
CLK OUT
A board-to-board communication link is a practical method of evaluating the
TLK1501 in a system-like environment as shown in Figure 2–4. A Parallel
BERT or a logic analyzer can be used to provide and monitor signals to and
from the transceiver pairs. The BERT would need to configure the TX_ER and
TX_EN signals for data transmission before any data is sent. On the receive
side the RX_ER and RX_DV can monitor the device for errors. Both GTX_CLK
sources must have the same frequency within 200 PPM for asynchronous
operation. Synchronous operation can be achieved by using either the BERT
or a synchronized pulse generator to supply both boards with GTX_CLK
inputs.
TLK1501 EVM Board Configuration
2-5
T ypical Test and Setup Configurations
Figure 2–4.TLK1501 Serial PRBS BERT Test Configuration
Jumper Selection
TESTEN
PRBSEN
LCKREFN
ENABLE
TX_ER
LOOPEN
TX_EN
EVM #1
GND
GND
J7
TD 0-15
TX_EN
TX_ER
TESTEN
PRBSEN
LCKREFN
ENABLE
TX_ER
LOOPEN
TX_EN
GTX_CLK
TX+
TX–
EVM #2
GND
GND
J7
Synchronous
RX+
RX–
HP8133A
Pulse Generator
(Asynchronous to BERT)
EXT INPUT
Channel 1
GTX_CLK
Trigger
O/P
Asynchronous
RD 0-15
RX_ER
Rx_DV
16 bits
2 bits
18 bits
TX Data Out 0-17
CLK Out
RX+
RD 0-15
TLK1501EVM #1
Evaluation Board EVM1
PRBS Disabled
Parallel BERT
Frequency = 30-80 MHz
Transmitter BERT
RX Data In 0-17
Receiver BERT
RX–
CLK IN
TX+
TX–
TLK1501EVM #2
Evaluation Board EVM2
Board configued to
send IDLE pattern:
TX_EN = 0
TX_ER = 0
18 bits
RX_CLK
TD 0-15
PRBS Disabled
Channel
1
2-6
2.2 Optical Interfacing and Configuration
An interface between the TLK1501EVM and an optical transceiver can be
achieved in many ways, depending on the design of the optics module and its
associated interface circuitry . Direct connection is achieved only if the optical
interface supports the current mode logic levels of the TLK1501 device (VDD
– 1 V). If the optics module does not support or can not be biased to the CML
levels then ac-coupling must be used. Both ac- and dc-coupling schemes are
shown in Figure 2–5. The
an ac-coupled optics module. The board is shipped with an ac-coupled output
and all that is required is external loopback cabling.
Figure 2–5.Optical Interface Configuration
Laser Module Section
Optical Interfacing and Configuration
of the EVM is configured as
AC Coupling
TLK1501 TX
DC Coupling
TLK1501 TX
V
DD
50 Ω
CMLDC bias levels
voltage ≈ (VDD-1 V)
Biased to CML Levels
Biased to PECL Levels
50 Ω
50 Ω
V
DD
Optical Module
V
CC
Optical Module
50 Ω
The
external loopback as shown in Figure 2–6. This makes for a versatile system
where the laser can be connected independently to other EVM systems.
Laser Module Section
is isolated from the rest of the board and requires
TLK1501 EVM Board Configuration
2-7
Optical Interfacing and Configuration
Figure 2–6.TLK1501 EVM to Laser Module Configuration
2-8
TLK2500 EVM Board Configuration
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