High Output-Current Capability
– Source...20 mA Typ
– Sink...20 mA Typ
description
In signal-conditioning applications utilizing a
single power source, a reference voltage equal to
one-half the supply voltage is required for
termination of all analog signal grounds. Texas
Instruments presents a precision virtual ground
whose output voltage is always equal to one-half
the input voltage, the TLE2426 “rail splitter.”
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
D
Excellent Output Regulation
– –45 µV Typ at I
– +15 µV Typ at I
D
Low-Impedance Output...0.0075 Ω Typ
D
Noise Reduction Pin (D, JG, and P
Packages Only)
INPUT/OUTPUT TRANSFER CHARACTERISTICS
10
V
I
8
6
V
Voltage – V
4
O
= 0 to –10 mA
O
= 0 to +10 mA
O
V
I
V
O
VO+
V
I
2
The unique combination of a high-performance,
micropower operational amplifier and a precision-
2
trimmed divider on a single silicon chip results in
a precise V
sourcing current. The TLE2426 provides a lowimpedance output with 20 mA of sink and source
capability while drawing less than 280 µA
ratio of 0.5 while sinking and
O/VI
0
00.250.50.751
t – Time – s
of supply current over the full input range of 4 V to 40 V. A designer need not pay the price in terms of board
space for a conventional signal ground consisting of resistors, capacitors, operational amplifiers, and voltage
references. The performance and precision of the TLE2426 is available in an easy-to-use, space saving,
3-terminal LP package. For increased performance, the optional 8-pin packages provide a noise-reduction pin.
With the addition of an external capacitor (C
), peak-to-peak noise is reduced while line ripple rejection is
NR
improved.
Initial output tolerance for a single 5-V or 12-V system is better than 1% with 3.6% over the full 40-V input range.
Ripple rejection exceeds 12 bits of accuracy . Whether the application is for a data acquisition front end, analog
signal termination, or simply a precision voltage reference, the TLE2426 eliminates a major source of system
error.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
T
A
0°C to 70°CTLE2426CD—TLE2426CLPTLE2426CP
–40°C to 85°CTLE2426ID—TLE2426ILPTLE2426IPTLE2426Y
–55°C to 125°CTLE2426MDTLE2426MJGTLE2426MLPTLE2426MP
The D and LP packages are available taped and reeled in the commercial temperature range only. Add R suffix
to the device type (e. g., TLC2426CDR). Chips are tested at 25°C.
OUTLINE
(D)
CERAMIC
DIP
(JG)
PLASTIC
(LP)
PLASTIC
DIP
(P)
CHIP
FORM
(Y)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
description (continued)
The C-suffix devices are characterized for operation from 0°C to 70°C. The I suffix devices are characterized
for operation from –40°C to 85°C. The M suffix devices are characterized over the full military temperature range
of –55°C to 125°C.
D, JG, OR P PACKAGE
(TOP VIEW)
LP PACKAGE
(TOP VIEW)
OUT
COMMON
NC – No internal connection
IN
NC
1
2
3
4
NOISE REDUCTION
8
NC
7
NC
6
NC
5
IN
COMMON
OUT
TLE2426Y chip information
This chip, properly assembled, displays characteristics similar to the TLE2426C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(2) (2)
(1)
(1)
NOISE
REDUCTION
IN
(8)
(2)
COMMON
(3)
+1
(1)
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 × 4 MILS MINIMUM
OUT
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN
MILS.
60
(3)
(3)
(8)
88
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTE A: Both bonding pads numbered 1, both numbered 2,
and both numbered 3, must be bonded out to the
corresponding functions pin.
TLE2426, TLE2426Y
PACKAGE
UNIT
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or LP package 300°C. . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The output may be shorted to either supply. T emperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
DISSIPATION RATING TABLE
TA ≤ 25°CDERATING FACTORTA = 70°CTA = 85°CTA = 125°C
POWER RATINGABOVE TA = 25°CPOWER RATING POWER RATINGPOWER RATING
Output voltageDistribution1,2
Output voltage changevs Free-air temperature3
Output voltage errorvs Input voltage4
p
Output voltage regulationvs Output current7
Output impedancevs Frequency8
p
Ripple rejectionvs Frequency13
Spectral noise voltage densityvs Frequency14
Output voltage response to output current stepvs Time15
Output voltage power-up responsevs Time16
Output currentvs Load capacitance17
vs Input voltage5
vs Free-air temperature6
vs Input voltage9,10
vs Free-air temperature11,12
TLE2426, TLE2426Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
TYPICAL CHARACTERISTICS
DISTRIBUTION
OF
OUTPUT VOLTAGE
3
98 Units Tested
From 2 Wafer Lots
2.5
VI = 5 V
TA = 25°C
2
1.5
1
Percentage of Units – %
0.5
0
2.482.492.52.512.52
VO – Output Voltage – V
Figure 1
†
DISTRIBUTION
OF
OUTPUT VOLTAGE
40
98 Units Tested
From 2 Wafer Lots
VI = 12 V
TA = 25°C
30
20
Percentage of Units – %
10
0
66.0256.1
VO – Output Voltage – V
6.056.075
Figure 2
VO – Output Voltage Change – mV
∆V
–75
O
–150
150
75
0
–75
OUTPUT VOLTAGE CHANGE
vs
FREE-AIR TEMPERATURE
VI = 40 VIO = 0
VI = 12 V
VI = 4 V, 5 V
–50 –25
TA – Free-Air Temperature – ° C
02550
Figure 3
75100125
OUTPUT VOLTAGE ERROR
4
IO = 0
TA = 25°C
3
Error Equals VO/VI Deviation From 50%
2
1
Output Voltage Error – %
0
–1
048121620
VI – Input Voltage – V
vs
INPUT VOLTAGE
2436 40
Figure 4
2832
†
Data at high and low temperatures are applicable within the rated operating free-air temperature ranges of the various devices.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
INPUT BIAS CURRENT
INPUT VOLTAGE
300
IO = 0
250
Aµ
200
150
100
IB
I
IIB – Input Bias Current –
50
0
TA = 125°C
0510152025
TA = 25°C
VI – Input Voltage – V
Figure 5
vs
TYPICAL CHARACTERISTICS
300
250
Aµ
200
TA = –55°C
150
100
IB
I
IIB – Input Bias Current –
50
303540
0
†
INPUT BIAS CURRENT
FREE-AIR TEMPERATURE
IO = 0
–50–75–20
02550
TA – Free-Air Temperature – ° C
Figure 6
vs
VI = 40 V
VI = 12 V
VI = 5 V
VI = 4 V
75100 125
OUTPUT VOLTAGE REGULATION
500
Max
µV
250
0
Typ
–250
Output Voltage Regulation –
Min
–500
–20–10
vs
OUTPUT CURRENT
VI = 5 V or 12 V
TA = 25°C
01020
IO – Output Current – mA
Figure 7
Max
Min
Typ
100
VI = 5 V or 12 V
IO = 0
TA = 25°C
10
1
0.1
– Output Impedance – Ωz
o
0.01
0.001
101001 k
OUTPUT IMPEDANCE
vs
FREQUENCY
10 k
f – Frequency – Hz
100 k
Figure 8
1 M
†
Data at high and low temperatures are applicable within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
SHORT-CIRCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
0
–20
–40
TA = –55°C
–60
OS
IOS – Short-Circuit Output Current – mA
I
–80
TA = 25°C
0510152025
VI – Input Voltage – V
Figure 9
TYPICAL CHARACTERISTICS
40
VO = GND
(Output Sourcing)
30
20
10
TA = 125°C
303540
OS
IOS – Short-Circuit Output Current – mA
I
0
0510152025
†
SHORT-CIRCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
TA = 25°C
TA = –55°C
TA = 125°C
VO = V
(Output Sinking)
I
303540
VI – Input Voltage – V
Figure 10
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
0
–10
–20
–30
–40
–50
–60
–70
OS
IOS – Short-Circuit Output Current – mA
I
–80
–75 –50–25
VO = GND
(Output Sourcing)
0255075100
TA – Free-Air Temperature – ° C
Figure 11
VI = 4 V
VI = 12 V
VI = 5 V
VI = 40 V
125
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
40
30
20
10
VO = V
OS
IOS – Short-Circuit Output Current – mA
I
(Output Sinking)
0
–75 –50–25
I
TA – Free-Air Temperature – ° C
VI = 40 V
VI = 12 V
VI = 5 V
VI = 4 V
02550
Figure 12
75100 125
†
Data at high and low temperatures are applicable within the rated operating free-air temperature ranges of the various devices.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
RIPPLE REJECTION
100
VI = 5 V or 12 V
90
∆V
= 1 V
I(PP)
IO = 0
80
TA = 25°C
70
60
50
40
30
Ripple Rejection – dB
20
10
0
101001 k10 k
CNR = 0
f – Frequency – Hz
Figure 13
OUTPUT VOLTAGE RESPONSE
TO OUTPUT CURRENT STEP
1.5 V
4
3
2
1
0
–1
–2
–3
O
VO – Change In Output Voltage – mV
∆V
–4
–1.5 V
0.1%
0.01%
10 mA
IO Step
010002000
Figure 15
vs
FREQUENCY
VI = 5 V
CL = 100 pF
TA = 25°C
Time – µs
CNR = 1 µF
100 k1 M
0.01%
0.1%
–10 mA
30004000
SPECTRAL NOISE VOLTAGE DENSITY
400
VI = 5 V or 12 V
TA = 25°C
nV/ Hz
300
200
100
– Spectral Noise Voltage Density –
n
V
0
1
OUTPUT VOLTAGE POWER-UP RESPONSE
3
2.5
2
1.5
1
0.5
O
V) – Output Voltage – V
V
0
5
0
vs
FREQUENCY
CNR = 0
CNR = 1 µF
101001 k10 k
f – Frequency – Hz
100 k
Figure 14
0.1%
Output Voltage Response
IO = 0
CL = 100 pF
TA = 25°C
Input Voltage Step
050100200
Time – µs
0.01%
150
Figure 16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
20
TYPICAL CHARACTERISTICS
STABILITY RANGE
OUTPUT CURRENT
vs
LOAD CAPACITANCE
VI = 5 V
15
TA = 25°C
10
5
0
–5
– Output Current – mA
–10
O
I
–15
–20
–6
10
10–510
CL– Load Capacitance – mF
–4
10
Figure 17
Unstable
Stable
–3
10
–2
10
–1
10
0
10
10
2
1
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
MACROMODEL INFORMATION
*TLE2426 OPERATIONAL AMPLIFIER “MACROMODEL” SUBCIRCUIT
*CREATED USING PARTS RELEASE 4.03 0N 08/21/90 AT 13:51
*REV (N/A)SUPPLY VOLTAGE: 5 V
*CONNECTIONS:FILTER
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
18
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
MECHANICAL INFORMATION
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
8
1
5
4
0.065 (1,65)
0.045 (1,14)
0.020 (0,51) MIN
0.280 (7,11)
0.245 (6,22)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0.310 (7,87)
0.290 (7,37)
Seating Plane
0°–15°
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4040107/C 08/96
19
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
MECHANICAL INFORMATION
LP (O-PBCY-W3) PLASTIC CYLINDRICAL P ACKAGE
0.205 (5,21)
0.175 (4,44)
0.210 (5,34)
0.170 (4,32)
0.022 (0,56)
0.016 (0,41)
0.016 (0,41)
0.014 (0,35)
Seating Plane
0.050 (1,27)
(see Note C)
DIA
Wide
Thick
3 Leads
0.500 (12,70) MIN
0.165 (4,19)
0.125 (3,17)
0.105 (2,67)
0.080 (2,03)
0.055 (1,40)
0.045 (1,14)
0.105 (2,67)
0.095 (2,41)
0.135 (3,43) MIN
3
2
1
0.105 (2,67)
0.080 (2,03)
4040001/B 01/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area.
D. Falls within JEDEC TO-226AA (TO-226AA replaces TO-92)
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2426, TLE2426Y
THE “RAIL SPLITTER”
PRECISION VIRTUAL GROUND
SLOS098D – AUGUST 1991 – REVISED MA Y 1998
MECHANICAL INFORMATION
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
58
0.260 (6,60)
0.240 (6,10)
41
0.070 (1,78) MAX
0.020 (0,51) MIN
0.200 (5,08) MAX
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
0.010 (0,25)
M
0.310 (7,87)
0.290 (7,37)
Seating Plane
0°–15°
0.010 (0,25) NOM
4040082/B 03/95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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