Texas Instruments TLC7524IPWR, TLC7524IPW, TLC7524IN, TLC7524IFNR, TLC7524CDR Datasheet

TLC7524C, TLC7524E, TLC7524I

8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Easily Interfaced to Microprocessors

D

On-Chip Data Latches

D

Monotonic Over the Entire A/D Conversion
Range

D

Segmented High-Order Bits Ensure
Low-Glitch Output

D

Interchangeable With Analog Devices
AD7524, PMI PM-7524, and Micro Power
Systems MP7524

D

Fast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320

D

CMOS Technology

KEY PERFORMANCE SPECIFICATIONS

Resolution
Linearity error
Power dissipation at VDD = 5 V
Setting time
Propagation delay time

8 Bits

1/2 LSB Max

5 mW Max

100 ns Max

80 ns Max

description

The TLC7524C, TLC7524E, and TLC7524I are
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
microprocessors.

The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory . Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2 LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5 mW typically.

Featuring operation from a 5-V to 15-V single supply, these devices interface easily to most microprocessor
buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.

The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation
from –25°C to 85°C. The TLC7524E is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

PLASTIC DIP

(D)

PLASTIC CHIP CARRIER

(FN)

PLASTIC DIP

(N)

SMALL OUTLINE

(PW)

0°C to 70°C TLC7524CD TLC7524CFN TLC7524CN TLC7524CPW
–25°C to 85°C TLC7524ID TLC7524IFN TLC7524IN TLC7524IPW
–40°C to 85°C TLC7524ED TLC7524EFN TLC7524EN –

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

OUT1
OUT2

GND

DB7
DB6
DB5
DB4
DB3

R

FB

REF
V

DD

WR
CS
DB0
DB1
DB2

3212019

910111213

4
5
6
7
8

18
17
16
15
14

V

DD

WR
NC
CS
DB0

GND

DB7

NC
DB6
DB5

FN PACKAGE

(TOP VIEW)

OUT2

OUT1

NC

DB2

DB1

REF

DB4

DB3

NC

NC–No internal connection

R

FB

D, N, OR PW PACKAGE

(TOP VIEW)

TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Data Inputs

Data Latches

13

WR

12

CS

REF

15

11

DB0

(LSB)

6

DB5

5

DB6

4

DB7

(MSB)

GND

3

OUT2

2

OUT1

1

R

FB

16

R

RRR

2R

2R

S-8

2R

S-3

2R

S-2

S-1

2R

Terminal numbers shown are for the D or N package.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD –0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range, V

I

–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage, V

ref

±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak digital input current, I

I

10 µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLC7524C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC7524I –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC7524E –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

C

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . .

TLC7524C, TLC7524E, TLC7524I

8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

VDD = 5 V VDD = 15 V

MIN NOM MAX MIN NOM MAX

UNIT

Supply voltage, V

DD

4.75 5 5.25 14.5 15 15.5 V

Reference voltage, V

ref

±10 ±10 V

High-level input voltage, V

IH

2.4 13.5 V

Low-level input voltage, V

IL

0.8 1.5 V

CS setup time, t

su(CS)

40 40 ns

CS hold time, t

h(CS)

0 0 ns

Data bus input setup time, t

su(D)

25 25 ns

Data bus input hold time, t

h(D)

10 10 ns

Pulse duration, WR low, t

w(WR)

40 40 ns

TLC7524C 0 70 0 70

Operating free-air temperature, T

A

TLC7524I –25 85 –25 85

°C

TLC7524E –40 85 –40 85

electrical characteristics over recommended operating free-air temperature range, V

ref

= ±10 V,

OUT1 and OUT2 at GND (unless otherwise noted)

VDD = 5 V VDD = 15 V

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

I

IH

High-level input current VI = V

DD

10 10 µA

I

IL

Low-level input current VI = 0 –10 –10 µA

Output leakage

OUT1

DB0–DB7 at 0 V ,
V

ref

= ±10 V

WR, CS at 0 V,

±400 ±200

I

Ikg

g

current

OUT2

DB0–DB7 at VDD,
V

ref

= ±10 V

WR, CS at 0 V,

±400 ±200

nA

pp

Quiescent DB0–DB7 at VIHmin or VILmax 1 2 mA

IDDSupply current

Standby DB0–DB7 at 0 V or V

DD

500 500 µA

k

SVS

Supply voltage sensitivity,
∆gain/∆V

DD

∆VDD = ±10% 0.01 0.16 0.005 0.04 %FSR/%

C

i

Input capacitance,
DB0–DB7, WR

, CS

VI = 0 5 5 pF

OUT1

30 30

p

p

OUT2

DB0–DB7 at 0 V

,

WR, CS at 0 V

120 120

p

CoOutput capacitance

OUT1

120 120

pF

OUT2

DB0–DB7 at V

DD

,

WR, CS at 0 V

30 30

Reference input impedance
(REF to GND)

5 20 5 20 kΩ

TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range, V

ref

= ±10 V,

OUT1 and OUT2 at GND (unless otherwise noted)

VDD = 5 V VDD = 15 V

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN

TYP

MAX

UNIT

Linearity error ±0.5 ±0.5 LSB
Gain error See Note 1 ±2.5 ±2.5 LSB
Settling time (to 1/2 LSB) See Note 2 100 100 ns
Propagation delay from digital input

to 90% of final analog output current

See Note 2 80 80 ns

Feedthrough at OUT1 or OUT2

Vref = ±10 V (100-kHz sinewave)
WR

and CS at 0 V, DB0–DB7 at 0 V

0.5 0.5 %FSR

Temperature coefficient of gain TA = 25°C to MAX ±0.004 ±0.001 %FSR/°C

NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = V

ref

– 1 LSB.

2. OUT1 load = 100 Ω, C

ext

= 13 pF, WR

at 0 V, CS at 0 V, DB0 – DB7 at 0 V to VDD or VDD to 0 V.

operating sequence

DB0–DB7

WR

CS

t

h(D)

t

su(D)

t

w(WR)

t

h(CS)

t

su(CS)

TLC7524C, TLC7524E, TLC7524I

8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

voltage-mode operation

It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.

R

10

REF (Analog Output Voltage)

OUT2

OUT1 (Fixed Input Voltage)

R

RR

2R2R2R2R

Figure 1. Voltage Mode Operation

The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:

V

O

= VI (D/256)

where

V

O

= analog output voltage

V

I

= fixed input voltage

D = digital input code converted to decimal

In voltage-mode operation, these devices meet the following specification:

PARAMETER TEST CONDITIONS MIN MAX UNIT

Linearity error at REF VDD = 5 V, OUT1 = 2.5 V, OUT2 at GND, TA = 25°C 1 LSB

TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.

The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, I

ref

, is switched to OUT2. The current source I/256 represents the constant current flowing through the

termination resistor of the R-2R ladder, while the current source I

Ikg

represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, I

ref

would

be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS

and WR control

signals. When CS

and WR are both low, analog output on these devices responds to the data activity on the
DB0–DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS

signal or WR signal goes high, the data on the DB0–DB7 inputs are latched

until the CS

and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state

of the WR

signal.

These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. T able 1 and T able 2 summarize input
coding for unipolar and bipolar operation respectively.

I

ref

REF OUT2

OUT1

R

FB

R

120 pF

30 pF

I

Ikg

I/256

I

Ikg

Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low

TLC7524C, TLC7524E, TLC7524I

8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

+

–

Output

RA = 2 kΩ

(see Note A)

WR

CS

DB0–DB7

V

ref

C (see Note B)

R

B

V

DD

GND

OUT2

OUT1

R

FB

NOTES: A. RA and RB used only if gain adjustment is required.

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent

ringing or oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

Output

20 kΩ

5 kΩ

10 kΩ

20 kΩ

–

+

+

–

R

FB

OUT1

OUT2

GND

V

DD

R

B

C (see Note B)

V

ref

DB0–DB7

CS

WR

(see Note A)

RA = 2 kΩ

NOTES: A. RA and RB used only if gain adjustment is required.

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code

DIGITAL INPUT

(see Note 3)

ANALOG OUTPUT

DIGITAL INPUT

(see Note 4)

ANALOG OUTPUT

MSB LSB MSB LSB

1 1 1 1 1 1 1 1 –V

ref

(255/256) 1 1 1 1 1 1 1 1 V

ref

(127/128)

1 0 0 0 0 0 0 1 –V

ref

(129/256) 1 0 0 0 0 0 0 1 V

ref

(1/128)

1 0 0 0 0 0 0 0 –V

ref

(128/256) = –V

ref

/2 1 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 –V

ref

(127/256) 0 1 1 1 1 1 1 1 –V

ref

(1/128)

0 0 0 0 0 0 0 1 –V

ref

(1/256) 0 0 0 0 0 0 0 1 –V

ref

(127/128)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 –V

ref

NOTE 3: LSB = 1/256 (V

ref

) NOTE 4: LSB = 1/128 (V

ref

)

TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

microprocessor interfaces

A0–A15

Z–80A

D0–D7

WR

IORQ

Address Bus

Decode

Logic

TLC7524

OUT2

OUT1

CS

WR

DB0–DB7

Data Bus

Figure 5. TLC7524 – Z-80A Interface

Data Bus

DB0–DB7

WR

CS

OUT1
OUT2

TLC7524

Decode

Logic

Address Bus

VMA

φ2

D0–D7

6800

A0–A15

Figure 6. TLC7524 – 6800 Interface

TLC7524C, TLC7524E, TLC7524I

8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

microprocessor interfaces (continued)

8-Bit

Latch

AD0–AD7

8051

A8–A15

ALE

Adress/Data Bus

Decode

Logic

TLC7524

OUT2

OUT1

CS

WR

DB0–DB7

Address Bus

WR

Figure 7. TLC7524 – 8051 Interface

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1998, Texas Instruments Incorporated