Texas Instruments TLC7225CDW, TLC7225IDWR, TLC7225IDW, TLC7225CDWR Datasheet

TLC7225C, TLC7225I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

OUTB

OUTA

V

SS

REFB

REFA

AGND

DGND

LDAC

DB6
DB5
DB4

DW PACKAGE

(TOP VIEW)

1

24

2

23

3

22

4

21

5

20

6

19

7

18

8

17

9

16

10

15

11

14

12

13

OUTC
OUTD
V

DD

REFC
REFD
A0
A1
WR
DB0 (LSB)
DB1
DB2
DB3

D

Four 8-Bit D/A Converters With Individual
References

D

Direct Bipolar Operation Without an
External Level-Shift Amplifier

D

Microprocessor Compatible

D

TTL/CMOS Compatible

D

Single Supply Operation Possible

D

Simultaneous Update Facility

D

Binary Input Coding

applications

D

Process Control

D

Automatic Test Equipment

D

Automatic Calibration of Large System
Parameters e.g., Gain/Offset

(MSB) DB7

description

The TLC7225 consists of four 8-bit voltage-output digital-to-analog converters (DACs), with output buffer
amplifiers and interface logic with double register-buffering.

Separate on-chip latches are provided for each of the DACs. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS-compatible (5 V) input port. Control inputs A0 and A1 determine which DAC
is loaded when WR
converters. The double register buffering allows simultaneous update of all four outputs under control of LDAC
All logic inputs are TTL- and CMOS-level compatible and the control logic is speed compatible with most 8-bit
microprocessors. Each DAC includes an output buffer amplifier capable of driving up to 5 mA of output current.

goes low. Only the data held in the DAC registers determines the analog outputs of the

.

The TLC7225 performance is specified for input reference voltages from 2 V to V

– 4 V with dual supplies.

DD

The voltage-mode configuration of the DACs allow the TLC7225 to be operated from a single power-supply rail
at a reference of 10 V.

The TLC7225 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7225 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.

Combining four DACs, four operational amplifiers, and interface logic into a small, 0.3-inch wide, 24-terminal
SOIC allows significant reduction in board space requirements and offers increased reliability in systems using
multiple converters. The pinout optimizes board layout with all of the analog inputs and outputs at one end of
the package and all of the digital inputs at the other.

The TLC7225C is characterized for operation from 0°C to 70°C. The TLC7225I is characterized for operation
from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC7225C, TLC7225I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

AVAILABLE OPTIONS

PACKAGED DEVICES

SMALL OUTLINE

(DW)

DAC

Latch

A

DAC

Latch

B

DAC

Latch

C

DAC

Latch

D

DAC

DAC

DAC

DAC

A

B

C

D

functional block diagram

5

REFA

4

REFB

REFC

REFD

LDAC

WR

A0
A1

9–16
21

20

8
17

19
18

DB0–DB7

8

Control

Logic

T

A

0°C to 70°C TLC7225CDW

–40°C to 85°C TLC7225IDW

Input

8

Latch

A

Input

8

Latch

B

Input

8

Latch

C

Input

8

Latch

D

_

+

_
+

_

+

_
+

24

23

2

1

OUTA

OUTB

OUTC

OUTD

schematic of outputs

EQUIVALENT ANALOG OUTPUT

V

DD

100 µA

V

SS

Output

450 µA

2

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I/O

DESCRIPTION

TLC7225C, TLC7225I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

Terminal Functions

TERMINAL

NAME NO.

AGND 6 Analog ground
A0, A1 18, 19 I DAC select inputs
DGND 7 Digital ground
DB0 – DB7 9 – 16 I Digital DAC data inputs
LDAC 8 Load DAC. A high level simultaneously loads all four DAC registers. DAC registers are transparent when LDAC

is low.
OUTA 2 O DACA output
OUTB 1 O DACB output
OUTC 24 O DACC output
OUTD 23 O DACD output
REFA 5 I Voltage reference input to DACA
REFB 4 I Voltage reference input to DACB
REFC 21 I V oltage reference input to DACC
REFD 20 I V oltage reference input to DACD
V

DD

V

SS

WR 17 I Write input selects DAC transparency or latch mode

22 Positive supply voltage

3 Negative supply voltage

absolute maximum ratings over operating free-air temperature range (unless otherwise note)

Supply voltage range, V
Supply voltage range, V

Voltage range between AGND and DGND –0.3 V to V
Input voltage range, V
Reference voltage range, V
Output voltage range, V
Continuous total power dissipation at (or below) T

: to AGND or DGND –0.3 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

to V

–0.3 V to 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SS

: to AGND or DGND –7 V to V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(to DGND) –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(to AGND) –0.3 V to V

ref

(to AGND) (see Note 1) VSS to V

O

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 25°C (see Note 2) 500 mW. . . . . . . . . . . . . . . . . . . . . . .

A

†

DD
DD

DD
DD

Operating free-air temperature range: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically sh ort circuit

current to AGND is 50 mA.

2. For operation above TA = 75°C derate linearly at the rate of 2.0 mW/°C.

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3

TLC7225C, TLC7225I

Operating free-air temperature, T

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

recommended operating conditions

Supply voltage, V
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Reference voltage, V
Load resistance, R

p

timing requirements (see Figure 1)

t

su(AW)

t

su(DW)

t

h(AW)

t

h(DW)

t

w1

t

w2

DD
SS

IH

IL

ref

L

p

PARAMETER TEST CONDITIONS MIN MAX UNIT

Setup time, address valid before WR↓ 0 ns
Setup time, data valid before WR↑
Hold time, address valid after WR↑
Hold time, data valid after WR↑
Pulse duration, WR low
Pulse duration, LDAC low

C suffix 0 70 °C

A

I suffix –40 85 °C

VDD = 11.4 V to 16.5 V, VSS = 0 or –5 V 45 ns
VDD = 11.4 V to 16.5 V, VSS = 0 or –5 V 0 ns
VDD = 11.4 V to 16.5 V, VSS = 0 or –5 V 10 ns
VDD = 11.4 V to 16.5 V, VSS = 0 or –5 V 50 ns
VDD = 11.4 V to 16.5 V, VSS = 0 or –5 V 50 ns

MIN MAX UNIT

11.4 16.5 V

–5.5 0 V

2 V

0.8 V
2 VDD–4 V
2 kΩ

4

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CiIn ut ca acitance, REFA, REFB, REFC, REFD

V

10 V

sine wave at 10 kH

TLC7225C, TLC7225I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

electrical characteristics over recommended operating free-air temperature range

reference inputs (all supply ranges)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

r

i

dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless
otherwise noted)

I

I

I

DD

I

SS

C

i

Input resistance, REFA, REFB, REFC, REFD 1.5 4 kΩ

p

p

Channel-to-channel isolation
ac feedthrough

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input current, digital VI = 0 or V
Supply current, V
Supply current, V
Power supply sensitivity ∆VDD = ±5% 0.01 %/%
Input capacitance Digital inputs 8 pF

DD
SS

DAC loaded with all 1s 300 pF
DAC loaded with all 0s 65 pF

60 dB

=

ref

VI = VIL or VIH, No load 10 16 mA
VI = VIL or VIH, No load 4 10 mA

pp

DD

z

70 dB

±1 µA

single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I
I

C

I
DD

i

Input current, digital VI = 0 or V
Supply current, V
Power supply sensitivity ∆VDD = ±5% 0.01 %/%
Input capacitance Digital inputs 8 pF

DD

VI = VIL or VIH, No load 5 13 mA

DD

(A, B, C, D) = 10 V

ref

±1 µA

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5

TLC7225C, TLC7225I

tsSettling time to 1/2 LSB

V

10 V

s

V

V

V

tsSettling time to 1/2 LSB

s

g

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS109A – OCTOBER 1996 – REVISED APRIL 1997

operating characteristics over recommended operating free-air temperature range

dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Slew rate 2.5 V/µs

Positive full scale

Negative full scale
Resolution 8 Bits
Total unadjusted error VDD = 15 V ±5%, V
Integral nonlinearity (INL) VDD = 15 V ±5%, V
Differential nonlinearity (DNL) VDD = 15 V ±5%, V

E
E

Full-scale error VDD = 15 V ±5%, V

FS

Gain error VDD = 15 V ±5%, V

G

Temperature coefficient
of gain

Zero-code error ±20 ±80 mV
Digital crosstalk or feedthrough glitch

impulse area

Full-scale error

Zero-code error

ref(A, B, C, D)

= 14 V to 16.5 V,

DD

V

ref(A, B, C, D)

=

ref(A, B, C, D)
ref(A, B, C, D)
ref(A, B, C, D)
ref(A, B, C, D)
ref(A, B, C, D)

ref(A, B, C, D)

= 0 50 nV–s

= 10 V ±2 LSB
= 10 V ±1 LSB
= 10 V ±1 LSB
= 10 V ±2 LSB
= 10 V ±0.25 LSB

= 10

±20 ppm/°C
±50 µV/°C

5

µ

7

single power supply , VDD = 14.25 V to 15.75 V , VSS = AGND = DGND = 0 V , V
noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Slew rate 2 V/µs

Positive full scale 5

Negative full scale 20
Resolution 8 Bits
Total unadjusted error ±2 LSB

E

Full-scale error ±2 LSB

FS

Temperature coefficient of gain

Differential nonlinearity error (DNL) ±1 LSB
Digital crosstalk or feedthrough glitch impulse area 50 nV–s

Full-scale error

Zero-code error ±50 µV/°C

VDD = 14 V to 16.5 V,
V

ref(A, B, C, D)

ref(A, B, C, D)

= 10 V

= 10 V (unless otherwise

µ

±20 ppm/°C

6

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