Texas Instruments TIBPAL16R8-30MWB, TIBPAL16R8-30MJB, TIBPAL16R8-30MJ, TIBPAL16R8-30MFKB, TIBPAL16R8-25CN Datasheet

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C

TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

High-Performance Operation:
Propagation Delay
C Suffix . . . 25 ns Max
M Suffix . . . 30 ns Max

D

Functionally Equivalent, but Faster Than
PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A

D

Power-Up Clear on Registered Devices (All
Register Outputs Are Set High, but Voltage
Levels at the Output Pins Go Low)

D

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

D

Dependable Texas Instruments Quality and
Reliability

DEVICE

I

INPUTS

3-STATE

O

OUTPUTS

REGISTERED

Q

OUTPUTS

I/O

PORTS

PAL16L8 10 2 0 6
PAL16R4 8 0

4 (3-state

buffers)

4

PAL16R6 8 0

6 (3-state

buffers)

2

PAL16R8 8 0

8 (3-state

buffers)

0

description

These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMP ACT circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for further
reduction in board space.

The TIBP AL16’ C series is characterized from 0°C
to 75°C. The TIBP AL16’ M series is characterized
for operation over the full military temperature
range of –55°C to 125°C.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments.
PAL is a registered trademark of Advanced Micro Devices Inc.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

I
I
I
I
I
I
I
I
I

GND

V

CC

O
I/O
I/O
I/O
I/O
I/O
I/O
O
I

TIBPAL16L8’

C SUFFIX ...J OR N PACKAGE

M SUFFIX ...J OR W PACKAGE

(TOP VIEW)

4
5
6
7
8

18
17
16
15
14

I/O
I/O
I/O
I/O
I/O

I
I
I
I
I

TIBPAL16L8’

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

I

I

O

I/O

O

I

GND

I

V

CC

3212019

910111213

TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 FEBRUARY 1984 – REVISED APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

CLK

I
I
I
I
I
I
I
I

GND

V

CC

I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE

TIBPAL16R4’

C SUFFIX ...J OR N PACKAGE

M SUFFIX ...J OR W PACKAGE

(TOP VIEW)

CLK

I
I
I
I
I
I
I
I

GND

V

CC

I/O
Q
Q
Q
Q
Q
Q
I/O
OE

TIBPAL16R6’

C SUFFIX ...J OR N PACKAGE

M SUFFIX ...J OR W PACKAGE

(TOP VIEW)

CLK

I
I
I
I
I
I
I
I

GND

V

CC

Q
Q
Q
Q
Q
Q
Q
Q
OE

TIBPAL16R8’

C SUFFIX ...J OR N PACKAGE

M SUFFIX ...J OR W PACKAGE

(TOP VIEW)

I

I

CLK

I/O

I/O

I/O

I

GND

V

CC

OE

I/O
Q
Q
Q
Q

I
I
I
I
I

TIBPAL16R4’

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

I

CLK

I/O

Q

I/O

I

GND

V

CC

Q
Q
Q
Q
Q

I
I
I
I
I

OE

TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

I

CLK

Q

Q

Q

I

GND

V

CC

OE

Q
Q
Q
Q
Q

I
I
I
I
I

TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

4
5
6
7
8

18
17
16
15
14

3212019

910111213

4
5
6
7
8

18
17
16
15
14

3212019

910111213

4
5
6
7
8

18
17
16
15
14

3212019

910111213

TIBPAL16L8-25C, TIBPAL16R4-25C

TIBPAL16L8-30M, TIBPAL16R4-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagrams (positive logic)

denotes fused inputs

TIBPAL16L8 ’

TIBPAL16R4’

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I

EN

≥ 1

&

32 × 64

10 16

166

7

7

7

7

7

7

7

7

6

Q

I/O

I/O

I/O

I/O

I

EN

816

164

7

7

7

8

8

8

7

4

≥ 1

≥ 1

8

Q

Q

Q

4

1D

I = 1

2

CLK

C1

EN 2

OE

4

16 ×

16 ×

&

32 × 64

TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagrams (positive logic)

denotes fused inputs

TIBPAL16R6’

TIBPAL16R8’

Q

I/O

I/O

I

EN

816

162

7

8

8

8

7

2

≥ 1

≥ 1

8

Q

Q

Q

6

1D

I = 1

2

CLK

C1

EN 2

OE

6

8

Q

8

Q

Q

I

816

168

8

8

8

8

8

Q

Q

Q

1D

I = 1

2

CLK

C1

EN 2

8

Q

8

Q

≥ 1

OE

8

Q

8

Q

16 ×

16 ×

&

32 × 64

&

32 × 64

TIBPAL16L8-25C

TIBPAL16L8-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I

2

I

3

4

I

5

I

6

I

7

I

8

I

9

O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

O

12

I

11

Increment

I

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First

Fuse

Numbers

I

TIBPAL16R4-25C
TIBPAL16R4-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

2016

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I/O

19

I/O

18

Q

17

Q

16

Q

15

Q

14

I/O

13

I/O

12

11

Increment

CLK

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984

First

Fuse

Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

TIBPAL16R6-25C

TIBPAL16R6-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

Fuse number = First fuse number + Increment

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I/O

19

Q

17

Q

16

Q

15

Q

14

I/O

12

11

Increment

CLK

1

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First

Fuse

Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

Q

18

C1

1D

I = 1

Q

13

C1

1D

I = 1

TIBPAL16R8-25C
TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

Q

17

Q

16

Q

15

Q

14

Increment

CLK

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First

Fuse

Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

Q

18

C1

1D

I = 1

Q

13

C1

1D

I = 1

Q

19

C1

1D

I = 1

Q

12

C1

1D

I = 1

11

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.75 5 5.25 V

V

IH

High-level input voltage 2 5.5 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –3.2 mA

I

OL

Low-level output current 24 mA

f

clock

Clock frequency 0 30 MHz

High 10

twPulse duration, clock (see Note 2)

Low 15

ns

t

su

Setup time, input or feedback before clock↑ 20 ns

t

h

Hold time, input or feedback after clock↑ 0 ns

T

A

Operating free-air temperature 0 25 75 °C

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f

clock

. The minimum pulse durations specified are

for clock high or low only, but not for both simultaneously.

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.75 V , II = –18 mA –1.5 V

V

OH

VCC = 4.75 V , IOH = –3.2 mA 2.4 3.3 V

V

OL

VCC = 4.75 V , IOL = 24 mA 0.35 0.5 V

Outputs

20

I

OZH

I/O ports

V

CC

= 5.25 V,

V

O

= 2.7

V

100

µ

A

Outputs

–20

I

OZL

I/O ports

V

CC

= 5.25 V,

V

O

= 0.4

V

–250

µ

A

I

I

VCC = 5.25 V , VI = 5.5 V 0.1 mA

I

IH

VCC = 5.25 V , VI = 2.7 V 20 µA

I

IL

VCC = 5.25 V , VI = 0.4 V –0.25 mA

I

O

‡

VCC = 5.25 V , VO = 2.25 V –30 –125 mA

I

CC

VCC = 5.25 V , VI = 0, Outputs open 75 100 mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, IOS.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS MIN TYP†MAX UNIT

f

max

30 MHz

t

pd

I, I/O O, I/O 15 25 ns

t

pd

CLK↑ Q

R1 = 500 Ω

,

10 15 ns

t

en

OE↓ Q

R1 500 Ω,

R2 = 500 Ω,

15 20 ns

t

dis

OE↑ Q

See Figure 3

10 20 ns

t

en

I, I/O O, I/O 14 25 ns

t

dis

I, I/O O, I/O 13 25 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 5.5 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –2 mA

I

OL

Low-level output current 12 mA

f

clock

Clock frequency 0 25 MHz

High 15

twPulse duration, clock (see Note 2)

Low 20

ns

t

su

Setup time, input or feedback before clock↑ 25 ns

t

h

Hold time, input or feedback after clock↑ 0 ns

T

A

Operating free-air temperature –55 25 125 °C

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f

clock

. The minimum pulse durations specified are

for clock high or low only, but not for both simultaneously.

TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.5 V

V

OH

VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V

V

OL

VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V

Outputs

20

I

OZH

I/O ports

V

CC

= 5.5

V

V

O

= 2.7

V

100

µ

A

Outputs

–20

I

OZL

I/O ports

V

CC

= 5.5 V,

V

O

= 0.4

V

–250

µ

A

Pin 1, 11

0.2

I

I

All others

V

CC

= 5.5 V,

V

I

= 5.5

V

0.1

mA

Pin 1, 11 50

I

IH

I/O ports

VCC = 5.5 V, VI = 2.7 V

100

µA
All others 20
I/O ports

–0.25

I

IL

All others

V

CC

= 5.5 V,

V

I

= 0.4

V

–0.2

mA

I

OS

‡

VCC = 5.5 V, VO = 0.5 V –30 –250 mA

I

CC

VCC = 5.5 V, VI = 0, Outputs open 75 105 mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to
avoid test-equipment degradation.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS MIN TYP†MAX UNIT

f

max

25 MHz

t

pd

I, I/O O, I/O

15 30 ns

t

pd

CLK↑ Q

R1 = 390 Ω

,

10 20 ns

t

en

OE↓ Q

R1 390 Ω,

R2 = 750 Ω,

15 25 ns

t

dis

OE↑ Q

See Figure 4

10 25 ns

t

en

I, I/O O, I/O 14 30 ns

t

dis

I, I/O O, I/O 13 30 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C

TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI
distributor, by calling Texas Instruments at [phone], or by visiting the TI Semiconductor Home Page
at www.ti.com/sc.

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.

Step 1. With V

CC

at 5 V and Pin 1 at VIL, raise Pin 11 to V

IHH

.

Step 2. Apply either V

IL

or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the

voltage level at the output pin.

t

d

t

su

t

w

t

d

V

IHH

V

IL

V

IL

V

OL

V

OH

V

IH

Pin 11

Pin 1

Registered I/O

Input Output

V

IH

V

IL

NOTE 3: td = tsu = th = 100 ns to 1000 ns V

IHH

= 10.25 V to 10.75 V

Figure 1. Preload Waveforms

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

power-up reset (see Figure 2)

Following power up, all registers are set high. This feature provides extra flexibility to the system designer and
is especially valuable in simplifying state-machine initialization. T o ensure a valid power-up reset, it is important
that the rise of V

CC

be monotonic. Following power-up reset, a low-to-high clock transition must not occur until

all applicable input and feedback setup times are met.

1.5 V

t

su

‡

t

pd

†

t

w

V

IL

V

IH

5 V

V

CC

Active-Low

Registered Output

CLK

4 V

V

OH

V

OL

1.5 V

(600 ns TYP, 1000 ns MAX)

1.5 V

†

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡

This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C

LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

dis

t

dis

t

su

S1

From Output

Under Test

Test
Point

R2

C

L

(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS

t

h

Timing

Input

Data

Input

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

t

pd

t

pd

t

pd

t

pd

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

OH

V

OH

V

OL

V

OL

t

w

High-Level

Pulse

Low-Level

Pulse

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

3.5 V

0.3 V

≈3.5 V

V

OL

V

OH

VOH – 0.3 V
≈0 V

t

en

t

en

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATIONS

R1

3.5 V

0.3 V

VOL + 0.3 V

7 V

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

dis

.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.

When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.

1.3 V

1.3 V 1.3 V

3.5 V

0.3 V

3.5 V

0.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

3.5 V

0.3 V

3.5 V

0.3 V

1.3 V 1.3 V

1.3 V

1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

Figure 3. Load Circuit and Voltage Waveforms

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

dis

t

dis

t

su

S1

From Output

Under Test

Test
Point

R2

C

L

(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS

t

h

Timing

Input

Data

Input

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

t

pd

t

pd

t

pd

t

pd

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

OH

V

OH

V

OL

V

OL

t

w

High-Level

Pulse

Low-Level

Pulse

Output

Control
(low-level
enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

3 V

0

≈3.3 V

V

OL

V

OH

VOH – 0.5 V
≈0 V

t

en

t

en

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATIONS

R1

3 V

0

VOL + 0.5 V

5 V

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

dis

.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.

1.5 V

1.5 V 1.5 V

3 V

0

3 V

0

1.5 V 1.5 V

1.5 V 1.5 V

3 V

0

3 V

0

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

Figure 4. Load Circuit and Voltage Waveforms

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