Texas Instruments THS1031 User Manual

T

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

D

10-Bit Resolution, 30 MSPS
Analog-to-Digital Converter

D

Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital

Clamp

– Differential

D

Built-In Programmable Gain Amplifier
(PGA)

D

Differential Nonlinearity: ±0.3 LSB

D

Signal-to-Noise: 56 dB

D

Spurious Free Dynamic Range: 60 dB

D

Adjustable Internal Voltage Reference

D

Straight Binary/2s Complement Output

D

Out-of-Range Indicator

D

Power-Down Mode

28-PIN TSSOP/SOIC PACKAGE

AGND

DV

DGND

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

OVR

(TOP VIEW)

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

AV

DD

AIN
VREF
REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK

description

The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The
analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier
whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital
clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small
signals. The THS1031 provides a wide selection of voltage references to match the user’s design requirements.
For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the application. The out-of-range output indicates any
out-of-range condition in THS1031’s input signal. The format of digital output can be coded in either unsigned
binary or 2s complement.

The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video applications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems.

The THS1031C is characterized for operation from 0°C to 70°C, while the THS1031I is characterized for
operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

Copyright  2002, Texas Instruments Incorporated

0°C to 70°C THS1031CPW THS1031CDW

–40°C to 85°C THS1031IPW THS1031IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

A

28-TSSOP (PW) 28-SOIC (DW)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

functional block diagram

CLAMPIN

CLAMP

AIN

REFTS

REFBS

MODE

REFTF

REFBF

Clamp

Amplifier

Sample

A

Reference

B

and

Hold

Internal

Buffer

3

PGA

DAC

Power Down

10-Bit

Clamp

10

DAC

Control

Register

Core

ADC

Output

Buffer

Timing
Circuit

WR

10

I/O(0–9)

OVR
OE

VBG

ORG

GND

CLKVREFREFSENSE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

CMOS ANALOG-TO-DIGITAL CONVERTER

Terminal Functions

TERMINAL

NAME NO.

AGND 1 I Analog ground
AIN 27 I Analog input
AV

DD

CLAMP 19 I High to enable clamp mode, low to disable clamp mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLK 15 I Clock input
DGND 14 I Digital ground
DV

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

MODE 23 I Mode input
OE 16 I High to 3-state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFBS 25 I Reference bottom sense
REFBF 24 I Reference bottom decoupling
REFSENSE 18 I Reference sense
REFTF 22 I Reference top decoupling
REFTS 21 I Reference top sense
VREF 26 I/O Internal and external reference
WR 17 I Write strobe

28 I Analog supply

2 I Digital driver supply
3

4
5
6
7
8

9
10
11
12

Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4

I/O

Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

THS1031

High-level input voltage, V

V

Low-level in ut voltage, V

IL

V

Supply voltage

Maximum sampling rate

MSPS

V

3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range: AV

to AGND, DVDD to DGND –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

†

AGND to DGND –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AV

to DVDD –6.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode input voltage range, MODE to AGND –0.3 V to AV
Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND –0.3 V to AV
Analog input voltage range, AIN to AGND –0.3 V to AV
Reference input voltage range, VREF to AGND –0.3 V to AV
Reference output voltage range, VREF to AGND –0.3 V to AV
Clock input voltage range, CLK to AGND –0.3 V to AV
Digital input voltage range, digital input to DGND –0.3 V to DV
Digital output voltage range, digital output to DGND –0.3 V to DV
Operating junction temperature range, T
Storage temperature range, T

DD

0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

J

DD
DD
DD
DD
DD
DD
DD
DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM MAX UNIT

p

p

Clock input 0.8 × AV

IH

All other inputs 0.8 × DV
Clock input 0.2 × AV

All other inputs 0.2 × DV

analog inputs

Analog input voltage, V
Reference input voltage, V
Clamp input voltage, V

(PGA = 1x, top, bottom, or external reference mode) REFBS REFTS V

I(AIN)

I(VREF)

I(CLAMPIN)

power supply

AV

pp

p

= 30

DV

DD

DD

REFTS, REFBS reference voltages (MODE = AVDD)

PARAMETER MIN NOM MAX UNIT

REFTS Reference input voltage (top) 1 AV
REFBS Reference input voltage (bottom) 0 AVDD–1 V

Differential input voltage (REFTS – REFBS) 1 2 V
Switched input capacitance on REFTS or REFBS 0.6 pF

DD
DD

DD
DD

MIN NOM MAX UNIT

1 2 V

0.1 AVDD–0.1 V

MIN NOM MAX UNIT

3 3.3 5.5
3 3.3 5.5

DD

V

sampling rate and resolution

f

Sample frequency 5 30 MHz

s

Resolution 10 Bits

4

PARAMETER MIN NOM MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Input common mode voltage (REFTF

REFBF)/2

V

VREF

V

V

REFTF voltage (MODE

AVDD)

VREF

V

V

VREF

V

V

REFBF voltage (MODE

AVDD)

VREF

V

V

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,

= 30 MSPS/50% duty cycle, MODE = A VDD, 2-V input span from 0.5 V to 2.5 V , external reference,

f

s

PGA = 1X, T

analog inputs

V

I(AIN)

C

I

BW Full power bandwidth (–3 dB) 150 MHz
I

lkg

VREF reference voltages

REFTF, REFBF reference voltages

Differential input voltage (REFTF – REFBF) 1 2 V

p

Input resistance between REFTF and REFBF 680 Ω

= T

A

Analog input voltage REFBS REFTS V
Switched sampling input capacitance 1.2 pF

DC leakage current (input = ± FS) 100 µA

Internal 1-V reference voltage (REFSENSE = VREF) 0.95 1 1.05 V
Internal 2-V reference voltage (REFSENSE = AVSS) 1.90 2 2.10 V
External reference voltage (REFSENSE = AVDD) 1 2 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2) 18 kΩ

to T

min

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

=

=

(unless otherwise noted)

max

PARAMETER MIN TYP MAX UNIT

PARAMETER MIN TYP MAX UNIT

+

= 1

= 2

= 1

= 2

AVDD = 3 V 1.3 1.5 1.7
AVDD = 5 V 2 2.5 3
AVDD = 3 V 2
AVDD = 5 V 3
AVDD = 3 V 2.5
AVDD = 5 V 3.5
AVDD = 3 V 1
AVDD = 5 V 2
AVDD = 3 V 0.5
AVDD = 5 V 1.5

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5

THS1031

ENOB

Effective number of bits

Bits

SFDR

Spurious free dynamic range

dB

THD

Total harmonic distortion

dB

SNR

Signal-to-noise ratio

dB

SINAD

Signal-to-noise and distortion

dB

3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,

= 30 MSPS/50% duty cycle, MODE = A VDD, 2-V input span from 0.5 V to 2.5 V , external reference,

f

s

PGA = 1X, T

dc accuracy

INL Integral nonlinearity (see Note 1) ±1 ±2 LSB
DNL Differential nonlinearity (see Note 2) ±0.3 ±1 LSB

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure

3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

4. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

= T

A

Offset error (see Note 3) 0.4 2 %FSR
Gain error (see Note 4) 1.4 3.5 %FSR
Missing code No missing code assured

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level) ÷ (2 n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).

the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (1024).

min

to T

(unless otherwise noted) (continued)

max

PARAMETER MIN TYP MAX UNIT

dynamic performance (ADC and PGA)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

f = 3.5 MHz 8.2 9
f = 3.5 MHz, AVDD = 5 V 8.8
f = 15 MHz 7.7
f = 15 MHz, AVDD = 5 V 7.64
f = 3.5 MHz 55 60
f = 3.5 MHz, AVDD = 5 V 63
f = 15 MHz 48
f = 15 MHz, AVDD = 5 V 52.4
f = 3.5 MHz –58.2 –54.7
f = 3.5 MHz, AVDD = 5 V –68.7
f = 15 MHz –47
f = 15 MHz, AVDD = 5 V –51.9
f = 3.5 MHz 51.2 56
f = 3.5 MHz, AVDD = 5 V 55
f = 15 MHz 53
f = 15 MHz, AVDD = 5 V 49.3
f = 3.5 MHz 51.1 56
f = 3.5 MHz, AVDD = 5 V 55
f = 15 MHz 48.1
f = 15 MHz, AVDD = 5 V 47.7

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PDPower dissipation

mW

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,

= 30 MSPS/50% duty cycle, MODE = A VDD, 2-V input span from 0.5 V to 2.5 V , external reference,

f

s

PGA = 1X, T

PGA

Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.5 V/V
Gain error from nominal 3%
Number of control bits 3 Bits

clamp amplifier and clamp DAC

Resolution 10 Bits
DAC output range REFBF REFTF V
DAC differential nonlinearity –1 1 LSB
DAC integral nonlinearity ±1 LSB
Clamping analog output voltage range 0.1 AVDD–0.1 V
Clamping analog output voltage error –40 40 mV

A

= T

min

to T

(unless otherwise noted) (continued)

max

PARAMETER MIN TYP MAX UNIT

PARAMETER MIN TYP MAX UNIT

clock

t

c

t

w(CKH)

t

w(CKL)

t

d(o)

t

d(AP)

timing

t

d(DZ)

t

d(DEN)

t

d(OEW)

t

d(WOE)

t

w(WP)

t

su

t

h

Output disable to Hi-Z output, delay time 0 20 ns
Output enable to output valid, delay time 0 20 ns
Output disable to write enable, delay time 12 ns
Write disable to output enable, delay time 12 ns
Write pulse duration 15 ns
Input data setup time 5 ns
Input data hold time 5 ns

power supply

I

CC

P

D(STBY)

Operating supply current AVDD = 3 V, MODE = AGND 30.6 45 mA

Standby power AVDD = DVDD = 3 V, MODE = AGND 3 5 mW

PARAMETER MIN TYP MAX UNIT

Clock cycle 33 ns
Pulse duration, clock high 15 16.5 ns
Pulse duration, clock high 15 16.5 ns
Clock to data valid, delay time 25 ns
Pipeline latency 3 Cycles
Aperture delay time 4 ns

Aperture uncertainty (jitter) 2 ps

PARAMETER MIN TYP MAX UNIT

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

AVDD = DVDD = 3 V 94 135
AVDD = DVDD = 5 V 160

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7

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

OE

WE

I/O

NOTE A: All timing measurements are based on 50% of edge transition.

Analog Input

t

d(DZ)

Sample 1

See Note A

t

d(OEW)

Sample 2

t

c

t

w(WP)

t

h

t

su

Hi-Z Hi-Z

Input OutputOutput

Figure 1. Write Timing Diagram

Sample 3

Sample 4

t

d(WOE)

t

d(DEN)

Sample 5

t

t

(CKH)

Input Clock

Digital Output

NOTE A: All timing measurements are based on 50% of edge transition.

See

Note A

w(CKL)

Pipeline Latency

Figure 2. Digital Output Timing Diagram

t

d(o)

Sample 1 Sample 2

8

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

POWER DISSIPATION

vs

SAMPLING FREQUENCY

96

AVDD = DVDD = 3 V

94

fi = 3.5 MHz
TA = 25°C

92
90
88
86
84

Power Dissipation – mW

82

5 1015202530

fs – Sampling Frequency – MHz

Figure 3

EFFECTIVE NUMBER OF BITS

vs

TEMPERATURE

10.0
AVDD = DVDD = 3 V

9.5

fi = 3.5 MHz
fs = 30 MSPS

9.0

8.5

8.0

7.5

Effective Number of Bits

7

–40 –15 10 35 60 85

TA – Temperature – °C

Figure 4

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9

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

Effective Number of Bits

AVDD = DVDD = 3 V
fi = 3.5 MHz
TA = 25°C

7

5 1015202530

fs – Sampling Frequency – MSPS

vs

Figure 5

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

AVDD = 5 V,

8.0
DVDD = 3 V

7.5

Effective Number of Bits

fi = 3.5 MHz
TA = 25°C

7

5 1015202530

fs – Sampling Frequency – MSPS

Figure 6

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

10.00

9.50

9.00

8.50

SAMPLING FREQUENCY

8.00

7.50

Effective Number of Bits

7.00

AVDD = DVDD= 5 V,
fi = 3.5 MHz
TA = 25°C

5 1015202530

fs – Sampling Frequency – MSPS

Figure 7

DIFFERENTIAL NONLINEARITY

vs

INPUT CODE

1.0

0.8

AVDD = 3 V, DVDD = 3 V

0.6

fs = 30 MSPS

0.4

0.2

–0.0
–0.2
–0.4
–0.6
–0.8

–1

0 128 256 384 512 640 768 896 1024

DNL – Differential Nonlinearity – LSB

Input Code

Figure 8

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11

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

2.0

1.5

1.0

0.5

0.0

–0.5
–1.0
–1.5
–2.0

INL – Integral Nonlinearity – LSB

0 128 256 384 512 640 768 896 1024

vs

INPUT CODE

AVDD = 3 V
DVDD = 3 V
fs = 30 MSPS

Input Code

Figure 9

FFT – dB

FFT

vs

FREQUENCY

0

–20
–40
–60

–80
–100
–120
–140

0 200 400 600 800 1000 1200 1400 1600 1800 2000

0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15

f – Frequency – MHz

AVDD = 3 V
DVDD = 3 V
fi = 3.5 MHz,
–1 dBFS

Figure 10

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

The analog input AIN is sampled in the sample-and-hold unit, the output of which goes to a programmable gain
amplifier (PGA). The PGA feeds the ADC core, where the process of analog to digital conversion is performed
against ADC reference voltages, REFTF and REFBF.

THS1031

Connecting the MODE pin to one of three voltages, AGND, A V

or A VDD/2 sets up operating configurations.

DD

The three settings open or close internal switches to select one of the three basic methods of ADC reference
generation.

Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the
internal reference buffer (IRB) or may be fed from completely external sources. Where the reference buffer is
employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external
voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and
REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user .

The THS1031 offers a clamp function for dc restoration of ac-coupled signals. The clamp voltage may be set
digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input.

The ADC core drives out through output buffers to the I/O pins I/O0 to I/O9. The output buffers can be disabled
by the OE

pin. Control input data on I/O0 to I/O9 can then be written, by pulses on WR, to the control registers.
These registers control clamp operation, output format (unsigned binary or twos complement), the PGA gain
setting and the device power down function.

A single-ended, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is
sampled on the rising edge of CLK, and corresponding data is output after the following third rising edge.

The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1031 can handle.

The following sections explain:

D

The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages;

D

The ways in which the ADC reference voltages can be buffered internally, or externally applied;

D

How to set the onboard reference generator output, if required, and several examples of complete
configurations.

D

Subsequent sections explain the clamp function and digital controls, followed by more detailed application
information.

signal processing chain (sample and hold, PGA, ADC)

Figure 11 shows the signal flow through the sample and hold unit and the PGA to the ADC core.

REFTF

PGA

VQ+

ADC

Core

VQ–

REFBF

AIN

REFTS

REFBS

VP+

1

Sample

–1/2
–1/2

and

Hold

VP–

Figure 11. Analog Input Signal Flow

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13

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

sample-and-hold

The analog input signal A
restoration using the THS1031 clamp circuit.

The differential sample and hold processes A
pins, to give a differential output VP+ – VP– = VP given by:

VP = A

Where:

VM

+

For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if
MODE = A V
pair of differential inputs (see Figures 15 and 16).

– VM

IN

(REFTS)REFBS)

2

/2 then REFTS and REFBS can be connected together to operate with AIN as a complementary

DD

is applied to the AIN pin, either dc-coupled, ac-coupled, or ac-coupled with dc

IN

with respect to the voltages applied to the REFTS and REFBS

IN

programmable gain amplifier

VP is amplified by the PGA and fed into the ADC as a differential voltage VQ+ – VQ– = VQ

VQ = Gain × VP = Gain × [A

The default PGA gain at power up is 1, but can be programmed from 0.5 to 4.0 via the control register.

– VM]

IN

analog-to-digital converter

In all operating configurations, VQ is digitized against ADC reference voltages REFTF and REFBF, full-scale
values of VQ being given by

(1)

(2)

)

VQFS

)+

VQFS

*+

VQ voltages outside the range VQFS– to VQFS+ lie outside the conversion range of the ADC. Attempts to
convert out-of-range inputs are signalled to the application by driving the OVR output pin high. VQ voltages less
than VQFS– give ADC output code 0. VQ voltages greater than VQFS+ give output code 1023.

complete system

Combining equations 1 to 3, the analog full-scale input voltages at AIN which give VQFS+ and VQFS– at the
PGA output are:

AIN+FS)+VM)

and

AIN+FS*+VM*

The analog input span (voltage range) that lies within the ADC conversion range is:

Input span+[(FS))*(FS*)]+(REFTF*REFBF)ńGain

(REFTF*REFBF)

2

*

(REFTF*REFBF)

2

(REFTF*REFBF)

(REFTF*REFBF)

(2 Gain)

(2 Gain)

(3)

(4)

(5)

(6)

14

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Internal

AVDD/2

to REFBS. This air then

15, 16, 17
Out ut of VREF can be

AV

18, 19

REFBS V

MID

(V

FS+

(to bottom

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

complete system (continued)

The REFTF and REFBF voltage difference and the gain sets the device input range. The next sections describe
in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span
and device performance.

ADC reference generation

The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to
the MODE pin.

Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC
reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum
power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the
possibility of Kelvin connection of the reference inputs to the THS1031 to eliminate any voltage drops from
remote references that may occur in the system. Only single-ended input is possible in this mode.

THS1031

Connecting the MODE pin to A V

/2 gives differential mode. In this mode, the ADC reference voltages REFTF

DD

and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode
is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins.
A special case of differential mode is center span mode, in which user applies a single-ended signal to AIN and
applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.

Connecting the MODE pin to A V

gives top/bottom mode. In this mode, the ADC reference voltages REFTF

DD

and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS
pins. Only single-ended input is possible in top/bottom mode.

Table 1. Typical Set of Reference Connections

REFERENCE MODE MODE REFSENSE

External AV

External (through internal
reference buffer)

p
externally tied to REFTS or
REFBS to provide one of the
reference voltages

SS

DD

AV

VREF 1 V
AGND 2 V
External

divider
AV
VREF 1 V

AGND 2 V
External

divider

DD

DD

VREF

VOLTAGE

Disabled

1 + Ra/Rb
(see Figure 22)

Disabled

1 + Ra/Rb
(see Figure 22)

REFTS, REFBS ANALOG INPUT FIGURES

Reference buffer powered
down, reference voltage pro­vided directly by REFTS and
REFBS

Externally connect REFTS

forms AIN– to the ADC.

REFTS = V
V

) × Gain/2

FS–

REFBS = V
V

) × Gain/2

FS–

MID

p

+ (V

– (V

FS+

Single-ended 12, 13, 14

Differential or
center span

– Single-ended

–(top-bottom

mode)

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

full external reference mode (mode = AGND)

REFTF

AIN+

REFTS

REFBS

1

–1/2
–1/2

Sample

and

Hold

Internal

Reference

Buffer

PGA

ADC
Core

REFBF

Figure 12. ADC Reference Generation, MODE = AGND

When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs
disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively . These nodes
are connected by the user to external sources to provide the ADC reference voltages. The internal connections
are designed for use in kelvin connection mode (Figure 14). When using external reference mode as shown
in Figure 13, REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally . The mean
of REFTF and REFBF must be equal to AV

AV

AV

DD

+ [(FS+) – (FS–)] ×

2

DD

– [(FS+) – (FS–)] ×

2

0.1 µF

DC SOURCE =

DC SOURCE =

/2 (see Figure 13).

DD

+FS

AV

DD

2

–FS

GAIN

2

GAIN

2

AIN

REFTS

REFBS

REFTF

REFSENSE

AV

DD

Figure 13. Full External Reference Mode

It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode)
to overcome any voltage drops within the system (see Figure 14).

16

0.1 µF

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0.1 µF10 µF

REFBF

MODE

CMOS ANALOG-TO-DIGITAL CONVERTER

PRINCIPLES OF OPERATION

full external reference mode (mode = AGND) (continued)

+FS

AV

DD

2

–FS

_

AV

REFT =

REFB =

AV

DD

2

DD

2

+ [(FS+) – (FS–)] ×

– [(FS+) – (FS–)] ×

GAIN

2

GAIN

2

+

0.1 µF

_
+

0.1 µF

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

AV

DD

AIN

REFTS

REFBS

REFTF

0.1 µF10 µF

REFBF

REFSENSE

MODE

Figure 14. Full External Reference With Kelvin Connections

differential mode (mode = AVDD/2)

REFTF =

1

–1/2
–1/2

Sample

and

Hold

Internal

Reference

Buffer

PGA

AIN–

AIN+
REFTS
REFBS

VREF

AGND

Figure 15. ADC Reference Generation, MODE = AVDD/2

When MODE = A V

/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and

DD

REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF
voltages are centered on A V

/2 by the internal reference buffer and the voltage difference between REFTF

DD

and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are
open in this mode, allowing REFTS and REFBS to form the AIN– to the sample and hold.

Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to
an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the onboard reference generator
configuration).

AVDD + VREF

ADC

Core

REFBF =

2

AVDD – VREF

2

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

differential mode (mode = AV

AIN+

AIN–

0.1 µF

0.1 µF

Figure 16. Differential Input Mode, 1-V Reference Span

DC SOURCE = VM

/2) (continued)

DD

+FS

–FS
+FS

–FS

+FS

VM

–FS

+

VM

_

AV

DD

2

AIN

REFTS

REFBS

REFTF

0.1 µF10 µF

REFBF

AIN

REFTS

REFBS

MODE

REFSENSE

VREF

MODE

AV

DD

2

0.1 µF

0.1 µF

0.1 µF10 µF

REFTF

REFBF

REFSENSE

Figure 17. Center Span Mode, 2-V Reference Span

18

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

top/bottom mode (MODE = AV

AIN+

REFTS

REFBS

Figure 18. ADC Reference Generation Mode = AV

DD

)

1

–1/2
–1/2

Sample

and

Hold

Internal

Reference

Buffer

REFTF = AVDD + (REFTS – REFBS)

ADC

PGA

Core

REFBF = AVDD – (REFTS – REFBS)

DD

2

2

Connecting MODE to A VDD enables the internal reference buffer . Its inputs are internally switched to the REFTS
and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections
(REFTS to REFTF) and (REFBS to REFBF) are broken.

T o match the signal span to the full ADC input span, the voltage difference between REFTS and REFBS should
be REFTS – REFBS = [(FS+) – (FS–)] × Gain, with the average of the REFTS and REFBS voltages being the
AIN midscale voltage, VM.

Typically, REFSENSE is tied to AV

to disable the ORG output to VREF (as in Figure 19), but the user can

DD

choose to use the ORG output to VREF as either REFTS or REFBS.

AV

DD

+FS

DC SOURCE = VM + [(FS+) – (FS–)] ×

DC SOURCE =VM – [(FS+) – (FS–)] ×

0.1 µF

0.1 µF

Figure 19. ADC Reference Generation Mode = AV

–FS

GAIN

2

GAIN

2

AIN

REFTS

REFBS

REFTF

0.1 µF10 µF

REFBF

MODE

REFSENSE

DD

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

onboard reference generator configuration

The onboard reference generator (ORG) can supply a supply-voltage-independent and temperature­independent voltage on pin VREF.

External connections to REFSENSE control the ORG’s output to the VREF pin as shown in Table 2.

Table 2. Effect of REFSENSE Connection on VREF Value

REFSENSE CONNECTION ORG OUTPUT TO VREF REFER TO:

VREF pin 1 V Figure 20

AGND 2 V Figure 21

External divider junction (1 + RA/RB) Figure 22

AV

DD

REFSENSE = AVDD powers the ORG down, saving power when the ORG function is not required.
If MODE = AV

REFTF

/2, the voltage on VREF determines the ADC reference voltages:

DD

+

AV

DD

2

)

VREF

2

Open circuit Figure 23

(7)

REFBF

+

AV

2

DD

*

VREF

2

REFTF*REFBF+VREF

+

VBG

+
_

_

Internal

Reference

Buffer

Mode =

AV

DD

2

VREF = 1 V

REFSENSE

Figure 20. 1-V VREF Using ORG

0.1 µF 1 µF

Tantalum

AGND

20

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CMOS ANALOG-TO-DIGITAL CONVERTER

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

AV

DD

2

VREF = 2 V

REFSENSE

VBG

+

+
_

_

10 kΩ

10 kΩ

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

0.1 µF 1 µF

Tantalum

AGND

VBG

Figure 21. 2-V VREF Using ORG

Internal

Reference

Buffer

Mode =

AV

DD

+

+
_

_

2

VREF = 1 + (Ra/Rb)

Ra

REFSENSE

Rb

AGND

0.1 µF 1 µF

Tantalum

Figure 22. External Divider Mode

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

AV

DD

2

VBG

+

+
_

_

VREF = External

REFSENSE

AV

DD

AGND

Figure 23. Drive VREF Mode

operating configuration examples

This section provides examples of operating configurations.
Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF

to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AV
mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are
user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the
input signal.

2 V

0.1 µF

0.1 µF

1 V
0 V

0.1 µF10 µF

AIN

REFTF

REFBF

MODE

VREF = 2 V

REFTS

REFSENSE

REFBS

puts the THS1031 in top/bottom

DD

AV

DD

Figure 24. Operation Configuration in Top/Bottom Mode

22

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CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

operating configuration examples (continued)

In Figure 25, the input signal is differential, so Mode = AVDD/2 (differential mode) is set to allow the inverse signal
to be applied to REFTS and REFBS. The differential input goes from –0.8 V to 0.8 V , giving a total input signal
span of 1.6 V . Using a PGA gain of 1, REFTF–REFBF should therefore, equal 1.6 V . REFSENSE is connected
to resistors RA and RB (external divider mode) to make VREF = 1.6 V, that is R

AV

DD

2

R

A

R

B

AIN+

AIN–

0.1 µF

1.4 V
1 V

0.6 V

1.4 V
1 V

0.6 V

AIN

REFTS

REFBS

REFTF

MODE

VREF = 1.6 V

REFSENSE

= 0.6 (see Figure 22).

A/RB

THS1031

0.1 µF

0.1 µF10 µF

REFBF

Figure 25. Differential Operation

Figure 26 shows a center span configuration for an input waveform swinging between 0.2 and 1.9 V. Pins
REFTS and REFBS are connected to a voltage source of 1.05 V , equal to the mid-scale of the input waveform.
With the PGA gain set to its default value of 1, REFTF–REFBF should be set equal to the span of the input
waveform, 1.7 V , so VREF is connected to an external source of 1.7 V . REFSENSE must be connected to A V

DD

to disable the ORG output to VREF (see Figure 23) to allow this external source to be applied.

AV

DD

2

DD

DC SOURCE = 1.7 V

1.9 V

1.05 V

0.2 V

DC SOURCE = 1.05 V

0.1 µF

0.1 µF

AV

AIN

REFTS

REFBS

REFTF

0.1 µF10 µF

REFBF

MODE

REFSENSE

VREF

Figure 26. Center Span Operation

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

operating configuration examples (continued)

Figure 27 shows an example of top/bottom mode operation on an input span of 800 mV with mid-scale value

1.5 V. Pin REFTS is set to 2.5 V and pin REFBS to 0.5 V, making their average value equal to the mid-scale
value of A
full-scale range of the ADC core for best resolution. The PGA gain then has to be set to 2.5, to amplify the
800 mV

and giving the maximum specified difference of 2 V between REFTS and REFBS to maximize the

IN

input signal to 2 VPP at the ADC core input.

PP

AV

DD

1.9 V

1.5 V

1.1 V

DC SOURCE = 2.5 V

AIN

REFTS

MODE

REFSENSE

DC SOURCE = 0.5 V

0.1 µF

0.1 µF

0.1 µF10 µF

REFBS

REFTF

REFBF

Figure 27. Top/Bottom Mode, PGA Gain 2.5

clamp operation

CLAMPIN

CLAMP

+

C

IN

R

IN

V

IN

AIN

SW1

_

Control Register (Bit CLINT)

V

(Clamp)

Figure 28. Schematic of Clamp Circuitry

The THS1031 provides a clamp function for restoring a dc reference level to the signal at AIN which has been
lost through ac-coupling from the signal source to this pin.

10-Bit

DAC

S/H

Figure 29 shows an example of using the clamp to restore the black level of a composite video input ac coupled
to AIN. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN to equal the clamp
reference voltage, setting the dc voltage at AIN for the video black level.

After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be
taken from the internal CLAMP DAC by suitably programming the THS1031 clamp and control registers.

Clamp acquisition and clamp droop design calculations are discussed later.

24

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CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

clamp operation (continued)

Line Sync

Black
Level

Video at AIN

CLAMP

Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level

clamp DAC output voltage range and limits

When using the internal clamp DAC in top/bottom or center span mode, the user must ensure that the desired
dc clamp level at AIN lies within the voltage range V
is constrained to lie within this range V

)

VDAC+V

REFBF

(V

REFTF

*

REFBF

V

to V

) (0.006)0.988 (DAC code)ń1024)

REFBF

REFBF

REFTF

to V

. Specifically:

. This is because the clamp DAC voltage

REFTF

THS1031

(8)

DAC codes can range from 0 to 1023. Figure 30 graphically shows the clamp DAC output voltage versus the
DAC code.

VDAC

V

REFTF

V

REFBF

V

0 1023

REFBF

+ 0.006(V

V

REFBF

REFTF–VREFBF

+ 0.987(V

REFTF–VREFBF

)

)

DAC Code

Figure 30. Clamp DAC Output Voltage Versus DAC Register Code Value

If the desired dc level at AIN does not lie within the voltage range V

REFTF

to V

, then either the CLAMPIN

REFBF

pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application
to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both top/bottom and center
span modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range
is to be moved.

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3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

power management

In power-sensitive applications (such as battery-powered systems) where the THS1031 ADC is not required
to convert continuously, power can be saved between conversion intervals by placing the THS1031 into
power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,
the device typically consumes less than 1 mW of power in either top/bottom or center-span modes. Power-down
mode is exited by resetting control register bit 3 to 0. On power up, the THS1031 typically requires 5 ms of
wake-up time before valid conversion results are available.

In systems where the ADC must run continuously , but where the clamp is not required, setting control register
bit 6 (CLDIS to 1), which disables only the clamp circuits, can save power.

Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by
1 mA analog I

output format and digital I/O

While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE

. This is achieved by connecting the REFSENSE pin to AVDD.

DD

is held high.

The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be
switched to 2s complement (output codes –512 to 511) by setting control register bit 5 (TWOC) to 1.

writing to the internal registers through the digital I/O bus

Pulling pin OE

high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance
state. This allows control register data to be loaded into the THS1031 by presenting it on the I/O0 to I/O9 pins
and pulsing the WR pin high to latch the data into the chosen control or DAC register.

Figure 31 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to
clamp registers 1 and 2 (see the register map in Table 3). Pins I/O0 to I/O7 are driven to the clamp DAC code
lower byte (0F hex) and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.
The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word
are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select
clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp
register 2. Interface timing parameters are given in Figures 1 and 2.

OE

WR

I/O (0–9)

Output Input 00F Input 101 Output

Load 0F Into
REGISTER 0

Load 01 Into
REGISTER 1

Figure 31. Example Register Write Cycle to Clamp DAC Register

26

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DESCRIPTION

I/O[9:8] = 10
Clamp Register 2

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

digital control registers

The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation.
Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE
previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01
clamp register 2, and 10 the control register.

Table 3. Register Map

pins (see the

THS1031

ADDRESS

I/O[9:8]

00 Clamp Reg. 1 00 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
01 Clamp Reg. 2 00 DAC[9] DAC[8]
10 Control Reg. 01 CLDIS TWOC CLINT PDWN PGA[2] PGA[1] PGA[0]
11 Reserved

DEF

(HEX)

B7 B6 B5 B4 B3 B2 B1 B0

BIT

Table 4. Register Contents

REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION

PGA gain:
000 = 0.5
001 = 1.0 (default value)
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0

Power down
0 = THS1031 powered up
1 = THS1031 powered down

Clamp voltage internal/external
0 = external analog clamp voltage from CLAMPIN pin
1 = from onboard DAC (see clamp register)

Output format
0 = unsigned binary
1 = two’s complement

Clamp amplifier disable (for power saving)
0 = Enable
1 = Disable

Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp voltage = REFBF
DAC[9:0] = 3Fh: Clamp voltage = REFTF

Clamp DAC voltage
(DAC[9] = MSB)

Control Register

Clamp Register 1
I/O[9:8] = 00

p

I/O[9:8] = 01

2:0 PGA[2:0] 0

3 PDWN 0

4 CLINT 0

5 TWOC 0

6 CLDIS 0

7 Unused

7:0 DAC[7:0] 0

7:2 Unused
1:0 DAC[9:8] 0

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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the THS1301 analog inputs

driving AIN

Figure 32 shows an equivalent circuit for the THS1031 AIN pin. The load presented to the system at the AIN
pin comprises the switched input sampling capacitor, C

AV

DD

CLK

AIN

C1
8 pF

SAMPLE

, and various stray capacitances, CP1 and CP2.

1.2 pF

C

C2

1.2 pF

SAMPLE

AGND

CLK

+
_

V

LAST

Figure 32. Equivalent Circuit of Analog Input AIN

In any single-ended input mode, V
of the voltages on pins REFTS and REFBS. In any differential mode, V

The external source driving AIN must be able to charge and settle into C

= the average of the previously sampled voltage at AIN and the average

LAST

= the common mode input voltage.

LAST

SAMPLE

and the CP1 and CP2 strays

to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution.

AIN input current and input load modeling

When CLK goes low, the source driving AIN must charge the total switched capacitance C

S

= C

SAMPLE

The total charge transferred depends on the voltage at AIN and is given by

Q

CHARGING

For a fixed voltage at AIN, so that AIN and V

+

(AIN*V

LAST

) CS.

do not change between samples, the maximum amount of

LAST

charge transfer occurs at AIN = FS– (charging current flows out of THS1030) and AIN = FS+ (current flows into
THS1030). If AIN is held at the voltage FS+, VLAST = [(FS+) + VM]/2, giving a maximum transferred charge:

Q(FS)

(FS))*[(FS)))VM]

+

2

CS+

[(FS))*VM] C

2

S

+ CP2.

(9)

(10)

+(1ń

4 of the input voltage span) C

If the input voltage changes between samples, then the maximum possible charge transfer is

Q(max)+3 Q(FS)

which occurs for a full-scale input change (FS+ to FS– or FS– to FS+) between samples.
The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive

at high frequencies. Inserting a small series resistor of 20 Ω or less in the input path can damp source ringing.
See Figure 33. This resistor can be made larger than 20 Ω if reduced input bandwidth or distortion performance
is acceptable.

28

S

(11)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

AIN input current and input load modeling (continued)

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

V

R< 20 Ω

S

AIN

Figure 33. Damping Source Ringing Using a Small Resistor

equivalent input resistance at AIN and ac-coupling to AIN

Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an
ac-coupling network such as shown in Figure 34.

AV

DD

R

C

in

(Bias1)

R

(Bias2)

AIN

Figure 34. AC-Coupling the Input Signal to the AIN Pin

Note that if the bias voltage is derived from the supplies, as shown in Figure 34, then additional filtering should
be used to ensure that noise from the supplies does not reach AIN.

Working with the input current pulse equations given in the previous section is awkward when designing
ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent
resistance, R

VM = (REFTS + REFBS)/2 and R

where f

clk

, from the AIN pin to a voltage source VM where

AIN

= 1 / (CS x f

AIN

is the CLK frequency.

clk

)

The high-pass –3 dB cutoff frequency for the circuit shown in Figure 34 is:

f

(*3dB)

+

ǒ

2 p RINtot

1

where RINtot is the parallel combination of Rbias1, Rbias2, and R
the clock frequency, f

, is much higher than f(–3 dB).

clk

Note also that the effect of the equivalent R
bias network dc level.

Ǔ

AIN

and VM at the AIN pin must be allowed for when designing the

AIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(12)

. This approximation is good provided that

29

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

details

The above value for R
by the ac coupling network. The average value of V

V

= V(AIN bias) – VM

LAST

For an input voltage V

Qin = (V

IN

Provided that f (–3 dB) is much lower than f
the input charging pulse

= Qin/t

I

IN

= Qin × f
= (Vin – V

The ac input resistance R

= dIin/dVin

R

AIN

= 1 / (dVin / dIin)
= 1 / (C

is derived by noting that the average AIN voltage must equal the bias voltage supplied

AIN

at the AIN pin,

in

– V

clk

clk

S

LAST

LAST

AIN

x f

clk

) × C

S

) × CS × f

is then

)

, a constant current flowing over the clock period can approximate

clk

clk

in equation 13 is thus a constant voltage

LAST

(13)

(14)

(15)

(16)

driving the VREF pin (differential mode)

Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin
(MODE = AV

/2 and REFSENSE = AVDD).

DD

AV

DD

VREF

AGND

R

IN

14 kΩ

REFSENSE = AVDD,

AV

AVDD + VREF/4

44

+
_

Mode =

DD

2

Figure 35. Equivalent Circuit of VREF

The current flowing into I

IIN+(3

VREF*AVDD)

is given by

IN

(4 RIN)

Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations
and allowing for operating temperature variations.

(17)

The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground
and capable of driving I

30

IN

.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the internal reference buffer (top/bottom mode)

Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal
reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.

AV

DD

R

4

IN

14 kΩ

+
_

Mode =

AV

DD

2

REFTS

REFBS

AGND

AVDD + REFTS + REFBS

Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer

THS1031

Equations for the currents flowing into REFTS and REFBS are:

IINTS

IINBS

(3 REFTS*AVDD*

+

(4 RIN)

(3 REFBS*AVDD*

+

(4 RIN)

REFBS)

REFTS)

These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving
the sample and hold. Tolerance on these currents are ±50%.

driving REFTS and REFBS

AV

DD

REFTS
REFBS

AGND

Internal

Reference

Buffer

C1
7 pF

Mode = AV

DD

CLK

C2

0.6 pF

CLK

+
_

V

LAST

0.6 pF

C

SAMPLE

(18)

Figure 37. Equivalent Circuit of REFTS and REFBS Inputs

This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also
driving a switched capacitor load like AIN, but with the sampling capacitor and C
and about 0.6 pF respectively.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

on each pin now being 0.6 pF

P2

31

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving REFTF and REFBF (full external reference mode)

AV

DD

REFTF

REFBF

AV

AGND

DD

AGND

680 Ω

To REFBS
(For Kelvin Connection)

To REFTS
(For Kelvin Connection)

Figure 38. Equivalent Circuit of REFTF and REFBF Inputs

Note the need for off-chip decoupling.

clamp operation

The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by
programming the on-chip clamp DAC.

clamp acquisition time

Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.

CLAMPIN

10-Bit

DAC

CLAMP

+

C

IN

R

IN

V

IN

AIN

SW1

_

Control Register

V

CLAMP

S/H

Figure 39. Schematic of Clamp Circuitry

After powerup, the clamp circuit requires SW1 to be closed to charge the coupling capacitor, C

, to the voltage

IN

required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called
the clamp acquisition time, t

t

+

ACQ

CIN

RIN

ACQ

ǒ

In

Vc
Ve

:

Ǔ

(19)

Vc is the difference between the dc bias voltage level of the input signal, VIN, and the target clamp output voltage,
V

(clamp)

. Ve is the dif ference between the ideal Vc and the actual Vc obtained during the acquisition time. The

maximum tolerable error depends on the application requirements.

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

clamp acquisition time (continued)

For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of

1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 – 0.3 = 1 V .
If a 10 mV or less clamp voltage error Ve will give acceptable system operation, if the source resistance Rin is
20 Ω and the coupling capacitor C

is 1 µF, then the total clamp pulse duration required to reach this error is:

IN

THS1031

Vc

ǒ

t

+

ACQ

Note that SW1 does not have to be closed continuously until the desired clamp voltage is achieved. The clamp
level can be acquired over a longer interval by using a series of shorter clamp pulses with total pulse duration
at least equal to the acquisition time calculated using equation 19.

droop

The charge pulses entering or leaving AIN caused by the sample and hold switched capacitor input can charge
or discharge C
time between clamp pulses. This effect is called clamp droop and can be seen as a slow change in the ADC
output code when the input signal is a constant dc level. Through careful clamp circuit design, this droop can
be kept below 1 LSB, giving no change in the ADC output between clamp pulses.

The clamp voltage droop is a function of the input current to the THS1031 and the time between clamp pulses,
td

V

DROOP

Where:

CIN

I

+

IN

+

RIN

, causing the voltage at AIN to drift toward VM (the average of REFTS and REFBS) during the

IN

I

IN

+

(V

td (approximately)

IN

– VM)

– VM) CS fclkń2

(V

C

AIN

AIN

Ǔ

In

Ve

ńǒ2 R

+1mF 20W In

Ǔ

AIN

1

ǒ

Ǔ

= 92 µs (approximately)

0.01

(20)

(21)

is the input resistance given by equation 20. Cs is approximately 2.5 pF. Substituting IIN into the droop

R

AIN

voltage equation gives

+

(V

V

DROOP

Note that I
level is near either full-scale input voltage. There is no droop when the clamp level equals VM because I
zero. Note that the actual voltage droop may be up to 50% more than given by equation 22 when allowing for
temperature variations and device to device processing variations.

For example, with C
REFBS = 0.5 V, the clamp droop over td = 63.5 ms when V

V

has maximum value when V

IN

DROOP

+

+

(2.5 V – 1.5 V) 2.5 pF 30 MMzń2

+

0.0024 mV

+

1.25 LSB (assuming PGA gain

– VM) CS tdń(2 CIN)

AIN

is either +FS or –FS, and so the droop rate is worst then the clamp

AIN

= 1 µF at f

IN

(V

– VM) CS fclk tdń(2 CIN)

AIN

= 30 MSPS conversion rate in top/bottom mode with REFTS = 2.5 V and

clk

+

1)

= +FS is

AIN

(22)

IN

(23)

is

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

33

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

clamp operation (continued)

Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no
over-range), then the ADC output code will slowly drop to code 1022, or possibly code 1021, over the period
t

.

d

If the calculated droop is greater than can be tolerated in the application then increase C
and hence reduce the voltage change between clamp pulses.

If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly
larger than calculated above due to the capacitor’s rapid rate of self-discharge. Avoid using electrolytic and
tantalum coupling capacitors as these usually exhibit much higher leakage then nonpolarized capacitor types.
Electrolytic and tantalum capacitors also tend to have higher parasitics inductance, which can cause further
problems at high input frequencies.

steady-state clamp voltage error

Under steady-state conditions, the change in the clamp voltage caused during clamping must equal the change
caused by clamp droop, otherwise the effect causing the largest voltage change would pull the clamp voltage
away until these charging and droop effects equalize.

to slow the droop

IN

Figure 40 shows the approximate voltage waveform at AIN resulting from clamp droop during t
voltage reacquisition during the clamp pulse time, t

V

(Clamp)

V

AIN

t

c

VM

.

c

V

COS

V

t

d

DROOP

= ∆V

AIN

and clamp

d

Figure 40. Approximate Waveforms at AIN During Droop and Clamping

The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of V
approximation when V

appears across RIN, giving a charging current V

COS

is large enough to be a problem). The voltage change at AIN during clamp acquisition

COS

/Rin (this is a reasonable

COS

is then

V

COS

IN

tc

(24)

D

V

+

AIN

R

The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives

V

COS

RIN

+

IIN

tc

td

Where IIN is the input current given by equation, thus for low offset voltage, keep RIN low and ensure that the
ratio t

34

is not unreasonably large.

d/tc

(25)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the clock input

Obtaining good performance from the THS1031 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should

ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.

The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at
the CLK input, any clock buffers external to the THS1031 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.

The CLK input threshold is nominally around A VDD/2—ensure that any clock buffers have an appropriate supply
voltage to drive above and below this level.

digital output loading and circuit board layout

The THS1031 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V
digital supply. Minimizing the load on the outputs will improve THS1031 signal-to-noise performance by
reducing the switching noise coupling from the THS1031 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1031 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1031 and this buffer.

THS1031

Noise levels at the output buffers, and hence coupling to the analog circuits within THS1031, becomes worse
as the THS1031 digital supply voltage is increased. Where possible, consider using the lowest DV
application can tolerate.

Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1031 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1031 should be soldered directly to the PCB for best performance. Socketing
the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.

user tips for obtaining best performance from the THS1031

D

Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.

D

ORG modes offer the simplest configurations for ADC reference generation.

D

Choose differential input mode for best distortion performance.

D

Choose a 2-V ADC input span for best noise performance.

D

Choose a 1-V ADC input span for best distortion performance.

D

If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the
system. Care should be taken to ensure noise is not injected into the THS1031.

D

Use external voltage sources for ADC reference generation where there are stringent requirements on
accuracy and drift.

D

Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB
traces.

that the

DD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

35

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE

16 PINS SHOWN

0.050 (1,27)

16

1

0.020 (0,51)

0.014 (0,35)
9

0.299 (7,59)

0.293 (7,45)

8

A

0.010 (0,25)

0.419 (10,65)

0.400 (10,15)

M

0.010 (0,25) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

0.104 (2,65) MAX

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

0.012 (0,30)

0.004 (0,10)

DIM

A MAX

A MIN

PINS **

16

0.410

(10,41)

0.400

(10,16)

Seating Plane

0.004 (0,10)

20

0.510

(12,95)

0.500

(12,70)

0.610

(15,49)

0.600

(15,24)

24

28

0.710

(18,03)

0.700

(17,78)

4040000/C 07/96

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30

0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

37

PACKAGE OPTION ADDENDUM

www.ti.com 27-Mar-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

THS1031CDW ACTIVE SOIC DW 28 20 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

no Sb/Br)

THS1031CDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031CPW ACTIVE TSSOP PW 28 50 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

THS1031CPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

THS1031CPWR ACTIVE TSSOP PW 28 2000 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

THS1031CPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

THS1031IDW ACTIVE SOIC DW 28 20 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031IPW ACTIVE TSSOP PW 28 50 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

THS1031IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &

Call TI Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

THS1031CPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

THS1031CPWR TSSOP PW 28 2000 346.0 346.0 33.0

Pack Materials-Page 2

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Broadband www.ti.com/broadband
DSP dsp.ti.com Digital Control www.ti.com/digitalcontrol
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Military www.ti.com/military
Logic logic.ti.com Optical Networking www.ti.com/opticalnetwork
Power Mgmt power.ti.com Security www.ti.com/security
Microcontrollers microcontroller.ti.com Telephony www.ti.com/telephony
RFID www.ti-rfid.com Video & Imaging www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless

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