Texas Instruments (TI) provides complete interface solutions that empower you to differentiate your products and accelerate time-to-market.
Our expertise in high-speed, mixed-signal circuits, system-on-a-chip integration and advanced product development processes ensures you will
eceive the silicon, support tools, software and technical documentation to create and deliver the best products on time and at competitive prices.
r
ncluded in this selection guide you will find design considerations, technical overviews, graphic representation of portfolios, parametric tables
I
nd resource information on the following families of devices:
a
LVDS: (p. 4) TIA/EIA-644A specification
d
esigned for differential transmission
delivering signaling rates into the Gbps range
and power in the mW range with low EMI to
the telecommunication and consumer markets.
xECL: (p. 4) Emitter coupled logic (xECL),
high-speed differential interface technology
designed for low jitter and skew.
CML: (p. 4) Current-mode logic (CML), high
speed differential interface technology.
M-LVDS: (p. 8) TIA/EIA-899 specification with
all the benefits of LVDS applicable to multipoint bus architecture in backplanes. Used
often for clock distribution, e.g. AdvancedTCA.
Digital Isolators: (p. 10) The new ISO72x
high-speed digital isolators use state-of-the-art
integrated capacitive coupling and silicondioxide isolation barrier to provide up to
150-Mbps signaling rate with only 1-ns jitter,
best-of-class noise immunity and high reliability.
RS-485/422: (p. 11) Robust TIA/EIA-485 and
TIA/ EIA-422 specifications specially designed
for harsh, industrial environments transmitting
a differential signal up to 50 Mbps or 1.2 km.
RS-232: (p. 13) TIA/EIA-232 specification
defining single-ended interface between data
terminal equipment (DTE) and data circuitterminating equipment (DCE).
UARTs: (p. 16) Universal Asynchronous
Receiver/T
nent of serial communication utilizing RS232,
RS485/422 or LVDS transceivers to transmit or
receive between remote devices performing
parallel
process and serial to parallel conversion in the
receive process.
CAN: (p. 18) Controller Area Network
(ISO11898) specification commonly used in
automotive and industrial applications describes
differential signaling at a rate up to 1 Mbps on
a 40-meter bus with multipoint topology.
ransmitters are the key logic compo
to serial conversion in the transmit
FlatLink™ 3G: (p. 19) A new family of serial-
i
zers and deserializers designed for mobile
phone displays.
SerDes: (p. 20) Serializers and deserializers
in the gigabit range designed to bridge large
numbers of data bits over a small number of
data lines in telecommunication applications.
DVI/PanelBus™: (p. 22) The Digital Visual
Interface Specification, DVI, is an industry
standard developed by the Digital Display
Working Group (DDWG) for high-speed digital
connection to digital displays. DVI uses
transition-minimized DC balanced (TMDS)
data signaling.
TMDS: (p. 24) Transition minimized differential
signaling is the electrical interface used by DVI
and HDMI.
USB Hub Controllers and Peripheral
Devices:
established to make connecting PCs, peripherals and consumer electronics flexible and easy.
The hub controller manages USB port connect/
disconnect activities and a peripheral controller
enables USB connectivity of a peripheral
device to either a host or hub.
USB Port Protection: (p. 26) Transient voltage
suppressor protects USB 1.1 devices from ESD
and electrical noise transients.
USB Power Managers: (p. 27)
like TPS204xA and TPS205xA, are designed to
-
meet all the USB 1.0 and 2.0 requirements for
current-limiting and power switching to reliably
control the power on the voltage bus.
PCI Express®: (p. 29)
flexible and cost-effective I/O interconnect.
PCI Bridges: (p. 33) A peripheral component
interconnect (PCI) bridge provides a highperformance connection path between either
two PCI buses or a PCI component and one or
more DSP devices.
(p. 25) The USB standard was
A robust, scalable,
TI products,
CardBus Power Switches: (p. 34) The
C
ardBus controller uses the card detect and
voltage sense pins to determine a PC card’s
voltage requirements and then directs the
PCMCIA power switch to enable the proper
voltages. Standard PC cards require that V
be switched between ground, 3.3 V, and 5 V,
while VPP is switched between ground, 3.3 V,
5 V, and 12 V. CardBay sockets have the standard requirements for VCC, but require ground,
3.3 V, and 5 V to VPP, and ground, 1.8 V, or 3.3
V to V
simply not need 12 V or VPP while still having
the standard requirements for V
consider the voltage requirements of the
application when selecting a PCMCIA
power switch.
1394: (p. 36) IEEE 1394 (FireWire®) high-speed
interconnection enables simple, low-cost,
high-bandwidth, real-time data connectivity
between computers, peripherals and consumer
electronics.
GTLP: (p. 39) Gunning transceiver logic plus
(GTLP) derived from the JEDEC JESD8-3 GTL
standard is a reduced-voltage-swing
technology designed for high-speed interface
between cards operating at LVTTL logic levels
and backplanes operating at GTLP signal levels.
VME: (p. 41)
64-bit, backplane architecture that is coordinated and controlled by VITA. VME is used
extensively in military
applications.
Clock Distribution Circuits: (p. 42)
TI offers both single-ended and differential
clock buffers that perform from below 200 MHz
up to 3.5 GHz in a variety of fan-out options. In
addition to simple option for customers needing
differential signals (LVPECL) and single-ended
signals (LVTTL/LVCMOS) from the same device.
signal timing event from its ideal position,
has become a priority for ensuring reliability
in high-speed data buses.
Skew — Excessive skew, the time delta
between the actual and expected arrival
LVDS Family of Products
time of a clock signal, can limit the maximum
bandwidth performance and lead to data
ampling errors. Low skew specifications
s
make high-speed interconnect devices
xcellent for signal buffering.
e
Power Consumption — Low-voltage
differential signaling (LVDS) offers a low-power
alternative to ECL and PECL devices. Currentmode drivers in LVDS produce a constant
current, which allows power consumption to
be relatively independent of frequency. The
constant current driver delivers about 3.5 mA
to a 100-W load.
Technical Information
• LVDS is based on the TIA/EIA-644A
standard conceived to provide a generalpurpose electrical-layer specification for
drivers and receivers connected in a
point-to-point or multidrop interface.
Resources For a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
Literature
Number
Description
Application Notes
SLLA014ALow-Voltage Differential Signaling (LVDS) Design Notes (Rev. A)
SLLA030CReducing Electromagnetic Interference with LVDS (Rev. C)
SLLA031AUsing an LVDS Receiver with TIA/EIA-422 Data (Rev. A)
SLLA034A
SLLA038B
SLLA053BPerformance of LVDS with Different Cables (Rev. B)
SLLA054A
SLLA065
SLLA082BActive Fail-Safe in TI's LVDS Receivers (Rev. B)
SLLA100Increase Current Drive Using LVDS
SLLA101Interfacing Different Logic with LVDS Receivers
Slew Rate Control of L
Interface Circuits for TIA/EIA-644 (LVDS) (Rev. B)
L
A Comparison of LinBiCMOS and CMOS Process T
VDS Multidrop Connections (Rev
VDS Circuits (Rev
. A)
. A)
echnologies in L
VDS ICs
SLLA103LVPECL and LVDS Power Comparison
SLLA104Suggestions for L
VDS Connections
SLLA105DSP to DSP Link Using LVDS
SLLA107Live Insertion with Differential Interface Products
SLLA147Suitable LVDS Architectures
Supply voltage for all devices listed above is 3.3 V and temperature range is –40 to 85°C. New products are listed in bold red.
2
Automotive version available, temperature range of –40 to 125°CPreview products are listed in bold blue.
*Suggested resale price in U.S. dollars in quantities of 1,000.
Resources For a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
Literature NumberDescription
Application Notes
SLLA106TIA/EIA-485 and M-LVDS, Power and Speed Comparison
SLLA088ATransmission at 200 Mbps in VME Card Cage Using LVDM (Rev. A)
SLLA108Introduction to M-LVDS (TIA/EIA-899)
SLLA121Interoperability of M-LVDS and BusLVDS
SLLA119Wired-Logic Signaling with M-LVDS
SLLA127M-LVDS Signaling Rate Versus Distance
SLLA067A
external magnetic fields to prevent data
corruption is a critical consideration for
industrial applications. 1E6 times higher
magnetic immunity than inductive couplers.
Signaling rate — TI offers digital isolators
with the highest signaling rates of up to
150 Mbps.
Jitter — To ensure signal integrity,
jitter reduction is a priority. ISO72xx products
offer the lowest jitter with 1-ns jitter at
150-Mbps PRBS NRZ data input.
Key Features
• 4000-V
••
UL 1577, IEC 60747-5-2
peak
isolation
(VDE 0884, Rev. 2)
••
IEC 61010-1 and CSA approved
••
50-kV/µs transient immunity
• Signaling rate 0 Mbps to 150 Mbps
••
Low propagation delay
••
Low pulse skew
(pulse-width distortion)
• Low-power sleep mode
• High-electromagnetic immunity
• Low-input current requirement of 10 µA
• Fail-safe output
T
echnical Information
he ISO72xx is a family of digital isolators
T
sing the industry’s first application of digital
u
capacitive isolation technology. Digital buffers
apacitively couple data signals through a
c
silicone-dioxide (SiO2) insulation barrier which
provides galvanic isolation of up to 4000 V.
The device receives digital inputs and provides
clean digital outputs while preventing noise
currents and/or excessive voltages from
entering the local ground.
Recently introduced alternative isolation
techniques that use magnetic coupling may
still share the deficiencies of the older optocoupler solutions such as a restricted operating
temperature along with new concerns such as
he absence of a fail-safe output, an inability to
t
operate with DC-only signals and concerns
associated with susceptibility to external
magnetic fields and operating life under highvoltage conditions. TI isolation solutions are
designed to eliminate such problems.
superset of RS-422. Compliance with the
TIA/EIA standard will ensure reliable data
communication in a variety of networks,
including Modbus, INTERBUS, PROFIBUS,
BACnet and a variety of proprietary protocols.
Robustness — RS-485 is a robust interface
standard for use in industrial environments.
It features a wide common mode range of
–7 V to 12 V. Parts from TI are available with
ESD protection up to 30 kV.
Reliability — Integrated fail-safe circuitry
protects the bus from interpreting noise as
valid data when short-circuit, open-circuit or
idle line fault conditions occur.
Speed and Distance — Low noise coupling
of differential signaling with twisted-pair
cabling and wide common-mode voltage
RS-485/422 Family of Products
range allows data exchange at signaling rates
of up to 50 Mbps or to distances of several
20 percent of the characteristic impedance
of the cable and can vary from 90 Ω to 120 Ω.
kilometers at lower rates.
Technical Information
Line Loading — RS-422 is capable of support-
ing one driver and up to 10 receivers on the bus
line. Standard RS-485 is capable of supporting
up to 32 unit loads or nodes on the bus line.
However, there are reduced unit load devices
available that can support up to 256 devices.
Termination — A multipoint bus architecture
requires termination at both ends of the bus
line. The termination resistors must be within
Resources F
Literature NumberDescription
Application Notes
SLLA036BInterface Circuits for TIA/EIA-485 (RS-485)
SLLA070C422 and 485 Standards Overview and System Configurations
SLLA112RS-485 for E-Meter Applications
SLLA177PROFIBUS Electrical-Layer Solutions
SLLA169Use Receiver Equalization to Extend RS-485 Data Communications
SLLA143RS-485 for Digital Motor Control Applications
Note: IBIS models are available at interface.ti.com
or a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
• The main difference between RS-422 and
RS-485 is the multidrop and multipoint
bus architecture—that is, one driver to
many receivers and many drivers to many
receivers, respectively.
• Typical signaling rates and distances for
these standards are up to 10 Mbps or up
to 1.2 km. TI offers devices capable of
reaching signaling rates of up to 50 Mbps.
*Suggested resale price in U.S. dollars in quantities of 1,000.
5
Triple
Quad-Drivers
Quad-Receivers
E, REHVD113.3V Supply – Low-Speed Slew-Rate Control1015Short, Open, Idle2568-PDIP, 8-SOIC1.80
DE, REHVD103.3V Supply – High-Speed Signaling2515Short, Open, Idle648-PDIP, 8-SOIC1.85
DE, REHVD08Wide Supply Range: 3 to 5.5V1015Short, Open, Idle2568-PDIP, 8-SOIC1.90
D
E, REHVD3085ELow Power Mode, Optimized for Mid-Speed115Short, Open, Idle2568-PDIP, 8-SOIC, 8-MSOP0.90
DE, REHVD3088ELow Power Mode, Optimized for High-Speed1015Short, Open, Idle2568-PDIP, 8-SOIC, 8-MSOP1.00
DE, REHVD485EHalf Duplex Transceiver1015Open648-PDIP, 8-SOIC, 8-MSOP0.70
DE, REHVD1176PROFIBUS Transceiver, EN 501704010Short, Open, Idle1608-SOIC1.55
DE, REHVD22–20V to 25V Common Mode Operation0.516Short, Open, Idle2568-PDIP, 8-SOIC1.65
DE, REHVD21–20V to 25V Common Mode, 5Mbps516Short, Open, Idle2568-PDIP, 8-SOIC1.65
DE, REHVD20–20V to 25V Common Mode, 25Mbps2516Short, Open, Idle648-PDIP, 8-SOIC1.65
DE, REHVD23Receiver Equalization, 160 Meters at 25 Mbps2516Short, Open, Idle648-PDIP, 8-SOIC1.80
DE, REHVD24Receiver Equalization, 500 Meters at 3 Mbps316Short, Open, Idle2568-PDIP, 8-SOIC1.80
DE, REHVD07Strong Driver Outputs – Low Signal Rate116Short, Open, Idle2568-PDIP, 8-SOIC1.50
DE, REHVD06Strong Driver Outputs – Mid Signal Rate1016Short, Open, Idle2568-PDIP, 8-SOIC1.55
DE, REHVD05Strong Driver Outputs – Fast Signal Rate4016Short, Open, Idle648-PDIP, 8-SOIC1.60
DE, RELBC176Low Power102Open328-PDIP, 8-SOIC0.90
DE, RELBC176ALow Power, Fast Signaling, ESD Protection3012Open328-PDIP, 8-SOIC1.20
DE, RELBC184Transient Protection, IEC Air, Contact, Surge0.2530Open1288-PDIP, 8-SOIC1.30
DE, RELBC182IEC ESD Protection, Air and Contact Tests
DE, REALS176Fast Signaling, Skew: 15ns352Open328-SOIC1.26
DE, RE176BCost Effective102None328-PDIP, 8-SOIC, 8-SOP0.44
NoHVD303.3V Supply, no Enables, 25Mbps2515Short, Open, Idle648-SOIC1.80
NoHVD313.3V Supply, no Enables, 5Mbps515Short, Open, Idle2568-SOIC1.80
NoHVD323.3V Supply, no Enables, 1Mbps115Short, Open, Idle2568-SOIC1.80
NoHVD379Balanced Receivers, Ideal for Interbus25
DE, REHVD333.3V Supply, with Enables, 25Mbps2515Short, Open, Idle6414-SOIC1.85
DE, REHVD343.3V Supply, with Enables, 5Mbps515Short, Open, Idle25614-SOIC1.85
DE, REHVD353.3V Supply, with Enables, 1Mbps115
NoHVD50Strong Bus Outputs, no Enables, 25Mbps2515Short, Open, Idle648-SOIC1.70
NoHVD51Strong Bus Outputs, no Enables, 5Mbps515Short, Open, Idle2568-SOIC1.70
NoHVD52Strong Bus Outputs, no Enables, 1Mbps115Short, Open, Idle2568-SOIC1.70
NoHVD179Balanced Receivers, Ideal for Interbus2515None2568-SOIC1.85
NoLBC179Low Power, without Enable102Open328-PDIP, 8-SOIC0.85
No
DE, REHVD53Strong Bus Outputs, with Enables, 25Mbps2515Short, Open, Idle6414-SOIC1.60
DE, REHVD54Strong Bus Outputs, with Enables, 5Mbps515Short, Open, Idle25614-SOIC1.60
DE, REHVD55Strong Bus Outputs, with Enables, 1Mbps115Short, Open, Idle25614-SOIC1.60
DE, RE
DE, REALS180High Signaling Rate, with Enables252Open3214-SOIC1.71
DE, REALS1177Dual full-duplex drivers/receivers102Open3216-PDIP, 16-SOIC3.24
1DE, 2DE
riple RE
DE, T
ComplementaryLBC172AHigh Signaling Rate, High ESD3013—3216-PDIP, 16-SOIC, 20-SOIC2.40
T
level IEC61000-4-2 electrostatic discharge
(ESD) protection. This protection makes the
RS-232 interface immune to damage from
ESD strikes that may occur while the system
is up and running, such as when a connection
to the RS-232 cable is made. These devices
are drop-in replacements and are functionally
identical to the existing industry-standard
solutions, providing a seamless transition in
the qualification process. These devices meet
the requirements for low-power, high-speed
applications such as portable/consumer,
telecom and computing equipment.
TI offers these new devices in the NiPdAu
Pb-Free finish, which eliminates tin whiskers
that might compromise long-term system reliability. TI offers the space-saving QFN package on select devices in addition to its
already extensive RS-232 portfolio.
Key Features
• No external ESD device needed with
these system-level ESD ratings:
– ±15-kV human-body model (HBM)
– ±8-kV IEC61000-4-2, contact
discharge
– ±15-kV IEC61000-4-2, air-gap
discharge
• Improved drop-in replacement of
popular RS-232 devices
• Data rates meet or exceed today’s
high-speed-application requirements
• Flexible power-saving options enable
longer battery life
• Wide portfolio permits selection of the
right form, fit and functionality
• Industry-leading interface product
space with assured source of supply
• Space-saving QFN package options for
portable applications
pplications
A
• The three-driver, five-receiver MAX3243E
is most popular in applications like PCs,
notebooks and servers.
• The MAX3238E/37E offer
complementary five-driver, threereceiver solutions. These two devices
are popular in PC peripheral
applications like data cables, printers,
modems, industrial control, etc.
• The MAX3227E/23E/22E/21E are
popular in portable handheld
applications due to their reduced bit
count, package size and low power
consumption.
• Higher-speed versions like the
SNx5C3232E/23E/22E/21E meet today’s
higher throughput needs through the
serial interface.
• The MAX232E and MAX213 provide a
higher noise margin for more rugged
environments such as industrial control.
The UART is a key component of an
asynchronous serial communications system.
For example, all internal modems have their
own UARTs. In this application, parallel data
within the computer is converted by the
UART to serial data before being transferred
to the modem. In addition to PC/peripheral
communication, UARTs can be used for
chip-to-chip communications.
As data transfer speeds have increased to
support applications such as telecommunication base stations, cell phones, PCs, fax
servers and rack modems, the transmission
rate of the UART has become critical to
Key Features
• Single-, dual- and quad-channel devices
• 16- and 64-byte FIFOs available
• 5-, 3.3-, 2.5- and 1.8-V supply
• Clock rates up to 24/20/16-MHz for
1.5/1.25/1.0-Mbps data transfer rates
• Hardware and software autoflow control
• Programmable sleep mode and
low-power mode
• Industrial temperature characterization
preventing system bottlenecks. When a fast
xternal modem is used, designers should be
e
ure the computer’s UART can handle the
s
odem’s maximum transmission rate. For
m
xample, the TL16C550D UART contains a
e
16-byte buffer, enabling it to support higher
sustained transmission rates than the older
8250 UART. To reduce software buffering
and data overruns, TI has added its patented
hardware autoflow control to all new
designs and most existing UARTs. Most
UARTs allow the divisor to be programmed
from 1 to 65,535 and sometimes with an
added predivisor factor of 1, 4, 16 or 64.
UART Family of Products
To accommodate the requirements of diverse
pplications, TI offers a wide portfolio of
a
arallel-to-serial and serial-to-parallel UARTs
p
n highly integrated, space-saving configura-
i
ions that allow designers to increase system
t
performance while decreasing space
requirements.
As one of the world’s leading high-volume
semiconductor manufacturers, TI offers
designers and OEMs the satisfaction of
knowing they are backed by a supplier with
the resources to meet their needs. These
include a dedicated marketing and technical
support team to assist with any issues.
TL16C2550216-Byte1.8/2.5/3.3/5–40 to 8532 QFN, 44 PLCC,Dual UART with Programmable Auto-RTS and Auto-CTS2.80
48 TQFP
TL16C2552216-Byte1.8/2.5/3.3/5–40 to 8532 QFN, 44 PLCCDual UART with Programmable Auto-RTS and Auto-CTS3.00
TL16C2752264-Byte1.8/2.5/3.3/5—44 PLCCDual UART with Customizable Trigger LevelsCall
TL16C4501None50 to 7040 DIP, 44 PLCCSingle UART1.50
TL16C4511None50 to 7068 PLCCSingle UART with Parallel Port2.50
TL16C4522None50 to 7068 PLCCDual UART with Parallel Port2.55
TL16C550C116-Byte3.3/5–40 to 8540 DIP, 44 PLCC,Single UART with Hardware Autoflow Control1.75
48 LQFP, 48 TQFP
TL16C550D116-Byte2.5/3.3/5–40 to 8532 QFNSingle UART with Hardware Autoflow Control1.75
48 LQFP, 48 TQFP
TL16C552A216-Byte5–40 to 8568 PLCC, 80 TQFPDual UART with Parallel Port3.85
TL16C554A416-Byte5–40 to 8568 PLCC, 80 LQFPQuad UART with Hardware Autoflow Control6.00
TL16C750116/64-Byte5–40 to 8544 PLCC, 64 LQFPSingle UART with Hardware Autoflow Control, Low-Power Modes3.70
TL16C752B264-Byte3.3–40 to 8548 LQFP, 48 TQFPDual UART with Hardware Autoflow Control, Low-Power Modes3.10
TL16C754B464-Byte3.3/5–40 to 8568 PLCC, 80 LQFPDual UART with Hardware Autoflow Control, Low-Power Modes8.35
TL16PC564B/BLV116/64-Byte3.3/50 to 70100 BGA, 100 LQFPSingle UART with PCMCIA Interface5.90/6.10
TL16PIR552216-Byte50 to 7080 QFPDual UART with Selectable IR & 1284 Modes6.10
*Suggested resale price in U.S. dollars in quantities of 1,000.
17
➔
*
TL16C550D Asynchronous Communications Element
Get samples, datasheets, EVMs and reports at: www.ti.com/sc/device/TL16C550D
Asynchronous Communications Element
with Autoflow Control
The TL16C550D is a performance-enhanced
version of TI’s industry-standard TL16C550C
single-channel UART with 16-byte FIFO. The
TL16C550D can support voltages of down to
2.5 V and data transfer rates of up to 1.5
Mbps. Combining these features with an
ultra-small 32-pin QFN package, the
TL16C550D is ideal for a variety of portable
applications.
• Independent clock input receiver
Fully programmable serial interface
•
characteristics
• Available packages: DIP, PLCC,
TQFP and QFN
Applications
• PDAs
• MP3 players
• Gaming systems
• Modems
• Serial ports
elecom
T
•
Functional block diagram.
18
➔
CAN (3.3-V and 5-V High-Speed CAN Transceivers)
D
esign Considerations
Bus Protection — Features such as
short-circuit protection, thermal shutdown
protection, glitch-free power-up and powerdown protection, high-ESD protection,
wide common-mode range that provides for
common-mode noise rejection, and currentlimiting circuitry to protect the transceivers
and system from damage during a fault
condition have been incorporated into
these devices.
Electromagnetic Compatibility — An
mportant requirement for products intended
i
for networking applications is that they
behave in a way that does not interfere with
the operation of other nearby components or
systems. TI offers specially designed and
tested transceivers for EM compatibility
without malfunction or degradation of
performance in rugged EM environments.
Compatibility in this definition means both
immunity to external EM fields, and the
limited strength of generated EM fields.
Supply Voltage — In addition to 5-V
transceivers, TI offers 3.3-V transceivers
that accomplish the same tasks with less
than half the power and save on the cost of
an additional voltage regulator in 3.3-V
powered applications.
Technical Information
• ISO11898 specifies the physical-layer
implementation of CAN.
• This specification describes a twisted
wire pair bus with 120-W characteristic
impedance (Zo) and differential signaling
rate of up to 1 Mbps on a 40-meter bus
with multi-drop topology.
CAN Transceiver Selection Guide
Supply I
VoltageDeviceDescriptionMax (mA)(kV)Protection (V)Temp Range Price*
5.0SN65HVD251Improved Drop-In Replacement for the PCA82C250 and PCA82C25165±14±36–40 to 125° C0.90
5.0
SN65HVD1050Improved Drop-In Replacement for the TJA1050 with Better ESD70±8–27 to 40–40 to 125° C0.55
3.3SN65HVD2303.3-V CAN Bus Transceiver, Standby Mode67±16–4 to 16–40 to 85° C1.35
SN65HVD2313.3-V CAN Bus Transceiver, Sleep Mode67±16–4 to 16–40 to 85° C1.35
SN65HVD2323.3-V CAN Bus Transceiver, Cost Effective67±16–4 to 16–40 to 85° C1.30
3.3
SN65HVD2333.3-V CAN Bus Transceiver, Standby Mode, Diagnostic Loop-back56±16±36–40 to 125° C1.50
SN65HVD2343.3-V CAN Bus Transceiver, Standby Mode, Sleep Mode56±16±36–40 to 125° C1.45
SN65HVD2353.3-V CAN Bus Transceiver, Standby Mode, Autobaud Loop-back56±16±36–40 to 125° C1.50
All devices have a signaling rate of 1 Mbps. New products are listed in bold red.
*Suggested resale price in U.S. dollars in quantities of 1,000.
CAN is a serial communications bus for robust
real-time control applications that is rapidly
gaining the attention of industrial process,
test, measurement and control engineers
worldwide. It has excellent error detection
and confinement capabilities, and has the
flexibility to operate either as a primary
backbone data communications network, as a
secondary local embedded system, or as both.
The engineering community is just now
exploring the limits of what this bus can do
when coupled with newly developed intelligent
sensing technologies.
Besides CAN’s high reliability, another of the
main advantages of CAN when compared to
alternative networks, is the availability of
higher layer protocols (HLPs). There are many
CAN-related system development packages
prepared for these HLPs – hardware interface
cards and easy-to-use software packages that
provide system designers with a wide range of
design and diagnostic tools. These compo
nents provide for the rapid development of
complex control applications without building
each node of a system network from scratch.
The HLP relieves a developer from the burden
of dealing with CAN-specific details such as
bit-timing and implementation functions. It
provides standardized communication objects
for real-time data with Process Data Objects
(PDOs) and Service Data Objects (SDOs), and
provides special functions such as a time
stamp, a sync message, and emergency
shut-down procedures as well as network
management, boot-up commands, and error
management.
Among the most popular HLPs are CANopen,
CANkingdom and DeviceNet with applications
ranging from medical equipment to process
control and assembly line coordination.
FlatLink 3G uses low EMI subLVDS to carry
24-bit color RGB data from applications
processors, such as OMAP™ from TI, to the
LCD Driver. It caters to screen resolutions
from QVGA to XGA.
*TIA, PA and LD are in development and not currrently available.
L
VDS
SN65LVDS93/94
S
N65LVDS95/96
SN65LV1023A/1224B
S
N75
L
V
DT1422
S
N75LVDS82/83
10 Gigabit
E
thernet
S
erDes
P
ortfolio
Gigabit
E
thernet/FC
EPON
TLK3114SC
T
LK3104SA
T
LK3104SC
TLK3118
TLK10021
TLK1201AI
T
NETE2201
T
LK2208B
TLK2226
T
LK2201BI
TLK2201AJR
TLK1211
G
eneral
Purpose
TLK3101
T
LK2711
T
LK2701
TLK2501
T
LK1501
TLK4015
T
LK2521
TLK1521
TLK4120
T
LK4250
S
N75LVDS84A/86
20
SerDes (Serial Gigabit Transceivers and LVDS)
➔
The serial gigabit transceiver family of
devices from TI provides low power dissipation while enabling multigigabit transmission
over copper backplanes, cable and optical
links. The transceivers can be used in a
variety of applications, including Gigabit
Ethernet, 10-Gigabit Ethernet modules,
synchronous optical network (SONET) OC-48
and OC-192 based equipment, wireless
infrastructure backplanes and general-purpose
backplane applications.
SerDes Solutions—Frontplane/Backplane
TLK1201AI/TLK2226/TLK2208B
Low-Power 1 GbE Transceiver
1 to 1.6 Gbps
(Backplane/Frontplane)
TLK3114SC
TLK2208B—8-Channel Gigabit Ethernet Xcvr (8 x 1-1.3-Gbps)
—10-Gigabit Ethernet Backplane Device XAUI (4 x 3.125 Gbps)
TLK2226—6-Channel Gigabit Ethernet Xcvr (6 x 1-1.3 Gbps)
TLK1201AI—1- to 1.6-Gbps Gigabit Ethernet-Compliant SerDes
TLK3101/TLK2501/TLK1501—600-Mbps to 3.2-Gbps General-Purpose Backplane SerDes
The Digital Visual Interface (DVI)
Specification, is an industry standard developed by the Digital Display Working Group
DDWG) for high-speed digital connection to
(
digital displays. DVI uses Transition-minimized
DC balanced (TMDS) data signaling. Single
link supports up to 165Mpixels/s – UXGA
FPDs, SXGA DCRTs, 720p and 1080i HDTVs.
High Bandwidth Digital Content
Protection (HDCP)
• Content protection for video sent over DVI
• Implementation of HDCP requires a
license from the Digital Content
Protection Licensing, L.L.C.
(www.digital-cp.com)
HDCP Elements
• Authentication is a process for verifying
that a device is authorized (e.g. licensed)
DVI-HDCP implementation.
to handle protected content.
• Encryption prevents eavesdropping of
protected content.
• Renewability enables revocation of
compromised devices.
Get datasheets at: www.ti.com/TFP501 or www.ti.com/TFP503
The TFP501 and TFP503 are TI PanelBus flat panel display products,
part of a comprehensive family of end-to-end DVI 1.0-compliant
solutions. The TFP501/TFP503 support display resolutions up to UXGA,
including the standard HDTV formats, in 24-bit true-color pixel format.
The TFP501/TFP503 offer design flexibility to drive one or two pixels
per clock, support TFT or DSTN panels and provide an option for
time-staggered pixel outputs for reduced ground-bounce.
Key Features
• Supports UXGA resolution (output pixel rates up to 165 MHz)
• Digital visual interface (DVI) and high-bandwidth digital content
protection (HDCP) specification compliant
Encrypted external HDCP device key storage for exceptional security
• 4x oversampling for reduced bit-error rates and better performance
over longer cables
• Embedded HDCP keys (TFP503 only)
• Supports hot-plug detection
• Packaging: 100-pin TQFP PowerPAD™
Applications
• Desktop LCD monitors
• DLP®and LCD projectors
• Digital TVs
TI PanelBus™ Digital Transmitters
FP510, TFP513
T
Get the datasheets and app reports at: www.ti.com/sc/device/TFP510 or
www.ti.com/sc/device/TFP513
The TFP510 and TFP513 provide a universal interface allowing a glueless connection to most commonly available graphics controllers. Some
of the advantages of this universal interface include selectable bus
widths, adjustable signal levels and differential and single-ended
clocking. The DVI interface supports flat panel display resolutions up
to UXGA at 165 MHz in 24-bit true color pixel format.
Key Features
• Digital visual interface (DVI) compliant
• Supports resolutions from VGA to UXGA
(25-MHz to 165-MHz pixel rates)
• Universal graphics controller interface
12-bit, dual-edge and 24-bit, single-edge input modes
••
••
Adjustable 1.1-V to 1.8-V and standard 3.3-V CMOS input signal
levels
Fully differential and single-ended input clocking modes
••
••
Standard Intel®12-bit digital video port compatible as on Intel
81x chipsets
• Programmable using I2C serial interface
• Monitor detection through hot-plug and receiver detection
(
to transmit Digital Visual Interface (DVI) and
High-Definition Multimedia Interface
(HDMI) data.
Design Considerations
Intra-Pair Skew – The time difference
between the true and complementary signals
of a given differential pair should be kept as
small as possible.
Residual Jitter – The difference in the
amount of measured jitter between the test
point and the signal source. It is the allowable
maximum residual jitter is equivalent to the
minimum jitter budget between transmitter
and receiver.
ESD – External connectors being exposed
to the outside world are especially susceptible
to electrostatic discharge. A higher ESD
rating provides improved protection.
r
high speed and allows complete backward
compatibility with USB 1.1.
USB products fall into three categories: hubs,
host controllers and peripherals. USB 1.1 supported speeds of up to 12 Mbps and cables
up to 5 meters long for these devices. USB
2.0 extends the connection speed to 480
Mbps to support next-generation peripherals
of higher-performance PCs and applications.
USB 2.0 officially defines three speeds: low
(1.5 Mbps), full (12 Mbps) and high (480
Mbps). The lowest speed is ideal for human
interface devices such as a mouse, game pad
or keyboard; while full speed is well suited
for “data dumps” to the PC via digital still
cameras, PDA cradles and flash-card readers.
Modems, printers, scanners and storage
drives are just a few of the items that can
take advantage of USB’s highest speed
specification.
USB Hub Controllers and Peripheral Devices
he USB On-The-Go (OTG) supplement to USB
T
.0 specifies a new class of devices aimed at
2
he portable market. USB OTG defines devices
t
hat can operate as standard USB peripherals
t
when connected to a standard USB host
controller.
However, these same devices can operate
as reduced-function host controllers to
support selected USB OTG peripheral
devices. End-equipment manufacturers
can specify what type of peripherals their
devices will support when in OTG host
mode. This new specification allows easy
sharing of contact information between
USB OTG PDAs and cell phones or printing
of photographs directly from an OTGenabled digital still camera without a PC.
Technical Information
Speed
• The USB 2.0 standard defines three
speeds: low speed (LS) 1.5 Mbps, full
speed (FS) 12 Mbps and high speed (HS)
480 Mbps. It requires full backward and
forward compatibility for devices and
cables. All three modes offer both asyn-
hronous and isochronous (real-time) data
c
transmission over a simple and inexpensive
4-wire cable to meet requirements of
peripherals including keyboards, mice,
printers, speakers, scanners, external
storage devices and digital still cameras.
Transfer Type
• USB 2.0 defines four types of transfers:
bulk, control, interrupt and isochronous.
Bulk transfer is intended for applications
such as printers, scanners and mass
storage, where latency isn’t critical but
accuracy is. All devices must include
control transfers for configuration.
Interrupt transfer is for devices such as
mice, keyboards and game pads that must
receive the host’s or device’s attention
periodically. Isochronous transfer offers
guaranteed delivery time but no errorchecking or automatic retransmission of
data received with errors, making it the
better choice for audio or video applications.
25
➔
RS232/IrDA Serial-to-USB Converter
TUSB3410
Get samples, datasheets, EVMs and app reports at: www.ti.com/sc/device/TUSB3410
USB-to-Serial Bridge
The TUSB3410 provides an easy way to move a
serial-based legacy device to a fast, flexible
USB interface by
bridging
and an enhanced UART serial port. The
TUSB3410 contains all the necessary logic to
communicate
• 8052 microcontroller with 16 Kbytes of
RAM that can be loaded from the host
or from external onboard memory via an
2
C bus
I
• Integrated, enhanced UART features
including:
••
Programmable software/hardware flow
control
Automatic RS-485 bus transceiver
••
control, with and without echo
Software-selectable baud rate from
••
50 to 921.6 kbaud
••
Built-in, two-channel DMA
controller for USB/UART bulk I/O
• Evaluation module to jump-start USB
development or for use as a complete
USB-to-RS-232 converter
Applications
• Handheld meters
• Health metrics/monitors
• Any legacy serial device that needs
to be upgraded to USB
U
SB Hub Controllers
U
SB Peripherals
USB Devices
TUSB2036
TUSB2046B
TUSB2077A
TUSB2136
T
USB5052
TUSB3210
TUSB3410
TUSB6250
U
SB OTG
TUSB6020
TUSB1105
TUSB1106
T
USB2551
U
SB PHY
26
USB Hub Controllers and Peripheral Devices
➔
USB Family of Products
Selection Guide
Voltage
DeviceSpeedPortsI2C(V)PackageDescriptionPrice
USB Hub Controllers
TUSB2036Full (1.1)2/3No3.332 LQFP2/3-port hub for USB with optional serial EEPROM interface1.15
TUSB2046BFull (1.1)4No3.332 LQFP4-port hub for USB with optional serial EEPROM interface 1.20
TUSB2077AFull (1.1)7No3.348 LQFP7-port USB hub with optional serial EEPROM interface1.95
TUSB2136Full (1.1)1/2Yes3.364 LQFP2-port hub with integrated general-purpose function controller3.25
TUSB5052Full (1.1)1-5Yes3.3100 LQFP5-port hub with integrated bridge to two serial ports5.10
*Suggested resale price in U.S. dollars in quantities of 1,000.Preview products are listed in bold blue.
USB Port Protection—Transient voltage suppressor protects USB 1.1
devices from ESD and electrical noise transients.
Temp Range
DeviceDescription°CPrice
USB Transceivers
SN65220Single suppressor –40 to 850.33
SN65240Dual suppressor –40 to 850.41
SN75240Dual suppressor0 to 700.38
*Suggested resale price in U.S. dollars in quantities of 1,000.
Interface Selection GuideT
*
Resources For a complete list of resources
(evaluation modules, data sheets and application notes), visit
Literature Number Description
Application Notes
SLLA122
SLLA154VIDs, PIDs and Firmware:
SLLU043 TUSB3410 UART Evaluation Board
SLLA170B USB/Serial Applications Using
SLLAA276MSP430 USB Connectivity Using
Selection and Specification of
Crystals for Texas Instruments
USB 2.0 Devices
Design Decisions When Using
TI USB Device Controllers
TUSB3410/5052 and the VCP
Software
TUSB3410
exas Instruments 4Q 2006
*
*
*
interface.ti.com
VIN/SW1
LDO_EN
EN1
SW2
EN2
GND
LDO_OUT
LDO_ADJ
OC1
OUT1
OUT2
OC2
TPS2145/55
TSSOP-14
LDO
VIN/SW1
EN1
SW2
EN2
GND
LDO_OUT
OC1
OUT1
OUT2
OC2
TPS2147/57
MSOP-10
LDO
VIN/SW1
LDO_EN
EN1
EN2
GND
LDO_OUT
OUT1
OUT2
TPS2148/58
MSOP-8
LDO
VIN
EN1
EN2
GND
LDO_OUT
OUT1
OC
OUT2
TPS2149/59
MSOP-8
LDO
D
esign Considerations
USB High-Power Peripheral Switch With
Dual Current Limit + LDO
Universal Serial Bus (USB) Power Managers
4-Port USB Hub Power Controllers
Power Distribution Switches
27
➔
TPS2140/41/50/51—The TPS2140/41/50/51
target high-power USB peripherals such as
ADSL modems. The devices contain a power
switch and an LDO. The dual-current-limiting
switch allows the use of high-value capacitance to stabilize the voltage from the USB bus.
Dual Power Switch + LDO for USB
Bus-Powered Peripherals and Hubs
TPS2148/49—TPS2148 is a complete power
management solution for USB bus-powered
peripherals such as zip drives, while TPS2149 is
for USB bus-powered hubs, such as keyboards
with integrated hubs. TPS2148/9 each combine
a 3.3-V LDO and dual power switch in a single
MSOP package. The TPS2148 switch configuration allows power and board capacitance
segmentation to meet USB system current
requirements. The TPS2149 switches manage
two independent or four ganged USB ports.
TPS207x—The TPS207x family provides the
complete power solution for 4-port selfpowered, bus-powered or hybrid USB hubs by
incorporating current-limited switches for four
ports, a 3.3-V 100-mA LDO, a 5-V LDO
controller for self power (TPS2070, TPS2071)
and a DP0 line control to signal an attach to
the host.
Ease of Use—USB allows simplified installa-
tion and improved performance for peripheral
devices by eliminating the need to repeatedly
load new drivers and establish individual settings. USB combines a multitude of existing
interfaces into a single easy-to-use connector,
greatly reducing system complexity and offering manufacturers the ability to develop highly
integrated products.
TPS204xB/5xB—The TPS204xB/5xB families
of 80-mΩ current-limiting power switches
meet all the USB power management
requirements for controlling downstream
ports, and include additional features to
improve the design reliability. For example,
when an over-current condition exists, the
device intelligently shuts down only the port
that sees the fault.
TPS202x/3x/6x—The TPS202x/3x/6x families
of low on-resistance current-limiting power
switches allow ganging of multiple ports to
a single switch, as described in Application
Note SLVA049. Though ganging can be costeffective, all ports are affected by a fault.
TPS21403.3 V3.3-V, 500-mA switch with active-low enable, 250-mA LDO
TPS21415.0 V5.0-V, 500-mA switch with active-low enable, 250-mA LDO
TPS21503.3 V3.3-V, 500-mA switch with active-high enable, 250-mA LDO
TPS21515.0 V5.0-V, 500-mA switch with active-high enable, 250-mA LDO
USB Power Managers Selection Guide
NumberI
OS
Deviceof FETs(min) (A)(mΩ) (V)(µA)OutputOutputEnablePredecessorPrice
USB Power Distribution Switches
TPS2020/3010.22332.7 to 5.573YesYesL/H
TPS2021/3110.66332.7 to 5.573YesYesL/HTPS20141.05
TPS2022/3211.1332.7 to 5.573YesYesL/HTPS20151.05
TPS2023/3311.65332.7 to 5.573YesYesL/H
TPS2024/3412.2332.7 to 5.573YesYesL/H
TPS2041B/51B10.7702.7 to 5.540YesYesL/HTPS2041/51/41A/51A0.50
TPS2042B/52B20.7702.7 to 5.553EachYesL/HTPS2042/52/42A/52A0.70
TPS2043B/53B30.7702.7 to 5.565EachYesL/HTPS2043/53/43A/53A0.90
TPS2044B/54B40.7702.7 to 5.575EachYesL/HTPS2044/54/44A/54A1.00
TPS2045A/55A10.3802.7 to 5.580YesYesL/HTPS2045/550.60
TPS2046B/56A20.3802.7 to 5.580EachYesL/HTPS2046/46A/560.65
TPS2047B/57A30.3802.7 to 5.5160EachYesL/HTPS2047/47A/570.90
TPS2048A/58A40.3802.7 to 5.5160EachYesL/HTPS2048/581.20
TPS2060/421.5702.7 to 5.550EachYesL/H—1.20
TPS2061/511.1702.7 to 5.543YesYesL/H—0.60
TPS2062/621.1702.7 to 5.550EachYesL/H—0.75
TPS2063/731.1702.7 to 5.565EachYesL/H—0.90
PCI Express®takes the best features and
ideas behind PCI and combines them with
more than 10 years of industry “lessons
learned.” The result is a robust, scalable,
flexible, cost-effective I/O interconnect that
will serve the industry for the next 10-15 years.
Key Features
• PCI Express architecture is an industry
standard high-performance, generalpurpose serial I/O interconnect designed
for use in enterprise, desktop, mobile,
communications and embedded platforms.
• It is PCI-compatible by using the established PCI software programming models.
PCI Express facilitates a smooth transition
to new hardware and allows software to
evolve and leverage the advantages of
PCI Express features.
• Gen I has a scalable bandwidth of 16
Gigabytes-per-second at its initial signaling rate of 2.5GHz. In the future, Gen II
promises much higher transfer rates using
higher frequency signaling technologies.
• Supports multiple interconnect widths via
1, 2, 4, 8, 12, 16 and 32 lane configurations aggregated to match application
bandwidth needs.
• Serves new and innovative, hot-plug/
hot-swap add-in card and module devices.
• Delivers unique, advanced features such
as Power Management, Quality of Service
and other native functions not available in
other I/O architectures.
et samples, datasheets, EVMs and app reports at: www.ti.com/sc/device/XIO2000A
G
TI’s PCI Express bridge chip, the XIO2000A, is
an industry first. It is designed for seamless
migration from the legacy PCI to the PCI
Express interface. It bridges an x1 PCI Express
bus to a 32-bit, 33/66-MHz PCI bus capable of
supporting up to six PCI devices downstream.
The XIO2000A fully supports PCI Express rates
of 2.5 Gbps. Its architecture supports the PCI
2.3 interface. The chip’s design enables PC
and I/O add-on card manufacturers to begin
transitioning to native PCI Express technology
while preserving compatibility with existing
PCI system software and firmware.
Key Features
• Compliant with PCI Express to PCI/PCI-X
Bridge Specification Revision 1.0
• Compliant with PCI Express Base
Specification 1.0a
• Compliant with PCI Local Bus Specification
rev 2.3
• Utilizes 100 MHz differential PCI Express
Common Reference Clock or 125 MHz
Single-Ended Reference Clock
• Full PCI Local Bus 66 MHz/32-bit Throughput
• Wake/Beacon Event Support
• Robust Architecture to Minimize Latency
ey Benefits
K
• Built-in adaptive receiver equalizer
••
Improves jitter tolerance thereby
reliably increasing PCB trace, or cable
length, supported by the XIO2000
• Software-programmable and hardware-autonomous power
management
• Supports low-power applications such as ExpressCard
• Compact footprint, 176-ball MicroStar BGA
• EEPROM configuration allows a global unique ID for the 1394
fabric to load
Target Market
• ExpressCards
• PC Add-In Cards
• PC Motherboards
4-Lane, 4-Port PCI Express Switch
XIO3130
www.ti.com/sc/pcl-e *
TI’s XIO3130 is an integrated PCI Express fan-out switch solution
with one upstream x1 port and three downstream x1 ports. This highperformance, integrated solution provides the latest in PCI Express
switch technology. It features cut-through architecture and integrated
reference clock buffers for downstream ports. The XIO3130 is fullycompliant with the PCI Express Base Specification Rev. 1.1. It supports
Advanced Error Reporting as defined in the PCI Express base specifications and is backwards-compatible with the PCI Local Bus
Specification, Rev. 2.3.
Key Features
• PCI Express fan-out switch with x1 upstream port and three x1
downstream ports
• Fully compliant with PCI Express Base Specification, Rev. 1.1
• Cut-through architecture
• Built-in Adaptive Equalizer in each of the four ports
• Wake-event and Beacon support
• Support for D1, D2, D3hot, and D3cold
• Active State Power Management (ASPM)
• Uses both L0s and L1
• Low power PCI Express transmitter mode (pre-emphasis disabled)
• Integrated AUX Power Switch drains VAUX power only when main
power is “off”
• Integrated Hot-Plug Support
• Integrated REFCLK Buffers for Switch Downstream Ports
• Advanced Error Reporting to assist with System Debug Tools
• 3.3V Multifunction I/O pins (e.g. for Hot-Plug status-and-control, or
General Purpose I/Os)
The primary purpose of the XIO3130 as a fan-out device is efficiently
expanding the chipset’s computing resources to multiple I/O ports and
enhancing system functionality and flexibility. Target applications for the
XIO3130 include PCs, servers, storage, industrial control and backplane.
TX Block
PLL
REFCLK±
TXP/TXN
RXP/RXN
TX_DATA 16/8
TX_CLK
TX_DATAK [1:0]
RX_DATAK [1:0]
STATUS
COMMAND
RX_DATA 16/8
RX_CLK
RX Block
FPGA
PCIe x1 IP Core
User
Application
Layer
Transaction
Layer
Data Link
Layer
MAC
Enhanced
PIPE
TI XIO1100
2.5
Gbps
2.5
Gbps
REF CLK
PCS PMA
32
PCI Express
®
➔
PCI Express PHY
XIO1100
et samples, datasheets, EVMs and app reports at: www.ti.com/sc/device/XIO1100
G
The XIO1100 is a PCI Express PHY, compliant with the PCI Express Base
Specification Revision 1.1 that interfaces the PCI Express Media Access
Layer (MAC) to a PCI Express serial link. It uses a modified version of
the “PHY Interface for the PCI Express” (PIPE) interface also referred to
as a TI-PIPE interface. The TI-PIPE interface is a pin-configurable
interface that can be configured as either a 16-bit or an 8-bit interface.
• The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface,
a 16 bits output bus (RXDATA) being clocked by the RXCLK output
clock, and a 16-bits Input bus (TXDATA) being clocked by the TXCLK
input clock. Both buses are clocked using Single Data Rate (SDR)
clocking in which the data transitions are on the rising-edge of the
associated clock.
• The 8-bit TI-PIPE interface is a 250 MHz 8-bit parallel interface, an
8-bit output bus (RXDATA) being clocked by the RXCLK output clock,
and an 8-bit input bus (TXDATA) being clocked by the TXCLK input
clock. Both buses are clocked using Double Data Rate (DDR) clocking
where the data transitions on both the clock’s rising-edge and
falling-edge.
The XIO1100 PHY interfaces to a 2.5Gbps PCI Express serial link with a
transmit differential pair (TXP and TXN) and a receive differential pair
(RXP and RXN). Incoming data at the XIO1100 PHY receive differential
pair (RXP and RXN) is forwarded to the MAC on the RXDATA output
bus. Data received from the MAC on the TXDATA input bus is forwarded
to the XIO1100 PHY transfer differential pair (TXP and TXN).
Key Benefits
• XIO1100 is TI’s Third-Generation PHY
Passed PCI SIG Workshop #49
••
• v1.0a and v1.1 compliant
••
Proven PCI Express Compatibility and Interoperability
• Source-Synchronous (SS) Clocking
••
Without SS clocking and running at 125 MHz the interface
must be tuned to the center capture window
• Painful and not robust
• XIO1100 is SS in BOTH RX and TX directions which makes
positioning I/O capture window easy to identify and robust
• SS approach works great from design without need for
experimental tuning
• Flexible MAC Interface
Selectable 8-bit or 16-bit Parallel Interface
• No need for extra clock buffer needed to generate 250MHz
• Flexible Digital I/O Power Supply
1.5V or 1.8V
••
••
Only two supply voltages needed: 3.3V and 1.5V
• Support for two PCI Express Reference Clocks
100 MHz differential for normal system clock designs
••
••
125 MHz single-ended for asynchronous clocking designs
The XIO1100 is also responsible for handling the 8B/10B encoding/
decoding of the outgoing data. In addition, XIO1100 can recover/
interpolate the clock on the receiver side based on the transitions
guaranteed by the use of the 8B/10B mechanism and supply this to
the receive side of the data link layer logic. In addition to the TI-PIPE
Interface, the XIO1100 has some TI proprietary side-band signals some
customers may wish to use to take advantage of additional low-power
state features (for example, disabling the PLL during the L1 power
state) of the XIO1100.
Peripheral Component Interconnect (PCI) is
an interconnection system between a microprocessor and attached devices in which
expansion slots are spaced closely for highspeed operation. A PCI-to-PCI bridge is a
high-performance connection path between
two PCI buses that allows bridge transactions
to occur concurrently on both buses. Burstmode transfers maximize data throughput
while the two bus traffic paths through the
bridge act independently. In future systems,
many PCI bus structures will be replaced by
he new serial PCI Express architecture. TI is
t
actively developing a portfolio of PCI Express
roducts to address this new market.
p
Key Features
• Two 32-bit, 33- or 66-MHz buses
• Configurable for PCI power-management
interface specification
• CompactPCI hot-swap functionality
• 3.3-V core logic with 3.3- to 5-V PCI
signaling compatibility
• Intel®bridge compatibility
• Transparent bridging
PCI Bridges
T
echnical Information
apabilities
C
• TI’s PCI2050B is a 32-bit, 66-MHz bridge
ith internal two-tier arbitration for up to
w
9 secondary bus masters and support for
an external secondary bus. There are
independent read/write buffers for each
direction and 10 secondary PCI clock outputs.
Functionality
• The PCI2250 is a 33-MHz bridge similar to
the PCI2050B but supports 4 secondary bus
masters and 5 secondary PCI clock outputs.
33
➔
PCI bridge family of products.
Selection Guide
Intel-Compatible SpeedExpansionMicroStar BGA™ Voltage
Suggested resale price in U.S. dollars in quantities of 1,000.
Resources For a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
Literature Number
Application Notes
SCPA029AAdding Debounce Logic to /HSSwitch Terminal
SLLA067Comparing Bus Solutions
SCPA027Connecting ENUM Terminal to an External Open-Drain Buffer
SCPA030
SPRA679Texas Instruments TMS320VC5409/5421 DSP to PCI Bus
T
power interface switches provide the total
power management solution required by the
ExpressCard specification. The TPS2231 and
TPS2236 ExpressCard power interface
switches distribute 3.3 V, AUX and 1.5 V to
the ExpressCard socket. Each voltage rail is
protected with integrated current-limiting
circuitry. The TPS2231 supports systems with
single-slot ExpressCardj34 or ExpressCardj54
sockets. The TPS2236 supports systems with
dual-slot ExpressCard sockets.
PCMCIA/CardBus Power Switches
Standard PC cards require that VCCbe
switched between ground, 3.3 V and 5 V,
while V
5 V and 12 V. CardBay sockets have the
standard requirements for VCC, but require
ground, 3.3 V and 5 V to VPP, and ground,
1.8 V or 3.3 V to V
applications may simply not need 12 V or V
while still having the standard requirements
for VCC. Therefore, consider the voltage
requirements of the application when selecting a PCMCIA power switch.
Current-Limiting Power Switches
Power switches are used to intelligently
turn power on and off, while providing fault
protection. They are useful anywhere controlled
allocation of power is needed to circuit
blocks, modules, add-in cards or cabled
connections. They are ideal for power
sequencing or segmentation.
To minimize voltage drop, select devices
with the lowest r
on-resistance.
Power MUX ICs
Power MUX ICs are designed to transition
from a main power supply to an auxiliary
source when the main supply shuts down
(e.g. switching from battery operation to a
wall adapter).
TPS2010A10.22302.7 to 5.573NoNoLTPS20100.75
TPS2011A10.66302.7 to 5.573NoNoLTPS20110.75
TPS2012A11.1302.7 to 5.573NoNoLTPS20120.75
TPS2013A11.65302.7 to 5.573NoNoLTPS20130.75
TPS2020/3010.22332.7 to 5.573YesYesL/H—1.05
TPS2021/3110.66332.7 to 5.573YesYesL/HTPS20141.05
TPS2022/3211.1332.7 to 5.573YesYesL/HTPS20151.05
TPS2023/3311.65332.7 to 5.573YesYesL/H—1.05
TPS2024/3412.2332.7 to 5.573YesYesL/H—1.05
TPS2041B/51B10.7702.7 to 5.543YesYesL/HTPS2041/51/41A/51A0.50
TPS2042B/52B20.7 ea702.7 to 5.550EachYesL/HTPS2042/52/42A/52A0.70
TPS2043B/53B30.7 ea702.7 to 5.565EachYesL/HTPS2043/53/43A/53A0.90
TPS2044B/54B40.7 ea702.7 to 5.575EachYesL/HTPS2044/54/44A/54A1.00
TPS2045A/55A10.3802.7 to 5.580YesYesL/HTPS2045/550.60
TPS2046B/56A20.3 ea802.7 to 5.580EachYesL/HTPS2046/46A/560.65
TPS2047B/57A30.3 ea802.7 to 5.5160EachYesL/HTPS2047/47A/570.90
TPS2060/421.5 ea702.7 to 5.550EachYesL/H—1.20
TPS2061/511.1702.7 to 5.543YesYesL/H—0.60
TPS2062/621.1 ea702.7 to 5.550EachYesL/H—0.75
TPS2063/731.1 ea702.7 to 5.565EachYesL/H—0.90
TPS2048A/58A40.3 ea802.7 to 5.5160EachYesL/HTPS2048/581.20
TPS2080/1/2
TPS2085/6/7
TPS2090/1/2
TPS2095/6/7
IEEE 1394 high-speed interconnection enables simple, low-cost, high-bandwidth real-time data connectivity between many types of electronic equip-
ent. As a multimedia network standard, 1394 is ideally suited for consumer electronics, computers and peripherals. It is also ideal for situations that
m
benefit from true peer-to-peer operation and maximum flexibility. 1394 is self-configuring, has strong power management/distribution capabilities and
obust error-detection that make it a leading choice in control applications, especially those that also need to accommodate streaming multimedia.
r
The new 1394b technology enables higher performance (up to 3.2 Gbps), longer distance (up to 100 meters) and a variety of cable media to fit any
application (STP, UTP, POF and GOF), making it ideal for home networking and high-speed data transfer applications. For example, in long-haul applications such as home networking, 1394b is capable of 100 Mbps over 100 meters of unshielded twisted pair Category 5 cable (called CAT5 or UTP5).
For high-speed applications, TI offers a 1394b chip set that enable speeds up to 800 Mbps for applications such as video-on-demand or backing up a
RAID array. TI 1394b is backward compatible to 1394a.
Design Considerations
Physical-Layer Selection Issues
• The 1394 PHY layer should support the
minimum number of nodes or ports
required by the end product. Having two
ports permits spanning to other devices
on the bus through daisy-chaining. Three
or more nodes enable branching or hub
capabilities.
• Will the end product need DC isolation at
the 1394 interface? The cable doesn’t
provide a DC-isolated path from node to
node. In cases where there’s a possibility
for the various equipment connected
across 1394 to be at different ground
potentials or different power domains,
the grounds may need to be isolated from
each other to prevent excessive currents
and noise. However, the ground signal on
the 1394 cable must not be DC-isolated
from the PHY power-distribution ground
plane. Thus when DC isolation between
units is required at the 1394 interface, it
is frequently performed at the PHY- and
link-layer interfaces—often through the
use of special I/O cells that allow for
capacitive coupling of the PHY-link signals.
• While the EIA-775 specification requires
a minimum speed of 200 Mbps at the
1394 interface, using 400-Mbps PHYs is
recommended. Slower nodes present on
the bus can be a source of speed traps.
Almost all 1394 silicon available today is
already 400-Mbps capable.
• The suspend/resume feature of the PHY
layer lets two currently inactive ports
achieve low-power states while maintain
ing their connection status. It also permits
them to quickly resume operation as soon
as they detect an applied port bias voltage.
Link-Layer Selection Issues
• What kind of data needs to be transferred?
Some link controllers are designed to
implement specific data protocols over
1394, such as the serial bus protocol
2 (SBP-2) for mass storage or IEC 61883-4
for MPEG-2 transport, and some are
designed as general purpose.
• What is being interfaced to 1394? If the
system has PCI, consider one of the
PCI/OHCI links. Applications involving
streaming compressed audio/video most
likely need a link from the iceLynx family.
Other TI links have interfaces for external
processors/memory or are dedicated for a
peripheral function (camera/storage).
• For audio/visual (A/V) applications,
different types of A/V data require different
formatting and transmission methods on
1394. Specifically identifying which types
of A/V to be supported is fundamental to
choosing the right 1394 chip set for the
digital set-top box (DSTB) or digital TV
(DTV) design. Standards define how to
carry MPEG-2 transport streams in both
digital video broadcasting (DVB) format
and in DirecTV format, which have different
packetization schemes.
• Another aspect of the link layer that
should be considered is the amount of
data-buffer memory supported. Typically,
the more bandwidth an application
requires, or the more simultaneous
isochronous/asynchronous traffic that
needs to be supported, the larger the
buffer memories must be.
-
• As the number of simultaneous isochronous channels present goes up, or the bit
rate of an individual stream increases, the
receive buffer needs to be larger.
Technical Information
• 1394-1995 is an IEEE designation for a
high-performance serial bus. A revision to
this standard has been published as IEEE
1394a-2000, and clarifies and adds to
portions of the IEEE 1394-1995 standard.
The 1394b standard increases the speed
of 1394 to 800, 1600 and 3200 Mbps, as
well as providing new connection options
such as plastic optical fiber (POF), glass
optical fiber (GOF) and UTP-5. This serial
bus defines both a backplane (for example, VME, FB+) physical layer and a pointto-point, cable-connected virtual bus. The
backplane version operates at 12.5, 25 or
50 Mbps, whereas the cable version
supports data rates of 100, 200, 400, 800
and 1,600 Mbps across the cable medium
supported in the current standard. Both
versions are totally compatible at the link
layer and above. The interface standard
defines transmission method, media and
protocol.
• Applications of the cable version are the
integration of I/O connectivity of personal
computers, peripherals, and consumer
electronics using a low-cost, scalable,
high-speed serial interface. The 1394
standard provides services such as
real-time I/O and live connect/disconnect
capability for devices including storage
(HDD, CD-ROM, CDRW, MO, ZIP, RAID,
SAN, etc.), printers, scanners, cameras,
set-top boxes, HDTVs and camcorders.
•
integration of I/O connectivity of personal
computers, peripherals, and consumer
electronics using a low-cost, scalable,
high-speed serial interface. The 1394
standard provides services such as realtime I/O and live connect/disconnect
capability for devices including storage
(HDD, CD-ROM, CDRW, MO, ZIP, RAID,
Key Features
• Real-time streaming of audio and video
• High-speed: up to 400 Mbps with IEEE
1394-1995 and 1394a-2000, up to 1, 2
and 4 Gbps with 1394b
• Plug-and-play hot pluggable
• Peer-to-peer communication
• Small, durable and flexible cable and
connectors
• Memory-mapped architecture
• Seamless I/O interconnect
1
394b Advantages
• Faster: speeds from 800 Mbps to
3200 Mbps
• Longer distances: 100 meters with GOF
and CAT5; 50 meters with POF
• TI1394b is bi-lingual: communicates in
1394a and 1394b modes
• More cabling options: STP, CAT5, POF, GOF
• More efficient: BOSS arbitration
• More user-friendly: loop-free build allows
any topology and redundancy
SAN, etc.), printers, scanners, cameras,
set-top boxes, HDTVs and camcorders.
Selection Guide
VoltageData Rate
DevicePorts(V)(Mbps)Package(s)DescriptionPrice
1394 Physical Layer Controllers
TSB14AA1A13.3up to 10048 TQFPIEEE 1394-1995, 3.3-V, 1-port, 50/100-Mbps, backplane PHY controller5.90
TSB41AB113.3up to 40048/64 HTQFP, IEEE 1394a 1-port cable transceiver/arbiter1.50
TSB41AB223.3up to 40064 HTQFP
TSB41AB333.3up to 40080 HTQFPIEEE 1394a 3-port cable transceiver/arbiter3.00
TSB41BA3B33.3up to 40080 TQFP1394b-2002 3-port physical layer device6.50
TSB41LV04A43.3up to 400
TSB41LV06A63.3up to 400100 HTQFPIEEE 1394a 6-port cable transceiver/arbiter6.40
TSB81BA3D31.8, 3.3up to 80080 HTQFPHigh-performance 1394b s800 3-port cable transceiver/arbiter5.55
*
Suggested resale price in U.S. dollars in quantities of 1,000.
† Unloaded backplane trace natural impedance (Z0) is 45 Ω to 60 Ω, with 60 Ω being ideal.
¥ Card stub natural impedance (Z
0
) is 60 Ω.
1"1"1"1"1"1"
Slot 1Slot 2Slot 3Slot 18Slot 19Slot 20
TI
Competitor A
2
1.5
1
0.5
0
1.98E-084.48E-08
Time
6.98E-08
Vol ts
Design Considerations
rimary
P
Speed — The speed of the GTLP family in
arallel backplanes is 4x that of traditional
p
logic. Optimized output edge-rate control
(OEC™) circuitry allows clock frequencies in
excess of 100 MHz in high-performance
system backplane applications.
Voltage Range — The GTLP family operates
at 3.3 V and with 5-V tolerant LVTTL inputs/
outputs and can operate in a mixed-voltage
environment. GTLP acts as LVTTL-to-GTLP
bi-directional translators with 5 V tolerance
on the LVTTL port.
Drive — The GTLP family provides ±24-mA
drive on the A-Port (LVTTL side) and the
choice of medium (50 mA) or high (100 mA)
drive on the B-Port (GTLP side). This offers
flexibility in matching the device to backplane
length, slot spacing and termination resistance.
GTLP (Gunning Transceiver Logic Plus)
ignal Integrity–TI-OPC
S
tection circuitry was designed specifically for
he GTLP family and incorporated into the
t
GTLP outputs. TI-OPC actively clamps any
overshoots that are caused by improperly
terminated backplanes, unevenly distributed
cards or empty slots. OEC on the rising and
falling edge of the GTLP outputs reduces line
reflections and extra EMI, improving overall
signal integrity.
True Live Insertion — GTLP backplane drivers
allow for Level 3 isolation and true liveinsertion capability. Level 1 isolation, partial
power-down: I
O
prevents damage by limiting the current
flowing from an energized bus when the
device V
goes to zero. Level 2 isolation,
CC
hot insertion: both I
(PU3S) circuitry allow insertion or removal of
a board into a backplane without powering
™
Overshoot pro-
—
circuitry within the device
FF
and power-up 3-state
OFF
down the host system and without suspending
signaling. Level 3 isolation, live insertion: for
ive insertion both I
l
nd PU3S circuitry are
a
FF
O
needed and the board I/Os must be precharged
to mid-swing levels prior to connector insertion/
removal.
Secondary
Compatibility — GTLP provides an easy
migration path from traditional backplane logic
like ABT, FCT, LVT, ALVT, LVC and FB+.
Portfolio — TI offers the broadest GTLP
portfolio in the industry, with both high-drive
(100 mA) and medium-drive (50 mA) devices.
Packaging — TI offers GTLP in a low-profile,
fine-pitch BGA package (LFBGA) and in a quad
flat no-lead package (QFN) for higher
performance and the ultimate reduction in
board-space requirements.
39
➔
Single Bit Representation of a Multipoint Parallel Backplane
SN74GTLP1394 2-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Xcvr w/ Split LVTTL Port, Feedback Path and Selectable Polarity2.09
SN74GTLP1395 Two 1-Bit LVTTL/GTLP Adjustable-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, Feedback Path and Selectable Polarity2.09
SN74GTLP2033 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver w/ Split LVTTL Port and Feedback Path5.17
SN74GTLP2034 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver w/ Split LVTTL Port and Feedback Path5.17
SN74GTLP21395 Two 1-Bit LVTTL/GTLP Adjustable-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, Feedback Path and Selectable Polarity2.09
SN74GTLP22033 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver w/ Split LVTTL Port and Feedback Path5.17
SN74GTLP22034 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path5.17
SN74GTLP817 GTLP-to-LVTTL 1-to-6 Fanout Driver1.95
SN74GTLPH1612 18-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Universal Bus Transceiver5.25
SN74GTLPH1616 17-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Universal Bus Transceiver w/ Buffered Clock Outputs5.25
SN74GTLPH1627 18-Bit LVTTL-to-GTLP Bus Xcvr w/Source Synchronous Clock Outputs5.63
SN74GTLPH1645 16-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Transceiver3.30
SN74GTLPH1655 16-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Universal Bus Transceiver5.25
SN74GTLPH16612 18-Bit LVTTL-to-GTLP Universal Bus Transceiver4.58
SN74GTLPH16912 18-Bit LVTTL-to-GTLP Universal Bus Transceiver4.88
SN74GTLPH16916 17-Bit LVTTL-to-GTLP Universal Bus Transceiver w/ Buffered Clock Outputs4.88
SN74GTLPH16927 18-Bit LVTTL-to-GTLP Bus Transceiver w/Source Synchronous Clock Outputs7.70
SN74GTLPH16945 16-Bit LVTTL-to-GTLP Bus Transceiver2.75
SN74GTLPH306 8-Bit LVTTL-to-GTLP Bus Transceiver2.42
SN74GTLPH3245 32-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Transceiver5.83
SN74GTLPH32912 36-Bit LVTTL-to-GTLP Universal Bus Transceiver7.50
SN74GTLPH3291634-Bit LVTTL-to-GTLP Universal Bus Transceiver w/ Buffered Clock Outputs7.50
SN74GTLPH32945 32-Bit LVTTL-to-GTLP Bus Transceiver4.29
*Suggested resale price in U.S. dollars in quantities of 1,000.
Resources For a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
Literature NumberDescription
Application Notes
SCEA017GTLP in BTL Applications
SCEA019Texas Instruments GTLP Frequently Asked Questions
SCEA026Logic in Live-Insertion Applications With a Focus on GTLP
SCEA022Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic
SCBA015AFast GTLP Backplanes With the GTLPH1655
Other Literature
SCYT126Advanced Bus Interface Logic Selection Guide
improves the performance up to 8X of the
VMEbus™ without making changes to
existing hardware.
Standard Specification — The VMEH22501/A
are referenced by the 2eSST VITA 1.5 spec
as a device that provides excellent signaling
at 40-Mbps data rate.
Increased Noise Immunity — The ±50-mV input
threshold allows the VMEH22501/A to provide
clean signaling under harsh environments.
Full Live Insertion—This device is fully
pecified for live-insertion applications using
s
power-up 3-state and BIAS V
I
,
FF
O
Speed/Signal Integrity—High-speed
backplane operation is a direct result of the
improved OEC circuitry that has been tested
on the standard VME backplane. Furthermore,
signal integrity is not compromised with
higher speed operation.
VME Parametric Table
Parameter NameSN74VMEH22501SN74VMEH2501A
Voltage Nodes (V)3.33.3
VCCRange (V)3.15 to 3.453.15 to 3.45
Input LevelLVTTLLVTTL
Output LevelLVTTLLVTTL
Output Drive (mA)–48/64–48/64
No. of Outputs1010
LogicTrueTrue
Static Current (mA)3030
tpdmax (ns)8.98.9
T
A
0° C to 85° C–40° C to 85° C
Technical Information
• TI’s SN74VMEH22501/A are specifically
designed for the VMEbus technology. The
.
C
C
device is an 8-bit universal bus transceiver
(UBT) with two bus transceivers. It
provides incident switching on the 21-slot
VMEbus backplane, thus providing data
signaling rates of up to 40 Mbps-—an 8X
improvement over the VME64 standard.
Highlights
• Ability to transmit data on the VMEbus
up to 2eSST protocol speed is an
improvement over VME64.
• Incident wave switching allows for higher
performance on the VMEbus compared to
conventional logic that depends on
reflective wave switching.
Resources For a complete list of resources (evaluation modules, data sheets and application notes), visit interface.ti.com
Literature NumberDescription
Application Notes
SCEA028VMEH22501 in 2eSST and Conventional VME Backplane Applications
oll Free Number
Australia1-800-999-084
China800-820-8682
Hong Kong800-96-5941
India+91-80-41381665 (Toll)
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New Zealand 0800-446-934
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Singapore800-886-1028
Taiwan0800-006800
Thailand001-800-886-0010
Fax+886-2-2378-6808
Emailtiasia@ti.com or ti-china@ti.com
Internetsupport.ti.com/sc/pic/asia.htm
D062706
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This publication may contain forward-looking statements that
involve a number of risks and uncertainties. These “forward-
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liability established by the Private Securities Litigation Reform Act
of 1995. These forward-looking statements generally can be
identified by phrases such as TI or its management “believes,”
“expects,” “anticipates,” “foresees,” “forecasts,” “estimates” or
other words or phrases of similar import. Similarly, su ch state-
ments herein that describe the company’s products, business
s
trategy, outlook, objectives, plans, intentions or goals also are
f
orward-looking statements. All such forward-looking state-
m
ents are subject to certain risks and uncertainties that could
c
ause actual results to differ materially from those in forward-
l
ooking statements. Please refer to TI’s most recent Form 10-K for
more information on the risks and uncertainties that could materi-
ally affect future results of operations. We disclaim any intention
or obligation to update any forward-looking statements as a result
of developments occurring after the date of this publication.
Important Notice: The products and services of Texas
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Customers are advised to obtain the most current and complete
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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ProductsApplications
Amplifiersamplifier.ti.comAudiowww.ti.com/audio
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Interfaceinterface.ti.comDigital Controlwww.ti.com/digitalcontrol
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Microcontrollersmicrocontroller.ti.comSecuritywww.ti.com/security
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