Texas Instruments SN74LVC1G66DBV, SN74LVC1G66DCK, SN74LVC1G66DRL, SN74LVC1G66DRY, SN74LVC1G66DSF Schematic [ru]

3

2

4

51

A V

CC

C

B

GND

DBV PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

3

2

4

51

A V

CC

C

B

GND

3

2

4

51

A V

CC

C

B

GND

A

GND

V

CC

C

B

DRL PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

1

423

5

DRY PACKAGE

(TOP VIEW)

B NC

A

6

5

4

2

3

GND

C

V

CC

1

A

GND

DSF PACKAGE

(TOP VIEW)

B

V

CC

C

NC

6

5

4

2

3

1

SN74LVC1G66

www.ti.com

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

SINGLE BILATERAL ANALOG SWITCH

Check for Samples: SN74LVC1G66

1

FEATURES

2

• Available in the Texas Instruments NanoFree™
Package (VCC= 4.5 V)

• 1.65-V to 5.5-V VCCOperation • Latch-Up Performance Exceeds 100 mA Per

• Inputs Accept Voltages to 5.5 V

• Max tpdof 0.8 ns at 3.3 V

• High On-Off Output Voltage Ratio

• High Degree of Linearity

• High Speed, Typically 0.5 ns
(VCC= 3 V, CL= 50 pF)

• Low On-State Resistance, Typically ≉≉5.5 Ω

JESD 78, Class II

• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This single analog switch is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of up

to 5.5 V (peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for

analog-to-digital and digital-to-analog conversion systems.

1

2NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2001–2012, Texas Instruments Incorporated

B

C

A

1

4

2

SN74LVC1G66

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

Table 1. ORDERING INFORMATION

T

A

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb- Reel of 3000 SN74LVC1G66YZPR _ _ _C6_
free)

SOT (SOT-23) – DBV C66_

–40°C to 85°C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

SOT (SC-70) – DCK

SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G66DRLR
QFN – DRY Reel of 5000 SN74LVC1G66DRYR
µQFN – DSF Reel of 5000 SN74LVC1G66DSFR

PACKAGE

(1)

Reel of 3000 SN74LVC1G66DBVR
Reel of 250 SN74LVC1G66DBVT
Reel of 3000 SN74LVC1G66DCKR
Reel of 250 SN74LVC1G66DCKT
Jumbo Reel of

10000

ORDERABLE PART NUMBER TOP-SIDE MARKING

SN74LVC1G66DCKJ

C6_

C6

FUNCTION TABLE

CONTROL

INPUT SWITCH

(C)

L OFF

H ON

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(2)

LOGIC DIAGRAM (POSITIVE LOGIC)

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Product Folder Links: SN74LVC1G66

SN74LVC1G66

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Absolute Maximum Ratings

(1)

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V
V
V
I
I
I

Supply voltage range

CC

Input voltage range

I

Switch I/O voltage range

I/O

Control input clamp current VI< 0 –50 mA

IK

I/O port diode current V

IOK

On-state switch current V

T

Continuous current through VCCor GND ±100 mA

θ

T

Package thermal impedance

JA

Storage temperature range –65 150 °C

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) The package thermal impedance is calculated in accordance with JESD 51-7.

(2)

(2) (3)

(2) (3) (4)

(5)

–0.5 6.5 V
–0.5 6.5 V
–0.5 VCC+ 0.5 V

I/O
I/O

< 0 or V
< 0 to V

CC

I/O

> V

CC

±50 mA
±50 mA

DBV package 206
DCK package 252
DRL package 142
YZP package 132

°C/W

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SN74LVC1G66

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

Recommended Operating Conditions

(1)

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MIN MAX UNIT

V
V

Supply voltage 1.65 5.5 V

CC

I/O port voltage 0 V

I/O

CC

VCC= 1.65 V to 1.95 V VCC× 0.65

V

High-level input voltage, control input V

IH

VCC= 2.3 V to 2.7 V VCC× 0.7
VCC= 3 V to 3.6 V VCC× 0.7
VCC= 4.5 V to 5.5 V VCC× 0.7
VCC= 1.65 V to 1.95 V VCC× 0.35

V

Low-level input voltage, control input V

IL

VCC= 2.3 V to 2.7 V VCC× 0.3
VCC= 3 V to 3.6 V VCC× 0.3
VCC= 4.5 V to 5.5 V VCC× 0.3

V

Control input voltage 0 5.5 V

I

VCC= 1.65 V to 1.95 V 20

Δt/Δv Input transition rise/fall time ns/V

VCC= 2.3 V to 2.7 V 20
VCC= 3 V to 3.6 V 10
VCC= 4.5 V to 5.5 V 10

T

Operating free-air temperature –40 85 °C

A

(1) All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

V

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IS= 4 mA 1.65 V 12 30
IS= 8 mA 2.3 V 9 20
IS= 24 mA 3 V 7.5 15
IS= 32 mA 4.5 V 5.5 10
IS= 4 mA 1.65 V 74.5 120
IS= 8 mA 2.3 V 20 30
IS= 24 mA 3 V 11.5 20
IS= 32 mA 4.5 V 7.5 15

r

r

I

I

I

I

ΔI
C

C

C

On-state switch resistance Ω

on

Peak on resistance Ω

on(p)

Off-state switch leakage

S(off)

current

On-state switch leakage VI= VCCor GND, VC= VIH, VO= Open

S(on)

current (see Figure 4)

Control input current VC= VCCor GND 5.5 V μA

I

Supply current VC= VCCor GND 5.5 V μA

CC

Supply current change VC= VCC– 0.6 V 5.5 V 500 μA

CC

Control input capacitance 5 V 2 pF

ic

Switch input/output

io(off)

capacitance
Switch input/output 5 V

io(on)

capacitance

(1) TA= 25°C

VI= VCCor GND,
VC= V

IH

(see Figure 1 and

Figure 2)

VI= VCCor GND,
VC= V

IH

(see Figure 1 and

Figure 2)

VI= VCCand VO= GND or ±1
VI= GND and VO= VCC, 5.5 V μA
VC= VIL(see Figure 3)

CC

MIN TYP

5.5 V μA

(1)

MAX UNIT

(1)

±0.1

±1

(1)

±0.1

±1

(1)

±0.1

10

(1)

1

5 V 6 pF

13 pF

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Product Folder Links: SN74LVC1G66

SN74LVC1G66

www.ti.com

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)

PARAMETER UNIT

(1)

t

pd

(2)

t

en

(3)

t

dis

(1) t
(2) t

(3) t

and t

PLH

switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

and t

PZL

and t

PLZ

are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the

PHL

are the same as ten.

PZH

are the same as t

PHZ

FROM TO

(INPUT) (OUTPUT)

A or B B or A 2 1.2 0.8 0.6 ns

C A or B 2.5 12 1.9 6.5 1.8 5 1.5 4.2 ns
C A or B 2.2 10 1.4 6.9 2 6.5 1.4 5 ns

.

dis

VCC= 1.8 V VCC= 2.5 V VCC= 3.3 V VCC= 5 V

± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V

MIN MAX MIN MAX MIN MAX MIN MAX

Analog Switch Characteristics

TA= 25°C

PARAMETER V

Frequency response

(1)

(switch ON)

Crosstalk
(control input to signal output)

Feedthrough attenuation

(2)

(switch OFF)

Sine-wave distortion A or B B or A %

(1) Adjust finvoltage to obtain 0 dBm at output. Increase finfrequency until dB meter reads –3 dB.
(2) Adjust finvoltage to obtain 0 dBm at input.

FROM TO TEST

(INPUT) (OUTPUT) CONDITIONS

CC

TYP UNIT

1.65 V 35

CL= 50 pF, RL= 600 Ω,
fin= sine wave
(see Figure 6)

A or B B or A MHz

CL= 5 pF, RL= 50 Ω,
fin= sine wave
(see Figure 6)

2.3 V 120
3 V 175

4.5 V 195

1.65 V >300

2.3 V >300
3 V >300

4.5 V >300

1.65 V 35

C A or B fin= 1 MHz (square wave) mV

CL= 50 pF, RL= 600 Ω,
(see Figure 7)

2.3 V 50
3 V 70

4.5 V 100

1.65 V –58

CL= 50 pF, RL= 600 Ω,
fin= 1 MHz (sine wave)
(see Figure 8)

A or B B or A dB

CL= 5 pF, RL= 50 Ω,
fin= 1 MHz (sine wave)
(see Figure 8)

2.3 V –58
3 V –58

4.5 V –58

1.65 V –42

2.3 V –42
3 V –42

4.5 V –42

1.65 V 0.1

CL= 50 pF, RL= 10 kΩ,
fin= 1 kHz (sine wave)
(see Figure 9)

2.3 V 0.025
3 V 0.015

4.5 V 0.01

1.65 V 0.15

CL= 50 pF, RL= 10 kΩ,
fin= 10 kHz (sine wave)
(see Figure 9)

2.3 V 0.025
3 V 0.015

4.5 V 0.01

Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: SN74LVC1G66

SN74LVC1G66

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

www.ti.com

Operating Characteristics

TA= 25°C

PARAMETER UNIT

CpdPower dissipation capacitance f = 10 MHz 8 9 9 11 pF

TEST

CONDITIONS

VCC= 1.8 V VCC= 2.5 V VCC= 3.3 V VCC= 5 V

TYP TYP TYP TYP

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Product Folder Links: SN74LVC1G66

100

10

1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VCC = 1.65 V

VCC = 2.3 V

VCC = 3.0 V

VCC = 4.5 V

VIN − V

r

on

− Ω

V

CC

VI = V

CC

or GND

V

O

r

on

+

VI* V

O

I

S

W

V

I

− V

O

GND(ON)

V

B or A

C

A or B

V

CC

V

IH

V

C

I

S

SN74LVC1G66

www.ti.com

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

PARAMETER MEASUREMENT INFORMATION

Figure 1. On-State Resistance Test Circuit

Figure 2. Typical ronas a Function of Input Voltage (VI) for VI= 0 to V

CC

Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: SN74LVC1G66

V

CC

V

O

GND(ON)

B or A

C

A or B

V

CC

V

IH

V

C

A

VI = V

CC

or GND

VO = Open

Condition 1: V

I

= GND, VO = V

CC

Condition 2: VI = VCC, VO = GND

V

CC

V

I

V

O

GND(OFF)

B or A

C

A or B

V

CC

V

IL

V

C

A

SN74LVC1G66

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

PARAMETER MEASUREMENT INFORMATION

Figure 3. Off-State Switch Leakage-Current Test Circuit

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Figure 4. On-State Switch Leakage-Current Test Circuit

8 Submit Documentation Feedback Copyright © 2001–2012, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G66

V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH − V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V
5 V ± 0.5 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

2 × V

CC

2 × V

CC

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

V

CC

V

CC

V

I

VCC/2
VCC/2
VCC/2
VCC/2

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUTS

SN74LVC1G66

www.ti.com

PARAMETER MEASUREMENT INFORMATION

SCES323N –JUNE 2001–REVISED NOVEMBER 2012

Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 5. Load Circuit and Voltage Waveforms

Product Folder Links: SN74LVC1G66