SN74LVC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
I
Feature Supports Partial-Power-Down
off
Mode Operation
D
Supports 5-V VCC Operation
D
Package Options Include Plastic
DBV OR DCK PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
Small-Outline Transistor (DBV, DCK)
Packages
description
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G00 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
A B
H H L
L XH
X L H
OUTPUT
Y
off
. The I
off
V
5
CC
Y
4
circuitry disables the outputs,
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
A
2
B
&
logic diagram (positive logic)
1
A
2
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
4
Y
PRODUCT PREVIEW
4
Y
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN74LVC1G00
VCCSuppl
oltage
V
VIHHigh-level input voltage
V
VILLow-level input voltage
V
V
3 V
V
V
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
p
p
V
PRODUCT PREVIEW
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 5.5
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × V
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × V
VCC = 1.65 V –4
VCC = 2.3 V –8
=
CC
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
= 3
CC
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 5
CC
CC
CC
–16
–24
16
24
10
CC
CC
†
V
mA
mA
ns/V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
3 V
V
V
3 V
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
SN74LVC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
IOH = –100 mA 1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
OH
OL
I
A or B inputs VI = 5.5 V or GND 0 to 5.5 V ±5
I
I
off
I
CC
∆I
CC
C
i
IOH = –8 mA 2.3 V 1.9
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 mA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
VI or VO = 5.5 V 0 ±10
VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500
VI = VCC or GND 3.3 V pF
CC
4.5 V 3.8
4.5 V 0.55
MIN
2.4
2.3
TYP
†
MAX UNIT
0.4
0.55
m
A
m
A
m
A
m
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
PARAMETER
t
pd
FROM
A or B
operating characteristics, T
C
Power dissipation capacitance f = 10 MHz pF
pd
= 25°C
A
TO
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
Y
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
VCC = 2.5 V
± 0.2 V
TYP TYP TYP TYP
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
ns
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
From Output
Under Test
CL = 30 pF
(see Note A)
1 kΩ
1 kΩ
S1
= 1.8 V ± 0.15 V
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2 VCC/2
VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
500 Ω
500 Ω
S1
SN74LVC1G00
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
PRODUCT PREVIEW
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74LVC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V ± 0.3 V
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
1.5 V 1.5 V
PRODUCT PREVIEW
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
6 V
S1
t
h
t
PHL
Open
GND
3 V
0 V
3 V
0 V
3 V
0 V
V
V
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
1.5 V
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
V
V
0 V
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
From Output
Under Test
Input
CL = 50 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
LOAD CIRCUIT
t
w
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
S1
= 5 V ± 0.5 V
V
CC
11 V
Open
GND
V
CC
0 V
SN74LVC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES212B – APRIL 1999 – REVISED FEBRUARY 2000
TEST S1
Timing Input
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
11 V
GND
VCC/2
t
h
VCC/2
V
0 V
V
0 V
CC
CC
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VCC/2 VCC/2
VCC/2
VOLTAGE WAVEFORMS
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
VCC/2
t
PHL
t
VCC/2
.
dis
PLH
Figure 4. Load Circuit and Voltage Waveforms
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 11 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2 VCC/2
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
V
CC
0 V
5.5 V
V
OL
V
OH
≈ 0 V
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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