Texas Instruments SN74LVC16652DL, SN74LVC16652DLR Datasheet

SN74LVC16652

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at VCC = 3.3 V, TA = 25°C

D

Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 16-bit bus transceiver and register is
designed for low-voltage (3.3-V) VCC operation.

The SN74LVC16652 consists of D-type flip-flops
and control circuitry arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The device can
be used as two 8-bit transceivers or one 16-bit
transceiver.

Complementary output-enable (OEAB and
OEBA) inputs control the transceiver functions.
Select-control (SAB and SBA) inputs select
whether real-time or stored data is transferred. A
low input level selects real-time data, and a high input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the SN74LVC16652.

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

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1OEAB

1CLKAB

1SAB

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

2SAB

2CLKAB

2OEAB

1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2SBA
2CLKBA
2OEBA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA

. In this configuration, each output
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set
of bus lines remains at its last level configuration.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVC16652 is characterized for operation from –40°C to 85°C.

SN74LVC16652

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

X
L
L

OEAB

LL

CLKABXCLKBAXSABXSBA

L

CLKABXCLKBAXSABLSBA

X

H

CLKAB CLKBAXSABXSBA

X

CLKAB CLKBA SAB SBA

X
H

XX

X

X
X

H L H or L H H

↑

↑
↑↑

OEBA

OEBA

HH

OEAB OEBA

OEAB OEBA

H or L

Figure 1. Bus-Management Functions