SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit bus transceiver and register is
designed for low-voltage (3.3-V) VCC operation.
The SN74LVC16652 consists of D-type flip-flops
and control circuitry arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The device can
be used as two 8-bit transceivers or one 16-bit
transceiver.
Complementary output-enable (OEAB and
OEBA) inputs control the transceiver functions.
Select-control (SAB and SBA) inputs select
whether real-time or stored data is transferred. A
low input level selects real-time data, and a high input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the SN74LVC16652.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
. In this configuration, each output
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set
of bus lines remains at its last level configuration.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVC16652 is characterized for operation from –40°C to 85°C.
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
LL
CLKABXCLKBAXSABXSBA
L
CLKABXCLKBAXSABLSBA
X
H
CLKAB CLKBAXSABXSBA
X
CLKAB CLKBA SAB SBA
X
H
XX
X
X
X
H L H or L H H
↑
↑
↑↑
OEBA
OEBA
HH
OEAB OEBA
OEAB OEBA
H or L
Figure 1. Bus-Management Functions
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
C3
EN7 [BA]
29
G12
26
2SAB
5
1A1
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
3D
27
2CLKAB
G10
31
2SBA
30
2CLKBA
EN8 [AB]
28
2OEAB
EN1 [BA]
56
G6
3
1SAB
2
1CLKAB
G4
54
1SBA
55
1CLKBA
EN2 [AB]
1
1OEAB
C5
C9
C11
15
2A1
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
9D
1OEBA
2OEBA
5D
1
≥ 1
≥ 1
2
16
6
441
11D
7
≥ 1
≥ 1
8
112
12
10101
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
1B1
1D
C1
1D
C1
One of Eight Channels
52
5
3
2
54
55
56
1
1SAB
1CLKAB
1SBA
1CLKBA
1OEAB
1OEBA
To Seven Other Channels
2A1
2B1
1D
C1
1D
C1
42
15
26
27
31
30
29
28
2SAB
2CLKAB
2SBA
2CLKBA
2OEAB
2OEBA
To Seven Other Channels
One of Eight Channels
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
†
OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8
OPERATION OR FUNCTION
L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
‡
Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
L X H or L ↑ X X Unspecified
‡
Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus and
Stored B data to A bus
†
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
§
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package 1 W. . . . . . . . . . . . . . . . . .
DL package 1.4 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Data Book
, literature number SCBD002B.
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 2.7 3.6 V
V
IH
High-level input voltage VCC = 2.7 V to 3.6 V 2 V
V
IL
Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
p
VCC = 2.7 V –12
IOHHigh-level output current
VCC = 3 V –24
mA
p
VCC = 2.7 V 12
IOLLow-level output current
VCC = 3 V 24
mA
∆t/∆V Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
†
MIN TYP‡MAX UNIT
IOH = –100 µA MIN to MAX VCC–0.2
2.7 2.2
VOHI
OH
= –12
mA
3 2.4
V
IOH = –24 mA 3 2
IOL = 100 µA MIN to MAX 0.2
V
OL
IOL = 12 mA 2.7 0.4
V
IOL = 24 mA 3 0.55
I
I
Control inputs VI = VCC or GND 3.6 ±5 µA
VI = 0.8 V
75
I
I(hold)
A or B ports
VI = 2 V
3
–75
µA
()
VI = 0 to 3.6 V 3.6 ±500
I
OZ
§
VO = VCC or GND 3.6 ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 40 µA
n
I
CC
One input at VCC – 0.6 V , Other inputs at VCC or GND 3 V to 3.6 V 500 µA
C
i
Control inputs VI = VCC or GND 3.3 3 pF
C
io
A or B ports VO = VCC or GND 3.3 7 pF
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
§
For I/O ports, the parameter IOZ includes the input leakage current.
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX
f
clock
Clock frequency 0 100 0 80 MHz
t
w
Pulse duration, CLK high or low 4.5 4.5 ns
t
su
Setup time, A or B before CLKAB↑ or CLKBA↑ Data high or low 5 5 ns
t
h
Hold time, A or B after CLKAB↑ or CLKBA↑ Data high or low 0 0 ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
f
max
100 80 MHz
A or B B or A 1.5 7 8
t
pd
CLKAB or CLKBA
1.5 8.5 9.5
ns
SAB or SBA
A or B
1.5 8.5 9.5
t
en
OE or OE A or B 1.5 8 9 ns
t
dis
OE or OE
A or B 1.5 8.5 9.5 ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
25
p
CpdPower dissipation capacitance per transceiver
Outputs disabled
C
L
=
50 pF
, f = 10 MHz
4
pF
SN74LVC16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS319B – NOVEMBER 1993 – REVISED JUL Y 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
500 Ω
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500 Ω
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V 1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
[
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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