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SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995
D
Member of the Texas Instruments
Widebus
D
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit bus transceiver and register is
designed for low-voltage (3.3-V) VCC operation.
The SN74LVC16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. The device
consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers.
Data on the A or B bus is clocked into the registers
on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
SN74LVC16646.
DGG OR DL PACKAGE
(TOP VIEW)
1A1
1A2
V
CC
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
V
CC
2A7
2A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1DIR
1CLKAB
1SAB
GND
GND
GND
GND
2SAB
2CLKAB
2DIR
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE
) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port may be stored in either register or in both. The select-control
(SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data. DIR determines which bus receives data when OE
is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVC16646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995
BUS A
DIRLCLKABXCLKBAXSABXSBA
OE
L
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
OE
L
BUS A
DIRHCLKABXCLKBAXSABLSBA
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
X
BUS A
DIRXCLKAB CLKBAXSABXSBA
X
X
H
X
X
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
X
X
X
X
OEOE
BUS A
DIRLCLKABXCLKBA
L
L H H or L X H X
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
H or L
TO A AND/OR B
BUS B
SABXSBA
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995
logic symbol
†
56
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1DIR
1CLKBA
1SBA
1CLKAB C6
1SAB
2DIR
2CLKBA
2SBA
2CLKAB C13
2SAB
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
G14
≥1
1
6D
177
≥1
8
13D
11414
≥1
≥1
155
11D
11212
4D
2
9
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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