TEXAS INSTRUMENTS SN74LVC16646 Technical data

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SN74LVC16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

D

Member of the Texas Instruments

Widebus

D

EPIC

 Family

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Typical V

(Output Ground Bounce)

OLP

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

Typical V

(Output VOH Undershoot)

OHV

> 2 V at VCC = 3.3 V, TA = 25°C

D

Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 16-bit bus transceiver and register is
designed for low-voltage (3.3-V) VCC operation.

The SN74LVC16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. The device
consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers.

Data on the A or B bus is clocked into the registers
on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
SN74LVC16646.

DGG OR DL PACKAGE

(TOP VIEW)

1A1
1A2

V

CC

1A3
1A4
1A5

1A6
1A7
1A8
2A1
2A2
2A3

2A4
2A5
2A6

V

CC

2A7
2A8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

1DIR

1CLKAB

1SAB

GND

GND

GND

GND

2SAB

2CLKAB

2DIR

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE
1CLKBA
1SBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2SBA
2CLKBA
2OE

Output-enable (OE

) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port may be stored in either register or in both. The select-control
(SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data. DIR determines which bus receives data when OE

is low. In the isolation mode (OE high),

A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVC16646 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

BUS A

DIRLCLKABXCLKBAXSABXSBA

OE

L

REAL-TIME TRANSFER

BUS B TO BUS A

BUS B

L

OE

L

BUS A

DIRHCLKABXCLKBAXSABLSBA

REAL-TIME TRANSFER

BUS A TO BUS B

BUS B

X

BUS A

DIRXCLKAB CLKBAXSABXSBA

X
X
H

X
X

↑

XX

STORAGE FROM

A, B, OR A AND B

↑
↑↑

BUS B

X
X

X

X

OEOE

BUS A

DIRLCLKABXCLKBA
L
L H H or L X H X

TRANSFER STORED DA TA

Figure 1. Bus-Management Functions

H or L

TO A AND/OR B

BUS B

SABXSBA

H

2

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SN74LVC16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

logic symbol

†

56

1OE

2OE

1A1

1A2
1A3
1A4
1A5
1A6
1A7
1A8

2A1

2A2
2A3
2A4
2A5
2A6
2A7
2A8

1

55
54
2
3
29
28

30
31
27
26

5

6
8
9
10
12
13
14

15

16
17
19
20
21
23
24

1DIR

1CLKBA

1SBA

1CLKAB C6

1SAB

2DIR

2CLKBA

2SBA

2CLKAB C13

2SAB

G3
3 EN1 [BA]

3 EN2 [AB]

C4

G5

G7
G10
10 EN8 [BA]

10 EN9 [AB]

C11

G12

G14

≥1

1

6D

177

≥1

8

13D

11414

≥1

≥1

155

11D

11212

4D

2

9

52

51
49
48
47
45
44
43
42

41
40
38
37
36
34
33

1B1

1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1

2B2
2B3
2B4
2B5
2B6
2B7
2B8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

logic diagram (positive logic)

56

1OE

1

1DIR

1CLKBA

1SBA

1CLKAB

1SAB

55
54

2

3

1A1

2OE

2DIR

2CLKBA

2SBA

2CLKAB

2SAB

One of Eight Channels

5

1D

C1

29

28
30
31
27

26

To Seven Other Channels

C1

1D

52

1B1

One of Eight Channels

15

2A1

1D

C1

To Seven Other Channels

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

C1

1D

42

2B1

OPERATION OR FUNCTION

SN74LVC16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

FUNCTION TABLE

INPUTS

OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8

X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus

†

The data output functions may be enabled or disabled by various signals at the OE
i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

DATA I/Os

†

†

Input Store B, A unspecified

and DIR inputs. Data input functions are always enabled;

Store A, B unspecified

†
†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package 1 W. . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Data Book

, literature number SCBD002B.

: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

DL package 1.4 W. . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

application note in the 1994

ABT Advanced BiCMOS T echnology

‡

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5

SN74LVC16646

IOHHigh-level output current

mA

IOLLow-level output current

mA

VOHI

mA

V

3

()

16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

CC

V

IH

V

IL

V

I

V

O

∆t/∆V Input transition rise or fall rate 0 10 ns/V
T

A

NOTE 4: Unused control inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V

OL

I

I

I

I(hold)

I

OZ

I

CC

n

C

i

C

io

†

For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.

‡

All typical values are at VCC = 3.3 V, TA = 25°C.

§

For I/O ports, the parameter IOZ includes the input leakage current.

Supply voltage 2.7 3.6 V
High-level input voltage VCC = 2.7 V to 3.6 V 2 V
Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
Input voltage 0 V
Output voltage 0 V

p

p

Operating free-air temperature –40 85 °C

PARAMETER TEST CONDITIONS V

IOH = –100 µA MIN to MAX VCC–0.2

= –12

OH

IOH = –24 mA 3 2
IOL = 100 µA MIN to MAX 0.2
IOL = 12 mA 2.7 0.4
IOL = 24 mA 3 0.55

Control inputs VI = VCC or GND 3.6 ±5 µA

VI = 0.8 V

A or B ports

§

I

CC

Control inputs VI = VCC or GND 3.3 3 pF
A or B ports VO = VCC or GND 3.3 7 pF

VI = 2 V
VI = 0 to 3.6 V 3.6 ±500
VO = VCC or GND 3.6 ±10 µA
VI = VCC or GND, IO = 0 3.6 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 500 µA

VCC = 2.7 V –12
VCC = 3 V –24
VCC = 2.7 V 12
VCC = 3 V 24

†

CC

2.7 2.2
3 2.4

MIN TYP‡MAX UNIT

75

–75

CC
CC

V
V

V

µA

6

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(INPUT)

(OUTPUT)

A or B

t

A

B

t

A or B

ns

CpdPower dissipation capacitance per transceiver

C

50 pF

pF

SN74LVC16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX

f

clock

t

w

t

su

t

h

Clock frequency 0 100 0 80 MHz
Pulse duration, CLK high or low 4.5 4.5 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ Data high or low 5 5 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ Data high or low 0 0 ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX

100 80 MHz

1.5 8.5 9.5

1.5 8.5 9.5

1.5 8 9

1.5 8 9

1.5 8.5 9.5

1.5 8.5 9.5

PARAMETER

f

max

t

pd

en

dis

FROM

A or B B or A 1.5 7 8

CLKAB or CLKBA

SAB or SBA

OE

DIR

OE

DIR

TO

or

VCC = 2.7 V

VCC = 2.7 V

UNIT

UNIT

ns

ns

operating characteristics, VCC = 3.3 V, TA = 25°C

PARAMETER

p

p

p

Outputs enabled
Outputs disabled

TEST CONDITIONS TYP UNIT

p

, f = 10 MHz

=

L

17

4

p

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7

SN74LVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS318B – NOVEMBER 1993 – REVISED JUL Y 1995

PARAMETER MEASUREMENT INFORMATION

t

w

1.5 V

500 Ω

500 Ω

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

Input

Output

Output

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

t

PLH

t

PHL

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

6 V

Open

GND

2.7 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

su

t

1.5 V

t

PHZ

1.5 V

PLZ

Open

6 V

GND

1.5 V

t

h

1.5 V

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

VOL + 0.3 V

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

[

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

PLZ
PZL
PLH

and t
and t
and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

8

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Copyright  1998, Texas Instruments Incorporated