Texas Instruments SN74LVC16543DL, SN74LVC16543DLR Datasheet
SN74LVC16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
low-voltage (3.3-V) VCC operation.
The SN74LVC16543 can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
The A-to-B enable (CEAB) input must be low in
order to enter data from A or to output data from
B. If CEAB is low and LEAB is low, the A-to-B
latches are transparent; a subsequent low-to-high
transition of LEAB
puts the A latches in the
storage mode. With CEAB and OEAB both low,
the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to
A is similar but requires using the CEBA
, LEBA, and OEBA inputs.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16543 is characterized for operation from –40°C to 85°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
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9
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11
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13
14
15
16
17
18
19
20
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26
27
28
56
55
54
53
52
51
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44
43
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38
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32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
SN74LVC16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
†
(each 8-bit section)
INPUTS
OUTPUT
CEAB LEAB OEAB A
B
H X X X Z
X XHX Z
L HLXB
0
‡
L LLL L
L L L H H
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
, LEBA, and OEBA.
‡
Output level before the indicated steady-state input
conditions were established
SN74LVC16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
15
2A1
8C12
27
5
1A1
6D
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
5D
3
4
G8
26
8EN10
28
7C11
30
G7
31
7EN9
29
2C6
2
G2
3
2EN4
1
1C5
55
G1
54
1EN3
56
12D
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
11D
9
10
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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